]>
git.proxmox.com Git - mirror_qemu.git/blob - target-arm/helper.c
9 #include "qemu-common.h"
10 #include "host-utils.h"
12 static uint32_t cortexa8_cp15_c0_c1
[8] =
13 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
15 static uint32_t cortexa8_cp15_c0_c2
[8] =
16 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
18 static uint32_t mpcore_cp15_c0_c1
[8] =
19 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
21 static uint32_t mpcore_cp15_c0_c2
[8] =
22 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
24 static uint32_t arm1136_cp15_c0_c1
[8] =
25 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
27 static uint32_t arm1136_cp15_c0_c2
[8] =
28 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
30 static uint32_t cpu_arm_find_by_name(const char *name
);
32 static inline void set_feature(CPUARMState
*env
, int feature
)
34 env
->features
|= 1u << feature
;
37 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
39 env
->cp15
.c0_cpuid
= id
;
41 case ARM_CPUID_ARM926
:
42 set_feature(env
, ARM_FEATURE_VFP
);
43 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
44 env
->cp15
.c0_cachetype
= 0x1dd20d2;
45 env
->cp15
.c1_sys
= 0x00090078;
47 case ARM_CPUID_ARM946
:
48 set_feature(env
, ARM_FEATURE_MPU
);
49 env
->cp15
.c0_cachetype
= 0x0f004006;
50 env
->cp15
.c1_sys
= 0x00000078;
52 case ARM_CPUID_ARM1026
:
53 set_feature(env
, ARM_FEATURE_VFP
);
54 set_feature(env
, ARM_FEATURE_AUXCR
);
55 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
56 env
->cp15
.c0_cachetype
= 0x1dd20d2;
57 env
->cp15
.c1_sys
= 0x00090078;
59 case ARM_CPUID_ARM1136_R2
:
60 case ARM_CPUID_ARM1136
:
61 set_feature(env
, ARM_FEATURE_V6
);
62 set_feature(env
, ARM_FEATURE_VFP
);
63 set_feature(env
, ARM_FEATURE_AUXCR
);
64 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
65 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
66 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
67 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
68 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
69 env
->cp15
.c0_cachetype
= 0x1dd20d2;
71 case ARM_CPUID_ARM11MPCORE
:
72 set_feature(env
, ARM_FEATURE_V6
);
73 set_feature(env
, ARM_FEATURE_V6K
);
74 set_feature(env
, ARM_FEATURE_VFP
);
75 set_feature(env
, ARM_FEATURE_AUXCR
);
76 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
77 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
78 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
79 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
80 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
81 env
->cp15
.c0_cachetype
= 0x1dd20d2;
83 case ARM_CPUID_CORTEXA8
:
84 set_feature(env
, ARM_FEATURE_V6
);
85 set_feature(env
, ARM_FEATURE_V6K
);
86 set_feature(env
, ARM_FEATURE_V7
);
87 set_feature(env
, ARM_FEATURE_AUXCR
);
88 set_feature(env
, ARM_FEATURE_THUMB2
);
89 set_feature(env
, ARM_FEATURE_VFP
);
90 set_feature(env
, ARM_FEATURE_VFP3
);
91 set_feature(env
, ARM_FEATURE_NEON
);
92 set_feature(env
, ARM_FEATURE_THUMB2EE
);
93 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
94 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
95 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
96 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
97 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
98 env
->cp15
.c0_cachetype
= 0x82048004;
99 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
100 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
101 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
102 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
104 case ARM_CPUID_CORTEXM3
:
105 set_feature(env
, ARM_FEATURE_V6
);
106 set_feature(env
, ARM_FEATURE_THUMB2
);
107 set_feature(env
, ARM_FEATURE_V7
);
108 set_feature(env
, ARM_FEATURE_M
);
109 set_feature(env
, ARM_FEATURE_DIV
);
111 case ARM_CPUID_ANY
: /* For userspace emulation. */
112 set_feature(env
, ARM_FEATURE_V6
);
113 set_feature(env
, ARM_FEATURE_V6K
);
114 set_feature(env
, ARM_FEATURE_V7
);
115 set_feature(env
, ARM_FEATURE_THUMB2
);
116 set_feature(env
, ARM_FEATURE_VFP
);
117 set_feature(env
, ARM_FEATURE_VFP3
);
118 set_feature(env
, ARM_FEATURE_NEON
);
119 set_feature(env
, ARM_FEATURE_THUMB2EE
);
120 set_feature(env
, ARM_FEATURE_DIV
);
122 case ARM_CPUID_TI915T
:
123 case ARM_CPUID_TI925T
:
124 set_feature(env
, ARM_FEATURE_OMAPCP
);
125 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
126 env
->cp15
.c0_cachetype
= 0x5109149;
127 env
->cp15
.c1_sys
= 0x00000070;
128 env
->cp15
.c15_i_max
= 0x000;
129 env
->cp15
.c15_i_min
= 0xff0;
131 case ARM_CPUID_PXA250
:
132 case ARM_CPUID_PXA255
:
133 case ARM_CPUID_PXA260
:
134 case ARM_CPUID_PXA261
:
135 case ARM_CPUID_PXA262
:
136 set_feature(env
, ARM_FEATURE_XSCALE
);
137 /* JTAG_ID is ((id << 28) | 0x09265013) */
138 env
->cp15
.c0_cachetype
= 0xd172172;
139 env
->cp15
.c1_sys
= 0x00000078;
141 case ARM_CPUID_PXA270_A0
:
142 case ARM_CPUID_PXA270_A1
:
143 case ARM_CPUID_PXA270_B0
:
144 case ARM_CPUID_PXA270_B1
:
145 case ARM_CPUID_PXA270_C0
:
146 case ARM_CPUID_PXA270_C5
:
147 set_feature(env
, ARM_FEATURE_XSCALE
);
148 /* JTAG_ID is ((id << 28) | 0x09265013) */
149 set_feature(env
, ARM_FEATURE_IWMMXT
);
150 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
151 env
->cp15
.c0_cachetype
= 0xd172172;
152 env
->cp15
.c1_sys
= 0x00000078;
155 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
160 void cpu_reset(CPUARMState
*env
)
164 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
165 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
166 log_cpu_state(env
, 0);
169 id
= env
->cp15
.c0_cpuid
;
170 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
172 cpu_reset_model_id(env
, id
);
173 #if defined (CONFIG_USER_ONLY)
174 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
175 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
177 /* SVC mode with interrupts disabled. */
178 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
179 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
182 env
->uncached_cpsr
&= ~CPSR_I
;
183 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
184 env
->cp15
.c2_base_mask
= 0xffffc000u
;
190 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
194 /* VFP data registers are always little-endian. */
195 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
197 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
200 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
201 /* Aliases for Q regs. */
204 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
205 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
209 switch (reg
- nregs
) {
210 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
211 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
212 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
217 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
221 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
223 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
226 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
229 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
230 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
234 switch (reg
- nregs
) {
235 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
236 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
237 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
); return 4;
242 CPUARMState
*cpu_arm_init(const char *cpu_model
)
246 static int inited
= 0;
248 id
= cpu_arm_find_by_name(cpu_model
);
251 env
= qemu_mallocz(sizeof(CPUARMState
));
255 arm_translate_init();
258 env
->cpu_model_str
= cpu_model
;
259 env
->cp15
.c0_cpuid
= id
;
261 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
262 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
263 51, "arm-neon.xml", 0);
264 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
265 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
266 35, "arm-vfp3.xml", 0);
267 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
268 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
269 19, "arm-vfp.xml", 0);
280 static const struct arm_cpu_t arm_cpu_names
[] = {
281 { ARM_CPUID_ARM926
, "arm926"},
282 { ARM_CPUID_ARM946
, "arm946"},
283 { ARM_CPUID_ARM1026
, "arm1026"},
284 { ARM_CPUID_ARM1136
, "arm1136"},
285 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
286 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
287 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
288 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
289 { ARM_CPUID_TI925T
, "ti925t" },
290 { ARM_CPUID_PXA250
, "pxa250" },
291 { ARM_CPUID_PXA255
, "pxa255" },
292 { ARM_CPUID_PXA260
, "pxa260" },
293 { ARM_CPUID_PXA261
, "pxa261" },
294 { ARM_CPUID_PXA262
, "pxa262" },
295 { ARM_CPUID_PXA270
, "pxa270" },
296 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
297 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
298 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
299 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
300 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
301 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
302 { ARM_CPUID_ANY
, "any"},
306 void arm_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
310 (*cpu_fprintf
)(f
, "Available CPUs:\n");
311 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
312 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
316 /* return 0 if not found */
317 static uint32_t cpu_arm_find_by_name(const char *name
)
323 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
324 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
325 id
= arm_cpu_names
[i
].id
;
332 void cpu_arm_close(CPUARMState
*env
)
337 uint32_t cpsr_read(CPUARMState
*env
)
341 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
342 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
343 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
344 | ((env
->condexec_bits
& 0xfc) << 8)
348 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
350 if (mask
& CPSR_NZCV
) {
351 env
->ZF
= (~val
) & CPSR_Z
;
353 env
->CF
= (val
>> 29) & 1;
354 env
->VF
= (val
<< 3) & 0x80000000;
357 env
->QF
= ((val
& CPSR_Q
) != 0);
359 env
->thumb
= ((val
& CPSR_T
) != 0);
360 if (mask
& CPSR_IT_0_1
) {
361 env
->condexec_bits
&= ~3;
362 env
->condexec_bits
|= (val
>> 25) & 3;
364 if (mask
& CPSR_IT_2_7
) {
365 env
->condexec_bits
&= 3;
366 env
->condexec_bits
|= (val
>> 8) & 0xfc;
368 if (mask
& CPSR_GE
) {
369 env
->GE
= (val
>> 16) & 0xf;
372 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
373 switch_mode(env
, val
& CPSR_M
);
375 mask
&= ~CACHED_CPSR_BITS
;
376 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
379 /* Sign/zero extend */
380 uint32_t HELPER(sxtb16
)(uint32_t x
)
383 res
= (uint16_t)(int8_t)x
;
384 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
388 uint32_t HELPER(uxtb16
)(uint32_t x
)
391 res
= (uint16_t)(uint8_t)x
;
392 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
396 uint32_t HELPER(clz
)(uint32_t x
)
401 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
408 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
415 uint32_t HELPER(rbit
)(uint32_t x
)
417 x
= ((x
& 0xff000000) >> 24)
418 | ((x
& 0x00ff0000) >> 8)
419 | ((x
& 0x0000ff00) << 8)
420 | ((x
& 0x000000ff) << 24);
421 x
= ((x
& 0xf0f0f0f0) >> 4)
422 | ((x
& 0x0f0f0f0f) << 4);
423 x
= ((x
& 0x88888888) >> 3)
424 | ((x
& 0x44444444) >> 1)
425 | ((x
& 0x22222222) << 1)
426 | ((x
& 0x11111111) << 3);
430 uint32_t HELPER(abs
)(uint32_t x
)
432 return ((int32_t)x
< 0) ? -x
: x
;
435 #if defined(CONFIG_USER_ONLY)
437 void do_interrupt (CPUState
*env
)
439 env
->exception_index
= -1;
442 /* Structure used to record exclusive memory locations. */
443 typedef struct mmon_state
{
444 struct mmon_state
*next
;
445 CPUARMState
*cpu_env
;
449 /* Chain of current locks. */
450 static mmon_state
* mmon_head
= NULL
;
452 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
453 int mmu_idx
, int is_softmmu
)
456 env
->exception_index
= EXCP_PREFETCH_ABORT
;
457 env
->cp15
.c6_insn
= address
;
459 env
->exception_index
= EXCP_DATA_ABORT
;
460 env
->cp15
.c6_data
= address
;
465 static void allocate_mmon_state(CPUState
*env
)
467 env
->mmon_entry
= malloc(sizeof (mmon_state
));
468 memset (env
->mmon_entry
, 0, sizeof (mmon_state
));
469 env
->mmon_entry
->cpu_env
= env
;
470 mmon_head
= env
->mmon_entry
;
473 /* Flush any monitor locks for the specified address. */
474 static void flush_mmon(uint32_t addr
)
478 for (mon
= mmon_head
; mon
; mon
= mon
->next
)
480 if (mon
->addr
!= addr
)
488 /* Mark an address for exclusive access. */
489 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
491 if (!env
->mmon_entry
)
492 allocate_mmon_state(env
);
493 /* Clear any previous locks. */
495 env
->mmon_entry
->addr
= addr
;
498 /* Test if an exclusive address is still exclusive. Returns zero
499 if the address is still exclusive. */
500 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
504 if (!env
->mmon_entry
)
506 if (env
->mmon_entry
->addr
== addr
)
514 void HELPER(clrex
)(CPUState
*env
)
516 if (!(env
->mmon_entry
&& env
->mmon_entry
->addr
))
518 flush_mmon(env
->mmon_entry
->addr
);
521 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
526 /* These should probably raise undefined insn exceptions. */
527 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
529 int op1
= (insn
>> 8) & 0xf;
530 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
534 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
536 int op1
= (insn
>> 8) & 0xf;
537 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
541 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
543 cpu_abort(env
, "cp15 insn %08x\n", insn
);
546 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
548 cpu_abort(env
, "cp15 insn %08x\n", insn
);
552 /* These should probably raise undefined insn exceptions. */
553 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
555 cpu_abort(env
, "v7m_mrs %d\n", reg
);
558 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
560 cpu_abort(env
, "v7m_mrs %d\n", reg
);
564 void switch_mode(CPUState
*env
, int mode
)
566 if (mode
!= ARM_CPU_MODE_USR
)
567 cpu_abort(env
, "Tried to switch out of user mode\n");
570 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
572 cpu_abort(env
, "banked r13 write\n");
575 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
577 cpu_abort(env
, "banked r13 read\n");
583 extern int semihosting_enabled
;
585 /* Map CPU modes onto saved register banks. */
586 static inline int bank_number (int mode
)
589 case ARM_CPU_MODE_USR
:
590 case ARM_CPU_MODE_SYS
:
592 case ARM_CPU_MODE_SVC
:
594 case ARM_CPU_MODE_ABT
:
596 case ARM_CPU_MODE_UND
:
598 case ARM_CPU_MODE_IRQ
:
600 case ARM_CPU_MODE_FIQ
:
603 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
607 void switch_mode(CPUState
*env
, int mode
)
612 old_mode
= env
->uncached_cpsr
& CPSR_M
;
613 if (mode
== old_mode
)
616 if (old_mode
== ARM_CPU_MODE_FIQ
) {
617 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
618 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
619 } else if (mode
== ARM_CPU_MODE_FIQ
) {
620 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
621 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
624 i
= bank_number(old_mode
);
625 env
->banked_r13
[i
] = env
->regs
[13];
626 env
->banked_r14
[i
] = env
->regs
[14];
627 env
->banked_spsr
[i
] = env
->spsr
;
629 i
= bank_number(mode
);
630 env
->regs
[13] = env
->banked_r13
[i
];
631 env
->regs
[14] = env
->banked_r14
[i
];
632 env
->spsr
= env
->banked_spsr
[i
];
635 static void v7m_push(CPUARMState
*env
, uint32_t val
)
638 stl_phys(env
->regs
[13], val
);
641 static uint32_t v7m_pop(CPUARMState
*env
)
644 val
= ldl_phys(env
->regs
[13]);
649 /* Switch to V7M main or process stack pointer. */
650 static void switch_v7m_sp(CPUARMState
*env
, int process
)
653 if (env
->v7m
.current_sp
!= process
) {
654 tmp
= env
->v7m
.other_sp
;
655 env
->v7m
.other_sp
= env
->regs
[13];
657 env
->v7m
.current_sp
= process
;
661 static void do_v7m_exception_exit(CPUARMState
*env
)
666 type
= env
->regs
[15];
667 if (env
->v7m
.exception
!= 0)
668 armv7m_nvic_complete_irq(env
->v7m
.nvic
, env
->v7m
.exception
);
670 /* Switch to the target stack. */
671 switch_v7m_sp(env
, (type
& 4) != 0);
673 env
->regs
[0] = v7m_pop(env
);
674 env
->regs
[1] = v7m_pop(env
);
675 env
->regs
[2] = v7m_pop(env
);
676 env
->regs
[3] = v7m_pop(env
);
677 env
->regs
[12] = v7m_pop(env
);
678 env
->regs
[14] = v7m_pop(env
);
679 env
->regs
[15] = v7m_pop(env
);
681 xpsr_write(env
, xpsr
, 0xfffffdff);
682 /* Undo stack alignment. */
685 /* ??? The exception return type specifies Thread/Handler mode. However
686 this is also implied by the xPSR value. Not sure what to do
687 if there is a mismatch. */
688 /* ??? Likewise for mismatches between the CONTROL register and the stack
692 static void do_interrupt_v7m(CPUARMState
*env
)
694 uint32_t xpsr
= xpsr_read(env
);
699 if (env
->v7m
.current_sp
)
701 if (env
->v7m
.exception
== 0)
704 /* For exceptions we just mark as pending on the NVIC, and let that
706 /* TODO: Need to escalate if the current priority is higher than the
707 one we're raising. */
708 switch (env
->exception_index
) {
710 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_USAGE
);
714 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_SVC
);
716 case EXCP_PREFETCH_ABORT
:
717 case EXCP_DATA_ABORT
:
718 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_MEM
);
721 if (semihosting_enabled
) {
723 nr
= lduw_code(env
->regs
[15]) & 0xff;
726 env
->regs
[0] = do_arm_semihosting(env
);
730 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_DEBUG
);
733 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->v7m
.nvic
);
735 case EXCP_EXCEPTION_EXIT
:
736 do_v7m_exception_exit(env
);
739 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
740 return; /* Never happens. Keep compiler happy. */
743 /* Align stack pointer. */
744 /* ??? Should only do this if Configuration Control Register
745 STACKALIGN bit is set. */
746 if (env
->regs
[13] & 4) {
750 /* Switch to the handler mode. */
752 v7m_push(env
, env
->regs
[15]);
753 v7m_push(env
, env
->regs
[14]);
754 v7m_push(env
, env
->regs
[12]);
755 v7m_push(env
, env
->regs
[3]);
756 v7m_push(env
, env
->regs
[2]);
757 v7m_push(env
, env
->regs
[1]);
758 v7m_push(env
, env
->regs
[0]);
759 switch_v7m_sp(env
, 0);
760 env
->uncached_cpsr
&= ~CPSR_IT
;
762 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
763 env
->regs
[15] = addr
& 0xfffffffe;
764 env
->thumb
= addr
& 1;
767 /* Handle a CPU exception. */
768 void do_interrupt(CPUARMState
*env
)
776 do_interrupt_v7m(env
);
779 /* TODO: Vectored interrupt controller. */
780 switch (env
->exception_index
) {
782 new_mode
= ARM_CPU_MODE_UND
;
791 if (semihosting_enabled
) {
792 /* Check for semihosting interrupt. */
794 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
796 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
798 /* Only intercept calls from privileged modes, to provide some
799 semblance of security. */
800 if (((mask
== 0x123456 && !env
->thumb
)
801 || (mask
== 0xab && env
->thumb
))
802 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
803 env
->regs
[0] = do_arm_semihosting(env
);
807 new_mode
= ARM_CPU_MODE_SVC
;
810 /* The PC already points to the next instruction. */
814 /* See if this is a semihosting syscall. */
815 if (env
->thumb
&& semihosting_enabled
) {
816 mask
= lduw_code(env
->regs
[15]) & 0xff;
818 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
820 env
->regs
[0] = do_arm_semihosting(env
);
824 /* Fall through to prefetch abort. */
825 case EXCP_PREFETCH_ABORT
:
826 new_mode
= ARM_CPU_MODE_ABT
;
828 mask
= CPSR_A
| CPSR_I
;
831 case EXCP_DATA_ABORT
:
832 new_mode
= ARM_CPU_MODE_ABT
;
834 mask
= CPSR_A
| CPSR_I
;
838 new_mode
= ARM_CPU_MODE_IRQ
;
840 /* Disable IRQ and imprecise data aborts. */
841 mask
= CPSR_A
| CPSR_I
;
845 new_mode
= ARM_CPU_MODE_FIQ
;
847 /* Disable FIQ, IRQ and imprecise data aborts. */
848 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
852 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
853 return; /* Never happens. Keep compiler happy. */
856 if (env
->cp15
.c1_sys
& (1 << 13)) {
859 switch_mode (env
, new_mode
);
860 env
->spsr
= cpsr_read(env
);
862 env
->condexec_bits
= 0;
863 /* Switch to the new mode, and switch to Arm mode. */
864 /* ??? Thumb interrupt handlers not implemented. */
865 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
866 env
->uncached_cpsr
|= mask
;
868 env
->regs
[14] = env
->regs
[15] + offset
;
869 env
->regs
[15] = addr
;
870 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
873 /* Check section/page access permissions.
874 Returns the page protection flags, or zero if the access is not
876 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
882 return PAGE_READ
| PAGE_WRITE
;
884 if (access_type
== 1)
891 if (access_type
== 1)
893 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
895 return is_user
? 0 : PAGE_READ
;
902 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
907 return PAGE_READ
| PAGE_WRITE
;
909 return PAGE_READ
| PAGE_WRITE
;
910 case 4: /* Reserved. */
913 return is_user
? 0 : prot_ro
;
917 if (!arm_feature (env
, ARM_FEATURE_V7
))
925 static uint32_t get_level1_table_address(CPUState
*env
, uint32_t address
)
929 if (address
& env
->cp15
.c2_mask
)
930 table
= env
->cp15
.c2_base1
& 0xffffc000;
932 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
934 table
|= (address
>> 18) & 0x3ffc;
938 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
939 int is_user
, uint32_t *phys_ptr
, int *prot
)
949 /* Pagetable walk. */
950 /* Lookup l1 descriptor. */
951 table
= get_level1_table_address(env
, address
);
952 desc
= ldl_phys(table
);
954 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
956 /* Section translation fault. */
960 if (domain
== 0 || domain
== 2) {
962 code
= 9; /* Section domain fault. */
964 code
= 11; /* Page domain fault. */
969 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
970 ap
= (desc
>> 10) & 3;
973 /* Lookup l2 entry. */
975 /* Coarse pagetable. */
976 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
978 /* Fine pagetable. */
979 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
981 desc
= ldl_phys(table
);
983 case 0: /* Page translation fault. */
986 case 1: /* 64k page. */
987 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
988 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
990 case 2: /* 4k page. */
991 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
992 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
994 case 3: /* 1k page. */
996 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
997 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
999 /* Page translation fault. */
1004 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1006 ap
= (desc
>> 4) & 3;
1009 /* Never happens, but compiler isn't smart enough to tell. */
1014 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1016 /* Access permission fault. */
1019 *phys_ptr
= phys_addr
;
1022 return code
| (domain
<< 4);
1025 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
1026 int is_user
, uint32_t *phys_ptr
, int *prot
)
1037 /* Pagetable walk. */
1038 /* Lookup l1 descriptor. */
1039 table
= get_level1_table_address(env
, address
);
1040 desc
= ldl_phys(table
);
1043 /* Section translation fault. */
1047 } else if (type
== 2 && (desc
& (1 << 18))) {
1051 /* Section or page. */
1052 domain
= (desc
>> 4) & 0x1e;
1054 domain
= (env
->cp15
.c3
>> domain
) & 3;
1055 if (domain
== 0 || domain
== 2) {
1057 code
= 9; /* Section domain fault. */
1059 code
= 11; /* Page domain fault. */
1063 if (desc
& (1 << 18)) {
1065 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1068 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1070 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1071 xn
= desc
& (1 << 4);
1074 /* Lookup l2 entry. */
1075 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1076 desc
= ldl_phys(table
);
1077 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1079 case 0: /* Page translation fault. */
1082 case 1: /* 64k page. */
1083 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1084 xn
= desc
& (1 << 15);
1086 case 2: case 3: /* 4k page. */
1087 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1091 /* Never happens, but compiler isn't smart enough to tell. */
1096 if (xn
&& access_type
== 2)
1099 /* The simplified model uses AP[0] as an access control bit. */
1100 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1101 /* Access flag fault. */
1102 code
= (code
== 15) ? 6 : 3;
1105 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1107 /* Access permission fault. */
1110 *phys_ptr
= phys_addr
;
1113 return code
| (domain
<< 4);
1116 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1117 int is_user
, uint32_t *phys_ptr
, int *prot
)
1123 *phys_ptr
= address
;
1124 for (n
= 7; n
>= 0; n
--) {
1125 base
= env
->cp15
.c6_region
[n
];
1126 if ((base
& 1) == 0)
1128 mask
= 1 << ((base
>> 1) & 0x1f);
1129 /* Keep this shift separate from the above to avoid an
1130 (undefined) << 32. */
1131 mask
= (mask
<< 1) - 1;
1132 if (((base
^ address
) & ~mask
) == 0)
1138 if (access_type
== 2) {
1139 mask
= env
->cp15
.c5_insn
;
1141 mask
= env
->cp15
.c5_data
;
1143 mask
= (mask
>> (n
* 4)) & 0xf;
1150 *prot
= PAGE_READ
| PAGE_WRITE
;
1155 *prot
|= PAGE_WRITE
;
1158 *prot
= PAGE_READ
| PAGE_WRITE
;
1169 /* Bad permission. */
1175 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1176 int access_type
, int is_user
,
1177 uint32_t *phys_ptr
, int *prot
)
1179 /* Fast Context Switch Extension. */
1180 if (address
< 0x02000000)
1181 address
+= env
->cp15
.c13_fcse
;
1183 if ((env
->cp15
.c1_sys
& 1) == 0) {
1184 /* MMU/MPU disabled. */
1185 *phys_ptr
= address
;
1186 *prot
= PAGE_READ
| PAGE_WRITE
;
1188 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1189 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1191 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1192 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1195 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1200 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1201 int access_type
, int mmu_idx
, int is_softmmu
)
1207 is_user
= mmu_idx
== MMU_USER_IDX
;
1208 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
);
1210 /* Map a single [sub]page. */
1211 phys_addr
&= ~(uint32_t)0x3ff;
1212 address
&= ~(uint32_t)0x3ff;
1213 return tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
,
1217 if (access_type
== 2) {
1218 env
->cp15
.c5_insn
= ret
;
1219 env
->cp15
.c6_insn
= address
;
1220 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1222 env
->cp15
.c5_data
= ret
;
1223 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1224 env
->cp15
.c5_data
|= (1 << 11);
1225 env
->cp15
.c6_data
= address
;
1226 env
->exception_index
= EXCP_DATA_ABORT
;
1231 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1237 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
);
1245 /* Not really implemented. Need to figure out a sane way of doing this.
1246 Maybe add generic watchpoint support and use that. */
1248 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
1250 env
->mmon_addr
= addr
;
1253 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
1255 return (env
->mmon_addr
!= addr
);
1258 void HELPER(clrex
)(CPUState
*env
)
1260 env
->mmon_addr
= -1;
1263 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1265 int cp_num
= (insn
>> 8) & 0xf;
1266 int cp_info
= (insn
>> 5) & 7;
1267 int src
= (insn
>> 16) & 0xf;
1268 int operand
= insn
& 0xf;
1270 if (env
->cp
[cp_num
].cp_write
)
1271 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1272 cp_info
, src
, operand
, val
);
1275 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1277 int cp_num
= (insn
>> 8) & 0xf;
1278 int cp_info
= (insn
>> 5) & 7;
1279 int dest
= (insn
>> 16) & 0xf;
1280 int operand
= insn
& 0xf;
1282 if (env
->cp
[cp_num
].cp_read
)
1283 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1284 cp_info
, dest
, operand
);
1288 /* Return basic MPU access permission bits. */
1289 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1296 for (i
= 0; i
< 16; i
+= 2) {
1297 ret
|= (val
>> i
) & mask
;
1303 /* Pad basic MPU access permission bits to extended format. */
1304 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1311 for (i
= 0; i
< 16; i
+= 2) {
1312 ret
|= (val
& mask
) << i
;
1318 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1324 op1
= (insn
>> 21) & 7;
1325 op2
= (insn
>> 5) & 7;
1327 switch ((insn
>> 16) & 0xf) {
1330 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1332 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1334 if (arm_feature(env
, ARM_FEATURE_V7
)
1335 && op1
== 2 && crm
== 0 && op2
== 0) {
1336 env
->cp15
.c0_cssel
= val
& 0xf;
1340 case 1: /* System configuration. */
1341 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1345 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1346 env
->cp15
.c1_sys
= val
;
1347 /* ??? Lots of these bits are not implemented. */
1348 /* This may enable/disable the MMU, so do a TLB flush. */
1351 case 1: /* Auxiliary cotrol register. */
1352 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1353 env
->cp15
.c1_xscaleauxcr
= val
;
1356 /* Not implemented. */
1359 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1361 if (env
->cp15
.c1_coproc
!= val
) {
1362 env
->cp15
.c1_coproc
= val
;
1363 /* ??? Is this safe when called from within a TB? */
1371 case 2: /* MMU Page table control / MPU cache control. */
1372 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1375 env
->cp15
.c2_data
= val
;
1378 env
->cp15
.c2_insn
= val
;
1386 env
->cp15
.c2_base0
= val
;
1389 env
->cp15
.c2_base1
= val
;
1393 env
->cp15
.c2_control
= val
;
1394 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1395 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1402 case 3: /* MMU Domain access control / MPU write buffer control. */
1404 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1406 case 4: /* Reserved. */
1408 case 5: /* MMU Fault status / MPU access permission. */
1409 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1413 if (arm_feature(env
, ARM_FEATURE_MPU
))
1414 val
= extended_mpu_ap_bits(val
);
1415 env
->cp15
.c5_data
= val
;
1418 if (arm_feature(env
, ARM_FEATURE_MPU
))
1419 val
= extended_mpu_ap_bits(val
);
1420 env
->cp15
.c5_insn
= val
;
1423 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1425 env
->cp15
.c5_data
= val
;
1428 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1430 env
->cp15
.c5_insn
= val
;
1436 case 6: /* MMU Fault address / MPU base/size. */
1437 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1440 env
->cp15
.c6_region
[crm
] = val
;
1442 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1446 env
->cp15
.c6_data
= val
;
1448 case 1: /* ??? This is WFAR on armv6 */
1450 env
->cp15
.c6_insn
= val
;
1457 case 7: /* Cache control. */
1458 env
->cp15
.c15_i_max
= 0x000;
1459 env
->cp15
.c15_i_min
= 0xff0;
1460 /* No cache, so nothing to do. */
1461 /* ??? MPCore has VA to PA translation functions. */
1463 case 8: /* MMU TLB control. */
1465 case 0: /* Invalidate all. */
1468 case 1: /* Invalidate single TLB entry. */
1470 /* ??? This is wrong for large pages and sections. */
1471 /* As an ugly hack to make linux work we always flush a 4K
1474 tlb_flush_page(env
, val
);
1475 tlb_flush_page(env
, val
+ 0x400);
1476 tlb_flush_page(env
, val
+ 0x800);
1477 tlb_flush_page(env
, val
+ 0xc00);
1482 case 2: /* Invalidate on ASID. */
1483 tlb_flush(env
, val
== 0);
1485 case 3: /* Invalidate single entry on MVA. */
1486 /* ??? This is like case 1, but ignores ASID. */
1494 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1497 case 0: /* Cache lockdown. */
1499 case 0: /* L1 cache. */
1502 env
->cp15
.c9_data
= val
;
1505 env
->cp15
.c9_insn
= val
;
1511 case 1: /* L2 cache. */
1512 /* Ignore writes to L2 lockdown/auxiliary registers. */
1518 case 1: /* TCM memory region registers. */
1519 /* Not implemented. */
1525 case 10: /* MMU TLB lockdown. */
1526 /* ??? TLB lockdown not implemented. */
1528 case 12: /* Reserved. */
1530 case 13: /* Process ID. */
1533 /* Unlike real hardware the qemu TLB uses virtual addresses,
1534 not modified virtual addresses, so this causes a TLB flush.
1536 if (env
->cp15
.c13_fcse
!= val
)
1538 env
->cp15
.c13_fcse
= val
;
1541 /* This changes the ASID, so do a TLB flush. */
1542 if (env
->cp15
.c13_context
!= val
1543 && !arm_feature(env
, ARM_FEATURE_MPU
))
1545 env
->cp15
.c13_context
= val
;
1548 env
->cp15
.c13_tls1
= val
;
1551 env
->cp15
.c13_tls2
= val
;
1554 env
->cp15
.c13_tls3
= val
;
1560 case 14: /* Reserved. */
1562 case 15: /* Implementation specific. */
1563 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1564 if (op2
== 0 && crm
== 1) {
1565 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1566 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1568 env
->cp15
.c15_cpar
= val
& 0x3fff;
1574 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1578 case 1: /* Set TI925T configuration. */
1579 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1580 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1581 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1583 case 2: /* Set I_max. */
1584 env
->cp15
.c15_i_max
= val
;
1586 case 3: /* Set I_min. */
1587 env
->cp15
.c15_i_min
= val
;
1589 case 4: /* Set thread-ID. */
1590 env
->cp15
.c15_threadid
= val
& 0xffff;
1592 case 8: /* Wait-for-interrupt (deprecated). */
1593 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1603 /* ??? For debugging only. Should raise illegal instruction exception. */
1604 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1605 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1608 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1614 op1
= (insn
>> 21) & 7;
1615 op2
= (insn
>> 5) & 7;
1617 switch ((insn
>> 16) & 0xf) {
1618 case 0: /* ID codes. */
1624 case 0: /* Device ID. */
1625 return env
->cp15
.c0_cpuid
;
1626 case 1: /* Cache Type. */
1627 return env
->cp15
.c0_cachetype
;
1628 case 2: /* TCM status. */
1630 case 3: /* TLB type register. */
1631 return 0; /* No lockable TLB entries. */
1632 case 5: /* CPU ID */
1633 return env
->cpu_index
;
1638 if (!arm_feature(env
, ARM_FEATURE_V6
))
1640 return env
->cp15
.c0_c1
[op2
];
1642 if (!arm_feature(env
, ARM_FEATURE_V6
))
1644 return env
->cp15
.c0_c2
[op2
];
1645 case 3: case 4: case 5: case 6: case 7:
1651 /* These registers aren't documented on arm11 cores. However
1652 Linux looks at them anyway. */
1653 if (!arm_feature(env
, ARM_FEATURE_V6
))
1657 if (!arm_feature(env
, ARM_FEATURE_V7
))
1662 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1664 return env
->cp15
.c0_clid
;
1670 if (op2
!= 0 || crm
!= 0)
1672 return env
->cp15
.c0_cssel
;
1676 case 1: /* System configuration. */
1677 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1680 case 0: /* Control register. */
1681 return env
->cp15
.c1_sys
;
1682 case 1: /* Auxiliary control register. */
1683 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1684 return env
->cp15
.c1_xscaleauxcr
;
1685 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1687 switch (ARM_CPUID(env
)) {
1688 case ARM_CPUID_ARM1026
:
1690 case ARM_CPUID_ARM1136
:
1691 case ARM_CPUID_ARM1136_R2
:
1693 case ARM_CPUID_ARM11MPCORE
:
1695 case ARM_CPUID_CORTEXA8
:
1700 case 2: /* Coprocessor access register. */
1701 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1703 return env
->cp15
.c1_coproc
;
1707 case 2: /* MMU Page table control / MPU cache control. */
1708 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1711 return env
->cp15
.c2_data
;
1714 return env
->cp15
.c2_insn
;
1722 return env
->cp15
.c2_base0
;
1724 return env
->cp15
.c2_base1
;
1726 return env
->cp15
.c2_control
;
1731 case 3: /* MMU Domain access control / MPU write buffer control. */
1732 return env
->cp15
.c3
;
1733 case 4: /* Reserved. */
1735 case 5: /* MMU Fault status / MPU access permission. */
1736 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1740 if (arm_feature(env
, ARM_FEATURE_MPU
))
1741 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1742 return env
->cp15
.c5_data
;
1744 if (arm_feature(env
, ARM_FEATURE_MPU
))
1745 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1746 return env
->cp15
.c5_insn
;
1748 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1750 return env
->cp15
.c5_data
;
1752 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1754 return env
->cp15
.c5_insn
;
1758 case 6: /* MMU Fault address. */
1759 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1762 return env
->cp15
.c6_region
[crm
];
1764 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1768 return env
->cp15
.c6_data
;
1770 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1771 /* Watchpoint Fault Adrress. */
1772 return 0; /* Not implemented. */
1774 /* Instruction Fault Adrress. */
1775 /* Arm9 doesn't have an IFAR, but implementing it anyway
1776 shouldn't do any harm. */
1777 return env
->cp15
.c6_insn
;
1780 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1781 /* Instruction Fault Adrress. */
1782 return env
->cp15
.c6_insn
;
1790 case 7: /* Cache control. */
1791 /* FIXME: Should only clear Z flag if destination is r15. */
1794 case 8: /* MMU TLB control. */
1796 case 9: /* Cache lockdown. */
1798 case 0: /* L1 cache. */
1799 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1803 return env
->cp15
.c9_data
;
1805 return env
->cp15
.c9_insn
;
1809 case 1: /* L2 cache */
1812 /* L2 Lockdown and Auxiliary control. */
1817 case 10: /* MMU TLB lockdown. */
1818 /* ??? TLB lockdown not implemented. */
1820 case 11: /* TCM DMA control. */
1821 case 12: /* Reserved. */
1823 case 13: /* Process ID. */
1826 return env
->cp15
.c13_fcse
;
1828 return env
->cp15
.c13_context
;
1830 return env
->cp15
.c13_tls1
;
1832 return env
->cp15
.c13_tls2
;
1834 return env
->cp15
.c13_tls3
;
1838 case 14: /* Reserved. */
1840 case 15: /* Implementation specific. */
1841 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1842 if (op2
== 0 && crm
== 1)
1843 return env
->cp15
.c15_cpar
;
1847 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1851 case 1: /* Read TI925T configuration. */
1852 return env
->cp15
.c15_ticonfig
;
1853 case 2: /* Read I_max. */
1854 return env
->cp15
.c15_i_max
;
1855 case 3: /* Read I_min. */
1856 return env
->cp15
.c15_i_min
;
1857 case 4: /* Read thread-ID. */
1858 return env
->cp15
.c15_threadid
;
1859 case 8: /* TI925T_status */
1862 /* TODO: Peripheral port remap register:
1863 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1864 * controller base address at $rn & ~0xfff and map size of
1865 * 0x200 << ($rn & 0xfff), when MMU is off. */
1871 /* ??? For debugging only. Should raise illegal instruction exception. */
1872 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1873 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1877 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1879 env
->banked_r13
[bank_number(mode
)] = val
;
1882 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1884 return env
->banked_r13
[bank_number(mode
)];
1887 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
1891 return xpsr_read(env
) & 0xf8000000;
1893 return xpsr_read(env
) & 0xf80001ff;
1895 return xpsr_read(env
) & 0xff00fc00;
1897 return xpsr_read(env
) & 0xff00fdff;
1899 return xpsr_read(env
) & 0x000001ff;
1901 return xpsr_read(env
) & 0x0700fc00;
1903 return xpsr_read(env
) & 0x0700edff;
1905 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1907 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1908 case 16: /* PRIMASK */
1909 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1910 case 17: /* FAULTMASK */
1911 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1912 case 18: /* BASEPRI */
1913 case 19: /* BASEPRI_MAX */
1914 return env
->v7m
.basepri
;
1915 case 20: /* CONTROL */
1916 return env
->v7m
.control
;
1918 /* ??? For debugging only. */
1919 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1924 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
1928 xpsr_write(env
, val
, 0xf8000000);
1931 xpsr_write(env
, val
, 0xf8000000);
1934 xpsr_write(env
, val
, 0xfe00fc00);
1937 xpsr_write(env
, val
, 0xfe00fc00);
1940 /* IPSR bits are readonly. */
1943 xpsr_write(env
, val
, 0x0600fc00);
1946 xpsr_write(env
, val
, 0x0600fc00);
1949 if (env
->v7m
.current_sp
)
1950 env
->v7m
.other_sp
= val
;
1952 env
->regs
[13] = val
;
1955 if (env
->v7m
.current_sp
)
1956 env
->regs
[13] = val
;
1958 env
->v7m
.other_sp
= val
;
1960 case 16: /* PRIMASK */
1962 env
->uncached_cpsr
|= CPSR_I
;
1964 env
->uncached_cpsr
&= ~CPSR_I
;
1966 case 17: /* FAULTMASK */
1968 env
->uncached_cpsr
|= CPSR_F
;
1970 env
->uncached_cpsr
&= ~CPSR_F
;
1972 case 18: /* BASEPRI */
1973 env
->v7m
.basepri
= val
& 0xff;
1975 case 19: /* BASEPRI_MAX */
1977 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1978 env
->v7m
.basepri
= val
;
1980 case 20: /* CONTROL */
1981 env
->v7m
.control
= val
& 3;
1982 switch_v7m_sp(env
, (val
& 2) != 0);
1985 /* ??? For debugging only. */
1986 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1991 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1992 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1995 if (cpnum
< 0 || cpnum
> 14) {
1996 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
2000 env
->cp
[cpnum
].cp_read
= cp_read
;
2001 env
->cp
[cpnum
].cp_write
= cp_write
;
2002 env
->cp
[cpnum
].opaque
= opaque
;
2007 /* Note that signed overflow is undefined in C. The following routines are
2008 careful to use unsigned types where modulo arithmetic is required.
2009 Failure to do so _will_ break on newer gcc. */
2011 /* Signed saturating arithmetic. */
2013 /* Perform 16-bit signed saturating addition. */
2014 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2019 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2028 /* Perform 8-bit signed saturating addition. */
2029 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2034 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2043 /* Perform 16-bit signed saturating subtraction. */
2044 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2049 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2058 /* Perform 8-bit signed saturating subtraction. */
2059 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2064 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2073 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2074 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2075 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2076 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2079 #include "op_addsub.h"
2081 /* Unsigned saturating arithmetic. */
2082 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2091 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2099 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2108 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2116 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2117 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2118 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2119 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2122 #include "op_addsub.h"
2124 /* Signed modulo arithmetic. */
2125 #define SARITH16(a, b, n, op) do { \
2127 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2128 RESULT(sum, n, 16); \
2130 ge |= 3 << (n * 2); \
2133 #define SARITH8(a, b, n, op) do { \
2135 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2136 RESULT(sum, n, 8); \
2142 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2143 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2144 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2145 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2149 #include "op_addsub.h"
2151 /* Unsigned modulo arithmetic. */
2152 #define ADD16(a, b, n) do { \
2154 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2155 RESULT(sum, n, 16); \
2156 if ((sum >> 16) == 1) \
2157 ge |= 3 << (n * 2); \
2160 #define ADD8(a, b, n) do { \
2162 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2163 RESULT(sum, n, 8); \
2164 if ((sum >> 8) == 1) \
2168 #define SUB16(a, b, n) do { \
2170 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2171 RESULT(sum, n, 16); \
2172 if ((sum >> 16) == 0) \
2173 ge |= 3 << (n * 2); \
2176 #define SUB8(a, b, n) do { \
2178 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2179 RESULT(sum, n, 8); \
2180 if ((sum >> 8) == 0) \
2187 #include "op_addsub.h"
2189 /* Halved signed arithmetic. */
2190 #define ADD16(a, b, n) \
2191 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2192 #define SUB16(a, b, n) \
2193 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2194 #define ADD8(a, b, n) \
2195 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2196 #define SUB8(a, b, n) \
2197 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2200 #include "op_addsub.h"
2202 /* Halved unsigned arithmetic. */
2203 #define ADD16(a, b, n) \
2204 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2205 #define SUB16(a, b, n) \
2206 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2207 #define ADD8(a, b, n) \
2208 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2209 #define SUB8(a, b, n) \
2210 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2213 #include "op_addsub.h"
2215 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2223 /* Unsigned sum of absolute byte differences. */
2224 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2227 sum
= do_usad(a
, b
);
2228 sum
+= do_usad(a
>> 8, b
>> 8);
2229 sum
+= do_usad(a
>> 16, b
>>16);
2230 sum
+= do_usad(a
>> 24, b
>> 24);
2234 /* For ARMv6 SEL instruction. */
2235 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2248 return (a
& mask
) | (b
& ~mask
);
2251 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2253 return (val
>> 32) | (val
!= 0);
2256 /* VFP support. We follow the convention used for VFP instrunctions:
2257 Single precition routines have a "s" suffix, double precision a
2260 /* Convert host exception flags to vfp form. */
2261 static inline int vfp_exceptbits_from_host(int host_bits
)
2263 int target_bits
= 0;
2265 if (host_bits
& float_flag_invalid
)
2267 if (host_bits
& float_flag_divbyzero
)
2269 if (host_bits
& float_flag_overflow
)
2271 if (host_bits
& float_flag_underflow
)
2273 if (host_bits
& float_flag_inexact
)
2274 target_bits
|= 0x10;
2278 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2283 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2284 | (env
->vfp
.vec_len
<< 16)
2285 | (env
->vfp
.vec_stride
<< 20);
2286 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2287 fpscr
|= vfp_exceptbits_from_host(i
);
2291 /* Convert vfp exception flags to target form. */
2292 static inline int vfp_exceptbits_to_host(int target_bits
)
2296 if (target_bits
& 1)
2297 host_bits
|= float_flag_invalid
;
2298 if (target_bits
& 2)
2299 host_bits
|= float_flag_divbyzero
;
2300 if (target_bits
& 4)
2301 host_bits
|= float_flag_overflow
;
2302 if (target_bits
& 8)
2303 host_bits
|= float_flag_underflow
;
2304 if (target_bits
& 0x10)
2305 host_bits
|= float_flag_inexact
;
2309 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2314 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2315 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2316 env
->vfp
.vec_len
= (val
>> 16) & 7;
2317 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2320 if (changed
& (3 << 22)) {
2321 i
= (val
>> 22) & 3;
2324 i
= float_round_nearest_even
;
2330 i
= float_round_down
;
2333 i
= float_round_to_zero
;
2336 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2338 if (changed
& (1 << 24))
2339 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2340 if (changed
& (1 << 25))
2341 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2343 i
= vfp_exceptbits_to_host((val
>> 8) & 0x1f);
2344 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2347 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2349 #define VFP_BINOP(name) \
2350 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2352 return float32_ ## name (a, b, &env->vfp.fp_status); \
2354 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2356 return float64_ ## name (a, b, &env->vfp.fp_status); \
2364 float32
VFP_HELPER(neg
, s
)(float32 a
)
2366 return float32_chs(a
);
2369 float64
VFP_HELPER(neg
, d
)(float64 a
)
2371 return float64_chs(a
);
2374 float32
VFP_HELPER(abs
, s
)(float32 a
)
2376 return float32_abs(a
);
2379 float64
VFP_HELPER(abs
, d
)(float64 a
)
2381 return float64_abs(a
);
2384 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2386 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2389 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2391 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2394 /* XXX: check quiet/signaling case */
2395 #define DO_VFP_cmp(p, type) \
2396 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2399 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2400 case 0: flags = 0x6; break; \
2401 case -1: flags = 0x8; break; \
2402 case 1: flags = 0x2; break; \
2403 default: case 2: flags = 0x3; break; \
2405 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2406 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2408 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2411 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2412 case 0: flags = 0x6; break; \
2413 case -1: flags = 0x8; break; \
2414 case 1: flags = 0x2; break; \
2415 default: case 2: flags = 0x3; break; \
2417 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2418 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2420 DO_VFP_cmp(s
, float32
)
2421 DO_VFP_cmp(d
, float64
)
2424 /* Helper routines to perform bitwise copies between float and int. */
2425 static inline float32
vfp_itos(uint32_t i
)
2436 static inline uint32_t vfp_stoi(float32 s
)
2447 static inline float64
vfp_itod(uint64_t i
)
2458 static inline uint64_t vfp_dtoi(float64 d
)
2469 /* Integer to float conversion. */
2470 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2472 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2475 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2477 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2480 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2482 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2485 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2487 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2490 /* Float to integer conversion. */
2491 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2493 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2496 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2498 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2501 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2503 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2506 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2508 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2511 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2513 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2516 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2518 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2521 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2523 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2526 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2528 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2531 /* floating point conversion */
2532 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2534 return float32_to_float64(x
, &env
->vfp
.fp_status
);
2537 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2539 return float64_to_float32(x
, &env
->vfp
.fp_status
);
2542 /* VFP3 fixed point conversion. */
2543 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2544 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2547 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2548 &env->vfp.fp_status); \
2549 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2551 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2554 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2555 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2556 &env->vfp.fp_status)); \
2559 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2560 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2561 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2562 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2563 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2564 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2565 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2566 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2569 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2571 float_status
*s
= &env
->vfp
.fp_status
;
2572 float32 two
= int32_to_float32(2, s
);
2573 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2576 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2578 float_status
*s
= &env
->vfp
.fp_status
;
2579 float32 three
= int32_to_float32(3, s
);
2580 return float32_sub(three
, float32_mul(a
, b
, s
), s
);
2585 /* TODO: The architecture specifies the value that the estimate functions
2586 should return. We return the exact reciprocal/root instead. */
2587 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2589 float_status
*s
= &env
->vfp
.fp_status
;
2590 float32 one
= int32_to_float32(1, s
);
2591 return float32_div(one
, a
, s
);
2594 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2596 float_status
*s
= &env
->vfp
.fp_status
;
2597 float32 one
= int32_to_float32(1, s
);
2598 return float32_div(one
, float32_sqrt(a
, s
), s
);
2601 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2603 float_status
*s
= &env
->vfp
.fp_status
;
2605 tmp
= int32_to_float32(a
, s
);
2606 tmp
= float32_scalbn(tmp
, -32, s
);
2607 tmp
= helper_recpe_f32(tmp
, env
);
2608 tmp
= float32_scalbn(tmp
, 31, s
);
2609 return float32_to_int32(tmp
, s
);
2612 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2614 float_status
*s
= &env
->vfp
.fp_status
;
2616 tmp
= int32_to_float32(a
, s
);
2617 tmp
= float32_scalbn(tmp
, -32, s
);
2618 tmp
= helper_rsqrte_f32(tmp
, env
);
2619 tmp
= float32_scalbn(tmp
, 31, s
);
2620 return float32_to_int32(tmp
, s
);
2623 void HELPER(set_teecr
)(CPUState
*env
, uint32_t val
)
2626 if (env
->teecr
!= val
) {