2 #include "exec/gdbstub.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/sysemu.h"
6 #include "qemu/bitops.h"
8 #ifndef CONFIG_USER_ONLY
9 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
10 int access_type
, int is_user
,
11 hwaddr
*phys_ptr
, int *prot
,
12 target_ulong
*page_size
);
15 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
19 /* VFP data registers are always little-endian. */
20 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
22 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
25 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
26 /* Aliases for Q regs. */
29 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
30 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
34 switch (reg
- nregs
) {
35 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
36 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
37 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
42 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
46 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
48 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
51 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
54 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
55 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
59 switch (reg
- nregs
) {
60 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
61 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
62 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
67 static int raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
70 *value
= CPREG_FIELD32(env
, ri
);
74 static int raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
77 CPREG_FIELD32(env
, ri
) = value
;
81 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
84 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
88 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
90 if (env
->cp15
.c13_fcse
!= value
) {
91 /* Unlike real hardware the qemu TLB uses virtual addresses,
92 * not modified virtual addresses, so this causes a TLB flush.
95 env
->cp15
.c13_fcse
= value
;
99 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
102 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
103 /* For VMSA (when not using the LPAE long descriptor page table
104 * format) this register includes the ASID, so do a TLB flush.
105 * For PMSA it is purely a process ID and no action is needed.
109 env
->cp15
.c13_context
= value
;
113 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
116 /* Invalidate all (TLBIALL) */
121 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
124 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
125 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
129 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
132 /* Invalidate by ASID (TLBIASID) */
133 tlb_flush(env
, value
== 0);
137 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
140 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
141 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
145 static const ARMCPRegInfo cp_reginfo
[] = {
146 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
147 * version" bits will read as a reserved value, which should cause
148 * Linux to not try to use the debug hardware.
150 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
151 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
152 /* MMU Domain access control / MPU write buffer control */
153 { .name
= "DACR", .cp
= 15,
154 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
155 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
156 .resetvalue
= 0, .writefn
= dacr_write
, .raw_writefn
= raw_write
, },
157 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
158 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
159 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
160 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
161 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
162 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
163 /* ??? This covers not just the impdef TLB lockdown registers but also
164 * some v7VMSA registers relating to TEX remap, so it is overly broad.
166 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
167 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
168 /* MMU TLB control. Note that the wildcarding means we cover not just
169 * the unified TLB ops but also the dside/iside/inner-shareable variants.
171 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
172 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
173 .type
= ARM_CP_NO_MIGRATE
},
174 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
175 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
176 .type
= ARM_CP_NO_MIGRATE
},
177 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
178 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
179 .type
= ARM_CP_NO_MIGRATE
},
180 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
181 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
182 .type
= ARM_CP_NO_MIGRATE
},
183 /* Cache maintenance ops; some of this space may be overridden later. */
184 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
185 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
186 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
190 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
191 /* Not all pre-v6 cores implemented this WFI, so this is slightly
194 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
195 .access
= PL1_W
, .type
= ARM_CP_WFI
},
199 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
200 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
201 * is UNPREDICTABLE; we choose to NOP as most implementations do).
203 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
204 .access
= PL1_W
, .type
= ARM_CP_WFI
},
205 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
206 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
207 * OMAPCP will override this space.
209 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
210 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
212 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
213 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
215 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
216 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
217 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
222 static int cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
224 if (env
->cp15
.c1_coproc
!= value
) {
225 env
->cp15
.c1_coproc
= value
;
226 /* ??? Is this safe when called from within a TB? */
232 static const ARMCPRegInfo v6_cp_reginfo
[] = {
233 /* prefetch by MVA in v6, NOP in v7 */
234 { .name
= "MVA_prefetch",
235 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
236 .access
= PL1_W
, .type
= ARM_CP_NOP
},
237 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
238 .access
= PL0_W
, .type
= ARM_CP_NOP
},
239 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
240 .access
= PL0_W
, .type
= ARM_CP_NOP
},
241 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
242 .access
= PL0_W
, .type
= ARM_CP_NOP
},
243 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
244 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
246 /* Watchpoint Fault Address Register : should actually only be present
247 * for 1136, 1176, 11MPCore.
249 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
250 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
251 { .name
= "CPACR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
252 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
253 .resetvalue
= 0, .writefn
= cpacr_write
},
258 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
261 /* Generic performance monitor register read function for where
262 * user access may be allowed by PMUSERENR.
264 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
267 *value
= CPREG_FIELD32(env
, ri
);
271 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
274 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
277 /* only the DP, X, D and E bits are writable */
278 env
->cp15
.c9_pmcr
&= ~0x39;
279 env
->cp15
.c9_pmcr
|= (value
& 0x39);
283 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
286 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
290 env
->cp15
.c9_pmcnten
|= value
;
294 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
297 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
301 env
->cp15
.c9_pmcnten
&= ~value
;
305 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
308 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
311 env
->cp15
.c9_pmovsr
&= ~value
;
315 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
318 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
321 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
325 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
328 env
->cp15
.c9_pmuserenr
= value
& 1;
332 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
335 /* We have no event counters so only the C bit can be changed */
337 env
->cp15
.c9_pminten
|= value
;
341 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
345 env
->cp15
.c9_pminten
&= ~value
;
349 static int ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
352 ARMCPU
*cpu
= arm_env_get_cpu(env
);
353 *value
= cpu
->ccsidr
[env
->cp15
.c0_cssel
];
357 static int csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
360 env
->cp15
.c0_cssel
= value
& 0xf;
364 static const ARMCPRegInfo v7_cp_reginfo
[] = {
365 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
368 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
369 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
370 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
371 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
372 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
373 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
374 .access
= PL1_W
, .type
= ARM_CP_NOP
},
375 /* Performance monitors are implementation defined in v7,
376 * but with an ARM recommended set of registers, which we
377 * follow (although we don't actually implement any counters)
379 * Performance registers fall into three categories:
380 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
381 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
382 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
383 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
384 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
386 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
387 .access
= PL0_RW
, .resetvalue
= 0,
388 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
389 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
,
390 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
391 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
392 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
393 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
,
394 .type
= ARM_CP_NO_MIGRATE
},
395 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
396 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
397 .readfn
= pmreg_read
, .writefn
= pmovsr_write
,
398 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
399 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
402 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
403 .access
= PL0_W
, .type
= ARM_CP_NOP
},
404 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
405 * We choose to RAZ/WI. XXX should respect PMUSERENR.
407 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
408 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
409 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
410 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
411 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
412 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
414 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
415 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
,
416 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
417 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
418 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
419 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
420 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
421 .access
= PL0_R
| PL1_RW
,
422 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
424 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
425 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
427 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
429 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
430 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
431 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
432 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
433 .resetvalue
= 0, .writefn
= pmintenclr_write
, },
434 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
435 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
437 { .name
= "CCSIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
438 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_MIGRATE
},
439 { .name
= "CSSELR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
440 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
441 .writefn
= csselr_write
, .resetvalue
= 0 },
442 /* Auxiliary ID register: this actually has an IMPDEF value but for now
443 * just RAZ for all cores:
445 { .name
= "AIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 7,
446 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
450 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
457 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
460 /* This is a helper function because the user access rights
461 * depend on the value of the TEECR.
463 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
466 *value
= env
->teehbr
;
470 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
473 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
480 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
481 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
482 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
484 .writefn
= teecr_write
},
485 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
486 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
487 .resetvalue
= 0, .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
488 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
492 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
493 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
495 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
497 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
498 .access
= PL0_R
|PL1_W
,
499 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
501 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
503 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
508 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
509 /* Dummy implementation: RAZ/WI the whole crn=14 space */
510 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
511 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
512 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
517 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
519 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
520 env
->cp15
.c7_par
= value
;
521 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
522 env
->cp15
.c7_par
= value
& 0xfffff6ff;
524 env
->cp15
.c7_par
= value
& 0xfffff1ff;
529 #ifndef CONFIG_USER_ONLY
530 /* get_phys_addr() isn't present for user-mode-only targets */
532 /* Return true if extended addresses are enabled, ie this is an
533 * LPAE implementation and we are using the long-descriptor translation
534 * table format because the TTBCR EAE bit is set.
536 static inline bool extended_addresses_enabled(CPUARMState
*env
)
538 return arm_feature(env
, ARM_FEATURE_LPAE
)
539 && (env
->cp15
.c2_control
& (1 << 31));
542 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
545 target_ulong page_size
;
547 int ret
, is_user
= ri
->opc2
& 2;
548 int access_type
= ri
->opc2
& 1;
551 /* Other states are only available with TrustZone */
554 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
555 &phys_addr
, &prot
, &page_size
);
556 if (extended_addresses_enabled(env
)) {
557 /* ret is a DFSR/IFSR value for the long descriptor
558 * translation table format, but with WnR always clear.
559 * Convert it to a 64-bit PAR.
561 uint64_t par64
= (1 << 11); /* LPAE bit always set */
563 par64
|= phys_addr
& ~0xfffULL
;
564 /* We don't set the ATTR or SH fields in the PAR. */
567 par64
|= (ret
& 0x3f) << 1; /* FS */
568 /* Note that S2WLK and FSTAGE are always zero, because we don't
569 * implement virtualization and therefore there can't be a stage 2
573 env
->cp15
.c7_par
= par64
;
574 env
->cp15
.c7_par_hi
= par64
>> 32;
576 /* ret is a DFSR/IFSR value for the short descriptor
577 * translation table format (with WnR always clear).
578 * Convert it to a 32-bit PAR.
581 /* We do not set any attribute bits in the PAR */
582 if (page_size
== (1 << 24)
583 && arm_feature(env
, ARM_FEATURE_V7
)) {
584 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
586 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
589 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
590 ((ret
& (12 << 1)) >> 6) |
591 ((ret
& 0xf) << 1) | 1;
593 env
->cp15
.c7_par_hi
= 0;
599 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
600 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
601 .access
= PL1_RW
, .resetvalue
= 0,
602 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
603 .writefn
= par_write
},
604 #ifndef CONFIG_USER_ONLY
605 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
606 .access
= PL1_W
, .writefn
= ats_write
, .type
= ARM_CP_NO_MIGRATE
},
611 /* Return basic MPU access permission bits. */
612 static uint32_t simple_mpu_ap_bits(uint32_t val
)
619 for (i
= 0; i
< 16; i
+= 2) {
620 ret
|= (val
>> i
) & mask
;
626 /* Pad basic MPU access permission bits to extended format. */
627 static uint32_t extended_mpu_ap_bits(uint32_t val
)
634 for (i
= 0; i
< 16; i
+= 2) {
635 ret
|= (val
& mask
) << i
;
641 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
644 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
648 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
651 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
655 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
658 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
662 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
665 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
669 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
675 *value
= env
->cp15
.c6_region
[ri
->crm
];
679 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
685 env
->cp15
.c6_region
[ri
->crm
] = value
;
689 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
690 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
691 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
692 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
693 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
694 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
695 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
696 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
697 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
698 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
700 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
701 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
703 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
704 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
706 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
707 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
709 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
710 /* Protection region base and size registers */
711 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
712 .opc2
= CP_ANY
, .access
= PL1_RW
,
713 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
717 static int vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
720 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
721 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
725 /* Note that we always calculate c2_mask and c2_base_mask, but
726 * they are only used for short-descriptor tables (ie if EAE is 0);
727 * for long-descriptor tables the TTBCR fields are used differently
728 * and the c2_mask and c2_base_mask values are meaningless.
730 env
->cp15
.c2_control
= value
;
731 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
732 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
736 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
739 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
740 /* With LPAE the TTBCR could result in a change of ASID
741 * via the TTBCR.A1 bit, so do a TLB flush.
745 return vmsa_ttbcr_raw_write(env
, ri
, value
);
748 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
750 env
->cp15
.c2_base_mask
= 0xffffc000u
;
751 env
->cp15
.c2_control
= 0;
752 env
->cp15
.c2_mask
= 0;
755 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
756 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
758 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
759 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
761 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
762 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
764 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
765 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
767 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base1
), .resetvalue
= 0, },
768 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
769 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
770 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
771 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
772 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
773 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
778 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
781 env
->cp15
.c15_ticonfig
= value
& 0xe7;
782 /* The OS_TYPE bit in this register changes the reported CPUID! */
783 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
784 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
788 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
791 env
->cp15
.c15_threadid
= value
& 0xffff;
795 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
798 /* Wait-for-interrupt (deprecated) */
799 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
803 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
806 /* On OMAP there are registers indicating the max/min index of dcache lines
807 * containing a dirty line; cache flush operations have to reset these.
809 env
->cp15
.c15_i_max
= 0x000;
810 env
->cp15
.c15_i_min
= 0xff0;
814 static const ARMCPRegInfo omap_cp_reginfo
[] = {
815 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
816 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
817 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
818 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
819 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
820 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
822 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
823 .writefn
= omap_ticonfig_write
},
824 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
826 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
827 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
828 .access
= PL1_RW
, .resetvalue
= 0xff0,
829 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
830 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
832 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
833 .writefn
= omap_threadid_write
},
834 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
835 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
836 .type
= ARM_CP_NO_MIGRATE
,
837 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
838 /* TODO: Peripheral port remap register:
839 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
840 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
843 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
844 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
845 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
,
846 .writefn
= omap_cachemaint_write
},
847 { .name
= "C9", .cp
= 15, .crn
= 9,
848 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
849 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
853 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
857 if (env
->cp15
.c15_cpar
!= value
) {
858 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
860 env
->cp15
.c15_cpar
= value
;
865 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
866 { .name
= "XSCALE_CPAR",
867 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
868 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
869 .writefn
= xscale_cpar_write
, },
870 { .name
= "XSCALE_AUXCR",
871 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
872 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
877 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
878 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
879 * implementation of this implementation-defined space.
880 * Ideally this should eventually disappear in favour of actually
881 * implementing the correct behaviour for all cores.
883 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
884 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
885 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
890 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
891 /* Cache status: RAZ because we have no cache so it's always clean */
892 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
893 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
898 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
899 /* We never have a a block transfer operation in progress */
900 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
901 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
903 /* The cache ops themselves: these all NOP for QEMU */
904 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
905 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
906 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
907 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
908 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
909 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
910 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
911 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
912 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
913 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
914 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
915 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
919 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
920 /* The cache test-and-clean instructions always return (1 << 30)
921 * to indicate that there are no dirty cache lines.
923 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
924 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
925 .resetvalue
= (1 << 30) },
926 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
927 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
928 .resetvalue
= (1 << 30) },
932 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
933 /* Ignore ReadBuffer accesses */
934 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
935 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
936 .access
= PL1_RW
, .resetvalue
= 0,
937 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
},
941 static int mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
944 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
945 uint32_t mpidr
= cs
->cpu_index
;
946 /* We don't support setting cluster ID ([8..11])
947 * so these bits always RAZ.
949 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
951 /* Cores which are uniprocessor (non-coherent)
952 * but still implement the MP extensions set
953 * bit 30. (For instance, A9UP.) However we do
954 * not currently model any of those cores.
961 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
962 { .name
= "MPIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
963 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_MIGRATE
},
967 static int par64_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
969 *value
= ((uint64_t)env
->cp15
.c7_par_hi
<< 32) | env
->cp15
.c7_par
;
973 static int par64_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
975 env
->cp15
.c7_par_hi
= value
>> 32;
976 env
->cp15
.c7_par
= value
;
980 static void par64_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
982 env
->cp15
.c7_par_hi
= 0;
983 env
->cp15
.c7_par
= 0;
986 static int ttbr064_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
989 *value
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
993 static int ttbr064_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
996 env
->cp15
.c2_base0_hi
= value
>> 32;
997 env
->cp15
.c2_base0
= value
;
1001 static int ttbr064_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1004 /* Writes to the 64 bit format TTBRs may change the ASID */
1006 return ttbr064_raw_write(env
, ri
, value
);
1009 static void ttbr064_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1011 env
->cp15
.c2_base0_hi
= 0;
1012 env
->cp15
.c2_base0
= 0;
1015 static int ttbr164_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1018 *value
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
1022 static int ttbr164_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1025 env
->cp15
.c2_base1_hi
= value
>> 32;
1026 env
->cp15
.c2_base1
= value
;
1030 static void ttbr164_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1032 env
->cp15
.c2_base1_hi
= 0;
1033 env
->cp15
.c2_base1
= 0;
1036 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
1037 /* NOP AMAIR0/1: the override is because these clash with the rather
1038 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1040 { .name
= "AMAIR0", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
1041 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1043 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
1044 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1046 /* 64 bit access versions of the (dummy) debug registers */
1047 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
1048 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1049 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
1050 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1051 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
1052 .access
= PL1_RW
, .type
= ARM_CP_64BIT
,
1053 .readfn
= par64_read
, .writefn
= par64_write
, .resetfn
= par64_reset
},
1054 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
1055 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr064_read
,
1056 .writefn
= ttbr064_write
, .raw_writefn
= ttbr064_raw_write
,
1057 .resetfn
= ttbr064_reset
},
1058 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
1059 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr164_read
,
1060 .writefn
= ttbr164_write
, .resetfn
= ttbr164_reset
},
1064 static int sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1066 env
->cp15
.c1_sys
= value
;
1067 /* ??? Lots of these bits are not implemented. */
1068 /* This may enable/disable the MMU, so do a TLB flush. */
1073 void register_cp_regs_for_features(ARMCPU
*cpu
)
1075 /* Register all the coprocessor registers based on feature bits */
1076 CPUARMState
*env
= &cpu
->env
;
1077 if (arm_feature(env
, ARM_FEATURE_M
)) {
1078 /* M profile has no coprocessor registers */
1082 define_arm_cp_regs(cpu
, cp_reginfo
);
1083 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1084 /* The ID registers all have impdef reset values */
1085 ARMCPRegInfo v6_idregs
[] = {
1086 { .name
= "ID_PFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1087 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1088 .resetvalue
= cpu
->id_pfr0
},
1089 { .name
= "ID_PFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1090 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1091 .resetvalue
= cpu
->id_pfr1
},
1092 { .name
= "ID_DFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1093 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1094 .resetvalue
= cpu
->id_dfr0
},
1095 { .name
= "ID_AFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1096 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1097 .resetvalue
= cpu
->id_afr0
},
1098 { .name
= "ID_MMFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1099 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1100 .resetvalue
= cpu
->id_mmfr0
},
1101 { .name
= "ID_MMFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1102 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1103 .resetvalue
= cpu
->id_mmfr1
},
1104 { .name
= "ID_MMFR2", .cp
= 15, .crn
= 0, .crm
= 1,
1105 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1106 .resetvalue
= cpu
->id_mmfr2
},
1107 { .name
= "ID_MMFR3", .cp
= 15, .crn
= 0, .crm
= 1,
1108 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1109 .resetvalue
= cpu
->id_mmfr3
},
1110 { .name
= "ID_ISAR0", .cp
= 15, .crn
= 0, .crm
= 2,
1111 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1112 .resetvalue
= cpu
->id_isar0
},
1113 { .name
= "ID_ISAR1", .cp
= 15, .crn
= 0, .crm
= 2,
1114 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1115 .resetvalue
= cpu
->id_isar1
},
1116 { .name
= "ID_ISAR2", .cp
= 15, .crn
= 0, .crm
= 2,
1117 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1118 .resetvalue
= cpu
->id_isar2
},
1119 { .name
= "ID_ISAR3", .cp
= 15, .crn
= 0, .crm
= 2,
1120 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1121 .resetvalue
= cpu
->id_isar3
},
1122 { .name
= "ID_ISAR4", .cp
= 15, .crn
= 0, .crm
= 2,
1123 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1124 .resetvalue
= cpu
->id_isar4
},
1125 { .name
= "ID_ISAR5", .cp
= 15, .crn
= 0, .crm
= 2,
1126 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1127 .resetvalue
= cpu
->id_isar5
},
1128 /* 6..7 are as yet unallocated and must RAZ */
1129 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
1130 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1132 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
1133 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1137 define_arm_cp_regs(cpu
, v6_idregs
);
1138 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
1140 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
1142 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1143 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
1145 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1146 /* v7 performance monitor control register: same implementor
1147 * field as main ID register, and we implement no event counters.
1149 ARMCPRegInfo pmcr
= {
1150 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
1151 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
1152 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
1153 .readfn
= pmreg_read
, .writefn
= pmcr_write
,
1154 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
1156 ARMCPRegInfo clidr
= {
1157 .name
= "CLIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
1158 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
1160 define_one_arm_cp_reg(cpu
, &pmcr
);
1161 define_one_arm_cp_reg(cpu
, &clidr
);
1162 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
1164 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
1166 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1167 /* These are the MPU registers prior to PMSAv6. Any new
1168 * PMSA core later than the ARM946 will require that we
1169 * implement the PMSAv6 or PMSAv7 registers, which are
1170 * completely different.
1172 assert(!arm_feature(env
, ARM_FEATURE_V6
));
1173 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
1175 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
1177 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
1178 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
1180 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1181 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
1183 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1184 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
1186 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
1187 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
1189 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
1190 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
1192 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
1193 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
1195 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1196 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
1198 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1199 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
1201 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1202 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
1204 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
1205 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
1207 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
1208 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
1210 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1211 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
1213 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1214 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1215 * be read-only (ie write causes UNDEF exception).
1218 ARMCPRegInfo id_cp_reginfo
[] = {
1219 /* Note that the MIDR isn't a simple constant register because
1220 * of the TI925 behaviour where writes to another register can
1221 * cause the MIDR value to change.
1224 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
1225 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
1226 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
1227 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
) },
1229 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
1230 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
1232 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
1233 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1235 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
1236 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1237 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1239 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
1240 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1242 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
1243 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1245 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
1246 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1248 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
1249 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1251 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
1252 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1255 ARMCPRegInfo crn0_wi_reginfo
= {
1256 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
1257 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
1258 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
1260 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
1261 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1263 /* Register the blanket "writes ignored" value first to cover the
1264 * whole space. Then define the specific ID registers, but update
1265 * their access field to allow write access, so that they ignore
1266 * writes rather than causing them to UNDEF.
1268 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
1269 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1271 define_one_arm_cp_reg(cpu
, r
);
1274 /* Just register the standard ID registers (read-only, meaning
1275 * that writes will UNDEF).
1277 define_arm_cp_regs(cpu
, id_cp_reginfo
);
1281 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
1282 ARMCPRegInfo auxcr
= {
1283 .name
= "AUXCR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1,
1284 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
1285 .resetvalue
= cpu
->reset_auxcr
1287 define_one_arm_cp_reg(cpu
, &auxcr
);
1290 /* Generic registers whose values depend on the implementation */
1292 ARMCPRegInfo sctlr
= {
1293 .name
= "SCTLR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
1294 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
1295 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
1296 .raw_writefn
= raw_write
,
1298 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1299 /* Normally we would always end the TB on an SCTLR write, but Linux
1300 * arch/arm/mach-pxa/sleep.S expects two instructions following
1301 * an MMU enable to execute from cache. Imitate this behaviour.
1303 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
1305 define_one_arm_cp_reg(cpu
, &sctlr
);
1309 ARMCPU
*cpu_arm_init(const char *cpu_model
)
1315 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
1319 cpu
= ARM_CPU(object_new(object_class_get_name(oc
)));
1321 env
->cpu_model_str
= cpu_model
;
1323 /* TODO this should be set centrally, once possible */
1324 object_property_set_bool(OBJECT(cpu
), true, "realized", NULL
);
1329 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
1331 CPUARMState
*env
= &cpu
->env
;
1333 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
1334 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1335 51, "arm-neon.xml", 0);
1336 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1337 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1338 35, "arm-vfp3.xml", 0);
1339 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1340 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1341 19, "arm-vfp.xml", 0);
1345 /* Sort alphabetically by type name, except for "any". */
1346 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1348 ObjectClass
*class_a
= (ObjectClass
*)a
;
1349 ObjectClass
*class_b
= (ObjectClass
*)b
;
1350 const char *name_a
, *name_b
;
1352 name_a
= object_class_get_name(class_a
);
1353 name_b
= object_class_get_name(class_b
);
1354 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
1356 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
1359 return strcmp(name_a
, name_b
);
1363 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
1365 ObjectClass
*oc
= data
;
1366 CPUListState
*s
= user_data
;
1367 const char *typename
;
1370 typename
= object_class_get_name(oc
);
1371 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
1372 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
1377 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1381 .cpu_fprintf
= cpu_fprintf
,
1385 list
= object_class_get_list(TYPE_ARM_CPU
, false);
1386 list
= g_slist_sort(list
, arm_cpu_list_compare
);
1387 (*cpu_fprintf
)(f
, "Available CPUs:\n");
1388 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
1392 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1393 const ARMCPRegInfo
*r
, void *opaque
)
1395 /* Define implementations of coprocessor registers.
1396 * We store these in a hashtable because typically
1397 * there are less than 150 registers in a space which
1398 * is 16*16*16*8*8 = 262144 in size.
1399 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1400 * If a register is defined twice then the second definition is
1401 * used, so this can be used to define some generic registers and
1402 * then override them with implementation specific variations.
1403 * At least one of the original and the second definition should
1404 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1405 * against accidental use.
1407 int crm
, opc1
, opc2
;
1408 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
1409 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
1410 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
1411 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
1412 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
1413 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
1414 /* 64 bit registers have only CRm and Opc1 fields */
1415 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
1416 /* Check that the register definition has enough info to handle
1417 * reads and writes if they are permitted.
1419 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
1420 if (r
->access
& PL3_R
) {
1421 assert(r
->fieldoffset
|| r
->readfn
);
1423 if (r
->access
& PL3_W
) {
1424 assert(r
->fieldoffset
|| r
->writefn
);
1427 /* Bad type field probably means missing sentinel at end of reg list */
1428 assert(cptype_valid(r
->type
));
1429 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
1430 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
1431 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
1432 uint32_t *key
= g_new(uint32_t, 1);
1433 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
1434 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
1435 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
1436 r2
->opaque
= opaque
;
1437 /* Make sure reginfo passed to helpers for wildcarded regs
1438 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1443 /* By convention, for wildcarded registers only the first
1444 * entry is used for migration; the others are marked as
1445 * NO_MIGRATE so we don't try to transfer the register
1446 * multiple times. Special registers (ie NOP/WFI) are
1449 if ((r
->type
& ARM_CP_SPECIAL
) ||
1450 ((r
->crm
== CP_ANY
) && crm
!= 0) ||
1451 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
1452 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
1453 r2
->type
|= ARM_CP_NO_MIGRATE
;
1456 /* Overriding of an existing definition must be explicitly
1459 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
1460 ARMCPRegInfo
*oldreg
;
1461 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
1462 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
1463 fprintf(stderr
, "Register redefined: cp=%d %d bit "
1464 "crn=%d crm=%d opc1=%d opc2=%d, "
1465 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
1466 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
1467 oldreg
->name
, r2
->name
);
1471 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
1477 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1478 const ARMCPRegInfo
*regs
, void *opaque
)
1480 /* Define a whole list of registers */
1481 const ARMCPRegInfo
*r
;
1482 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1483 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1487 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1489 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1492 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1495 /* Helper coprocessor write function for write-ignore registers */
1499 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1501 /* Helper coprocessor write function for read-as-zero registers */
1506 static int bad_mode_switch(CPUARMState
*env
, int mode
)
1508 /* Return true if it is not valid for us to switch to
1509 * this CPU mode (ie all the UNPREDICTABLE cases in
1510 * the ARM ARM CPSRWriteByInstr pseudocode).
1513 case ARM_CPU_MODE_USR
:
1514 case ARM_CPU_MODE_SYS
:
1515 case ARM_CPU_MODE_SVC
:
1516 case ARM_CPU_MODE_ABT
:
1517 case ARM_CPU_MODE_UND
:
1518 case ARM_CPU_MODE_IRQ
:
1519 case ARM_CPU_MODE_FIQ
:
1526 uint32_t cpsr_read(CPUARMState
*env
)
1529 ZF
= (env
->ZF
== 0);
1530 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
1531 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1532 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
1533 | ((env
->condexec_bits
& 0xfc) << 8)
1537 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1539 if (mask
& CPSR_NZCV
) {
1540 env
->ZF
= (~val
) & CPSR_Z
;
1542 env
->CF
= (val
>> 29) & 1;
1543 env
->VF
= (val
<< 3) & 0x80000000;
1546 env
->QF
= ((val
& CPSR_Q
) != 0);
1548 env
->thumb
= ((val
& CPSR_T
) != 0);
1549 if (mask
& CPSR_IT_0_1
) {
1550 env
->condexec_bits
&= ~3;
1551 env
->condexec_bits
|= (val
>> 25) & 3;
1553 if (mask
& CPSR_IT_2_7
) {
1554 env
->condexec_bits
&= 3;
1555 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1557 if (mask
& CPSR_GE
) {
1558 env
->GE
= (val
>> 16) & 0xf;
1561 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
1562 if (bad_mode_switch(env
, val
& CPSR_M
)) {
1563 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1564 * We choose to ignore the attempt and leave the CPSR M field
1569 switch_mode(env
, val
& CPSR_M
);
1572 mask
&= ~CACHED_CPSR_BITS
;
1573 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
1576 /* Sign/zero extend */
1577 uint32_t HELPER(sxtb16
)(uint32_t x
)
1580 res
= (uint16_t)(int8_t)x
;
1581 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
1585 uint32_t HELPER(uxtb16
)(uint32_t x
)
1588 res
= (uint16_t)(uint8_t)x
;
1589 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
1593 uint32_t HELPER(clz
)(uint32_t x
)
1598 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
1602 if (num
== INT_MIN
&& den
== -1)
1607 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
1614 uint32_t HELPER(rbit
)(uint32_t x
)
1616 x
= ((x
& 0xff000000) >> 24)
1617 | ((x
& 0x00ff0000) >> 8)
1618 | ((x
& 0x0000ff00) << 8)
1619 | ((x
& 0x000000ff) << 24);
1620 x
= ((x
& 0xf0f0f0f0) >> 4)
1621 | ((x
& 0x0f0f0f0f) << 4);
1622 x
= ((x
& 0x88888888) >> 3)
1623 | ((x
& 0x44444444) >> 1)
1624 | ((x
& 0x22222222) << 1)
1625 | ((x
& 0x11111111) << 3);
1629 #if defined(CONFIG_USER_ONLY)
1631 void arm_cpu_do_interrupt(CPUState
*cs
)
1633 ARMCPU
*cpu
= ARM_CPU(cs
);
1634 CPUARMState
*env
= &cpu
->env
;
1636 env
->exception_index
= -1;
1639 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
1643 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1644 env
->cp15
.c6_insn
= address
;
1646 env
->exception_index
= EXCP_DATA_ABORT
;
1647 env
->cp15
.c6_data
= address
;
1652 /* These should probably raise undefined insn exceptions. */
1653 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
1655 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1658 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
1660 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1664 void switch_mode(CPUARMState
*env
, int mode
)
1666 if (mode
!= ARM_CPU_MODE_USR
)
1667 cpu_abort(env
, "Tried to switch out of user mode\n");
1670 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1672 cpu_abort(env
, "banked r13 write\n");
1675 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1677 cpu_abort(env
, "banked r13 read\n");
1683 /* Map CPU modes onto saved register banks. */
1684 int bank_number(int mode
)
1687 case ARM_CPU_MODE_USR
:
1688 case ARM_CPU_MODE_SYS
:
1690 case ARM_CPU_MODE_SVC
:
1692 case ARM_CPU_MODE_ABT
:
1694 case ARM_CPU_MODE_UND
:
1696 case ARM_CPU_MODE_IRQ
:
1698 case ARM_CPU_MODE_FIQ
:
1701 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode
);
1704 void switch_mode(CPUARMState
*env
, int mode
)
1709 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1710 if (mode
== old_mode
)
1713 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1714 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1715 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1716 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1717 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1718 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1721 i
= bank_number(old_mode
);
1722 env
->banked_r13
[i
] = env
->regs
[13];
1723 env
->banked_r14
[i
] = env
->regs
[14];
1724 env
->banked_spsr
[i
] = env
->spsr
;
1726 i
= bank_number(mode
);
1727 env
->regs
[13] = env
->banked_r13
[i
];
1728 env
->regs
[14] = env
->banked_r14
[i
];
1729 env
->spsr
= env
->banked_spsr
[i
];
1732 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1735 stl_phys(env
->regs
[13], val
);
1738 static uint32_t v7m_pop(CPUARMState
*env
)
1741 val
= ldl_phys(env
->regs
[13]);
1746 /* Switch to V7M main or process stack pointer. */
1747 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1750 if (env
->v7m
.current_sp
!= process
) {
1751 tmp
= env
->v7m
.other_sp
;
1752 env
->v7m
.other_sp
= env
->regs
[13];
1753 env
->regs
[13] = tmp
;
1754 env
->v7m
.current_sp
= process
;
1758 static void do_v7m_exception_exit(CPUARMState
*env
)
1763 type
= env
->regs
[15];
1764 if (env
->v7m
.exception
!= 0)
1765 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1767 /* Switch to the target stack. */
1768 switch_v7m_sp(env
, (type
& 4) != 0);
1769 /* Pop registers. */
1770 env
->regs
[0] = v7m_pop(env
);
1771 env
->regs
[1] = v7m_pop(env
);
1772 env
->regs
[2] = v7m_pop(env
);
1773 env
->regs
[3] = v7m_pop(env
);
1774 env
->regs
[12] = v7m_pop(env
);
1775 env
->regs
[14] = v7m_pop(env
);
1776 env
->regs
[15] = v7m_pop(env
);
1777 xpsr
= v7m_pop(env
);
1778 xpsr_write(env
, xpsr
, 0xfffffdff);
1779 /* Undo stack alignment. */
1782 /* ??? The exception return type specifies Thread/Handler mode. However
1783 this is also implied by the xPSR value. Not sure what to do
1784 if there is a mismatch. */
1785 /* ??? Likewise for mismatches between the CONTROL register and the stack
1789 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
1791 ARMCPU
*cpu
= ARM_CPU(cs
);
1792 CPUARMState
*env
= &cpu
->env
;
1793 uint32_t xpsr
= xpsr_read(env
);
1798 if (env
->v7m
.current_sp
)
1800 if (env
->v7m
.exception
== 0)
1803 /* For exceptions we just mark as pending on the NVIC, and let that
1805 /* TODO: Need to escalate if the current priority is higher than the
1806 one we're raising. */
1807 switch (env
->exception_index
) {
1809 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1812 /* The PC already points to the next instruction. */
1813 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1815 case EXCP_PREFETCH_ABORT
:
1816 case EXCP_DATA_ABORT
:
1817 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1820 if (semihosting_enabled
) {
1822 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
1825 env
->regs
[0] = do_arm_semihosting(env
);
1829 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1832 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1834 case EXCP_EXCEPTION_EXIT
:
1835 do_v7m_exception_exit(env
);
1838 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1839 return; /* Never happens. Keep compiler happy. */
1842 /* Align stack pointer. */
1843 /* ??? Should only do this if Configuration Control Register
1844 STACKALIGN bit is set. */
1845 if (env
->regs
[13] & 4) {
1849 /* Switch to the handler mode. */
1850 v7m_push(env
, xpsr
);
1851 v7m_push(env
, env
->regs
[15]);
1852 v7m_push(env
, env
->regs
[14]);
1853 v7m_push(env
, env
->regs
[12]);
1854 v7m_push(env
, env
->regs
[3]);
1855 v7m_push(env
, env
->regs
[2]);
1856 v7m_push(env
, env
->regs
[1]);
1857 v7m_push(env
, env
->regs
[0]);
1858 switch_v7m_sp(env
, 0);
1860 env
->condexec_bits
= 0;
1862 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1863 env
->regs
[15] = addr
& 0xfffffffe;
1864 env
->thumb
= addr
& 1;
1867 /* Handle a CPU exception. */
1868 void arm_cpu_do_interrupt(CPUState
*cs
)
1870 ARMCPU
*cpu
= ARM_CPU(cs
);
1871 CPUARMState
*env
= &cpu
->env
;
1879 /* TODO: Vectored interrupt controller. */
1880 switch (env
->exception_index
) {
1882 new_mode
= ARM_CPU_MODE_UND
;
1891 if (semihosting_enabled
) {
1892 /* Check for semihosting interrupt. */
1894 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
1897 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
1900 /* Only intercept calls from privileged modes, to provide some
1901 semblance of security. */
1902 if (((mask
== 0x123456 && !env
->thumb
)
1903 || (mask
== 0xab && env
->thumb
))
1904 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1905 env
->regs
[0] = do_arm_semihosting(env
);
1909 new_mode
= ARM_CPU_MODE_SVC
;
1912 /* The PC already points to the next instruction. */
1916 /* See if this is a semihosting syscall. */
1917 if (env
->thumb
&& semihosting_enabled
) {
1918 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
1920 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1922 env
->regs
[0] = do_arm_semihosting(env
);
1926 env
->cp15
.c5_insn
= 2;
1927 /* Fall through to prefetch abort. */
1928 case EXCP_PREFETCH_ABORT
:
1929 new_mode
= ARM_CPU_MODE_ABT
;
1931 mask
= CPSR_A
| CPSR_I
;
1934 case EXCP_DATA_ABORT
:
1935 new_mode
= ARM_CPU_MODE_ABT
;
1937 mask
= CPSR_A
| CPSR_I
;
1941 new_mode
= ARM_CPU_MODE_IRQ
;
1943 /* Disable IRQ and imprecise data aborts. */
1944 mask
= CPSR_A
| CPSR_I
;
1948 new_mode
= ARM_CPU_MODE_FIQ
;
1950 /* Disable FIQ, IRQ and imprecise data aborts. */
1951 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1955 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1956 return; /* Never happens. Keep compiler happy. */
1959 if (env
->cp15
.c1_sys
& (1 << 13)) {
1962 switch_mode (env
, new_mode
);
1963 env
->spsr
= cpsr_read(env
);
1964 /* Clear IT bits. */
1965 env
->condexec_bits
= 0;
1966 /* Switch to the new mode, and to the correct instruction set. */
1967 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1968 env
->uncached_cpsr
|= mask
;
1969 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1970 * and we should just guard the thumb mode on V4 */
1971 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1972 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1974 env
->regs
[14] = env
->regs
[15] + offset
;
1975 env
->regs
[15] = addr
;
1976 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1979 /* Check section/page access permissions.
1980 Returns the page protection flags, or zero if the access is not
1982 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1983 int access_type
, int is_user
)
1987 if (domain_prot
== 3) {
1988 return PAGE_READ
| PAGE_WRITE
;
1991 if (access_type
== 1)
1994 prot_ro
= PAGE_READ
;
1998 if (access_type
== 1)
2000 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
2002 return is_user
? 0 : PAGE_READ
;
2009 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
2014 return PAGE_READ
| PAGE_WRITE
;
2016 return PAGE_READ
| PAGE_WRITE
;
2017 case 4: /* Reserved. */
2020 return is_user
? 0 : prot_ro
;
2024 if (!arm_feature (env
, ARM_FEATURE_V6K
))
2032 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
2036 if (address
& env
->cp15
.c2_mask
)
2037 table
= env
->cp15
.c2_base1
& 0xffffc000;
2039 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
2041 table
|= (address
>> 18) & 0x3ffc;
2045 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
2046 int is_user
, hwaddr
*phys_ptr
,
2047 int *prot
, target_ulong
*page_size
)
2058 /* Pagetable walk. */
2059 /* Lookup l1 descriptor. */
2060 table
= get_level1_table_address(env
, address
);
2061 desc
= ldl_phys(table
);
2063 domain
= (desc
>> 5) & 0x0f;
2064 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2066 /* Section translation fault. */
2070 if (domain_prot
== 0 || domain_prot
== 2) {
2072 code
= 9; /* Section domain fault. */
2074 code
= 11; /* Page domain fault. */
2079 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2080 ap
= (desc
>> 10) & 3;
2082 *page_size
= 1024 * 1024;
2084 /* Lookup l2 entry. */
2086 /* Coarse pagetable. */
2087 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2089 /* Fine pagetable. */
2090 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
2092 desc
= ldl_phys(table
);
2094 case 0: /* Page translation fault. */
2097 case 1: /* 64k page. */
2098 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2099 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2100 *page_size
= 0x10000;
2102 case 2: /* 4k page. */
2103 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2104 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2105 *page_size
= 0x1000;
2107 case 3: /* 1k page. */
2109 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2110 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2112 /* Page translation fault. */
2117 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
2119 ap
= (desc
>> 4) & 3;
2123 /* Never happens, but compiler isn't smart enough to tell. */
2128 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2130 /* Access permission fault. */
2134 *phys_ptr
= phys_addr
;
2137 return code
| (domain
<< 4);
2140 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
2141 int is_user
, hwaddr
*phys_ptr
,
2142 int *prot
, target_ulong
*page_size
)
2155 /* Pagetable walk. */
2156 /* Lookup l1 descriptor. */
2157 table
= get_level1_table_address(env
, address
);
2158 desc
= ldl_phys(table
);
2160 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
2161 /* Section translation fault, or attempt to use the encoding
2162 * which is Reserved on implementations without PXN.
2167 if ((type
== 1) || !(desc
& (1 << 18))) {
2168 /* Page or Section. */
2169 domain
= (desc
>> 5) & 0x0f;
2171 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2172 if (domain_prot
== 0 || domain_prot
== 2) {
2174 code
= 9; /* Section domain fault. */
2176 code
= 11; /* Page domain fault. */
2181 if (desc
& (1 << 18)) {
2183 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
2184 *page_size
= 0x1000000;
2187 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2188 *page_size
= 0x100000;
2190 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
2191 xn
= desc
& (1 << 4);
2195 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
2196 pxn
= (desc
>> 2) & 1;
2198 /* Lookup l2 entry. */
2199 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2200 desc
= ldl_phys(table
);
2201 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
2203 case 0: /* Page translation fault. */
2206 case 1: /* 64k page. */
2207 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2208 xn
= desc
& (1 << 15);
2209 *page_size
= 0x10000;
2211 case 2: case 3: /* 4k page. */
2212 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2214 *page_size
= 0x1000;
2217 /* Never happens, but compiler isn't smart enough to tell. */
2222 if (domain_prot
== 3) {
2223 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2225 if (pxn
&& !is_user
) {
2228 if (xn
&& access_type
== 2)
2231 /* The simplified model uses AP[0] as an access control bit. */
2232 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
2233 /* Access flag fault. */
2234 code
= (code
== 15) ? 6 : 3;
2237 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2239 /* Access permission fault. */
2246 *phys_ptr
= phys_addr
;
2249 return code
| (domain
<< 4);
2252 /* Fault type for long-descriptor MMU fault reporting; this corresponds
2253 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2256 translation_fault
= 1,
2258 permission_fault
= 3,
2261 static int get_phys_addr_lpae(CPUARMState
*env
, uint32_t address
,
2262 int access_type
, int is_user
,
2263 hwaddr
*phys_ptr
, int *prot
,
2264 target_ulong
*page_size_ptr
)
2266 /* Read an LPAE long-descriptor translation table. */
2267 MMUFaultType fault_type
= translation_fault
;
2275 uint32_t tableattrs
;
2276 target_ulong page_size
;
2279 /* Determine whether this address is in the region controlled by
2280 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2281 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2282 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2284 uint32_t t0sz
= extract32(env
->cp15
.c2_control
, 0, 3);
2285 uint32_t t1sz
= extract32(env
->cp15
.c2_control
, 16, 3);
2286 if (t0sz
&& !extract32(address
, 32 - t0sz
, t0sz
)) {
2287 /* there is a ttbr0 region and we are in it (high bits all zero) */
2289 } else if (t1sz
&& !extract32(~address
, 32 - t1sz
, t1sz
)) {
2290 /* there is a ttbr1 region and we are in it (high bits all one) */
2293 /* ttbr0 region is "everything not in the ttbr1 region" */
2296 /* ttbr1 region is "everything not in the ttbr0 region" */
2299 /* in the gap between the two regions, this is a Translation fault */
2300 fault_type
= translation_fault
;
2304 /* Note that QEMU ignores shareability and cacheability attributes,
2305 * so we don't need to do anything with the SH, ORGN, IRGN fields
2306 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2307 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2308 * implement any ASID-like capability so we can ignore it (instead
2309 * we will always flush the TLB any time the ASID is changed).
2311 if (ttbr_select
== 0) {
2312 ttbr
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
2313 epd
= extract32(env
->cp15
.c2_control
, 7, 1);
2316 ttbr
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
2317 epd
= extract32(env
->cp15
.c2_control
, 23, 1);
2322 /* Translation table walk disabled => Translation fault on TLB miss */
2326 /* If the region is small enough we will skip straight to a 2nd level
2327 * lookup. This affects the number of bits of the address used in
2328 * combination with the TTBR to find the first descriptor. ('n' here
2329 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2330 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2339 /* Clear the vaddr bits which aren't part of the within-region address,
2340 * so that we don't have to special case things when calculating the
2341 * first descriptor address.
2343 address
&= (0xffffffffU
>> tsz
);
2345 /* Now we can extract the actual base address from the TTBR */
2346 descaddr
= extract64(ttbr
, 0, 40);
2347 descaddr
&= ~((1ULL << n
) - 1);
2351 uint64_t descriptor
;
2353 descaddr
|= ((address
>> (9 * (4 - level
))) & 0xff8);
2354 descriptor
= ldq_phys(descaddr
);
2355 if (!(descriptor
& 1) ||
2356 (!(descriptor
& 2) && (level
== 3))) {
2357 /* Invalid, or the Reserved level 3 encoding */
2360 descaddr
= descriptor
& 0xfffffff000ULL
;
2362 if ((descriptor
& 2) && (level
< 3)) {
2363 /* Table entry. The top five bits are attributes which may
2364 * propagate down through lower levels of the table (and
2365 * which are all arranged so that 0 means "no effect", so
2366 * we can gather them up by ORing in the bits at each level).
2368 tableattrs
|= extract64(descriptor
, 59, 5);
2372 /* Block entry at level 1 or 2, or page entry at level 3.
2373 * These are basically the same thing, although the number
2374 * of bits we pull in from the vaddr varies.
2376 page_size
= (1 << (39 - (9 * level
)));
2377 descaddr
|= (address
& (page_size
- 1));
2378 /* Extract attributes from the descriptor and merge with table attrs */
2379 attrs
= extract64(descriptor
, 2, 10)
2380 | (extract64(descriptor
, 52, 12) << 10);
2381 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
2382 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
2383 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2384 * means "force PL1 access only", which means forcing AP[1] to 0.
2386 if (extract32(tableattrs
, 2, 1)) {
2389 /* Since we're always in the Non-secure state, NSTable is ignored. */
2392 /* Here descaddr is the final physical address, and attributes
2395 fault_type
= access_fault
;
2396 if ((attrs
& (1 << 8)) == 0) {
2400 fault_type
= permission_fault
;
2401 if (is_user
&& !(attrs
& (1 << 4))) {
2402 /* Unprivileged access not enabled */
2405 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2406 if (attrs
& (1 << 12) || (!is_user
&& (attrs
& (1 << 11)))) {
2408 if (access_type
== 2) {
2411 *prot
&= ~PAGE_EXEC
;
2413 if (attrs
& (1 << 5)) {
2414 /* Write access forbidden */
2415 if (access_type
== 1) {
2418 *prot
&= ~PAGE_WRITE
;
2421 *phys_ptr
= descaddr
;
2422 *page_size_ptr
= page_size
;
2426 /* Long-descriptor format IFSR/DFSR value */
2427 return (1 << 9) | (fault_type
<< 2) | level
;
2430 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
2431 int access_type
, int is_user
,
2432 hwaddr
*phys_ptr
, int *prot
)
2438 *phys_ptr
= address
;
2439 for (n
= 7; n
>= 0; n
--) {
2440 base
= env
->cp15
.c6_region
[n
];
2441 if ((base
& 1) == 0)
2443 mask
= 1 << ((base
>> 1) & 0x1f);
2444 /* Keep this shift separate from the above to avoid an
2445 (undefined) << 32. */
2446 mask
= (mask
<< 1) - 1;
2447 if (((base
^ address
) & ~mask
) == 0)
2453 if (access_type
== 2) {
2454 mask
= env
->cp15
.c5_insn
;
2456 mask
= env
->cp15
.c5_data
;
2458 mask
= (mask
>> (n
* 4)) & 0xf;
2465 *prot
= PAGE_READ
| PAGE_WRITE
;
2470 *prot
|= PAGE_WRITE
;
2473 *prot
= PAGE_READ
| PAGE_WRITE
;
2484 /* Bad permission. */
2491 /* get_phys_addr - get the physical address for this virtual address
2493 * Find the physical address corresponding to the given virtual address,
2494 * by doing a translation table walk on MMU based systems or using the
2495 * MPU state on MPU based systems.
2497 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2498 * prot and page_size are not filled in, and the return value provides
2499 * information on why the translation aborted, in the format of a
2500 * DFSR/IFSR fault register, with the following caveats:
2501 * * we honour the short vs long DFSR format differences.
2502 * * the WnR bit is never set (the caller must do this).
2503 * * for MPU based systems we don't bother to return a full FSR format
2507 * @address: virtual address to get physical address for
2508 * @access_type: 0 for read, 1 for write, 2 for execute
2509 * @is_user: 0 for privileged access, 1 for user
2510 * @phys_ptr: set to the physical address corresponding to the virtual address
2511 * @prot: set to the permissions for the page containing phys_ptr
2512 * @page_size: set to the size of the page containing phys_ptr
2514 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
2515 int access_type
, int is_user
,
2516 hwaddr
*phys_ptr
, int *prot
,
2517 target_ulong
*page_size
)
2519 /* Fast Context Switch Extension. */
2520 if (address
< 0x02000000)
2521 address
+= env
->cp15
.c13_fcse
;
2523 if ((env
->cp15
.c1_sys
& 1) == 0) {
2524 /* MMU/MPU disabled. */
2525 *phys_ptr
= address
;
2526 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2527 *page_size
= TARGET_PAGE_SIZE
;
2529 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2530 *page_size
= TARGET_PAGE_SIZE
;
2531 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
2533 } else if (extended_addresses_enabled(env
)) {
2534 return get_phys_addr_lpae(env
, address
, access_type
, is_user
, phys_ptr
,
2536 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
2537 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
2540 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
2545 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
2546 int access_type
, int mmu_idx
)
2549 target_ulong page_size
;
2553 is_user
= mmu_idx
== MMU_USER_IDX
;
2554 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
2557 /* Map a single [sub]page. */
2558 phys_addr
&= ~(hwaddr
)0x3ff;
2559 address
&= ~(uint32_t)0x3ff;
2560 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
2564 if (access_type
== 2) {
2565 env
->cp15
.c5_insn
= ret
;
2566 env
->cp15
.c6_insn
= address
;
2567 env
->exception_index
= EXCP_PREFETCH_ABORT
;
2569 env
->cp15
.c5_data
= ret
;
2570 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
2571 env
->cp15
.c5_data
|= (1 << 11);
2572 env
->cp15
.c6_data
= address
;
2573 env
->exception_index
= EXCP_DATA_ABORT
;
2578 hwaddr
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
2581 target_ulong page_size
;
2585 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
2593 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2595 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2596 env
->regs
[13] = val
;
2598 env
->banked_r13
[bank_number(mode
)] = val
;
2602 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2604 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2605 return env
->regs
[13];
2607 return env
->banked_r13
[bank_number(mode
)];
2611 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2615 return xpsr_read(env
) & 0xf8000000;
2617 return xpsr_read(env
) & 0xf80001ff;
2619 return xpsr_read(env
) & 0xff00fc00;
2621 return xpsr_read(env
) & 0xff00fdff;
2623 return xpsr_read(env
) & 0x000001ff;
2625 return xpsr_read(env
) & 0x0700fc00;
2627 return xpsr_read(env
) & 0x0700edff;
2629 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2631 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2632 case 16: /* PRIMASK */
2633 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2634 case 17: /* BASEPRI */
2635 case 18: /* BASEPRI_MAX */
2636 return env
->v7m
.basepri
;
2637 case 19: /* FAULTMASK */
2638 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2639 case 20: /* CONTROL */
2640 return env
->v7m
.control
;
2642 /* ??? For debugging only. */
2643 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2648 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2652 xpsr_write(env
, val
, 0xf8000000);
2655 xpsr_write(env
, val
, 0xf8000000);
2658 xpsr_write(env
, val
, 0xfe00fc00);
2661 xpsr_write(env
, val
, 0xfe00fc00);
2664 /* IPSR bits are readonly. */
2667 xpsr_write(env
, val
, 0x0600fc00);
2670 xpsr_write(env
, val
, 0x0600fc00);
2673 if (env
->v7m
.current_sp
)
2674 env
->v7m
.other_sp
= val
;
2676 env
->regs
[13] = val
;
2679 if (env
->v7m
.current_sp
)
2680 env
->regs
[13] = val
;
2682 env
->v7m
.other_sp
= val
;
2684 case 16: /* PRIMASK */
2686 env
->uncached_cpsr
|= CPSR_I
;
2688 env
->uncached_cpsr
&= ~CPSR_I
;
2690 case 17: /* BASEPRI */
2691 env
->v7m
.basepri
= val
& 0xff;
2693 case 18: /* BASEPRI_MAX */
2695 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2696 env
->v7m
.basepri
= val
;
2698 case 19: /* FAULTMASK */
2700 env
->uncached_cpsr
|= CPSR_F
;
2702 env
->uncached_cpsr
&= ~CPSR_F
;
2704 case 20: /* CONTROL */
2705 env
->v7m
.control
= val
& 3;
2706 switch_v7m_sp(env
, (val
& 2) != 0);
2709 /* ??? For debugging only. */
2710 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2717 /* Note that signed overflow is undefined in C. The following routines are
2718 careful to use unsigned types where modulo arithmetic is required.
2719 Failure to do so _will_ break on newer gcc. */
2721 /* Signed saturating arithmetic. */
2723 /* Perform 16-bit signed saturating addition. */
2724 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2729 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2738 /* Perform 8-bit signed saturating addition. */
2739 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2744 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2753 /* Perform 16-bit signed saturating subtraction. */
2754 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2759 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2768 /* Perform 8-bit signed saturating subtraction. */
2769 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2774 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2783 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2784 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2785 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2786 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2789 #include "op_addsub.h"
2791 /* Unsigned saturating arithmetic. */
2792 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2801 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2809 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2818 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2826 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2827 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2828 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2829 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2832 #include "op_addsub.h"
2834 /* Signed modulo arithmetic. */
2835 #define SARITH16(a, b, n, op) do { \
2837 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2838 RESULT(sum, n, 16); \
2840 ge |= 3 << (n * 2); \
2843 #define SARITH8(a, b, n, op) do { \
2845 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2846 RESULT(sum, n, 8); \
2852 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2853 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2854 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2855 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2859 #include "op_addsub.h"
2861 /* Unsigned modulo arithmetic. */
2862 #define ADD16(a, b, n) do { \
2864 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2865 RESULT(sum, n, 16); \
2866 if ((sum >> 16) == 1) \
2867 ge |= 3 << (n * 2); \
2870 #define ADD8(a, b, n) do { \
2872 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2873 RESULT(sum, n, 8); \
2874 if ((sum >> 8) == 1) \
2878 #define SUB16(a, b, n) do { \
2880 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2881 RESULT(sum, n, 16); \
2882 if ((sum >> 16) == 0) \
2883 ge |= 3 << (n * 2); \
2886 #define SUB8(a, b, n) do { \
2888 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2889 RESULT(sum, n, 8); \
2890 if ((sum >> 8) == 0) \
2897 #include "op_addsub.h"
2899 /* Halved signed arithmetic. */
2900 #define ADD16(a, b, n) \
2901 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2902 #define SUB16(a, b, n) \
2903 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2904 #define ADD8(a, b, n) \
2905 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2906 #define SUB8(a, b, n) \
2907 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2910 #include "op_addsub.h"
2912 /* Halved unsigned arithmetic. */
2913 #define ADD16(a, b, n) \
2914 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2915 #define SUB16(a, b, n) \
2916 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2917 #define ADD8(a, b, n) \
2918 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2919 #define SUB8(a, b, n) \
2920 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2923 #include "op_addsub.h"
2925 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2933 /* Unsigned sum of absolute byte differences. */
2934 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2937 sum
= do_usad(a
, b
);
2938 sum
+= do_usad(a
>> 8, b
>> 8);
2939 sum
+= do_usad(a
>> 16, b
>>16);
2940 sum
+= do_usad(a
>> 24, b
>> 24);
2944 /* For ARMv6 SEL instruction. */
2945 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2958 return (a
& mask
) | (b
& ~mask
);
2961 /* VFP support. We follow the convention used for VFP instructions:
2962 Single precision routines have a "s" suffix, double precision a
2965 /* Convert host exception flags to vfp form. */
2966 static inline int vfp_exceptbits_from_host(int host_bits
)
2968 int target_bits
= 0;
2970 if (host_bits
& float_flag_invalid
)
2972 if (host_bits
& float_flag_divbyzero
)
2974 if (host_bits
& float_flag_overflow
)
2976 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2978 if (host_bits
& float_flag_inexact
)
2979 target_bits
|= 0x10;
2980 if (host_bits
& float_flag_input_denormal
)
2981 target_bits
|= 0x80;
2985 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2990 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2991 | (env
->vfp
.vec_len
<< 16)
2992 | (env
->vfp
.vec_stride
<< 20);
2993 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2994 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2995 fpscr
|= vfp_exceptbits_from_host(i
);
2999 uint32_t vfp_get_fpscr(CPUARMState
*env
)
3001 return HELPER(vfp_get_fpscr
)(env
);
3004 /* Convert vfp exception flags to target form. */
3005 static inline int vfp_exceptbits_to_host(int target_bits
)
3009 if (target_bits
& 1)
3010 host_bits
|= float_flag_invalid
;
3011 if (target_bits
& 2)
3012 host_bits
|= float_flag_divbyzero
;
3013 if (target_bits
& 4)
3014 host_bits
|= float_flag_overflow
;
3015 if (target_bits
& 8)
3016 host_bits
|= float_flag_underflow
;
3017 if (target_bits
& 0x10)
3018 host_bits
|= float_flag_inexact
;
3019 if (target_bits
& 0x80)
3020 host_bits
|= float_flag_input_denormal
;
3024 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
3029 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
3030 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
3031 env
->vfp
.vec_len
= (val
>> 16) & 7;
3032 env
->vfp
.vec_stride
= (val
>> 20) & 3;
3035 if (changed
& (3 << 22)) {
3036 i
= (val
>> 22) & 3;
3039 i
= float_round_nearest_even
;
3045 i
= float_round_down
;
3048 i
= float_round_to_zero
;
3051 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
3053 if (changed
& (1 << 24)) {
3054 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
3055 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
3057 if (changed
& (1 << 25))
3058 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
3060 i
= vfp_exceptbits_to_host(val
);
3061 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
3062 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
3065 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
3067 HELPER(vfp_set_fpscr
)(env
, val
);
3070 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3072 #define VFP_BINOP(name) \
3073 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3075 float_status *fpst = fpstp; \
3076 return float32_ ## name(a, b, fpst); \
3078 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3080 float_status *fpst = fpstp; \
3081 return float64_ ## name(a, b, fpst); \
3089 float32
VFP_HELPER(neg
, s
)(float32 a
)
3091 return float32_chs(a
);
3094 float64
VFP_HELPER(neg
, d
)(float64 a
)
3096 return float64_chs(a
);
3099 float32
VFP_HELPER(abs
, s
)(float32 a
)
3101 return float32_abs(a
);
3104 float64
VFP_HELPER(abs
, d
)(float64 a
)
3106 return float64_abs(a
);
3109 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
3111 return float32_sqrt(a
, &env
->vfp
.fp_status
);
3114 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
3116 return float64_sqrt(a
, &env
->vfp
.fp_status
);
3119 /* XXX: check quiet/signaling case */
3120 #define DO_VFP_cmp(p, type) \
3121 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3124 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3125 case 0: flags = 0x6; break; \
3126 case -1: flags = 0x8; break; \
3127 case 1: flags = 0x2; break; \
3128 default: case 2: flags = 0x3; break; \
3130 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3131 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3133 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3136 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3137 case 0: flags = 0x6; break; \
3138 case -1: flags = 0x8; break; \
3139 case 1: flags = 0x2; break; \
3140 default: case 2: flags = 0x3; break; \
3142 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3143 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3145 DO_VFP_cmp(s
, float32
)
3146 DO_VFP_cmp(d
, float64
)
3149 /* Integer to float and float to integer conversions */
3151 #define CONV_ITOF(name, fsz, sign) \
3152 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3154 float_status *fpst = fpstp; \
3155 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3158 #define CONV_FTOI(name, fsz, sign, round) \
3159 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3161 float_status *fpst = fpstp; \
3162 if (float##fsz##_is_any_nan(x)) { \
3163 float_raise(float_flag_invalid, fpst); \
3166 return float##fsz##_to_##sign##int32##round(x, fpst); \
3169 #define FLOAT_CONVS(name, p, fsz, sign) \
3170 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3171 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3172 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3174 FLOAT_CONVS(si
, s
, 32, )
3175 FLOAT_CONVS(si
, d
, 64, )
3176 FLOAT_CONVS(ui
, s
, 32, u
)
3177 FLOAT_CONVS(ui
, d
, 64, u
)
3183 /* floating point conversion */
3184 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
3186 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
3187 /* ARM requires that S<->D conversion of any kind of NaN generates
3188 * a quiet NaN by forcing the most significant frac bit to 1.
3190 return float64_maybe_silence_nan(r
);
3193 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
3195 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
3196 /* ARM requires that S<->D conversion of any kind of NaN generates
3197 * a quiet NaN by forcing the most significant frac bit to 1.
3199 return float32_maybe_silence_nan(r
);
3202 /* VFP3 fixed point conversion. */
3203 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
3204 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3207 float_status *fpst = fpstp; \
3209 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3210 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
3212 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3215 float_status *fpst = fpstp; \
3217 if (float##fsz##_is_any_nan(x)) { \
3218 float_raise(float_flag_invalid, fpst); \
3221 tmp = float##fsz##_scalbn(x, shift, fpst); \
3222 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
3225 VFP_CONV_FIX(sh
, d
, 64, int16
, )
3226 VFP_CONV_FIX(sl
, d
, 64, int32
, )
3227 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
3228 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
3229 VFP_CONV_FIX(sh
, s
, 32, int16
, )
3230 VFP_CONV_FIX(sl
, s
, 32, int32
, )
3231 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
3232 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
3235 /* Half precision conversions. */
3236 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
3238 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
3239 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
3241 return float32_maybe_silence_nan(r
);
3246 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
3248 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
3249 float16 r
= float32_to_float16(a
, ieee
, s
);
3251 r
= float16_maybe_silence_nan(r
);
3253 return float16_val(r
);
3256 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3258 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
3261 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3263 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
3266 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3268 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
3271 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3273 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
3276 #define float32_two make_float32(0x40000000)
3277 #define float32_three make_float32(0x40400000)
3278 #define float32_one_point_five make_float32(0x3fc00000)
3280 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3282 float_status
*s
= &env
->vfp
.standard_fp_status
;
3283 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3284 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3285 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3286 float_raise(float_flag_input_denormal
, s
);
3290 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
3293 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3295 float_status
*s
= &env
->vfp
.standard_fp_status
;
3297 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3298 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3299 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3300 float_raise(float_flag_input_denormal
, s
);
3302 return float32_one_point_five
;
3304 product
= float32_mul(a
, b
, s
);
3305 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
3310 /* Constants 256 and 512 are used in some helpers; we avoid relying on
3311 * int->float conversions at run-time. */
3312 #define float64_256 make_float64(0x4070000000000000LL)
3313 #define float64_512 make_float64(0x4080000000000000LL)
3315 /* The algorithm that must be used to calculate the estimate
3316 * is specified by the ARM ARM.
3318 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
3320 /* These calculations mustn't set any fp exception flags,
3321 * so we use a local copy of the fp_status.
3323 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3324 float_status
*s
= &dummy_status
;
3325 /* q = (int)(a * 512.0) */
3326 float64 q
= float64_mul(float64_512
, a
, s
);
3327 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3329 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3330 q
= int64_to_float64(q_int
, s
);
3331 q
= float64_add(q
, float64_half
, s
);
3332 q
= float64_div(q
, float64_512
, s
);
3333 q
= float64_div(float64_one
, q
, s
);
3335 /* s = (int)(256.0 * r + 0.5) */
3336 q
= float64_mul(q
, float64_256
, s
);
3337 q
= float64_add(q
, float64_half
, s
);
3338 q_int
= float64_to_int64_round_to_zero(q
, s
);
3340 /* return (double)s / 256.0 */
3341 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3344 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
3346 float_status
*s
= &env
->vfp
.standard_fp_status
;
3348 uint32_t val32
= float32_val(a
);
3351 int a_exp
= (val32
& 0x7f800000) >> 23;
3352 int sign
= val32
& 0x80000000;
3354 if (float32_is_any_nan(a
)) {
3355 if (float32_is_signaling_nan(a
)) {
3356 float_raise(float_flag_invalid
, s
);
3358 return float32_default_nan
;
3359 } else if (float32_is_infinity(a
)) {
3360 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3361 } else if (float32_is_zero_or_denormal(a
)) {
3362 if (!float32_is_zero(a
)) {
3363 float_raise(float_flag_input_denormal
, s
);
3365 float_raise(float_flag_divbyzero
, s
);
3366 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3367 } else if (a_exp
>= 253) {
3368 float_raise(float_flag_underflow
, s
);
3369 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3372 f64
= make_float64((0x3feULL
<< 52)
3373 | ((int64_t)(val32
& 0x7fffff) << 29));
3375 result_exp
= 253 - a_exp
;
3377 f64
= recip_estimate(f64
, env
);
3380 | ((result_exp
& 0xff) << 23)
3381 | ((float64_val(f64
) >> 29) & 0x7fffff);
3382 return make_float32(val32
);
3385 /* The algorithm that must be used to calculate the estimate
3386 * is specified by the ARM ARM.
3388 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
3390 /* These calculations mustn't set any fp exception flags,
3391 * so we use a local copy of the fp_status.
3393 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3394 float_status
*s
= &dummy_status
;
3398 if (float64_lt(a
, float64_half
, s
)) {
3399 /* range 0.25 <= a < 0.5 */
3401 /* a in units of 1/512 rounded down */
3402 /* q0 = (int)(a * 512.0); */
3403 q
= float64_mul(float64_512
, a
, s
);
3404 q_int
= float64_to_int64_round_to_zero(q
, s
);
3406 /* reciprocal root r */
3407 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3408 q
= int64_to_float64(q_int
, s
);
3409 q
= float64_add(q
, float64_half
, s
);
3410 q
= float64_div(q
, float64_512
, s
);
3411 q
= float64_sqrt(q
, s
);
3412 q
= float64_div(float64_one
, q
, s
);
3414 /* range 0.5 <= a < 1.0 */
3416 /* a in units of 1/256 rounded down */
3417 /* q1 = (int)(a * 256.0); */
3418 q
= float64_mul(float64_256
, a
, s
);
3419 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3421 /* reciprocal root r */
3422 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3423 q
= int64_to_float64(q_int
, s
);
3424 q
= float64_add(q
, float64_half
, s
);
3425 q
= float64_div(q
, float64_256
, s
);
3426 q
= float64_sqrt(q
, s
);
3427 q
= float64_div(float64_one
, q
, s
);
3429 /* r in units of 1/256 rounded to nearest */
3430 /* s = (int)(256.0 * r + 0.5); */
3432 q
= float64_mul(q
, float64_256
,s
);
3433 q
= float64_add(q
, float64_half
, s
);
3434 q_int
= float64_to_int64_round_to_zero(q
, s
);
3436 /* return (double)s / 256.0;*/
3437 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3440 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3442 float_status
*s
= &env
->vfp
.standard_fp_status
;
3448 val
= float32_val(a
);
3450 if (float32_is_any_nan(a
)) {
3451 if (float32_is_signaling_nan(a
)) {
3452 float_raise(float_flag_invalid
, s
);
3454 return float32_default_nan
;
3455 } else if (float32_is_zero_or_denormal(a
)) {
3456 if (!float32_is_zero(a
)) {
3457 float_raise(float_flag_input_denormal
, s
);
3459 float_raise(float_flag_divbyzero
, s
);
3460 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3461 } else if (float32_is_neg(a
)) {
3462 float_raise(float_flag_invalid
, s
);
3463 return float32_default_nan
;
3464 } else if (float32_is_infinity(a
)) {
3465 return float32_zero
;
3468 /* Normalize to a double-precision value between 0.25 and 1.0,
3469 * preserving the parity of the exponent. */
3470 if ((val
& 0x800000) == 0) {
3471 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3473 | ((uint64_t)(val
& 0x7fffff) << 29));
3475 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3477 | ((uint64_t)(val
& 0x7fffff) << 29));
3480 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3482 f64
= recip_sqrt_estimate(f64
, env
);
3484 val64
= float64_val(f64
);
3486 val
= ((result_exp
& 0xff) << 23)
3487 | ((val64
>> 29) & 0x7fffff);
3488 return make_float32(val
);
3491 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3495 if ((a
& 0x80000000) == 0) {
3499 f64
= make_float64((0x3feULL
<< 52)
3500 | ((int64_t)(a
& 0x7fffffff) << 21));
3502 f64
= recip_estimate (f64
, env
);
3504 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3507 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3511 if ((a
& 0xc0000000) == 0) {
3515 if (a
& 0x80000000) {
3516 f64
= make_float64((0x3feULL
<< 52)
3517 | ((uint64_t)(a
& 0x7fffffff) << 21));
3518 } else { /* bits 31-30 == '01' */
3519 f64
= make_float64((0x3fdULL
<< 52)
3520 | ((uint64_t)(a
& 0x3fffffff) << 22));
3523 f64
= recip_sqrt_estimate(f64
, env
);
3525 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3528 /* VFPv4 fused multiply-accumulate */
3529 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3531 float_status
*fpst
= fpstp
;
3532 return float32_muladd(a
, b
, c
, 0, fpst
);
3535 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3537 float_status
*fpst
= fpstp
;
3538 return float64_muladd(a
, b
, c
, 0, fpst
);