target-arm/internals.h

   1 /*
   2  * QEMU ARM CPU -- internal functions and types
   3  *
   4  * Copyright (c) 2014 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  *
  20  * This header defines functions, types, etc which need to be shared
  21  * between different source files within target-arm/ but which are
  22  * private to it and not required by the rest of QEMU.
  23  */
  24
  25 #ifndef TARGET_ARM_INTERNALS_H
  26 #define TARGET_ARM_INTERNALS_H
  27
  28 static inline bool excp_is_internal(int excp)
  29 {
  30     /* Return true if this exception number represents a QEMU-internal
  31      * exception that will not be passed to the guest.
  32      */
  33     return excp == EXCP_INTERRUPT
  34         || excp == EXCP_HLT
  35         || excp == EXCP_DEBUG
  36         || excp == EXCP_HALTED
  37         || excp == EXCP_EXCEPTION_EXIT
  38         || excp == EXCP_KERNEL_TRAP
  39         || excp == EXCP_STREX;
  40 }
  41
  42 /* Exception names for debug logging; note that not all of these
  43  * precisely correspond to architectural exceptions.
  44  */
  45 static const char * const excnames[] = {
  46     [EXCP_UDEF] = "Undefined Instruction",
  47     [EXCP_SWI] = "SVC",
  48     [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
  49     [EXCP_DATA_ABORT] = "Data Abort",
  50     [EXCP_IRQ] = "IRQ",
  51     [EXCP_FIQ] = "FIQ",
  52     [EXCP_BKPT] = "Breakpoint",
  53     [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
  54     [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
  55     [EXCP_STREX] = "QEMU intercept of STREX",
  56     [EXCP_HVC] = "Hypervisor Call",
  57     [EXCP_HYP_TRAP] = "Hypervisor Trap",
  58 };
  59
  60 static inline void arm_log_exception(int idx)
  61 {
  62     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  63         const char *exc = NULL;
  64
  65         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
  66             exc = excnames[idx];
  67         }
  68         if (!exc) {
  69             exc = "unknown";
  70         }
  71         qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
  72     }
  73 }
  74
  75 /* Scale factor for generic timers, ie number of ns per tick.
  76  * This gives a 62.5MHz timer.
  77  */
  78 #define GTIMER_SCALE 16
  79
  80 /*
  81  * For AArch64, map a given EL to an index in the banked_spsr array.
  82  */
  83 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
  84 {
  85     static const unsigned int map[4] = {
  86         [1] = 0, /* EL1.  */
  87         [2] = 6, /* EL2.  */
  88         [3] = 7, /* EL3.  */
  89     };
  90     assert(el >= 1 && el <= 3);
  91     return map[el];
  92 }
  93
  94 int bank_number(int mode);
  95 void switch_mode(CPUARMState *, int);
  96 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
  97 void arm_translate_init(void);
  98
  99 enum arm_fprounding {
 100     FPROUNDING_TIEEVEN,
 101     FPROUNDING_POSINF,
 102     FPROUNDING_NEGINF,
 103     FPROUNDING_ZERO,
 104     FPROUNDING_TIEAWAY,
 105     FPROUNDING_ODD
 106 };
 107
 108 int arm_rmode_to_sf(int rmode);
 109
 110 static inline void aarch64_save_sp(CPUARMState *env, int el)
 111 {
 112     if (env->pstate & PSTATE_SP) {
 113         env->sp_el[el] = env->xregs[31];
 114     } else {
 115         env->sp_el[0] = env->xregs[31];
 116     }
 117 }
 118
 119 static inline void aarch64_restore_sp(CPUARMState *env, int el)
 120 {
 121     if (env->pstate & PSTATE_SP) {
 122         env->xregs[31] = env->sp_el[el];
 123     } else {
 124         env->xregs[31] = env->sp_el[0];
 125     }
 126 }
 127
 128 static inline void update_spsel(CPUARMState *env, uint32_t imm)
 129 {
 130     unsigned int cur_el = arm_current_pl(env);
 131     /* Update PSTATE SPSel bit; this requires us to update the
 132      * working stack pointer in xregs[31].
 133      */
 134     if (!((imm ^ env->pstate) & PSTATE_SP)) {
 135         return;
 136     }
 137     aarch64_save_sp(env, cur_el);
 138     env->pstate = deposit32(env->pstate, 0, 1, imm);
 139
 140     /* We rely on illegal updates to SPsel from EL0 to get trapped
 141      * at translation time.
 142      */
 143     assert(cur_el >= 1 && cur_el <= 3);
 144     aarch64_restore_sp(env, cur_el);
 145 }
 146
 147 /* Return true if extended addresses are enabled.
 148  * This is always the case if our translation regime is 64 bit,
 149  * but depends on TTBCR.EAE for 32 bit.
 150  */
 151 static inline bool extended_addresses_enabled(CPUARMState *env)
 152 {
 153     return arm_el_is_aa64(env, 1)
 154         || ((arm_feature(env, ARM_FEATURE_LPAE)
 155              && (env->cp15.c2_control & TTBCR_EAE)));
 156 }
 157
 158 /* Valid Syndrome Register EC field values */
 159 enum arm_exception_class {
 160     EC_UNCATEGORIZED          = 0x00,
 161     EC_WFX_TRAP               = 0x01,
 162     EC_CP15RTTRAP             = 0x03,
 163     EC_CP15RRTTRAP            = 0x04,
 164     EC_CP14RTTRAP             = 0x05,
 165     EC_CP14DTTRAP             = 0x06,
 166     EC_ADVSIMDFPACCESSTRAP    = 0x07,
 167     EC_FPIDTRAP               = 0x08,
 168     EC_CP14RRTTRAP            = 0x0c,
 169     EC_ILLEGALSTATE           = 0x0e,
 170     EC_AA32_SVC               = 0x11,
 171     EC_AA32_HVC               = 0x12,
 172     EC_AA32_SMC               = 0x13,
 173     EC_AA64_SVC               = 0x15,
 174     EC_AA64_HVC               = 0x16,
 175     EC_AA64_SMC               = 0x17,
 176     EC_SYSTEMREGISTERTRAP     = 0x18,
 177     EC_INSNABORT              = 0x20,
 178     EC_INSNABORT_SAME_EL      = 0x21,
 179     EC_PCALIGNMENT            = 0x22,
 180     EC_DATAABORT              = 0x24,
 181     EC_DATAABORT_SAME_EL      = 0x25,
 182     EC_SPALIGNMENT            = 0x26,
 183     EC_AA32_FPTRAP            = 0x28,
 184     EC_AA64_FPTRAP            = 0x2c,
 185     EC_SERROR                 = 0x2f,
 186     EC_BREAKPOINT             = 0x30,
 187     EC_BREAKPOINT_SAME_EL     = 0x31,
 188     EC_SOFTWARESTEP           = 0x32,
 189     EC_SOFTWARESTEP_SAME_EL   = 0x33,
 190     EC_WATCHPOINT             = 0x34,
 191     EC_WATCHPOINT_SAME_EL     = 0x35,
 192     EC_AA32_BKPT              = 0x38,
 193     EC_VECTORCATCH            = 0x3a,
 194     EC_AA64_BKPT              = 0x3c,
 195 };
 196
 197 #define ARM_EL_EC_SHIFT 26
 198 #define ARM_EL_IL_SHIFT 25
 199 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
 200
 201 /* Utility functions for constructing various kinds of syndrome value.
 202  * Note that in general we follow the AArch64 syndrome values; in a
 203  * few cases the value in HSR for exceptions taken to AArch32 Hyp
 204  * mode differs slightly, so if we ever implemented Hyp mode then the
 205  * syndrome value would need some massaging on exception entry.
 206  * (One example of this is that AArch64 defaults to IL bit set for
 207  * exceptions which don't specifically indicate information about the
 208  * trapping instruction, whereas AArch32 defaults to IL bit clear.)
 209  */
 210 static inline uint32_t syn_uncategorized(void)
 211 {
 212     return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 213 }
 214
 215 static inline uint32_t syn_aa64_svc(uint32_t imm16)
 216 {
 217     return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 218 }
 219
 220 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
 221 {
 222     return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 223 }
 224
 225 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
 226 {
 227     return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 228         | (is_thumb ? 0 : ARM_EL_IL);
 229 }
 230
 231 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
 232 {
 233     return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 234 }
 235
 236 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
 237 {
 238     return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 239         | (is_thumb ? 0 : ARM_EL_IL);
 240 }
 241
 242 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
 243                                            int crn, int crm, int rt,
 244                                            int isread)
 245 {
 246     return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
 247         | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
 248         | (crm << 1) | isread;
 249 }
 250
 251 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
 252                                         int crn, int crm, int rt, int isread,
 253                                         bool is_thumb)
 254 {
 255     return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
 256         | (is_thumb ? 0 : ARM_EL_IL)
 257         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 258         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 259 }
 260
 261 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
 262                                         int crn, int crm, int rt, int isread,
 263                                         bool is_thumb)
 264 {
 265     return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
 266         | (is_thumb ? 0 : ARM_EL_IL)
 267         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 268         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 269 }
 270
 271 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
 272                                          int rt, int rt2, int isread,
 273                                          bool is_thumb)
 274 {
 275     return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
 276         | (is_thumb ? 0 : ARM_EL_IL)
 277         | (cv << 24) | (cond << 20) | (opc1 << 16)
 278         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 279 }
 280
 281 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
 282                                          int rt, int rt2, int isread,
 283                                          bool is_thumb)
 284 {
 285     return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
 286         | (is_thumb ? 0 : ARM_EL_IL)
 287         | (cv << 24) | (cond << 20) | (opc1 << 16)
 288         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 289 }
 290
 291 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
 292 {
 293     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
 294         | (is_thumb ? 0 : ARM_EL_IL)
 295         | (cv << 24) | (cond << 20);
 296 }
 297
 298 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
 299 {
 300     return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 301         | (ea << 9) | (s1ptw << 7) | fsc;
 302 }
 303
 304 static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
 305                                       int wnr, int fsc)
 306 {
 307     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 308         | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 309 }
 310
 311 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
 312 {
 313     return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 314         | (isv << 24) | (ex << 6) | 0x22;
 315 }
 316
 317 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
 318 {
 319     return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 320         | (cm << 8) | (wnr << 6) | 0x22;
 321 }
 322
 323 static inline uint32_t syn_breakpoint(int same_el)
 324 {
 325     return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 326         | ARM_EL_IL | 0x22;
 327 }
 328
 329 /* Update a QEMU watchpoint based on the information the guest has set in the
 330  * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
 331  */
 332 void hw_watchpoint_update(ARMCPU *cpu, int n);
 333 /* Update the QEMU watchpoints for every guest watchpoint. This does a
 334  * complete delete-and-reinstate of the QEMU watchpoint list and so is
 335  * suitable for use after migration or on reset.
 336  */
 337 void hw_watchpoint_update_all(ARMCPU *cpu);
 338 /* Update a QEMU breakpoint based on the information the guest has set in the
 339  * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
 340  */
 341 void hw_breakpoint_update(ARMCPU *cpu, int n);
 342 /* Update the QEMU breakpoints for every guest breakpoint. This does a
 343  * complete delete-and-reinstate of the QEMU breakpoint list and so is
 344  * suitable for use after migration or on reset.
 345  */
 346 void hw_breakpoint_update_all(ARMCPU *cpu);
 347
 348 /* Callback function for when a watchpoint or breakpoint triggers. */
 349 void arm_debug_excp_handler(CPUState *cs);
 350
 351 #endif