target-arm/internals.h

   1 /*
   2  * QEMU ARM CPU -- internal functions and types
   3  *
   4  * Copyright (c) 2014 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  *
  20  * This header defines functions, types, etc which need to be shared
  21  * between different source files within target-arm/ but which are
  22  * private to it and not required by the rest of QEMU.
  23  */
  24
  25 #ifndef TARGET_ARM_INTERNALS_H
  26 #define TARGET_ARM_INTERNALS_H
  27
  28 static inline bool excp_is_internal(int excp)
  29 {
  30     /* Return true if this exception number represents a QEMU-internal
  31      * exception that will not be passed to the guest.
  32      */
  33     return excp == EXCP_INTERRUPT
  34         || excp == EXCP_HLT
  35         || excp == EXCP_DEBUG
  36         || excp == EXCP_HALTED
  37         || excp == EXCP_EXCEPTION_EXIT
  38         || excp == EXCP_KERNEL_TRAP
  39         || excp == EXCP_SEMIHOST
  40         || excp == EXCP_STREX;
  41 }
  42
  43 /* Exception names for debug logging; note that not all of these
  44  * precisely correspond to architectural exceptions.
  45  */
  46 static const char * const excnames[] = {
  47     [EXCP_UDEF] = "Undefined Instruction",
  48     [EXCP_SWI] = "SVC",
  49     [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
  50     [EXCP_DATA_ABORT] = "Data Abort",
  51     [EXCP_IRQ] = "IRQ",
  52     [EXCP_FIQ] = "FIQ",
  53     [EXCP_BKPT] = "Breakpoint",
  54     [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
  55     [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
  56     [EXCP_STREX] = "QEMU intercept of STREX",
  57     [EXCP_HVC] = "Hypervisor Call",
  58     [EXCP_HYP_TRAP] = "Hypervisor Trap",
  59     [EXCP_SMC] = "Secure Monitor Call",
  60     [EXCP_VIRQ] = "Virtual IRQ",
  61     [EXCP_VFIQ] = "Virtual FIQ",
  62     [EXCP_SEMIHOST] = "Semihosting call",
  63 };
  64
  65 static inline void arm_log_exception(int idx)
  66 {
  67     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  68         const char *exc = NULL;
  69
  70         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
  71             exc = excnames[idx];
  72         }
  73         if (!exc) {
  74             exc = "unknown";
  75         }
  76         qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
  77     }
  78 }
  79
  80 /* Scale factor for generic timers, ie number of ns per tick.
  81  * This gives a 62.5MHz timer.
  82  */
  83 #define GTIMER_SCALE 16
  84
  85 /*
  86  * For AArch64, map a given EL to an index in the banked_spsr array.
  87  * Note that this mapping and the AArch32 mapping defined in bank_number()
  88  * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
  89  * mandated mapping between each other.
  90  */
  91 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
  92 {
  93     static const unsigned int map[4] = {
  94         [1] = 1, /* EL1.  */
  95         [2] = 6, /* EL2.  */
  96         [3] = 7, /* EL3.  */
  97     };
  98     assert(el >= 1 && el <= 3);
  99     return map[el];
 100 }
 101
 102 int bank_number(int mode);
 103 void switch_mode(CPUARMState *, int);
 104 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 105 void arm_translate_init(void);
 106
 107 enum arm_fprounding {
 108     FPROUNDING_TIEEVEN,
 109     FPROUNDING_POSINF,
 110     FPROUNDING_NEGINF,
 111     FPROUNDING_ZERO,
 112     FPROUNDING_TIEAWAY,
 113     FPROUNDING_ODD
 114 };
 115
 116 int arm_rmode_to_sf(int rmode);
 117
 118 static inline void aarch64_save_sp(CPUARMState *env, int el)
 119 {
 120     if (env->pstate & PSTATE_SP) {
 121         env->sp_el[el] = env->xregs[31];
 122     } else {
 123         env->sp_el[0] = env->xregs[31];
 124     }
 125 }
 126
 127 static inline void aarch64_restore_sp(CPUARMState *env, int el)
 128 {
 129     if (env->pstate & PSTATE_SP) {
 130         env->xregs[31] = env->sp_el[el];
 131     } else {
 132         env->xregs[31] = env->sp_el[0];
 133     }
 134 }
 135
 136 static inline void update_spsel(CPUARMState *env, uint32_t imm)
 137 {
 138     unsigned int cur_el = arm_current_el(env);
 139     /* Update PSTATE SPSel bit; this requires us to update the
 140      * working stack pointer in xregs[31].
 141      */
 142     if (!((imm ^ env->pstate) & PSTATE_SP)) {
 143         return;
 144     }
 145     aarch64_save_sp(env, cur_el);
 146     env->pstate = deposit32(env->pstate, 0, 1, imm);
 147
 148     /* We rely on illegal updates to SPsel from EL0 to get trapped
 149      * at translation time.
 150      */
 151     assert(cur_el >= 1 && cur_el <= 3);
 152     aarch64_restore_sp(env, cur_el);
 153 }
 154
 155 /*
 156  * arm_pamax
 157  * @cpu: ARMCPU
 158  *
 159  * Returns the implementation defined bit-width of physical addresses.
 160  * The ARMv8 reference manuals refer to this as PAMax().
 161  */
 162 static inline unsigned int arm_pamax(ARMCPU *cpu)
 163 {
 164     static const unsigned int pamax_map[] = {
 165         [0] = 32,
 166         [1] = 36,
 167         [2] = 40,
 168         [3] = 42,
 169         [4] = 44,
 170         [5] = 48,
 171     };
 172     unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
 173
 174     /* id_aa64mmfr0 is a read-only register so values outside of the
 175      * supported mappings can be considered an implementation error.  */
 176     assert(parange < ARRAY_SIZE(pamax_map));
 177     return pamax_map[parange];
 178 }
 179
 180 /* Return true if extended addresses are enabled.
 181  * This is always the case if our translation regime is 64 bit,
 182  * but depends on TTBCR.EAE for 32 bit.
 183  */
 184 static inline bool extended_addresses_enabled(CPUARMState *env)
 185 {
 186     TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
 187     return arm_el_is_aa64(env, 1) ||
 188            (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
 189 }
 190
 191 /* Valid Syndrome Register EC field values */
 192 enum arm_exception_class {
 193     EC_UNCATEGORIZED          = 0x00,
 194     EC_WFX_TRAP               = 0x01,
 195     EC_CP15RTTRAP             = 0x03,
 196     EC_CP15RRTTRAP            = 0x04,
 197     EC_CP14RTTRAP             = 0x05,
 198     EC_CP14DTTRAP             = 0x06,
 199     EC_ADVSIMDFPACCESSTRAP    = 0x07,
 200     EC_FPIDTRAP               = 0x08,
 201     EC_CP14RRTTRAP            = 0x0c,
 202     EC_ILLEGALSTATE           = 0x0e,
 203     EC_AA32_SVC               = 0x11,
 204     EC_AA32_HVC               = 0x12,
 205     EC_AA32_SMC               = 0x13,
 206     EC_AA64_SVC               = 0x15,
 207     EC_AA64_HVC               = 0x16,
 208     EC_AA64_SMC               = 0x17,
 209     EC_SYSTEMREGISTERTRAP     = 0x18,
 210     EC_INSNABORT              = 0x20,
 211     EC_INSNABORT_SAME_EL      = 0x21,
 212     EC_PCALIGNMENT            = 0x22,
 213     EC_DATAABORT              = 0x24,
 214     EC_DATAABORT_SAME_EL      = 0x25,
 215     EC_SPALIGNMENT            = 0x26,
 216     EC_AA32_FPTRAP            = 0x28,
 217     EC_AA64_FPTRAP            = 0x2c,
 218     EC_SERROR                 = 0x2f,
 219     EC_BREAKPOINT             = 0x30,
 220     EC_BREAKPOINT_SAME_EL     = 0x31,
 221     EC_SOFTWARESTEP           = 0x32,
 222     EC_SOFTWARESTEP_SAME_EL   = 0x33,
 223     EC_WATCHPOINT             = 0x34,
 224     EC_WATCHPOINT_SAME_EL     = 0x35,
 225     EC_AA32_BKPT              = 0x38,
 226     EC_VECTORCATCH            = 0x3a,
 227     EC_AA64_BKPT              = 0x3c,
 228 };
 229
 230 #define ARM_EL_EC_SHIFT 26
 231 #define ARM_EL_IL_SHIFT 25
 232 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
 233
 234 /* Utility functions for constructing various kinds of syndrome value.
 235  * Note that in general we follow the AArch64 syndrome values; in a
 236  * few cases the value in HSR for exceptions taken to AArch32 Hyp
 237  * mode differs slightly, so if we ever implemented Hyp mode then the
 238  * syndrome value would need some massaging on exception entry.
 239  * (One example of this is that AArch64 defaults to IL bit set for
 240  * exceptions which don't specifically indicate information about the
 241  * trapping instruction, whereas AArch32 defaults to IL bit clear.)
 242  */
 243 static inline uint32_t syn_uncategorized(void)
 244 {
 245     return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 246 }
 247
 248 static inline uint32_t syn_aa64_svc(uint32_t imm16)
 249 {
 250     return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 251 }
 252
 253 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
 254 {
 255     return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 256 }
 257
 258 static inline uint32_t syn_aa64_smc(uint32_t imm16)
 259 {
 260     return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 261 }
 262
 263 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
 264 {
 265     return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 266         | (is_thumb ? 0 : ARM_EL_IL);
 267 }
 268
 269 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
 270 {
 271     return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 272 }
 273
 274 static inline uint32_t syn_aa32_smc(void)
 275 {
 276     return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 277 }
 278
 279 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
 280 {
 281     return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 282 }
 283
 284 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
 285 {
 286     return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 287         | (is_thumb ? 0 : ARM_EL_IL);
 288 }
 289
 290 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
 291                                            int crn, int crm, int rt,
 292                                            int isread)
 293 {
 294     return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
 295         | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
 296         | (crm << 1) | isread;
 297 }
 298
 299 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
 300                                         int crn, int crm, int rt, int isread,
 301                                         bool is_thumb)
 302 {
 303     return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
 304         | (is_thumb ? 0 : ARM_EL_IL)
 305         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 306         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 307 }
 308
 309 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
 310                                         int crn, int crm, int rt, int isread,
 311                                         bool is_thumb)
 312 {
 313     return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
 314         | (is_thumb ? 0 : ARM_EL_IL)
 315         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 316         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 317 }
 318
 319 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
 320                                          int rt, int rt2, int isread,
 321                                          bool is_thumb)
 322 {
 323     return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
 324         | (is_thumb ? 0 : ARM_EL_IL)
 325         | (cv << 24) | (cond << 20) | (opc1 << 16)
 326         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 327 }
 328
 329 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
 330                                          int rt, int rt2, int isread,
 331                                          bool is_thumb)
 332 {
 333     return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
 334         | (is_thumb ? 0 : ARM_EL_IL)
 335         | (cv << 24) | (cond << 20) | (opc1 << 16)
 336         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 337 }
 338
 339 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
 340 {
 341     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
 342         | (is_thumb ? 0 : ARM_EL_IL)
 343         | (cv << 24) | (cond << 20);
 344 }
 345
 346 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
 347 {
 348     return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 349         | (ea << 9) | (s1ptw << 7) | fsc;
 350 }
 351
 352 static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
 353                                       int wnr, int fsc)
 354 {
 355     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 356         | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 357 }
 358
 359 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
 360 {
 361     return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 362         | (isv << 24) | (ex << 6) | 0x22;
 363 }
 364
 365 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
 366 {
 367     return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 368         | (cm << 8) | (wnr << 6) | 0x22;
 369 }
 370
 371 static inline uint32_t syn_breakpoint(int same_el)
 372 {
 373     return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 374         | ARM_EL_IL | 0x22;
 375 }
 376
 377 static inline uint32_t syn_wfx(int cv, int cond, int ti)
 378 {
 379     return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
 380            (cv << 24) | (cond << 20) | ti;
 381 }
 382
 383 /* Update a QEMU watchpoint based on the information the guest has set in the
 384  * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
 385  */
 386 void hw_watchpoint_update(ARMCPU *cpu, int n);
 387 /* Update the QEMU watchpoints for every guest watchpoint. This does a
 388  * complete delete-and-reinstate of the QEMU watchpoint list and so is
 389  * suitable for use after migration or on reset.
 390  */
 391 void hw_watchpoint_update_all(ARMCPU *cpu);
 392 /* Update a QEMU breakpoint based on the information the guest has set in the
 393  * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
 394  */
 395 void hw_breakpoint_update(ARMCPU *cpu, int n);
 396 /* Update the QEMU breakpoints for every guest breakpoint. This does a
 397  * complete delete-and-reinstate of the QEMU breakpoint list and so is
 398  * suitable for use after migration or on reset.
 399  */
 400 void hw_breakpoint_update_all(ARMCPU *cpu);
 401
 402 /* Callback function for when a watchpoint or breakpoint triggers. */
 403 void arm_debug_excp_handler(CPUState *cs);
 404
 405 #ifdef CONFIG_USER_ONLY
 406 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
 407 {
 408     return false;
 409 }
 410 #else
 411 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
 412 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
 413 /* Actually handle a PSCI call */
 414 void arm_handle_psci_call(ARMCPU *cpu);
 415 #endif
 416
 417 /**
 418  * ARMMMUFaultInfo: Information describing an ARM MMU Fault
 419  * @s2addr: Address that caused a fault at stage 2
 420  * @stage2: True if we faulted at stage 2
 421  * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
 422  */
 423 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 424 struct ARMMMUFaultInfo {
 425     target_ulong s2addr;
 426     bool stage2;
 427     bool s1ptw;
 428 };
 429
 430 /* Do a page table walk and add page to TLB if possible */
 431 bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
 432                   uint32_t *fsr, ARMMMUFaultInfo *fi);
 433
 434 #endif