target-arm/kvm64.c

   1 /*
   2  * ARM implementation of KVM hooks, 64 bit specific code
   3  *
   4  * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include <stdio.h>
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/timer.h"
  20 #include "sysemu/sysemu.h"
  21 #include "sysemu/kvm.h"
  22 #include "kvm_arm.h"
  23 #include "cpu.h"
  24 #include "internals.h"
  25 #include "hw/arm/arm.h"
  26
  27 static inline void set_feature(uint64_t *features, int feature)
  28 {
  29     *features |= 1ULL << feature;
  30 }
  31
  32 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
  33 {
  34     /* Identify the feature bits corresponding to the host CPU, and
  35      * fill out the ARMHostCPUClass fields accordingly. To do this
  36      * we have to create a scratch VM, create a single CPU inside it,
  37      * and then query that CPU for the relevant ID registers.
  38      * For AArch64 we currently don't care about ID registers at
  39      * all; we just want to know the CPU type.
  40      */
  41     int fdarray[3];
  42     uint64_t features = 0;
  43     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  44      * we know these will only support creating one kind of guest CPU,
  45      * which is its preferred CPU type. Fortunately these old kernels
  46      * support only a very limited number of CPUs.
  47      */
  48     static const uint32_t cpus_to_try[] = {
  49         KVM_ARM_TARGET_AEM_V8,
  50         KVM_ARM_TARGET_FOUNDATION_V8,
  51         KVM_ARM_TARGET_CORTEX_A57,
  52         QEMU_KVM_ARM_TARGET_NONE
  53     };
  54     struct kvm_vcpu_init init;
  55
  56     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  57         return false;
  58     }
  59
  60     ahcc->target = init.target;
  61     ahcc->dtb_compatible = "arm,arm-v8";
  62
  63     kvm_arm_destroy_scratch_host_vcpu(fdarray);
  64
  65    /* We can assume any KVM supporting CPU is at least a v8
  66      * with VFPv4+Neon; this in turn implies most of the other
  67      * feature bits.
  68      */
  69     set_feature(&features, ARM_FEATURE_V8);
  70     set_feature(&features, ARM_FEATURE_VFP4);
  71     set_feature(&features, ARM_FEATURE_NEON);
  72     set_feature(&features, ARM_FEATURE_AARCH64);
  73
  74     ahcc->features = features;
  75
  76     return true;
  77 }
  78
  79 int kvm_arch_init_vcpu(CPUState *cs)
  80 {
  81     int ret;
  82     ARMCPU *cpu = ARM_CPU(cs);
  83
  84     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
  85         !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
  86         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
  87         return -EINVAL;
  88     }
  89
  90     /* Determine init features for this CPU */
  91     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
  92     if (cpu->start_powered_off) {
  93         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
  94     }
  95     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
  96         cpu->psci_version = 2;
  97         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
  98     }
  99
 100     /* Do KVM_ARM_VCPU_INIT ioctl */
 101     ret = kvm_arm_vcpu_init(cs);
 102     if (ret) {
 103         return ret;
 104     }
 105
 106     return kvm_arm_init_cpreg_list(cpu);
 107 }
 108
 109 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 110 {
 111     /* Return true if the regidx is a register we should synchronize
 112      * via the cpreg_tuples array (ie is not a core reg we sync by
 113      * hand in kvm_arch_get/put_registers())
 114      */
 115     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 116     case KVM_REG_ARM_CORE:
 117         return false;
 118     default:
 119         return true;
 120     }
 121 }
 122
 123 #define AARCH64_CORE_REG(x)   (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
 124                  KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
 125
 126 int kvm_arch_put_registers(CPUState *cs, int level)
 127 {
 128     struct kvm_one_reg reg;
 129     uint64_t val;
 130     int i;
 131     int ret;
 132
 133     ARMCPU *cpu = ARM_CPU(cs);
 134     CPUARMState *env = &cpu->env;
 135
 136     for (i = 0; i < 31; i++) {
 137         reg.id = AARCH64_CORE_REG(regs.regs[i]);
 138         reg.addr = (uintptr_t) &env->xregs[i];
 139         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 140         if (ret) {
 141             return ret;
 142         }
 143     }
 144
 145     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
 146      * QEMU side we keep the current SP in xregs[31] as well.
 147      */
 148     aarch64_save_sp(env, 1);
 149
 150     reg.id = AARCH64_CORE_REG(regs.sp);
 151     reg.addr = (uintptr_t) &env->sp_el[0];
 152     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 153     if (ret) {
 154         return ret;
 155     }
 156
 157     reg.id = AARCH64_CORE_REG(sp_el1);
 158     reg.addr = (uintptr_t) &env->sp_el[1];
 159     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 160     if (ret) {
 161         return ret;
 162     }
 163
 164     /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
 165     val = pstate_read(env);
 166     reg.id = AARCH64_CORE_REG(regs.pstate);
 167     reg.addr = (uintptr_t) &val;
 168     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 169     if (ret) {
 170         return ret;
 171     }
 172
 173     reg.id = AARCH64_CORE_REG(regs.pc);
 174     reg.addr = (uintptr_t) &env->pc;
 175     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 176     if (ret) {
 177         return ret;
 178     }
 179
 180     reg.id = AARCH64_CORE_REG(elr_el1);
 181     reg.addr = (uintptr_t) &env->elr_el[1];
 182     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 183     if (ret) {
 184         return ret;
 185     }
 186
 187     for (i = 0; i < KVM_NR_SPSR; i++) {
 188         reg.id = AARCH64_CORE_REG(spsr[i]);
 189         reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
 190         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 191         if (ret) {
 192             return ret;
 193         }
 194     }
 195
 196     if (!write_list_to_kvmstate(cpu)) {
 197         return EINVAL;
 198     }
 199
 200     /* TODO:
 201      * FP state
 202      */
 203     return ret;
 204 }
 205
 206 int kvm_arch_get_registers(CPUState *cs)
 207 {
 208     struct kvm_one_reg reg;
 209     uint64_t val;
 210     int i;
 211     int ret;
 212
 213     ARMCPU *cpu = ARM_CPU(cs);
 214     CPUARMState *env = &cpu->env;
 215
 216     for (i = 0; i < 31; i++) {
 217         reg.id = AARCH64_CORE_REG(regs.regs[i]);
 218         reg.addr = (uintptr_t) &env->xregs[i];
 219         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 220         if (ret) {
 221             return ret;
 222         }
 223     }
 224
 225     reg.id = AARCH64_CORE_REG(regs.sp);
 226     reg.addr = (uintptr_t) &env->sp_el[0];
 227     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 228     if (ret) {
 229         return ret;
 230     }
 231
 232     reg.id = AARCH64_CORE_REG(sp_el1);
 233     reg.addr = (uintptr_t) &env->sp_el[1];
 234     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 235     if (ret) {
 236         return ret;
 237     }
 238
 239     reg.id = AARCH64_CORE_REG(regs.pstate);
 240     reg.addr = (uintptr_t) &val;
 241     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 242     if (ret) {
 243         return ret;
 244     }
 245     pstate_write(env, val);
 246
 247     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
 248      * QEMU side we keep the current SP in xregs[31] as well.
 249      */
 250     aarch64_restore_sp(env, 1);
 251
 252     reg.id = AARCH64_CORE_REG(regs.pc);
 253     reg.addr = (uintptr_t) &env->pc;
 254     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 255     if (ret) {
 256         return ret;
 257     }
 258
 259     reg.id = AARCH64_CORE_REG(elr_el1);
 260     reg.addr = (uintptr_t) &env->elr_el[1];
 261     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 262     if (ret) {
 263         return ret;
 264     }
 265
 266     for (i = 0; i < KVM_NR_SPSR; i++) {
 267         reg.id = AARCH64_CORE_REG(spsr[i]);
 268         reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
 269         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 270         if (ret) {
 271             return ret;
 272         }
 273     }
 274
 275     if (!write_kvmstate_to_list(cpu)) {
 276         return EINVAL;
 277     }
 278     /* Note that it's OK to have registers which aren't in CPUState,
 279      * so we can ignore a failure return here.
 280      */
 281     write_list_to_cpustate(cpu);
 282
 283     /* TODO: other registers */
 284     return ret;
 285 }