1 #include "qemu/osdep.h"
4 #include "qemu/error-report.h"
5 #include "sysemu/kvm.h"
8 #include "migration/cpu.h"
10 static bool vfp_needed(void *opaque
)
13 CPUARMState
*env
= &cpu
->env
;
15 return arm_feature(env
, ARM_FEATURE_VFP
);
18 static int get_fpscr(QEMUFile
*f
, void *opaque
, size_t size
)
21 CPUARMState
*env
= &cpu
->env
;
22 uint32_t val
= qemu_get_be32(f
);
24 vfp_set_fpscr(env
, val
);
28 static void put_fpscr(QEMUFile
*f
, void *opaque
, size_t size
)
31 CPUARMState
*env
= &cpu
->env
;
33 qemu_put_be32(f
, vfp_get_fpscr(env
));
36 static const VMStateInfo vmstate_fpscr
= {
42 static const VMStateDescription vmstate_vfp
= {
45 .minimum_version_id
= 3,
47 .fields
= (VMStateField
[]) {
48 VMSTATE_FLOAT64_ARRAY(env
.vfp
.regs
, ARMCPU
, 64),
49 /* The xregs array is a little awkward because element 1 (FPSCR)
50 * requires a specific accessor, so we have to split it up in
53 VMSTATE_UINT32(env
.vfp
.xregs
[0], ARMCPU
),
54 VMSTATE_UINT32_SUB_ARRAY(env
.vfp
.xregs
, ARMCPU
, 2, 14),
58 .size
= sizeof(uint32_t),
59 .info
= &vmstate_fpscr
,
67 static bool iwmmxt_needed(void *opaque
)
70 CPUARMState
*env
= &cpu
->env
;
72 return arm_feature(env
, ARM_FEATURE_IWMMXT
);
75 static const VMStateDescription vmstate_iwmmxt
= {
78 .minimum_version_id
= 1,
79 .needed
= iwmmxt_needed
,
80 .fields
= (VMStateField
[]) {
81 VMSTATE_UINT64_ARRAY(env
.iwmmxt
.regs
, ARMCPU
, 16),
82 VMSTATE_UINT32_ARRAY(env
.iwmmxt
.cregs
, ARMCPU
, 16),
87 static bool m_needed(void *opaque
)
90 CPUARMState
*env
= &cpu
->env
;
92 return arm_feature(env
, ARM_FEATURE_M
);
95 static const VMStateDescription vmstate_m
= {
98 .minimum_version_id
= 1,
100 .fields
= (VMStateField
[]) {
101 VMSTATE_UINT32(env
.v7m
.other_sp
, ARMCPU
),
102 VMSTATE_UINT32(env
.v7m
.vecbase
, ARMCPU
),
103 VMSTATE_UINT32(env
.v7m
.basepri
, ARMCPU
),
104 VMSTATE_UINT32(env
.v7m
.control
, ARMCPU
),
105 VMSTATE_INT32(env
.v7m
.current_sp
, ARMCPU
),
106 VMSTATE_INT32(env
.v7m
.exception
, ARMCPU
),
107 VMSTATE_END_OF_LIST()
111 static bool thumb2ee_needed(void *opaque
)
113 ARMCPU
*cpu
= opaque
;
114 CPUARMState
*env
= &cpu
->env
;
116 return arm_feature(env
, ARM_FEATURE_THUMB2EE
);
119 static const VMStateDescription vmstate_thumb2ee
= {
120 .name
= "cpu/thumb2ee",
122 .minimum_version_id
= 1,
123 .needed
= thumb2ee_needed
,
124 .fields
= (VMStateField
[]) {
125 VMSTATE_UINT32(env
.teecr
, ARMCPU
),
126 VMSTATE_UINT32(env
.teehbr
, ARMCPU
),
127 VMSTATE_END_OF_LIST()
131 static bool pmsav7_needed(void *opaque
)
133 ARMCPU
*cpu
= opaque
;
134 CPUARMState
*env
= &cpu
->env
;
136 return arm_feature(env
, ARM_FEATURE_MPU
) &&
137 arm_feature(env
, ARM_FEATURE_V7
);
140 static bool pmsav7_rgnr_vmstate_validate(void *opaque
, int version_id
)
142 ARMCPU
*cpu
= opaque
;
144 return cpu
->env
.cp15
.c6_rgnr
< cpu
->pmsav7_dregion
;
147 static const VMStateDescription vmstate_pmsav7
= {
148 .name
= "cpu/pmsav7",
150 .minimum_version_id
= 1,
151 .needed
= pmsav7_needed
,
152 .fields
= (VMStateField
[]) {
153 VMSTATE_VARRAY_UINT32(env
.pmsav7
.drbar
, ARMCPU
, pmsav7_dregion
, 0,
154 vmstate_info_uint32
, uint32_t),
155 VMSTATE_VARRAY_UINT32(env
.pmsav7
.drsr
, ARMCPU
, pmsav7_dregion
, 0,
156 vmstate_info_uint32
, uint32_t),
157 VMSTATE_VARRAY_UINT32(env
.pmsav7
.dracr
, ARMCPU
, pmsav7_dregion
, 0,
158 vmstate_info_uint32
, uint32_t),
159 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate
),
160 VMSTATE_END_OF_LIST()
164 static int get_cpsr(QEMUFile
*f
, void *opaque
, size_t size
)
166 ARMCPU
*cpu
= opaque
;
167 CPUARMState
*env
= &cpu
->env
;
168 uint32_t val
= qemu_get_be32(f
);
170 env
->aarch64
= ((val
& PSTATE_nRW
) == 0);
173 pstate_write(env
, val
);
177 cpsr_write(env
, val
, 0xffffffff, CPSRWriteRaw
);
181 static void put_cpsr(QEMUFile
*f
, void *opaque
, size_t size
)
183 ARMCPU
*cpu
= opaque
;
184 CPUARMState
*env
= &cpu
->env
;
188 val
= pstate_read(env
);
190 val
= cpsr_read(env
);
193 qemu_put_be32(f
, val
);
196 static const VMStateInfo vmstate_cpsr
= {
202 static void cpu_pre_save(void *opaque
)
204 ARMCPU
*cpu
= opaque
;
207 if (!write_kvmstate_to_list(cpu
)) {
208 /* This should never fail */
212 if (!write_cpustate_to_list(cpu
)) {
213 /* This should never fail. */
218 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
219 memcpy(cpu
->cpreg_vmstate_indexes
, cpu
->cpreg_indexes
,
220 cpu
->cpreg_array_len
* sizeof(uint64_t));
221 memcpy(cpu
->cpreg_vmstate_values
, cpu
->cpreg_values
,
222 cpu
->cpreg_array_len
* sizeof(uint64_t));
225 static int cpu_post_load(void *opaque
, int version_id
)
227 ARMCPU
*cpu
= opaque
;
230 /* Update the values list from the incoming migration data.
231 * Anything in the incoming data which we don't know about is
232 * a migration failure; anything we know about but the incoming
233 * data doesn't specify retains its current (reset) value.
234 * The indexes list remains untouched -- we only inspect the
235 * incoming migration index list so we can match the values array
236 * entries with the right slots in our own values array.
239 for (i
= 0, v
= 0; i
< cpu
->cpreg_array_len
240 && v
< cpu
->cpreg_vmstate_array_len
; i
++) {
241 if (cpu
->cpreg_vmstate_indexes
[v
] > cpu
->cpreg_indexes
[i
]) {
242 /* register in our list but not incoming : skip it */
245 if (cpu
->cpreg_vmstate_indexes
[v
] < cpu
->cpreg_indexes
[i
]) {
246 /* register in their list but not ours: fail migration */
249 /* matching register, copy the value over */
250 cpu
->cpreg_values
[i
] = cpu
->cpreg_vmstate_values
[v
];
255 if (!write_list_to_kvmstate(cpu
, KVM_PUT_FULL_STATE
)) {
258 /* Note that it's OK for the TCG side not to know about
259 * every register in the list; KVM is authoritative if
262 write_list_to_cpustate(cpu
);
264 if (!write_list_to_cpustate(cpu
)) {
269 hw_breakpoint_update_all(cpu
);
270 hw_watchpoint_update_all(cpu
);
275 const VMStateDescription vmstate_arm_cpu
= {
278 .minimum_version_id
= 22,
279 .pre_save
= cpu_pre_save
,
280 .post_load
= cpu_post_load
,
281 .fields
= (VMStateField
[]) {
282 VMSTATE_UINT32_ARRAY(env
.regs
, ARMCPU
, 16),
283 VMSTATE_UINT64_ARRAY(env
.xregs
, ARMCPU
, 32),
284 VMSTATE_UINT64(env
.pc
, ARMCPU
),
288 .size
= sizeof(uint32_t),
289 .info
= &vmstate_cpsr
,
293 VMSTATE_UINT32(env
.spsr
, ARMCPU
),
294 VMSTATE_UINT64_ARRAY(env
.banked_spsr
, ARMCPU
, 8),
295 VMSTATE_UINT32_ARRAY(env
.banked_r13
, ARMCPU
, 8),
296 VMSTATE_UINT32_ARRAY(env
.banked_r14
, ARMCPU
, 8),
297 VMSTATE_UINT32_ARRAY(env
.usr_regs
, ARMCPU
, 5),
298 VMSTATE_UINT32_ARRAY(env
.fiq_regs
, ARMCPU
, 5),
299 VMSTATE_UINT64_ARRAY(env
.elr_el
, ARMCPU
, 4),
300 VMSTATE_UINT64_ARRAY(env
.sp_el
, ARMCPU
, 4),
301 /* The length-check must come before the arrays to avoid
302 * incoming data possibly overflowing the array.
304 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len
, ARMCPU
),
305 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes
, ARMCPU
,
306 cpreg_vmstate_array_len
,
307 0, vmstate_info_uint64
, uint64_t),
308 VMSTATE_VARRAY_INT32(cpreg_vmstate_values
, ARMCPU
,
309 cpreg_vmstate_array_len
,
310 0, vmstate_info_uint64
, uint64_t),
311 VMSTATE_UINT64(env
.exclusive_addr
, ARMCPU
),
312 VMSTATE_UINT64(env
.exclusive_val
, ARMCPU
),
313 VMSTATE_UINT64(env
.exclusive_high
, ARMCPU
),
314 VMSTATE_UINT64(env
.features
, ARMCPU
),
315 VMSTATE_UINT32(env
.exception
.syndrome
, ARMCPU
),
316 VMSTATE_UINT32(env
.exception
.fsr
, ARMCPU
),
317 VMSTATE_UINT64(env
.exception
.vaddress
, ARMCPU
),
318 VMSTATE_TIMER_PTR(gt_timer
[GTIMER_PHYS
], ARMCPU
),
319 VMSTATE_TIMER_PTR(gt_timer
[GTIMER_VIRT
], ARMCPU
),
320 VMSTATE_BOOL(powered_off
, ARMCPU
),
321 VMSTATE_END_OF_LIST()
323 .subsections
= (const VMStateDescription
*[]) {
333 const char *gicv3_class_name(void)
335 if (kvm_irqchip_in_kernel()) {
336 #ifdef TARGET_AARCH64
337 return "kvm-arm-gicv3";
339 error_report("KVM GICv3 acceleration is not supported on this "
343 /* TODO: Software emulation is not implemented yet */
344 error_report("KVM is currently required for GICv3 emulation");