target-arm/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "sysemu/kvm.h"
   4 #include "kvm_arm.h"
   5 #include "internals.h"
   6
   7 static bool vfp_needed(void *opaque)
   8 {
   9     ARMCPU *cpu = opaque;
  10     CPUARMState *env = &cpu->env;
  11
  12     return arm_feature(env, ARM_FEATURE_VFP);
  13 }
  14
  15 static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
  16 {
  17     ARMCPU *cpu = opaque;
  18     CPUARMState *env = &cpu->env;
  19     uint32_t val = qemu_get_be32(f);
  20
  21     vfp_set_fpscr(env, val);
  22     return 0;
  23 }
  24
  25 static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
  26 {
  27     ARMCPU *cpu = opaque;
  28     CPUARMState *env = &cpu->env;
  29
  30     qemu_put_be32(f, vfp_get_fpscr(env));
  31 }
  32
  33 static const VMStateInfo vmstate_fpscr = {
  34     .name = "fpscr",
  35     .get = get_fpscr,
  36     .put = put_fpscr,
  37 };
  38
  39 static const VMStateDescription vmstate_vfp = {
  40     .name = "cpu/vfp",
  41     .version_id = 3,
  42     .minimum_version_id = 3,
  43     .needed = vfp_needed,
  44     .fields = (VMStateField[]) {
  45         VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
  46         /* The xregs array is a little awkward because element 1 (FPSCR)
  47          * requires a specific accessor, so we have to split it up in
  48          * the vmstate:
  49          */
  50         VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
  51         VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
  52         {
  53             .name = "fpscr",
  54             .version_id = 0,
  55             .size = sizeof(uint32_t),
  56             .info = &vmstate_fpscr,
  57             .flags = VMS_SINGLE,
  58             .offset = 0,
  59         },
  60         VMSTATE_END_OF_LIST()
  61     }
  62 };
  63
  64 static bool iwmmxt_needed(void *opaque)
  65 {
  66     ARMCPU *cpu = opaque;
  67     CPUARMState *env = &cpu->env;
  68
  69     return arm_feature(env, ARM_FEATURE_IWMMXT);
  70 }
  71
  72 static const VMStateDescription vmstate_iwmmxt = {
  73     .name = "cpu/iwmmxt",
  74     .version_id = 1,
  75     .minimum_version_id = 1,
  76     .needed = iwmmxt_needed,
  77     .fields = (VMStateField[]) {
  78         VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
  79         VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
  80         VMSTATE_END_OF_LIST()
  81     }
  82 };
  83
  84 static bool m_needed(void *opaque)
  85 {
  86     ARMCPU *cpu = opaque;
  87     CPUARMState *env = &cpu->env;
  88
  89     return arm_feature(env, ARM_FEATURE_M);
  90 }
  91
  92 static const VMStateDescription vmstate_m = {
  93     .name = "cpu/m",
  94     .version_id = 1,
  95     .minimum_version_id = 1,
  96     .needed = m_needed,
  97     .fields = (VMStateField[]) {
  98         VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
  99         VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
 100         VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
 101         VMSTATE_UINT32(env.v7m.control, ARMCPU),
 102         VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
 103         VMSTATE_INT32(env.v7m.exception, ARMCPU),
 104         VMSTATE_END_OF_LIST()
 105     }
 106 };
 107
 108 static bool thumb2ee_needed(void *opaque)
 109 {
 110     ARMCPU *cpu = opaque;
 111     CPUARMState *env = &cpu->env;
 112
 113     return arm_feature(env, ARM_FEATURE_THUMB2EE);
 114 }
 115
 116 static const VMStateDescription vmstate_thumb2ee = {
 117     .name = "cpu/thumb2ee",
 118     .version_id = 1,
 119     .minimum_version_id = 1,
 120     .needed = thumb2ee_needed,
 121     .fields = (VMStateField[]) {
 122         VMSTATE_UINT32(env.teecr, ARMCPU),
 123         VMSTATE_UINT32(env.teehbr, ARMCPU),
 124         VMSTATE_END_OF_LIST()
 125     }
 126 };
 127
 128 static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
 129 {
 130     ARMCPU *cpu = opaque;
 131     CPUARMState *env = &cpu->env;
 132     uint32_t val = qemu_get_be32(f);
 133
 134     env->aarch64 = ((val & PSTATE_nRW) == 0);
 135
 136     if (is_a64(env)) {
 137         pstate_write(env, val);
 138         return 0;
 139     }
 140
 141     /* Avoid mode switch when restoring CPSR */
 142     env->uncached_cpsr = val & CPSR_M;
 143     cpsr_write(env, val, 0xffffffff);
 144     return 0;
 145 }
 146
 147 static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
 148 {
 149     ARMCPU *cpu = opaque;
 150     CPUARMState *env = &cpu->env;
 151     uint32_t val;
 152
 153     if (is_a64(env)) {
 154         val = pstate_read(env);
 155     } else {
 156         val = cpsr_read(env);
 157     }
 158
 159     qemu_put_be32(f, val);
 160 }
 161
 162 static const VMStateInfo vmstate_cpsr = {
 163     .name = "cpsr",
 164     .get = get_cpsr,
 165     .put = put_cpsr,
 166 };
 167
 168 static void cpu_pre_save(void *opaque)
 169 {
 170     ARMCPU *cpu = opaque;
 171
 172     if (kvm_enabled()) {
 173         if (!write_kvmstate_to_list(cpu)) {
 174             /* This should never fail */
 175             abort();
 176         }
 177     } else {
 178         if (!write_cpustate_to_list(cpu)) {
 179             /* This should never fail. */
 180             abort();
 181         }
 182     }
 183
 184     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 185     memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
 186            cpu->cpreg_array_len * sizeof(uint64_t));
 187     memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
 188            cpu->cpreg_array_len * sizeof(uint64_t));
 189 }
 190
 191 static int cpu_post_load(void *opaque, int version_id)
 192 {
 193     ARMCPU *cpu = opaque;
 194     int i, v;
 195
 196     /* Update the values list from the incoming migration data.
 197      * Anything in the incoming data which we don't know about is
 198      * a migration failure; anything we know about but the incoming
 199      * data doesn't specify retains its current (reset) value.
 200      * The indexes list remains untouched -- we only inspect the
 201      * incoming migration index list so we can match the values array
 202      * entries with the right slots in our own values array.
 203      */
 204
 205     for (i = 0, v = 0; i < cpu->cpreg_array_len
 206              && v < cpu->cpreg_vmstate_array_len; i++) {
 207         if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
 208             /* register in our list but not incoming : skip it */
 209             continue;
 210         }
 211         if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
 212             /* register in their list but not ours: fail migration */
 213             return -1;
 214         }
 215         /* matching register, copy the value over */
 216         cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
 217         v++;
 218     }
 219
 220     if (kvm_enabled()) {
 221         if (!write_list_to_kvmstate(cpu)) {
 222             return -1;
 223         }
 224         /* Note that it's OK for the TCG side not to know about
 225          * every register in the list; KVM is authoritative if
 226          * we're using it.
 227          */
 228         write_list_to_cpustate(cpu);
 229     } else {
 230         if (!write_list_to_cpustate(cpu)) {
 231             return -1;
 232         }
 233     }
 234
 235     hw_breakpoint_update_all(cpu);
 236     hw_watchpoint_update_all(cpu);
 237
 238     return 0;
 239 }
 240
 241 const VMStateDescription vmstate_arm_cpu = {
 242     .name = "cpu",
 243     .version_id = 22,
 244     .minimum_version_id = 22,
 245     .pre_save = cpu_pre_save,
 246     .post_load = cpu_post_load,
 247     .fields = (VMStateField[]) {
 248         VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
 249         VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
 250         VMSTATE_UINT64(env.pc, ARMCPU),
 251         {
 252             .name = "cpsr",
 253             .version_id = 0,
 254             .size = sizeof(uint32_t),
 255             .info = &vmstate_cpsr,
 256             .flags = VMS_SINGLE,
 257             .offset = 0,
 258         },
 259         VMSTATE_UINT32(env.spsr, ARMCPU),
 260         VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
 261         VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
 262         VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
 263         VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
 264         VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
 265         VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
 266         VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
 267         /* The length-check must come before the arrays to avoid
 268          * incoming data possibly overflowing the array.
 269          */
 270         VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
 271         VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
 272                              cpreg_vmstate_array_len,
 273                              0, vmstate_info_uint64, uint64_t),
 274         VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
 275                              cpreg_vmstate_array_len,
 276                              0, vmstate_info_uint64, uint64_t),
 277         VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
 278         VMSTATE_UINT64(env.exclusive_val, ARMCPU),
 279         VMSTATE_UINT64(env.exclusive_high, ARMCPU),
 280         VMSTATE_UINT64(env.features, ARMCPU),
 281         VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
 282         VMSTATE_UINT32(env.exception.fsr, ARMCPU),
 283         VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
 284         VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
 285         VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
 286         VMSTATE_BOOL(powered_off, ARMCPU),
 287         VMSTATE_END_OF_LIST()
 288     },
 289     .subsections = (const VMStateDescription*[]) {
 290         &vmstate_vfp,
 291         &vmstate_iwmmxt,
 292         &vmstate_m,
 293         &vmstate_thumb2ee,
 294         NULL
 295     }
 296 };