4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
29 #include "translate.h"
30 #include "internals.h"
31 #include "qemu/host-utils.h"
33 #include "exec/gen-icount.h"
35 #include "exec/helper-proto.h"
36 #include "exec/helper-gen.h"
38 static TCGv_i64 cpu_X
[32];
39 static TCGv_i64 cpu_pc
;
40 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_addr
;
44 static TCGv_i64 cpu_exclusive_val
;
45 static TCGv_i64 cpu_exclusive_high
;
46 #ifdef CONFIG_USER_ONLY
47 static TCGv_i64 cpu_exclusive_test
;
48 static TCGv_i32 cpu_exclusive_info
;
51 static const char *regnames
[] = {
52 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
53 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
54 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
55 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
59 A64_SHIFT_TYPE_LSL
= 0,
60 A64_SHIFT_TYPE_LSR
= 1,
61 A64_SHIFT_TYPE_ASR
= 2,
62 A64_SHIFT_TYPE_ROR
= 3
65 /* Table based decoder typedefs - used when the relevant bits for decode
66 * are too awkwardly scattered across the instruction (eg SIMD).
68 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
70 typedef struct AArch64DecodeTable
{
73 AArch64DecodeFn
*disas_fn
;
76 /* Function prototype for gen_ functions for calling Neon helpers */
77 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
78 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
79 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
80 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
81 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
82 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
83 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
84 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
85 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
86 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
87 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
89 /* initialize TCG globals. */
90 void a64_translate_init(void)
94 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
95 offsetof(CPUARMState
, pc
),
97 for (i
= 0; i
< 32; i
++) {
98 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
99 offsetof(CPUARMState
, xregs
[i
]),
103 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
104 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
105 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
106 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
108 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
109 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
110 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
111 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
112 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
113 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
114 #ifdef CONFIG_USER_ONLY
115 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
116 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
117 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
118 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
122 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
123 fprintf_function cpu_fprintf
, int flags
)
125 ARMCPU
*cpu
= ARM_CPU(cs
);
126 CPUARMState
*env
= &cpu
->env
;
127 uint32_t psr
= pstate_read(env
);
130 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
131 env
->pc
, env
->xregs
[31]);
132 for (i
= 0; i
< 31; i
++) {
133 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
135 cpu_fprintf(f
, "\n");
140 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
142 psr
& PSTATE_N
? 'N' : '-',
143 psr
& PSTATE_Z
? 'Z' : '-',
144 psr
& PSTATE_C
? 'C' : '-',
145 psr
& PSTATE_V
? 'V' : '-');
146 cpu_fprintf(f
, "\n");
148 if (flags
& CPU_DUMP_FPU
) {
150 for (i
= 0; i
< numvfpregs
; i
+= 2) {
151 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
152 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
153 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
155 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
156 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
157 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
160 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
161 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
165 void gen_a64_set_pc_im(uint64_t val
)
167 tcg_gen_movi_i64(cpu_pc
, val
);
170 static void gen_exception_internal(int excp
)
172 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
174 assert(excp_is_internal(excp
));
175 gen_helper_exception_internal(cpu_env
, tcg_excp
);
176 tcg_temp_free_i32(tcg_excp
);
179 static void gen_exception(int excp
, uint32_t syndrome
)
181 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
182 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
184 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
, tcg_syn
);
185 tcg_temp_free_i32(tcg_syn
);
186 tcg_temp_free_i32(tcg_excp
);
189 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
191 gen_a64_set_pc_im(s
->pc
- offset
);
192 gen_exception_internal(excp
);
193 s
->is_jmp
= DISAS_EXC
;
196 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
199 gen_a64_set_pc_im(s
->pc
- offset
);
200 gen_exception(excp
, syndrome
);
201 s
->is_jmp
= DISAS_EXC
;
204 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
206 /* No direct tb linking with singlestep or deterministic io */
207 if (s
->singlestep_enabled
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
211 /* Only link tbs from inside the same guest page */
212 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
219 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
221 TranslationBlock
*tb
;
224 if (use_goto_tb(s
, n
, dest
)) {
226 gen_a64_set_pc_im(dest
);
227 tcg_gen_exit_tb((intptr_t)tb
+ n
);
228 s
->is_jmp
= DISAS_TB_JUMP
;
230 gen_a64_set_pc_im(dest
);
231 if (s
->singlestep_enabled
) {
232 gen_exception_internal(EXCP_DEBUG
);
235 s
->is_jmp
= DISAS_JUMP
;
239 static void unallocated_encoding(DisasContext
*s
)
241 /* Unallocated and reserved encodings are uncategorized */
242 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized());
245 #define unsupported_encoding(s, insn) \
247 qemu_log_mask(LOG_UNIMP, \
248 "%s:%d: unsupported instruction encoding 0x%08x " \
249 "at pc=%016" PRIx64 "\n", \
250 __FILE__, __LINE__, insn, s->pc - 4); \
251 unallocated_encoding(s); \
254 static void init_tmp_a64_array(DisasContext
*s
)
256 #ifdef CONFIG_DEBUG_TCG
258 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
259 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
262 s
->tmp_a64_count
= 0;
265 static void free_tmp_a64(DisasContext
*s
)
268 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
269 tcg_temp_free_i64(s
->tmp_a64
[i
]);
271 init_tmp_a64_array(s
);
274 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
276 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
277 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
280 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
282 TCGv_i64 t
= new_tmp_a64(s
);
283 tcg_gen_movi_i64(t
, 0);
288 * Register access functions
290 * These functions are used for directly accessing a register in where
291 * changes to the final register value are likely to be made. If you
292 * need to use a register for temporary calculation (e.g. index type
293 * operations) use the read_* form.
295 * B1.2.1 Register mappings
297 * In instruction register encoding 31 can refer to ZR (zero register) or
298 * the SP (stack pointer) depending on context. In QEMU's case we map SP
299 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
300 * This is the point of the _sp forms.
302 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
305 return new_tmp_a64_zero(s
);
311 /* register access for when 31 == SP */
312 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
317 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
318 * representing the register contents. This TCGv is an auto-freed
319 * temporary so it need not be explicitly freed, and may be modified.
321 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
323 TCGv_i64 v
= new_tmp_a64(s
);
326 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
328 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
331 tcg_gen_movi_i64(v
, 0);
336 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
338 TCGv_i64 v
= new_tmp_a64(s
);
340 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
342 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
347 /* We should have at some point before trying to access an FP register
348 * done the necessary access check, so assert that
349 * (a) we did the check and
350 * (b) we didn't then just plough ahead anyway if it failed.
351 * Print the instruction pattern in the abort message so we can figure
352 * out what we need to fix if a user encounters this problem in the wild.
354 static inline void assert_fp_access_checked(DisasContext
*s
)
356 #ifdef CONFIG_DEBUG_TCG
357 if (unlikely(!s
->fp_access_checked
|| !s
->cpacr_fpen
)) {
358 fprintf(stderr
, "target-arm: FP access check missing for "
359 "instruction 0x%08x\n", s
->insn
);
365 /* Return the offset into CPUARMState of an element of specified
366 * size, 'element' places in from the least significant end of
367 * the FP/vector register Qn.
369 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
370 int element
, TCGMemOp size
)
372 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
373 #ifdef HOST_WORDS_BIGENDIAN
374 /* This is complicated slightly because vfp.regs[2n] is
375 * still the low half and vfp.regs[2n+1] the high half
376 * of the 128 bit vector, even on big endian systems.
377 * Calculate the offset assuming a fully bigendian 128 bits,
378 * then XOR to account for the order of the two 64 bit halves.
380 offs
+= (16 - ((element
+ 1) * (1 << size
)));
383 offs
+= element
* (1 << size
);
385 assert_fp_access_checked(s
);
389 /* Return the offset into CPUARMState of a slice (from
390 * the least significant end) of FP register Qn (ie
392 * (Note that this is not the same mapping as for A32; see cpu.h)
394 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
396 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
397 #ifdef HOST_WORDS_BIGENDIAN
398 offs
+= (8 - (1 << size
));
400 assert_fp_access_checked(s
);
404 /* Offset of the high half of the 128 bit vector Qn */
405 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
407 assert_fp_access_checked(s
);
408 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
411 /* Convenience accessors for reading and writing single and double
412 * FP registers. Writing clears the upper parts of the associated
413 * 128 bit vector register, as required by the architecture.
414 * Note that unlike the GP register accessors, the values returned
415 * by the read functions must be manually freed.
417 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
419 TCGv_i64 v
= tcg_temp_new_i64();
421 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
425 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
427 TCGv_i32 v
= tcg_temp_new_i32();
429 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
433 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
435 TCGv_i64 tcg_zero
= tcg_const_i64(0);
437 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
438 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
439 tcg_temp_free_i64(tcg_zero
);
442 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
444 TCGv_i64 tmp
= tcg_temp_new_i64();
446 tcg_gen_extu_i32_i64(tmp
, v
);
447 write_fp_dreg(s
, reg
, tmp
);
448 tcg_temp_free_i64(tmp
);
451 static TCGv_ptr
get_fpstatus_ptr(void)
453 TCGv_ptr statusptr
= tcg_temp_new_ptr();
456 /* In A64 all instructions (both FP and Neon) use the FPCR;
457 * there is no equivalent of the A32 Neon "standard FPSCR value"
458 * and all operations use vfp.fp_status.
460 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
461 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
465 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
466 * than the 32 bit equivalent.
468 static inline void gen_set_NZ64(TCGv_i64 result
)
470 TCGv_i64 flag
= tcg_temp_new_i64();
472 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
473 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
474 tcg_gen_shri_i64(flag
, result
, 32);
475 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
476 tcg_temp_free_i64(flag
);
479 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
480 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
483 gen_set_NZ64(result
);
485 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
486 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
488 tcg_gen_movi_i32(cpu_CF
, 0);
489 tcg_gen_movi_i32(cpu_VF
, 0);
492 /* dest = T0 + T1; compute C, N, V and Z flags */
493 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
496 TCGv_i64 result
, flag
, tmp
;
497 result
= tcg_temp_new_i64();
498 flag
= tcg_temp_new_i64();
499 tmp
= tcg_temp_new_i64();
501 tcg_gen_movi_i64(tmp
, 0);
502 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
504 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
506 gen_set_NZ64(result
);
508 tcg_gen_xor_i64(flag
, result
, t0
);
509 tcg_gen_xor_i64(tmp
, t0
, t1
);
510 tcg_gen_andc_i64(flag
, flag
, tmp
);
511 tcg_temp_free_i64(tmp
);
512 tcg_gen_shri_i64(flag
, flag
, 32);
513 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
515 tcg_gen_mov_i64(dest
, result
);
516 tcg_temp_free_i64(result
);
517 tcg_temp_free_i64(flag
);
519 /* 32 bit arithmetic */
520 TCGv_i32 t0_32
= tcg_temp_new_i32();
521 TCGv_i32 t1_32
= tcg_temp_new_i32();
522 TCGv_i32 tmp
= tcg_temp_new_i32();
524 tcg_gen_movi_i32(tmp
, 0);
525 tcg_gen_trunc_i64_i32(t0_32
, t0
);
526 tcg_gen_trunc_i64_i32(t1_32
, t1
);
527 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
528 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
529 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
530 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
531 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
532 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
534 tcg_temp_free_i32(tmp
);
535 tcg_temp_free_i32(t0_32
);
536 tcg_temp_free_i32(t1_32
);
540 /* dest = T0 - T1; compute C, N, V and Z flags */
541 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
544 /* 64 bit arithmetic */
545 TCGv_i64 result
, flag
, tmp
;
547 result
= tcg_temp_new_i64();
548 flag
= tcg_temp_new_i64();
549 tcg_gen_sub_i64(result
, t0
, t1
);
551 gen_set_NZ64(result
);
553 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
554 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
556 tcg_gen_xor_i64(flag
, result
, t0
);
557 tmp
= tcg_temp_new_i64();
558 tcg_gen_xor_i64(tmp
, t0
, t1
);
559 tcg_gen_and_i64(flag
, flag
, tmp
);
560 tcg_temp_free_i64(tmp
);
561 tcg_gen_shri_i64(flag
, flag
, 32);
562 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
563 tcg_gen_mov_i64(dest
, result
);
564 tcg_temp_free_i64(flag
);
565 tcg_temp_free_i64(result
);
567 /* 32 bit arithmetic */
568 TCGv_i32 t0_32
= tcg_temp_new_i32();
569 TCGv_i32 t1_32
= tcg_temp_new_i32();
572 tcg_gen_trunc_i64_i32(t0_32
, t0
);
573 tcg_gen_trunc_i64_i32(t1_32
, t1
);
574 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
575 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
576 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
577 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
578 tmp
= tcg_temp_new_i32();
579 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
580 tcg_temp_free_i32(t0_32
);
581 tcg_temp_free_i32(t1_32
);
582 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
583 tcg_temp_free_i32(tmp
);
584 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
588 /* dest = T0 + T1 + CF; do not compute flags. */
589 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
591 TCGv_i64 flag
= tcg_temp_new_i64();
592 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
593 tcg_gen_add_i64(dest
, t0
, t1
);
594 tcg_gen_add_i64(dest
, dest
, flag
);
595 tcg_temp_free_i64(flag
);
598 tcg_gen_ext32u_i64(dest
, dest
);
602 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
603 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
606 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
607 result
= tcg_temp_new_i64();
608 cf_64
= tcg_temp_new_i64();
609 vf_64
= tcg_temp_new_i64();
610 tmp
= tcg_const_i64(0);
612 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
613 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
614 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
615 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
616 gen_set_NZ64(result
);
618 tcg_gen_xor_i64(vf_64
, result
, t0
);
619 tcg_gen_xor_i64(tmp
, t0
, t1
);
620 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
621 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
622 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
624 tcg_gen_mov_i64(dest
, result
);
626 tcg_temp_free_i64(tmp
);
627 tcg_temp_free_i64(vf_64
);
628 tcg_temp_free_i64(cf_64
);
629 tcg_temp_free_i64(result
);
631 TCGv_i32 t0_32
, t1_32
, tmp
;
632 t0_32
= tcg_temp_new_i32();
633 t1_32
= tcg_temp_new_i32();
634 tmp
= tcg_const_i32(0);
636 tcg_gen_trunc_i64_i32(t0_32
, t0
);
637 tcg_gen_trunc_i64_i32(t1_32
, t1
);
638 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
639 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
641 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
642 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
643 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
644 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
645 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
647 tcg_temp_free_i32(tmp
);
648 tcg_temp_free_i32(t1_32
);
649 tcg_temp_free_i32(t0_32
);
654 * Load/Store generators
658 * Store from GPR register to memory.
660 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
661 TCGv_i64 tcg_addr
, int size
, int memidx
)
664 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
667 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
668 TCGv_i64 tcg_addr
, int size
)
670 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
674 * Load from memory to GPR register
676 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
677 int size
, bool is_signed
, bool extend
, int memidx
)
679 TCGMemOp memop
= MO_TE
+ size
;
687 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
689 if (extend
&& is_signed
) {
691 tcg_gen_ext32u_i64(dest
, dest
);
695 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
696 int size
, bool is_signed
, bool extend
)
698 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
703 * Store from FP register to memory
705 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
707 /* This writes the bottom N bits of a 128 bit wide vector to memory */
708 TCGv_i64 tmp
= tcg_temp_new_i64();
709 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
711 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
713 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
714 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
715 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
716 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
717 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
718 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
719 tcg_temp_free_i64(tcg_hiaddr
);
722 tcg_temp_free_i64(tmp
);
726 * Load from memory to FP register
728 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
730 /* This always zero-extends and writes to a full 128 bit wide vector */
731 TCGv_i64 tmplo
= tcg_temp_new_i64();
735 TCGMemOp memop
= MO_TE
+ size
;
736 tmphi
= tcg_const_i64(0);
737 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
740 tmphi
= tcg_temp_new_i64();
741 tcg_hiaddr
= tcg_temp_new_i64();
743 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
744 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
745 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
746 tcg_temp_free_i64(tcg_hiaddr
);
749 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
750 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
752 tcg_temp_free_i64(tmplo
);
753 tcg_temp_free_i64(tmphi
);
757 * Vector load/store helpers.
759 * The principal difference between this and a FP load is that we don't
760 * zero extend as we are filling a partial chunk of the vector register.
761 * These functions don't support 128 bit loads/stores, which would be
762 * normal load/store operations.
764 * The _i32 versions are useful when operating on 32 bit quantities
765 * (eg for floating point single or using Neon helper functions).
768 /* Get value of an element within a vector register */
769 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
770 int element
, TCGMemOp memop
)
772 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
775 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
778 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
781 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
784 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
787 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
790 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
794 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
797 g_assert_not_reached();
801 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
802 int element
, TCGMemOp memop
)
804 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
807 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
810 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
813 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
816 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
820 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
823 g_assert_not_reached();
827 /* Set value of an element within a vector register */
828 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
829 int element
, TCGMemOp memop
)
831 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
834 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
837 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
840 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
843 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
846 g_assert_not_reached();
850 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
851 int destidx
, int element
, TCGMemOp memop
)
853 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
856 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
859 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
862 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
865 g_assert_not_reached();
869 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
870 * vector ops all need to do this).
872 static void clear_vec_high(DisasContext
*s
, int rd
)
874 TCGv_i64 tcg_zero
= tcg_const_i64(0);
876 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
877 tcg_temp_free_i64(tcg_zero
);
880 /* Store from vector register to memory */
881 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
882 TCGv_i64 tcg_addr
, int size
)
884 TCGMemOp memop
= MO_TE
+ size
;
885 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
887 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
888 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
890 tcg_temp_free_i64(tcg_tmp
);
893 /* Load from memory to vector register */
894 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
895 TCGv_i64 tcg_addr
, int size
)
897 TCGMemOp memop
= MO_TE
+ size
;
898 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
900 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
901 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
903 tcg_temp_free_i64(tcg_tmp
);
906 /* Check that FP/Neon access is enabled. If it is, return
907 * true. If not, emit code to generate an appropriate exception,
908 * and return false; the caller should not emit any code for
909 * the instruction. Note that this check must happen after all
910 * unallocated-encoding checks (otherwise the syndrome information
911 * for the resulting exception will be incorrect).
913 static inline bool fp_access_check(DisasContext
*s
)
915 assert(!s
->fp_access_checked
);
916 s
->fp_access_checked
= true;
922 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false));
927 * This utility function is for doing register extension with an
928 * optional shift. You will likely want to pass a temporary for the
929 * destination register. See DecodeRegExtend() in the ARM ARM.
931 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
932 int option
, unsigned int shift
)
934 int extsize
= extract32(option
, 0, 2);
935 bool is_signed
= extract32(option
, 2, 1);
940 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
943 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
946 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
949 tcg_gen_mov_i64(tcg_out
, tcg_in
);
955 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
958 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
961 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
964 tcg_gen_mov_i64(tcg_out
, tcg_in
);
970 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
974 static inline void gen_check_sp_alignment(DisasContext
*s
)
976 /* The AArch64 architecture mandates that (if enabled via PSTATE
977 * or SCTLR bits) there is a check that SP is 16-aligned on every
978 * SP-relative load or store (with an exception generated if it is not).
979 * In line with general QEMU practice regarding misaligned accesses,
980 * we omit these checks for the sake of guest program performance.
981 * This function is provided as a hook so we can more easily add these
982 * checks in future (possibly as a "favour catching guest program bugs
983 * over speed" user selectable option).
988 * This provides a simple table based table lookup decoder. It is
989 * intended to be used when the relevant bits for decode are too
990 * awkwardly placed and switch/if based logic would be confusing and
991 * deeply nested. Since it's a linear search through the table, tables
992 * should be kept small.
994 * It returns the first handler where insn & mask == pattern, or
995 * NULL if there is no match.
996 * The table is terminated by an empty mask (i.e. 0)
998 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1001 const AArch64DecodeTable
*tptr
= table
;
1003 while (tptr
->mask
) {
1004 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1005 return tptr
->disas_fn
;
1013 * the instruction disassembly implemented here matches
1014 * the instruction encoding classifications in chapter 3 (C3)
1015 * of the ARM Architecture Reference Manual (DDI0487A_a)
1018 /* C3.2.7 Unconditional branch (immediate)
1020 * +----+-----------+-------------------------------------+
1021 * | op | 0 0 1 0 1 | imm26 |
1022 * +----+-----------+-------------------------------------+
1024 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1026 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1028 if (insn
& (1 << 31)) {
1029 /* C5.6.26 BL Branch with link */
1030 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1033 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1034 gen_goto_tb(s
, 0, addr
);
1037 /* C3.2.1 Compare & branch (immediate)
1038 * 31 30 25 24 23 5 4 0
1039 * +----+-------------+----+---------------------+--------+
1040 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1041 * +----+-------------+----+---------------------+--------+
1043 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1045 unsigned int sf
, op
, rt
;
1050 sf
= extract32(insn
, 31, 1);
1051 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1052 rt
= extract32(insn
, 0, 5);
1053 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1055 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1056 label_match
= gen_new_label();
1058 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1059 tcg_cmp
, 0, label_match
);
1061 gen_goto_tb(s
, 0, s
->pc
);
1062 gen_set_label(label_match
);
1063 gen_goto_tb(s
, 1, addr
);
1066 /* C3.2.5 Test & branch (immediate)
1067 * 31 30 25 24 23 19 18 5 4 0
1068 * +----+-------------+----+-------+-------------+------+
1069 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1070 * +----+-------------+----+-------+-------------+------+
1072 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1074 unsigned int bit_pos
, op
, rt
;
1079 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1080 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1081 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1082 rt
= extract32(insn
, 0, 5);
1084 tcg_cmp
= tcg_temp_new_i64();
1085 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1086 label_match
= gen_new_label();
1087 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1088 tcg_cmp
, 0, label_match
);
1089 tcg_temp_free_i64(tcg_cmp
);
1090 gen_goto_tb(s
, 0, s
->pc
);
1091 gen_set_label(label_match
);
1092 gen_goto_tb(s
, 1, addr
);
1095 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1096 * 31 25 24 23 5 4 3 0
1097 * +---------------+----+---------------------+----+------+
1098 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1099 * +---------------+----+---------------------+----+------+
1101 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1106 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1107 unallocated_encoding(s
);
1110 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1111 cond
= extract32(insn
, 0, 4);
1114 /* genuinely conditional branches */
1115 int label_match
= gen_new_label();
1116 arm_gen_test_cc(cond
, label_match
);
1117 gen_goto_tb(s
, 0, s
->pc
);
1118 gen_set_label(label_match
);
1119 gen_goto_tb(s
, 1, addr
);
1121 /* 0xe and 0xf are both "always" conditions */
1122 gen_goto_tb(s
, 0, addr
);
1127 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1128 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1130 unsigned int selector
= crm
<< 3 | op2
;
1133 unallocated_encoding(s
);
1141 s
->is_jmp
= DISAS_WFI
;
1145 s
->is_jmp
= DISAS_WFE
;
1149 /* we treat all as NOP at least for now */
1152 /* default specified as NOP equivalent */
1157 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1159 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1162 /* CLREX, DSB, DMB, ISB */
1163 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1164 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1167 unallocated_encoding(s
);
1178 /* We don't emulate caches so barriers are no-ops */
1181 unallocated_encoding(s
);
1186 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1187 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1188 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1190 int op
= op1
<< 3 | op2
;
1192 case 0x05: /* SPSel */
1193 if (s
->current_pl
== 0) {
1194 unallocated_encoding(s
);
1198 case 0x1e: /* DAIFSet */
1199 case 0x1f: /* DAIFClear */
1201 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1202 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1203 gen_a64_set_pc_im(s
->pc
- 4);
1204 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1205 tcg_temp_free_i32(tcg_imm
);
1206 tcg_temp_free_i32(tcg_op
);
1207 s
->is_jmp
= DISAS_UPDATE
;
1211 unallocated_encoding(s
);
1216 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1218 TCGv_i32 tmp
= tcg_temp_new_i32();
1219 TCGv_i32 nzcv
= tcg_temp_new_i32();
1221 /* build bit 31, N */
1222 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
1223 /* build bit 30, Z */
1224 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1225 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1226 /* build bit 29, C */
1227 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1228 /* build bit 28, V */
1229 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1230 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1231 /* generate result */
1232 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1234 tcg_temp_free_i32(nzcv
);
1235 tcg_temp_free_i32(tmp
);
1238 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1241 TCGv_i32 nzcv
= tcg_temp_new_i32();
1243 /* take NZCV from R[t] */
1244 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1247 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
1249 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1250 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1252 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1253 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1255 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1256 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1257 tcg_temp_free_i32(nzcv
);
1260 /* C5.6.129 MRS - move from system register
1261 * C5.6.131 MSR (register) - move to system register
1264 * These are all essentially the same insn in 'read' and 'write'
1265 * versions, with varying op0 fields.
1267 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1268 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1269 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1271 const ARMCPRegInfo
*ri
;
1274 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1275 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1276 crn
, crm
, op0
, op1
, op2
));
1279 /* Unknown register; this might be a guest error or a QEMU
1280 * unimplemented feature.
1282 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1283 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1284 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1285 unallocated_encoding(s
);
1289 /* Check access permissions */
1290 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
1291 unallocated_encoding(s
);
1296 /* Emit code to perform further access permissions checks at
1297 * runtime; this may result in an exception.
1303 gen_a64_set_pc_im(s
->pc
- 4);
1304 tmpptr
= tcg_const_ptr(ri
);
1305 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1306 tcg_syn
= tcg_const_i32(syndrome
);
1307 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
);
1308 tcg_temp_free_ptr(tmpptr
);
1309 tcg_temp_free_i32(tcg_syn
);
1312 /* Handle special cases first */
1313 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1317 tcg_rt
= cpu_reg(s
, rt
);
1319 gen_get_nzcv(tcg_rt
);
1321 gen_set_nzcv(tcg_rt
);
1324 case ARM_CP_CURRENTEL
:
1325 /* Reads as current EL value from pstate, which is
1326 * guaranteed to be constant by the tb flags.
1328 tcg_rt
= cpu_reg(s
, rt
);
1329 tcg_gen_movi_i64(tcg_rt
, s
->current_pl
<< 2);
1332 /* Writes clear the aligned block of memory which rt points into. */
1333 tcg_rt
= cpu_reg(s
, rt
);
1334 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1340 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1344 tcg_rt
= cpu_reg(s
, rt
);
1347 if (ri
->type
& ARM_CP_CONST
) {
1348 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1349 } else if (ri
->readfn
) {
1351 tmpptr
= tcg_const_ptr(ri
);
1352 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1353 tcg_temp_free_ptr(tmpptr
);
1355 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1358 if (ri
->type
& ARM_CP_CONST
) {
1359 /* If not forbidden by access permissions, treat as WI */
1361 } else if (ri
->writefn
) {
1363 tmpptr
= tcg_const_ptr(ri
);
1364 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1365 tcg_temp_free_ptr(tmpptr
);
1367 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1371 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1372 /* I/O operations must end the TB here (whether read or write) */
1374 s
->is_jmp
= DISAS_UPDATE
;
1375 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1376 /* We default to ending the TB on a coprocessor register write,
1377 * but allow this to be suppressed by the register definition
1378 * (usually only necessary to work around guest bugs).
1380 s
->is_jmp
= DISAS_UPDATE
;
1385 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1386 * +---------------------+---+-----+-----+-------+-------+-----+------+
1387 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1388 * +---------------------+---+-----+-----+-------+-------+-----+------+
1390 static void disas_system(DisasContext
*s
, uint32_t insn
)
1392 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1393 l
= extract32(insn
, 21, 1);
1394 op0
= extract32(insn
, 19, 2);
1395 op1
= extract32(insn
, 16, 3);
1396 crn
= extract32(insn
, 12, 4);
1397 crm
= extract32(insn
, 8, 4);
1398 op2
= extract32(insn
, 5, 3);
1399 rt
= extract32(insn
, 0, 5);
1402 if (l
|| rt
!= 31) {
1403 unallocated_encoding(s
);
1407 case 2: /* C5.6.68 HINT */
1408 handle_hint(s
, insn
, op1
, op2
, crm
);
1410 case 3: /* CLREX, DSB, DMB, ISB */
1411 handle_sync(s
, insn
, op1
, op2
, crm
);
1413 case 4: /* C5.6.130 MSR (immediate) */
1414 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1417 unallocated_encoding(s
);
1422 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1425 /* C3.2.3 Exception generation
1427 * 31 24 23 21 20 5 4 2 1 0
1428 * +-----------------+-----+------------------------+-----+----+
1429 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1430 * +-----------------------+------------------------+----------+
1432 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1434 int opc
= extract32(insn
, 21, 3);
1435 int op2_ll
= extract32(insn
, 0, 5);
1436 int imm16
= extract32(insn
, 5, 16);
1440 /* SVC, HVC, SMC; since we don't support the Virtualization
1441 * or TrustZone extensions these all UNDEF except SVC.
1444 unallocated_encoding(s
);
1447 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
));
1451 unallocated_encoding(s
);
1455 gen_exception_insn(s
, 0, EXCP_BKPT
, syn_aa64_bkpt(imm16
));
1459 unallocated_encoding(s
);
1463 unsupported_encoding(s
, insn
);
1466 if (op2_ll
< 1 || op2_ll
> 3) {
1467 unallocated_encoding(s
);
1470 /* DCPS1, DCPS2, DCPS3 */
1471 unsupported_encoding(s
, insn
);
1474 unallocated_encoding(s
);
1479 /* C3.2.7 Unconditional branch (register)
1480 * 31 25 24 21 20 16 15 10 9 5 4 0
1481 * +---------------+-------+-------+-------+------+-------+
1482 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1483 * +---------------+-------+-------+-------+------+-------+
1485 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1487 unsigned int opc
, op2
, op3
, rn
, op4
;
1489 opc
= extract32(insn
, 21, 4);
1490 op2
= extract32(insn
, 16, 5);
1491 op3
= extract32(insn
, 10, 6);
1492 rn
= extract32(insn
, 5, 5);
1493 op4
= extract32(insn
, 0, 5);
1495 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1496 unallocated_encoding(s
);
1503 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1506 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1507 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1510 if (s
->current_pl
== 0) {
1511 unallocated_encoding(s
);
1514 gen_helper_exception_return(cpu_env
);
1515 s
->is_jmp
= DISAS_JUMP
;
1519 unallocated_encoding(s
);
1521 unsupported_encoding(s
, insn
);
1525 unallocated_encoding(s
);
1529 s
->is_jmp
= DISAS_JUMP
;
1532 /* C3.2 Branches, exception generating and system instructions */
1533 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1535 switch (extract32(insn
, 25, 7)) {
1536 case 0x0a: case 0x0b:
1537 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1538 disas_uncond_b_imm(s
, insn
);
1540 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1541 disas_comp_b_imm(s
, insn
);
1543 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1544 disas_test_b_imm(s
, insn
);
1546 case 0x2a: /* Conditional branch (immediate) */
1547 disas_cond_b_imm(s
, insn
);
1549 case 0x6a: /* Exception generation / System */
1550 if (insn
& (1 << 24)) {
1551 disas_system(s
, insn
);
1556 case 0x6b: /* Unconditional branch (register) */
1557 disas_uncond_b_reg(s
, insn
);
1560 unallocated_encoding(s
);
1566 * Load/Store exclusive instructions are implemented by remembering
1567 * the value/address loaded, and seeing if these are the same
1568 * when the store is performed. This is not actually the architecturally
1569 * mandated semantics, but it works for typical guest code sequences
1570 * and avoids having to monitor regular stores.
1572 * In system emulation mode only one CPU will be running at once, so
1573 * this sequence is effectively atomic. In user emulation mode we
1574 * throw an exception and handle the atomic operation elsewhere.
1576 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1577 TCGv_i64 addr
, int size
, bool is_pair
)
1579 TCGv_i64 tmp
= tcg_temp_new_i64();
1580 TCGMemOp memop
= MO_TE
+ size
;
1582 g_assert(size
<= 3);
1583 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1586 TCGv_i64 addr2
= tcg_temp_new_i64();
1587 TCGv_i64 hitmp
= tcg_temp_new_i64();
1589 g_assert(size
>= 2);
1590 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1591 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1592 tcg_temp_free_i64(addr2
);
1593 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1594 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1595 tcg_temp_free_i64(hitmp
);
1598 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1599 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1601 tcg_temp_free_i64(tmp
);
1602 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1605 #ifdef CONFIG_USER_ONLY
1606 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1607 TCGv_i64 addr
, int size
, int is_pair
)
1609 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1610 tcg_gen_movi_i32(cpu_exclusive_info
,
1611 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1612 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1615 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1616 TCGv_i64 inaddr
, int size
, int is_pair
)
1618 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1619 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1622 * [addr + datasize] = {Rt2};
1628 * env->exclusive_addr = -1;
1630 int fail_label
= gen_new_label();
1631 int done_label
= gen_new_label();
1632 TCGv_i64 addr
= tcg_temp_local_new_i64();
1635 /* Copy input into a local temp so it is not trashed when the
1636 * basic block ends at the branch insn.
1638 tcg_gen_mov_i64(addr
, inaddr
);
1639 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1641 tmp
= tcg_temp_new_i64();
1642 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1643 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1644 tcg_temp_free_i64(tmp
);
1647 TCGv_i64 addrhi
= tcg_temp_new_i64();
1648 TCGv_i64 tmphi
= tcg_temp_new_i64();
1650 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1651 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1652 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1654 tcg_temp_free_i64(tmphi
);
1655 tcg_temp_free_i64(addrhi
);
1658 /* We seem to still have the exclusive monitor, so do the store */
1659 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1661 TCGv_i64 addrhi
= tcg_temp_new_i64();
1663 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1664 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1665 get_mem_index(s
), MO_TE
+ size
);
1666 tcg_temp_free_i64(addrhi
);
1669 tcg_temp_free_i64(addr
);
1671 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1672 tcg_gen_br(done_label
);
1673 gen_set_label(fail_label
);
1674 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1675 gen_set_label(done_label
);
1676 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1681 /* C3.3.6 Load/store exclusive
1683 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1684 * +-----+-------------+----+---+----+------+----+-------+------+------+
1685 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1686 * +-----+-------------+----+---+----+------+----+-------+------+------+
1688 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1689 * L: 0 -> store, 1 -> load
1690 * o2: 0 -> exclusive, 1 -> not
1691 * o1: 0 -> single register, 1 -> register pair
1692 * o0: 1 -> load-acquire/store-release, 0 -> not
1694 * o0 == 0 AND o2 == 1 is un-allocated
1695 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1697 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1699 int rt
= extract32(insn
, 0, 5);
1700 int rn
= extract32(insn
, 5, 5);
1701 int rt2
= extract32(insn
, 10, 5);
1702 int is_lasr
= extract32(insn
, 15, 1);
1703 int rs
= extract32(insn
, 16, 5);
1704 int is_pair
= extract32(insn
, 21, 1);
1705 int is_store
= !extract32(insn
, 22, 1);
1706 int is_excl
= !extract32(insn
, 23, 1);
1707 int size
= extract32(insn
, 30, 2);
1710 if ((!is_excl
&& !is_lasr
) ||
1711 (is_pair
&& size
< 2)) {
1712 unallocated_encoding(s
);
1717 gen_check_sp_alignment(s
);
1719 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1721 /* Note that since TCG is single threaded load-acquire/store-release
1722 * semantics require no extra if (is_lasr) { ... } handling.
1727 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1729 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1732 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1734 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1736 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1739 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1740 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1742 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1744 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1751 * C3.3.5 Load register (literal)
1753 * 31 30 29 27 26 25 24 23 5 4 0
1754 * +-----+-------+---+-----+-------------------+-------+
1755 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1756 * +-----+-------+---+-----+-------------------+-------+
1758 * V: 1 -> vector (simd/fp)
1759 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1760 * 10-> 32 bit signed, 11 -> prefetch
1761 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1763 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1765 int rt
= extract32(insn
, 0, 5);
1766 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1767 bool is_vector
= extract32(insn
, 26, 1);
1768 int opc
= extract32(insn
, 30, 2);
1769 bool is_signed
= false;
1771 TCGv_i64 tcg_rt
, tcg_addr
;
1775 unallocated_encoding(s
);
1779 if (!fp_access_check(s
)) {
1784 /* PRFM (literal) : prefetch */
1787 size
= 2 + extract32(opc
, 0, 1);
1788 is_signed
= extract32(opc
, 1, 1);
1791 tcg_rt
= cpu_reg(s
, rt
);
1793 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1795 do_fp_ld(s
, rt
, tcg_addr
, size
);
1797 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1799 tcg_temp_free_i64(tcg_addr
);
1803 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1804 * C5.6.81 LDP (Load Pair - non vector)
1805 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1806 * C5.6.176 STNP (Store Pair - non-temporal hint)
1807 * C5.6.177 STP (Store Pair - non vector)
1808 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1809 * C6.3.165 LDP (Load Pair of SIMD&FP)
1810 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1811 * C6.3.284 STP (Store Pair of SIMD&FP)
1813 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1814 * +-----+-------+---+---+-------+---+-----------------------------+
1815 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1816 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1818 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1820 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1821 * V: 0 -> GPR, 1 -> Vector
1822 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1823 * 10 -> signed offset, 11 -> pre-index
1824 * L: 0 -> Store 1 -> Load
1826 * Rt, Rt2 = GPR or SIMD registers to be stored
1827 * Rn = general purpose register containing address
1828 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1830 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1832 int rt
= extract32(insn
, 0, 5);
1833 int rn
= extract32(insn
, 5, 5);
1834 int rt2
= extract32(insn
, 10, 5);
1835 int64_t offset
= sextract32(insn
, 15, 7);
1836 int index
= extract32(insn
, 23, 2);
1837 bool is_vector
= extract32(insn
, 26, 1);
1838 bool is_load
= extract32(insn
, 22, 1);
1839 int opc
= extract32(insn
, 30, 2);
1841 bool is_signed
= false;
1842 bool postindex
= false;
1845 TCGv_i64 tcg_addr
; /* calculated address */
1849 unallocated_encoding(s
);
1856 size
= 2 + extract32(opc
, 1, 1);
1857 is_signed
= extract32(opc
, 0, 1);
1858 if (!is_load
&& is_signed
) {
1859 unallocated_encoding(s
);
1865 case 1: /* post-index */
1870 /* signed offset with "non-temporal" hint. Since we don't emulate
1871 * caches we don't care about hints to the cache system about
1872 * data access patterns, and handle this identically to plain
1876 /* There is no non-temporal-hint version of LDPSW */
1877 unallocated_encoding(s
);
1882 case 2: /* signed offset, rn not updated */
1885 case 3: /* pre-index */
1891 if (is_vector
&& !fp_access_check(s
)) {
1898 gen_check_sp_alignment(s
);
1901 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1904 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1909 do_fp_ld(s
, rt
, tcg_addr
, size
);
1911 do_fp_st(s
, rt
, tcg_addr
, size
);
1914 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1916 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1918 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1921 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1924 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1926 do_fp_st(s
, rt2
, tcg_addr
, size
);
1929 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1931 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1933 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1939 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1941 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1943 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1948 * C3.3.8 Load/store (immediate post-indexed)
1949 * C3.3.9 Load/store (immediate pre-indexed)
1950 * C3.3.12 Load/store (unscaled immediate)
1952 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1953 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1954 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1955 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1957 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1959 * V = 0 -> non-vector
1960 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1961 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1963 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
1965 int rt
= extract32(insn
, 0, 5);
1966 int rn
= extract32(insn
, 5, 5);
1967 int imm9
= sextract32(insn
, 12, 9);
1968 int opc
= extract32(insn
, 22, 2);
1969 int size
= extract32(insn
, 30, 2);
1970 int idx
= extract32(insn
, 10, 2);
1971 bool is_signed
= false;
1972 bool is_store
= false;
1973 bool is_extended
= false;
1974 bool is_unpriv
= (idx
== 2);
1975 bool is_vector
= extract32(insn
, 26, 1);
1982 size
|= (opc
& 2) << 1;
1983 if (size
> 4 || is_unpriv
) {
1984 unallocated_encoding(s
);
1987 is_store
= ((opc
& 1) == 0);
1988 if (!fp_access_check(s
)) {
1992 if (size
== 3 && opc
== 2) {
1993 /* PRFM - prefetch */
1995 unallocated_encoding(s
);
2000 if (opc
== 3 && size
> 1) {
2001 unallocated_encoding(s
);
2004 is_store
= (opc
== 0);
2005 is_signed
= opc
& (1<<1);
2006 is_extended
= (size
< 3) && (opc
& 1);
2026 gen_check_sp_alignment(s
);
2028 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2031 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2036 do_fp_st(s
, rt
, tcg_addr
, size
);
2038 do_fp_ld(s
, rt
, tcg_addr
, size
);
2041 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2042 int memidx
= is_unpriv
? 1 : get_mem_index(s
);
2045 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2047 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2048 is_signed
, is_extended
, memidx
);
2053 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2055 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2057 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2062 * C3.3.10 Load/store (register offset)
2064 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2065 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2066 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2067 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2070 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2071 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2073 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2074 * opc<0>: 0 -> store, 1 -> load
2075 * V: 1 -> vector/simd
2076 * opt: extend encoding (see DecodeRegExtend)
2077 * S: if S=1 then scale (essentially index by sizeof(size))
2078 * Rt: register to transfer into/out of
2079 * Rn: address register or SP for base
2080 * Rm: offset register or ZR for offset
2082 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
2084 int rt
= extract32(insn
, 0, 5);
2085 int rn
= extract32(insn
, 5, 5);
2086 int shift
= extract32(insn
, 12, 1);
2087 int rm
= extract32(insn
, 16, 5);
2088 int opc
= extract32(insn
, 22, 2);
2089 int opt
= extract32(insn
, 13, 3);
2090 int size
= extract32(insn
, 30, 2);
2091 bool is_signed
= false;
2092 bool is_store
= false;
2093 bool is_extended
= false;
2094 bool is_vector
= extract32(insn
, 26, 1);
2099 if (extract32(opt
, 1, 1) == 0) {
2100 unallocated_encoding(s
);
2105 size
|= (opc
& 2) << 1;
2107 unallocated_encoding(s
);
2110 is_store
= !extract32(opc
, 0, 1);
2111 if (!fp_access_check(s
)) {
2115 if (size
== 3 && opc
== 2) {
2116 /* PRFM - prefetch */
2119 if (opc
== 3 && size
> 1) {
2120 unallocated_encoding(s
);
2123 is_store
= (opc
== 0);
2124 is_signed
= extract32(opc
, 1, 1);
2125 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2129 gen_check_sp_alignment(s
);
2131 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2133 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2134 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2136 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2140 do_fp_st(s
, rt
, tcg_addr
, size
);
2142 do_fp_ld(s
, rt
, tcg_addr
, size
);
2145 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2147 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2149 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2155 * C3.3.13 Load/store (unsigned immediate)
2157 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2158 * +----+-------+---+-----+-----+------------+-------+------+
2159 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2160 * +----+-------+---+-----+-----+------------+-------+------+
2163 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2164 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2166 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2167 * opc<0>: 0 -> store, 1 -> load
2168 * Rn: base address register (inc SP)
2169 * Rt: target register
2171 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2173 int rt
= extract32(insn
, 0, 5);
2174 int rn
= extract32(insn
, 5, 5);
2175 unsigned int imm12
= extract32(insn
, 10, 12);
2176 bool is_vector
= extract32(insn
, 26, 1);
2177 int size
= extract32(insn
, 30, 2);
2178 int opc
= extract32(insn
, 22, 2);
2179 unsigned int offset
;
2184 bool is_signed
= false;
2185 bool is_extended
= false;
2188 size
|= (opc
& 2) << 1;
2190 unallocated_encoding(s
);
2193 is_store
= !extract32(opc
, 0, 1);
2194 if (!fp_access_check(s
)) {
2198 if (size
== 3 && opc
== 2) {
2199 /* PRFM - prefetch */
2202 if (opc
== 3 && size
> 1) {
2203 unallocated_encoding(s
);
2206 is_store
= (opc
== 0);
2207 is_signed
= extract32(opc
, 1, 1);
2208 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2212 gen_check_sp_alignment(s
);
2214 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2215 offset
= imm12
<< size
;
2216 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2220 do_fp_st(s
, rt
, tcg_addr
, size
);
2222 do_fp_ld(s
, rt
, tcg_addr
, size
);
2225 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2227 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2229 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2234 /* Load/store register (all forms) */
2235 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2237 switch (extract32(insn
, 24, 2)) {
2239 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2240 disas_ldst_reg_roffset(s
, insn
);
2242 /* Load/store register (unscaled immediate)
2243 * Load/store immediate pre/post-indexed
2244 * Load/store register unprivileged
2246 disas_ldst_reg_imm9(s
, insn
);
2250 disas_ldst_reg_unsigned_imm(s
, insn
);
2253 unallocated_encoding(s
);
2258 /* C3.3.1 AdvSIMD load/store multiple structures
2260 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2261 * +---+---+---------------+---+-------------+--------+------+------+------+
2262 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2263 * +---+---+---------------+---+-------------+--------+------+------+------+
2265 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2267 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2268 * +---+---+---------------+---+---+---------+--------+------+------+------+
2269 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2270 * +---+---+---------------+---+---+---------+--------+------+------+------+
2272 * Rt: first (or only) SIMD&FP register to be transferred
2273 * Rn: base address or SP
2274 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2276 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2278 int rt
= extract32(insn
, 0, 5);
2279 int rn
= extract32(insn
, 5, 5);
2280 int size
= extract32(insn
, 10, 2);
2281 int opcode
= extract32(insn
, 12, 4);
2282 bool is_store
= !extract32(insn
, 22, 1);
2283 bool is_postidx
= extract32(insn
, 23, 1);
2284 bool is_q
= extract32(insn
, 30, 1);
2285 TCGv_i64 tcg_addr
, tcg_rn
;
2287 int ebytes
= 1 << size
;
2288 int elements
= (is_q
? 128 : 64) / (8 << size
);
2289 int rpt
; /* num iterations */
2290 int selem
; /* structure elements */
2293 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2294 unallocated_encoding(s
);
2298 /* From the shared decode logic */
2329 unallocated_encoding(s
);
2333 if (size
== 3 && !is_q
&& selem
!= 1) {
2335 unallocated_encoding(s
);
2339 if (!fp_access_check(s
)) {
2344 gen_check_sp_alignment(s
);
2347 tcg_rn
= cpu_reg_sp(s
, rn
);
2348 tcg_addr
= tcg_temp_new_i64();
2349 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2351 for (r
= 0; r
< rpt
; r
++) {
2353 for (e
= 0; e
< elements
; e
++) {
2354 int tt
= (rt
+ r
) % 32;
2356 for (xs
= 0; xs
< selem
; xs
++) {
2358 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2360 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2362 /* For non-quad operations, setting a slice of the low
2363 * 64 bits of the register clears the high 64 bits (in
2364 * the ARM ARM pseudocode this is implicit in the fact
2365 * that 'rval' is a 64 bit wide variable). We optimize
2366 * by noticing that we only need to do this the first
2367 * time we touch a register.
2369 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2370 clear_vec_high(s
, tt
);
2373 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2380 int rm
= extract32(insn
, 16, 5);
2382 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2384 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2387 tcg_temp_free_i64(tcg_addr
);
2390 /* C3.3.3 AdvSIMD load/store single structure
2392 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2393 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2394 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2395 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2397 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2399 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2400 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2401 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2402 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2404 * Rt: first (or only) SIMD&FP register to be transferred
2405 * Rn: base address or SP
2406 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2407 * index = encoded in Q:S:size dependent on size
2409 * lane_size = encoded in R, opc
2410 * transfer width = encoded in opc, S, size
2412 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2414 int rt
= extract32(insn
, 0, 5);
2415 int rn
= extract32(insn
, 5, 5);
2416 int size
= extract32(insn
, 10, 2);
2417 int S
= extract32(insn
, 12, 1);
2418 int opc
= extract32(insn
, 13, 3);
2419 int R
= extract32(insn
, 21, 1);
2420 int is_load
= extract32(insn
, 22, 1);
2421 int is_postidx
= extract32(insn
, 23, 1);
2422 int is_q
= extract32(insn
, 30, 1);
2424 int scale
= extract32(opc
, 1, 2);
2425 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2426 bool replicate
= false;
2427 int index
= is_q
<< 3 | S
<< 2 | size
;
2429 TCGv_i64 tcg_addr
, tcg_rn
;
2433 if (!is_load
|| S
) {
2434 unallocated_encoding(s
);
2443 if (extract32(size
, 0, 1)) {
2444 unallocated_encoding(s
);
2450 if (extract32(size
, 1, 1)) {
2451 unallocated_encoding(s
);
2454 if (!extract32(size
, 0, 1)) {
2458 unallocated_encoding(s
);
2466 g_assert_not_reached();
2469 if (!fp_access_check(s
)) {
2473 ebytes
= 1 << scale
;
2476 gen_check_sp_alignment(s
);
2479 tcg_rn
= cpu_reg_sp(s
, rn
);
2480 tcg_addr
= tcg_temp_new_i64();
2481 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2483 for (xs
= 0; xs
< selem
; xs
++) {
2485 /* Load and replicate to all elements */
2487 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2489 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2490 get_mem_index(s
), MO_TE
+ scale
);
2493 mulconst
= 0x0101010101010101ULL
;
2496 mulconst
= 0x0001000100010001ULL
;
2499 mulconst
= 0x0000000100000001ULL
;
2505 g_assert_not_reached();
2508 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2510 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2512 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2514 clear_vec_high(s
, rt
);
2516 tcg_temp_free_i64(tcg_tmp
);
2518 /* Load/store one element per register */
2520 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2522 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2525 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2530 int rm
= extract32(insn
, 16, 5);
2532 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2534 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2537 tcg_temp_free_i64(tcg_addr
);
2540 /* C3.3 Loads and stores */
2541 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2543 switch (extract32(insn
, 24, 6)) {
2544 case 0x08: /* Load/store exclusive */
2545 disas_ldst_excl(s
, insn
);
2547 case 0x18: case 0x1c: /* Load register (literal) */
2548 disas_ld_lit(s
, insn
);
2550 case 0x28: case 0x29:
2551 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2552 disas_ldst_pair(s
, insn
);
2554 case 0x38: case 0x39:
2555 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2556 disas_ldst_reg(s
, insn
);
2558 case 0x0c: /* AdvSIMD load/store multiple structures */
2559 disas_ldst_multiple_struct(s
, insn
);
2561 case 0x0d: /* AdvSIMD load/store single structure */
2562 disas_ldst_single_struct(s
, insn
);
2565 unallocated_encoding(s
);
2570 /* C3.4.6 PC-rel. addressing
2571 * 31 30 29 28 24 23 5 4 0
2572 * +----+-------+-----------+-------------------+------+
2573 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2574 * +----+-------+-----------+-------------------+------+
2576 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2578 unsigned int page
, rd
;
2582 page
= extract32(insn
, 31, 1);
2583 /* SignExtend(immhi:immlo) -> offset */
2584 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
2585 rd
= extract32(insn
, 0, 5);
2589 /* ADRP (page based) */
2594 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2598 * C3.4.1 Add/subtract (immediate)
2600 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2601 * +--+--+--+-----------+-----+-------------+-----+-----+
2602 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2603 * +--+--+--+-----------+-----+-------------+-----+-----+
2605 * sf: 0 -> 32bit, 1 -> 64bit
2606 * op: 0 -> add , 1 -> sub
2608 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2610 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2612 int rd
= extract32(insn
, 0, 5);
2613 int rn
= extract32(insn
, 5, 5);
2614 uint64_t imm
= extract32(insn
, 10, 12);
2615 int shift
= extract32(insn
, 22, 2);
2616 bool setflags
= extract32(insn
, 29, 1);
2617 bool sub_op
= extract32(insn
, 30, 1);
2618 bool is_64bit
= extract32(insn
, 31, 1);
2620 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2621 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2622 TCGv_i64 tcg_result
;
2631 unallocated_encoding(s
);
2635 tcg_result
= tcg_temp_new_i64();
2638 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2640 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2643 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2645 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2647 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2649 tcg_temp_free_i64(tcg_imm
);
2653 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2655 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2658 tcg_temp_free_i64(tcg_result
);
2661 /* The input should be a value in the bottom e bits (with higher
2662 * bits zero); returns that value replicated into every element
2663 * of size e in a 64 bit integer.
2665 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2675 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2676 static inline uint64_t bitmask64(unsigned int length
)
2678 assert(length
> 0 && length
<= 64);
2679 return ~0ULL >> (64 - length
);
2682 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2683 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2684 * value (ie should cause a guest UNDEF exception), and true if they are
2685 * valid, in which case the decoded bit pattern is written to result.
2687 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2688 unsigned int imms
, unsigned int immr
)
2691 unsigned e
, levels
, s
, r
;
2694 assert(immn
< 2 && imms
< 64 && immr
< 64);
2696 /* The bit patterns we create here are 64 bit patterns which
2697 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2698 * 64 bits each. Each element contains the same value: a run
2699 * of between 1 and e-1 non-zero bits, rotated within the
2700 * element by between 0 and e-1 bits.
2702 * The element size and run length are encoded into immn (1 bit)
2703 * and imms (6 bits) as follows:
2704 * 64 bit elements: immn = 1, imms = <length of run - 1>
2705 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2706 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2707 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2708 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2709 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2710 * Notice that immn = 0, imms = 11111x is the only combination
2711 * not covered by one of the above options; this is reserved.
2712 * Further, <length of run - 1> all-ones is a reserved pattern.
2714 * In all cases the rotation is by immr % e (and immr is 6 bits).
2717 /* First determine the element size */
2718 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2720 /* This is the immn == 0, imms == 0x11111x case */
2730 /* <length of run - 1> mustn't be all-ones. */
2734 /* Create the value of one element: s+1 set bits rotated
2735 * by r within the element (which is e bits wide)...
2737 mask
= bitmask64(s
+ 1);
2738 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2739 /* ...then replicate the element over the whole 64 bit value */
2740 mask
= bitfield_replicate(mask
, e
);
2745 /* C3.4.4 Logical (immediate)
2746 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2747 * +----+-----+-------------+---+------+------+------+------+
2748 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2749 * +----+-----+-------------+---+------+------+------+------+
2751 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2753 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2754 TCGv_i64 tcg_rd
, tcg_rn
;
2756 bool is_and
= false;
2758 sf
= extract32(insn
, 31, 1);
2759 opc
= extract32(insn
, 29, 2);
2760 is_n
= extract32(insn
, 22, 1);
2761 immr
= extract32(insn
, 16, 6);
2762 imms
= extract32(insn
, 10, 6);
2763 rn
= extract32(insn
, 5, 5);
2764 rd
= extract32(insn
, 0, 5);
2767 unallocated_encoding(s
);
2771 if (opc
== 0x3) { /* ANDS */
2772 tcg_rd
= cpu_reg(s
, rd
);
2774 tcg_rd
= cpu_reg_sp(s
, rd
);
2776 tcg_rn
= cpu_reg(s
, rn
);
2778 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2779 /* some immediate field values are reserved */
2780 unallocated_encoding(s
);
2785 wmask
&= 0xffffffff;
2789 case 0x3: /* ANDS */
2791 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2795 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2798 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2801 assert(FALSE
); /* must handle all above */
2805 if (!sf
&& !is_and
) {
2806 /* zero extend final result; we know we can skip this for AND
2807 * since the immediate had the high 32 bits clear.
2809 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2812 if (opc
== 3) { /* ANDS */
2813 gen_logic_CC(sf
, tcg_rd
);
2818 * C3.4.5 Move wide (immediate)
2820 * 31 30 29 28 23 22 21 20 5 4 0
2821 * +--+-----+-------------+-----+----------------+------+
2822 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2823 * +--+-----+-------------+-----+----------------+------+
2825 * sf: 0 -> 32 bit, 1 -> 64 bit
2826 * opc: 00 -> N, 10 -> Z, 11 -> K
2827 * hw: shift/16 (0,16, and sf only 32, 48)
2829 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2831 int rd
= extract32(insn
, 0, 5);
2832 uint64_t imm
= extract32(insn
, 5, 16);
2833 int sf
= extract32(insn
, 31, 1);
2834 int opc
= extract32(insn
, 29, 2);
2835 int pos
= extract32(insn
, 21, 2) << 4;
2836 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2839 if (!sf
&& (pos
>= 32)) {
2840 unallocated_encoding(s
);
2854 tcg_gen_movi_i64(tcg_rd
, imm
);
2857 tcg_imm
= tcg_const_i64(imm
);
2858 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2859 tcg_temp_free_i64(tcg_imm
);
2861 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2865 unallocated_encoding(s
);
2871 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2872 * +----+-----+-------------+---+------+------+------+------+
2873 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2874 * +----+-----+-------------+---+------+------+------+------+
2876 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2878 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2879 TCGv_i64 tcg_rd
, tcg_tmp
;
2881 sf
= extract32(insn
, 31, 1);
2882 opc
= extract32(insn
, 29, 2);
2883 n
= extract32(insn
, 22, 1);
2884 ri
= extract32(insn
, 16, 6);
2885 si
= extract32(insn
, 10, 6);
2886 rn
= extract32(insn
, 5, 5);
2887 rd
= extract32(insn
, 0, 5);
2888 bitsize
= sf
? 64 : 32;
2890 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2891 unallocated_encoding(s
);
2895 tcg_rd
= cpu_reg(s
, rd
);
2896 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2898 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2900 if (opc
!= 1) { /* SBFM or UBFM */
2901 tcg_gen_movi_i64(tcg_rd
, 0);
2904 /* do the bit move operation */
2906 /* Wd<s-r:0> = Wn<s:r> */
2907 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2909 len
= (si
- ri
) + 1;
2911 /* Wd<32+s-r,32-r> = Wn<s:0> */
2916 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2918 if (opc
== 0) { /* SBFM - sign extend the destination field */
2919 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2920 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2923 if (!sf
) { /* zero extend final result */
2924 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2929 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2930 * +----+------+-------------+---+----+------+--------+------+------+
2931 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2932 * +----+------+-------------+---+----+------+--------+------+------+
2934 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2936 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2938 sf
= extract32(insn
, 31, 1);
2939 n
= extract32(insn
, 22, 1);
2940 rm
= extract32(insn
, 16, 5);
2941 imm
= extract32(insn
, 10, 6);
2942 rn
= extract32(insn
, 5, 5);
2943 rd
= extract32(insn
, 0, 5);
2944 op21
= extract32(insn
, 29, 2);
2945 op0
= extract32(insn
, 21, 1);
2946 bitsize
= sf
? 64 : 32;
2948 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2949 unallocated_encoding(s
);
2951 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2953 tcg_rd
= cpu_reg(s
, rd
);
2956 /* OPTME: we can special case rm==rn as a rotate */
2957 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2958 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2959 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
2960 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
2961 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
2963 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2966 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2967 * so an extract from bit 0 is a special case.
2970 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
2972 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
2979 /* C3.4 Data processing - immediate */
2980 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
2982 switch (extract32(insn
, 23, 6)) {
2983 case 0x20: case 0x21: /* PC-rel. addressing */
2984 disas_pc_rel_adr(s
, insn
);
2986 case 0x22: case 0x23: /* Add/subtract (immediate) */
2987 disas_add_sub_imm(s
, insn
);
2989 case 0x24: /* Logical (immediate) */
2990 disas_logic_imm(s
, insn
);
2992 case 0x25: /* Move wide (immediate) */
2993 disas_movw_imm(s
, insn
);
2995 case 0x26: /* Bitfield */
2996 disas_bitfield(s
, insn
);
2998 case 0x27: /* Extract */
2999 disas_extract(s
, insn
);
3002 unallocated_encoding(s
);
3007 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3008 * Note that it is the caller's responsibility to ensure that the
3009 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3010 * mandated semantics for out of range shifts.
3012 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3013 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3015 switch (shift_type
) {
3016 case A64_SHIFT_TYPE_LSL
:
3017 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3019 case A64_SHIFT_TYPE_LSR
:
3020 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3022 case A64_SHIFT_TYPE_ASR
:
3024 tcg_gen_ext32s_i64(dst
, src
);
3026 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3028 case A64_SHIFT_TYPE_ROR
:
3030 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3033 t0
= tcg_temp_new_i32();
3034 t1
= tcg_temp_new_i32();
3035 tcg_gen_trunc_i64_i32(t0
, src
);
3036 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
3037 tcg_gen_rotr_i32(t0
, t0
, t1
);
3038 tcg_gen_extu_i32_i64(dst
, t0
);
3039 tcg_temp_free_i32(t0
);
3040 tcg_temp_free_i32(t1
);
3044 assert(FALSE
); /* all shift types should be handled */
3048 if (!sf
) { /* zero extend final result */
3049 tcg_gen_ext32u_i64(dst
, dst
);
3053 /* Shift a TCGv src by immediate, put result in dst.
3054 * The shift amount must be in range (this should always be true as the
3055 * relevant instructions will UNDEF on bad shift immediates).
3057 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3058 enum a64_shift_type shift_type
, unsigned int shift_i
)
3060 assert(shift_i
< (sf
? 64 : 32));
3063 tcg_gen_mov_i64(dst
, src
);
3065 TCGv_i64 shift_const
;
3067 shift_const
= tcg_const_i64(shift_i
);
3068 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3069 tcg_temp_free_i64(shift_const
);
3073 /* C3.5.10 Logical (shifted register)
3074 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3075 * +----+-----+-----------+-------+---+------+--------+------+------+
3076 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3077 * +----+-----+-----------+-------+---+------+--------+------+------+
3079 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3081 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3082 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3084 sf
= extract32(insn
, 31, 1);
3085 opc
= extract32(insn
, 29, 2);
3086 shift_type
= extract32(insn
, 22, 2);
3087 invert
= extract32(insn
, 21, 1);
3088 rm
= extract32(insn
, 16, 5);
3089 shift_amount
= extract32(insn
, 10, 6);
3090 rn
= extract32(insn
, 5, 5);
3091 rd
= extract32(insn
, 0, 5);
3093 if (!sf
&& (shift_amount
& (1 << 5))) {
3094 unallocated_encoding(s
);
3098 tcg_rd
= cpu_reg(s
, rd
);
3100 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3101 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3102 * register-register MOV and MVN, so it is worth special casing.
3104 tcg_rm
= cpu_reg(s
, rm
);
3106 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3108 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3112 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3114 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3120 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3123 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3126 tcg_rn
= cpu_reg(s
, rn
);
3128 switch (opc
| (invert
<< 2)) {
3131 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3134 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3137 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3141 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3144 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3147 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3155 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3159 gen_logic_CC(sf
, tcg_rd
);
3164 * C3.5.1 Add/subtract (extended register)
3166 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3167 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3168 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3169 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3171 * sf: 0 -> 32bit, 1 -> 64bit
3172 * op: 0 -> add , 1 -> sub
3175 * option: extension type (see DecodeRegExtend)
3176 * imm3: optional shift to Rm
3178 * Rd = Rn + LSL(extend(Rm), amount)
3180 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3182 int rd
= extract32(insn
, 0, 5);
3183 int rn
= extract32(insn
, 5, 5);
3184 int imm3
= extract32(insn
, 10, 3);
3185 int option
= extract32(insn
, 13, 3);
3186 int rm
= extract32(insn
, 16, 5);
3187 bool setflags
= extract32(insn
, 29, 1);
3188 bool sub_op
= extract32(insn
, 30, 1);
3189 bool sf
= extract32(insn
, 31, 1);
3191 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3193 TCGv_i64 tcg_result
;
3196 unallocated_encoding(s
);
3200 /* non-flag setting ops may use SP */
3202 tcg_rd
= cpu_reg_sp(s
, rd
);
3204 tcg_rd
= cpu_reg(s
, rd
);
3206 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3208 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3209 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3211 tcg_result
= tcg_temp_new_i64();
3215 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3217 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3221 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3223 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3228 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3230 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3233 tcg_temp_free_i64(tcg_result
);
3237 * C3.5.2 Add/subtract (shifted register)
3239 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3240 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3241 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3242 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3244 * sf: 0 -> 32bit, 1 -> 64bit
3245 * op: 0 -> add , 1 -> sub
3247 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3248 * imm6: Shift amount to apply to Rm before the add/sub
3250 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3252 int rd
= extract32(insn
, 0, 5);
3253 int rn
= extract32(insn
, 5, 5);
3254 int imm6
= extract32(insn
, 10, 6);
3255 int rm
= extract32(insn
, 16, 5);
3256 int shift_type
= extract32(insn
, 22, 2);
3257 bool setflags
= extract32(insn
, 29, 1);
3258 bool sub_op
= extract32(insn
, 30, 1);
3259 bool sf
= extract32(insn
, 31, 1);
3261 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3262 TCGv_i64 tcg_rn
, tcg_rm
;
3263 TCGv_i64 tcg_result
;
3265 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3266 unallocated_encoding(s
);
3270 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3271 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3273 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3275 tcg_result
= tcg_temp_new_i64();
3279 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3281 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3285 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3287 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3292 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3294 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3297 tcg_temp_free_i64(tcg_result
);
3300 /* C3.5.9 Data-processing (3 source)
3302 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3303 +--+------+-----------+------+------+----+------+------+------+
3304 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3305 +--+------+-----------+------+------+----+------+------+------+
3308 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3310 int rd
= extract32(insn
, 0, 5);
3311 int rn
= extract32(insn
, 5, 5);
3312 int ra
= extract32(insn
, 10, 5);
3313 int rm
= extract32(insn
, 16, 5);
3314 int op_id
= (extract32(insn
, 29, 3) << 4) |
3315 (extract32(insn
, 21, 3) << 1) |
3316 extract32(insn
, 15, 1);
3317 bool sf
= extract32(insn
, 31, 1);
3318 bool is_sub
= extract32(op_id
, 0, 1);
3319 bool is_high
= extract32(op_id
, 2, 1);
3320 bool is_signed
= false;
3325 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3327 case 0x42: /* SMADDL */
3328 case 0x43: /* SMSUBL */
3329 case 0x44: /* SMULH */
3332 case 0x0: /* MADD (32bit) */
3333 case 0x1: /* MSUB (32bit) */
3334 case 0x40: /* MADD (64bit) */
3335 case 0x41: /* MSUB (64bit) */
3336 case 0x4a: /* UMADDL */
3337 case 0x4b: /* UMSUBL */
3338 case 0x4c: /* UMULH */
3341 unallocated_encoding(s
);
3346 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3347 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3348 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3349 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3352 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3354 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3357 tcg_temp_free_i64(low_bits
);
3361 tcg_op1
= tcg_temp_new_i64();
3362 tcg_op2
= tcg_temp_new_i64();
3363 tcg_tmp
= tcg_temp_new_i64();
3366 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3367 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3370 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3371 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3373 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3374 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3378 if (ra
== 31 && !is_sub
) {
3379 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3380 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3382 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3384 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3386 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3391 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3394 tcg_temp_free_i64(tcg_op1
);
3395 tcg_temp_free_i64(tcg_op2
);
3396 tcg_temp_free_i64(tcg_tmp
);
3399 /* C3.5.3 - Add/subtract (with carry)
3400 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3401 * +--+--+--+------------------------+------+---------+------+-----+
3402 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3403 * +--+--+--+------------------------+------+---------+------+-----+
3407 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3409 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3410 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3412 if (extract32(insn
, 10, 6) != 0) {
3413 unallocated_encoding(s
);
3417 sf
= extract32(insn
, 31, 1);
3418 op
= extract32(insn
, 30, 1);
3419 setflags
= extract32(insn
, 29, 1);
3420 rm
= extract32(insn
, 16, 5);
3421 rn
= extract32(insn
, 5, 5);
3422 rd
= extract32(insn
, 0, 5);
3424 tcg_rd
= cpu_reg(s
, rd
);
3425 tcg_rn
= cpu_reg(s
, rn
);
3428 tcg_y
= new_tmp_a64(s
);
3429 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3431 tcg_y
= cpu_reg(s
, rm
);
3435 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3437 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3441 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3442 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3443 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3444 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3445 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3448 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3450 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3451 int label_continue
= -1;
3452 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3454 if (!extract32(insn
, 29, 1)) {
3455 unallocated_encoding(s
);
3458 if (insn
& (1 << 10 | 1 << 4)) {
3459 unallocated_encoding(s
);
3462 sf
= extract32(insn
, 31, 1);
3463 op
= extract32(insn
, 30, 1);
3464 is_imm
= extract32(insn
, 11, 1);
3465 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3466 cond
= extract32(insn
, 12, 4);
3467 rn
= extract32(insn
, 5, 5);
3468 nzcv
= extract32(insn
, 0, 4);
3470 if (cond
< 0x0e) { /* not always */
3471 int label_match
= gen_new_label();
3472 label_continue
= gen_new_label();
3473 arm_gen_test_cc(cond
, label_match
);
3475 tcg_tmp
= tcg_temp_new_i64();
3476 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3477 gen_set_nzcv(tcg_tmp
);
3478 tcg_temp_free_i64(tcg_tmp
);
3479 tcg_gen_br(label_continue
);
3480 gen_set_label(label_match
);
3482 /* match, or condition is always */
3484 tcg_y
= new_tmp_a64(s
);
3485 tcg_gen_movi_i64(tcg_y
, y
);
3487 tcg_y
= cpu_reg(s
, y
);
3489 tcg_rn
= cpu_reg(s
, rn
);
3491 tcg_tmp
= tcg_temp_new_i64();
3493 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3495 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3497 tcg_temp_free_i64(tcg_tmp
);
3499 if (cond
< 0x0e) { /* continue */
3500 gen_set_label(label_continue
);
3504 /* C3.5.6 Conditional select
3505 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3506 * +----+----+---+-----------------+------+------+-----+------+------+
3507 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3508 * +----+----+---+-----------------+------+------+-----+------+------+
3510 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3512 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3513 TCGv_i64 tcg_rd
, tcg_src
;
3515 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3516 /* S == 1 or op2<1> == 1 */
3517 unallocated_encoding(s
);
3520 sf
= extract32(insn
, 31, 1);
3521 else_inv
= extract32(insn
, 30, 1);
3522 rm
= extract32(insn
, 16, 5);
3523 cond
= extract32(insn
, 12, 4);
3524 else_inc
= extract32(insn
, 10, 1);
3525 rn
= extract32(insn
, 5, 5);
3526 rd
= extract32(insn
, 0, 5);
3529 /* silly no-op write; until we use movcond we must special-case
3530 * this to avoid a dead temporary across basic blocks.
3535 tcg_rd
= cpu_reg(s
, rd
);
3537 if (cond
>= 0x0e) { /* condition "always" */
3538 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3539 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3541 /* OPTME: we could use movcond here, at the cost of duplicating
3542 * a lot of the arm_gen_test_cc() logic.
3544 int label_match
= gen_new_label();
3545 int label_continue
= gen_new_label();
3547 arm_gen_test_cc(cond
, label_match
);
3549 tcg_src
= cpu_reg(s
, rm
);
3551 if (else_inv
&& else_inc
) {
3552 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3553 } else if (else_inv
) {
3554 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3555 } else if (else_inc
) {
3556 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3558 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3561 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3563 tcg_gen_br(label_continue
);
3565 gen_set_label(label_match
);
3566 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3567 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3569 gen_set_label(label_continue
);
3573 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3574 unsigned int rn
, unsigned int rd
)
3576 TCGv_i64 tcg_rd
, tcg_rn
;
3577 tcg_rd
= cpu_reg(s
, rd
);
3578 tcg_rn
= cpu_reg(s
, rn
);
3581 gen_helper_clz64(tcg_rd
, tcg_rn
);
3583 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3584 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3585 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3586 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3587 tcg_temp_free_i32(tcg_tmp32
);
3591 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3592 unsigned int rn
, unsigned int rd
)
3594 TCGv_i64 tcg_rd
, tcg_rn
;
3595 tcg_rd
= cpu_reg(s
, rd
);
3596 tcg_rn
= cpu_reg(s
, rn
);
3599 gen_helper_cls64(tcg_rd
, tcg_rn
);
3601 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3602 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3603 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3604 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3605 tcg_temp_free_i32(tcg_tmp32
);
3609 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3610 unsigned int rn
, unsigned int rd
)
3612 TCGv_i64 tcg_rd
, tcg_rn
;
3613 tcg_rd
= cpu_reg(s
, rd
);
3614 tcg_rn
= cpu_reg(s
, rn
);
3617 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3619 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3620 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3621 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3622 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3623 tcg_temp_free_i32(tcg_tmp32
);
3627 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3628 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3629 unsigned int rn
, unsigned int rd
)
3632 unallocated_encoding(s
);
3635 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3638 /* C5.6.149 REV with sf==0, opcode==2
3639 * C5.6.151 REV32 (sf==1, opcode==2)
3641 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3642 unsigned int rn
, unsigned int rd
)
3644 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3647 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3648 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3650 /* bswap32_i64 requires zero high word */
3651 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3652 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3653 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3654 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3655 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3657 tcg_temp_free_i64(tcg_tmp
);
3659 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3660 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3664 /* C5.6.150 REV16 (opcode==1) */
3665 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3666 unsigned int rn
, unsigned int rd
)
3668 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3669 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3670 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3672 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3673 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3675 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3676 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3677 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3678 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3681 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3682 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3683 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3684 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3686 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3687 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3688 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3691 tcg_temp_free_i64(tcg_tmp
);
3694 /* C3.5.7 Data-processing (1 source)
3695 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3696 * +----+---+---+-----------------+---------+--------+------+------+
3697 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3698 * +----+---+---+-----------------+---------+--------+------+------+
3700 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3702 unsigned int sf
, opcode
, rn
, rd
;
3704 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3705 unallocated_encoding(s
);
3709 sf
= extract32(insn
, 31, 1);
3710 opcode
= extract32(insn
, 10, 6);
3711 rn
= extract32(insn
, 5, 5);
3712 rd
= extract32(insn
, 0, 5);
3716 handle_rbit(s
, sf
, rn
, rd
);
3719 handle_rev16(s
, sf
, rn
, rd
);
3722 handle_rev32(s
, sf
, rn
, rd
);
3725 handle_rev64(s
, sf
, rn
, rd
);
3728 handle_clz(s
, sf
, rn
, rd
);
3731 handle_cls(s
, sf
, rn
, rd
);
3736 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3737 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3739 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3740 tcg_rd
= cpu_reg(s
, rd
);
3742 if (!sf
&& is_signed
) {
3743 tcg_n
= new_tmp_a64(s
);
3744 tcg_m
= new_tmp_a64(s
);
3745 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3746 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3748 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3749 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3753 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3755 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3758 if (!sf
) { /* zero extend final result */
3759 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3763 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3764 static void handle_shift_reg(DisasContext
*s
,
3765 enum a64_shift_type shift_type
, unsigned int sf
,
3766 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3768 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3769 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3770 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3772 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3773 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3774 tcg_temp_free_i64(tcg_shift
);
3777 /* C3.5.8 Data-processing (2 source)
3778 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3779 * +----+---+---+-----------------+------+--------+------+------+
3780 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3781 * +----+---+---+-----------------+------+--------+------+------+
3783 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3785 unsigned int sf
, rm
, opcode
, rn
, rd
;
3786 sf
= extract32(insn
, 31, 1);
3787 rm
= extract32(insn
, 16, 5);
3788 opcode
= extract32(insn
, 10, 6);
3789 rn
= extract32(insn
, 5, 5);
3790 rd
= extract32(insn
, 0, 5);
3792 if (extract32(insn
, 29, 1)) {
3793 unallocated_encoding(s
);
3799 handle_div(s
, false, sf
, rm
, rn
, rd
);
3802 handle_div(s
, true, sf
, rm
, rn
, rd
);
3805 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3808 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3811 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3814 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3823 case 23: /* CRC32 */
3824 unsupported_encoding(s
, insn
);
3827 unallocated_encoding(s
);
3832 /* C3.5 Data processing - register */
3833 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3835 switch (extract32(insn
, 24, 5)) {
3836 case 0x0a: /* Logical (shifted register) */
3837 disas_logic_reg(s
, insn
);
3839 case 0x0b: /* Add/subtract */
3840 if (insn
& (1 << 21)) { /* (extended register) */
3841 disas_add_sub_ext_reg(s
, insn
);
3843 disas_add_sub_reg(s
, insn
);
3846 case 0x1b: /* Data-processing (3 source) */
3847 disas_data_proc_3src(s
, insn
);
3850 switch (extract32(insn
, 21, 3)) {
3851 case 0x0: /* Add/subtract (with carry) */
3852 disas_adc_sbc(s
, insn
);
3854 case 0x2: /* Conditional compare */
3855 disas_cc(s
, insn
); /* both imm and reg forms */
3857 case 0x4: /* Conditional select */
3858 disas_cond_select(s
, insn
);
3860 case 0x6: /* Data-processing */
3861 if (insn
& (1 << 30)) { /* (1 source) */
3862 disas_data_proc_1src(s
, insn
);
3863 } else { /* (2 source) */
3864 disas_data_proc_2src(s
, insn
);
3868 unallocated_encoding(s
);
3873 unallocated_encoding(s
);
3878 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
3879 unsigned int rn
, unsigned int rm
,
3880 bool cmp_with_zero
, bool signal_all_nans
)
3882 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
3883 TCGv_ptr fpst
= get_fpstatus_ptr();
3886 TCGv_i64 tcg_vn
, tcg_vm
;
3888 tcg_vn
= read_fp_dreg(s
, rn
);
3889 if (cmp_with_zero
) {
3890 tcg_vm
= tcg_const_i64(0);
3892 tcg_vm
= read_fp_dreg(s
, rm
);
3894 if (signal_all_nans
) {
3895 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3897 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3899 tcg_temp_free_i64(tcg_vn
);
3900 tcg_temp_free_i64(tcg_vm
);
3902 TCGv_i32 tcg_vn
, tcg_vm
;
3904 tcg_vn
= read_fp_sreg(s
, rn
);
3905 if (cmp_with_zero
) {
3906 tcg_vm
= tcg_const_i32(0);
3908 tcg_vm
= read_fp_sreg(s
, rm
);
3910 if (signal_all_nans
) {
3911 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3913 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3915 tcg_temp_free_i32(tcg_vn
);
3916 tcg_temp_free_i32(tcg_vm
);
3919 tcg_temp_free_ptr(fpst
);
3921 gen_set_nzcv(tcg_flags
);
3923 tcg_temp_free_i64(tcg_flags
);
3926 /* C3.6.22 Floating point compare
3927 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
3928 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3929 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
3930 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3932 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
3934 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
3936 mos
= extract32(insn
, 29, 3);
3937 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3938 rm
= extract32(insn
, 16, 5);
3939 op
= extract32(insn
, 14, 2);
3940 rn
= extract32(insn
, 5, 5);
3941 opc
= extract32(insn
, 3, 2);
3942 op2r
= extract32(insn
, 0, 3);
3944 if (mos
|| op
|| op2r
|| type
> 1) {
3945 unallocated_encoding(s
);
3949 if (!fp_access_check(s
)) {
3953 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
3956 /* C3.6.23 Floating point conditional compare
3957 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3958 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3959 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
3960 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3962 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
3964 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
3966 int label_continue
= -1;
3968 mos
= extract32(insn
, 29, 3);
3969 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3970 rm
= extract32(insn
, 16, 5);
3971 cond
= extract32(insn
, 12, 4);
3972 rn
= extract32(insn
, 5, 5);
3973 op
= extract32(insn
, 4, 1);
3974 nzcv
= extract32(insn
, 0, 4);
3976 if (mos
|| type
> 1) {
3977 unallocated_encoding(s
);
3981 if (!fp_access_check(s
)) {
3985 if (cond
< 0x0e) { /* not always */
3986 int label_match
= gen_new_label();
3987 label_continue
= gen_new_label();
3988 arm_gen_test_cc(cond
, label_match
);
3990 tcg_flags
= tcg_const_i64(nzcv
<< 28);
3991 gen_set_nzcv(tcg_flags
);
3992 tcg_temp_free_i64(tcg_flags
);
3993 tcg_gen_br(label_continue
);
3994 gen_set_label(label_match
);
3997 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4000 gen_set_label(label_continue
);
4004 /* copy src FP register to dst FP register; type specifies single or double */
4005 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
4008 TCGv_i64 v
= read_fp_dreg(s
, src
);
4009 write_fp_dreg(s
, dst
, v
);
4010 tcg_temp_free_i64(v
);
4012 TCGv_i32 v
= read_fp_sreg(s
, src
);
4013 write_fp_sreg(s
, dst
, v
);
4014 tcg_temp_free_i32(v
);
4018 /* C3.6.24 Floating point conditional select
4019 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4020 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4021 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4022 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4024 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4026 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4027 int label_continue
= -1;
4029 mos
= extract32(insn
, 29, 3);
4030 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4031 rm
= extract32(insn
, 16, 5);
4032 cond
= extract32(insn
, 12, 4);
4033 rn
= extract32(insn
, 5, 5);
4034 rd
= extract32(insn
, 0, 5);
4036 if (mos
|| type
> 1) {
4037 unallocated_encoding(s
);
4041 if (!fp_access_check(s
)) {
4045 if (cond
< 0x0e) { /* not always */
4046 int label_match
= gen_new_label();
4047 label_continue
= gen_new_label();
4048 arm_gen_test_cc(cond
, label_match
);
4050 gen_mov_fp2fp(s
, type
, rd
, rm
);
4051 tcg_gen_br(label_continue
);
4052 gen_set_label(label_match
);
4055 gen_mov_fp2fp(s
, type
, rd
, rn
);
4057 if (cond
< 0x0e) { /* continue */
4058 gen_set_label(label_continue
);
4062 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4063 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4069 fpst
= get_fpstatus_ptr();
4070 tcg_op
= read_fp_sreg(s
, rn
);
4071 tcg_res
= tcg_temp_new_i32();
4074 case 0x0: /* FMOV */
4075 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4077 case 0x1: /* FABS */
4078 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4080 case 0x2: /* FNEG */
4081 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4083 case 0x3: /* FSQRT */
4084 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4086 case 0x8: /* FRINTN */
4087 case 0x9: /* FRINTP */
4088 case 0xa: /* FRINTM */
4089 case 0xb: /* FRINTZ */
4090 case 0xc: /* FRINTA */
4092 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4094 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4095 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4097 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4098 tcg_temp_free_i32(tcg_rmode
);
4101 case 0xe: /* FRINTX */
4102 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4104 case 0xf: /* FRINTI */
4105 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4111 write_fp_sreg(s
, rd
, tcg_res
);
4113 tcg_temp_free_ptr(fpst
);
4114 tcg_temp_free_i32(tcg_op
);
4115 tcg_temp_free_i32(tcg_res
);
4118 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4119 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4125 fpst
= get_fpstatus_ptr();
4126 tcg_op
= read_fp_dreg(s
, rn
);
4127 tcg_res
= tcg_temp_new_i64();
4130 case 0x0: /* FMOV */
4131 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4133 case 0x1: /* FABS */
4134 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4136 case 0x2: /* FNEG */
4137 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4139 case 0x3: /* FSQRT */
4140 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4142 case 0x8: /* FRINTN */
4143 case 0x9: /* FRINTP */
4144 case 0xa: /* FRINTM */
4145 case 0xb: /* FRINTZ */
4146 case 0xc: /* FRINTA */
4148 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4150 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4151 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4153 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4154 tcg_temp_free_i32(tcg_rmode
);
4157 case 0xe: /* FRINTX */
4158 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4160 case 0xf: /* FRINTI */
4161 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4167 write_fp_dreg(s
, rd
, tcg_res
);
4169 tcg_temp_free_ptr(fpst
);
4170 tcg_temp_free_i64(tcg_op
);
4171 tcg_temp_free_i64(tcg_res
);
4174 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4175 int rd
, int rn
, int dtype
, int ntype
)
4180 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4182 /* Single to double */
4183 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4184 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4185 write_fp_dreg(s
, rd
, tcg_rd
);
4186 tcg_temp_free_i64(tcg_rd
);
4188 /* Single to half */
4189 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4190 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4191 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4192 write_fp_sreg(s
, rd
, tcg_rd
);
4193 tcg_temp_free_i32(tcg_rd
);
4195 tcg_temp_free_i32(tcg_rn
);
4200 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4201 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4203 /* Double to single */
4204 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4206 /* Double to half */
4207 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4208 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4210 write_fp_sreg(s
, rd
, tcg_rd
);
4211 tcg_temp_free_i32(tcg_rd
);
4212 tcg_temp_free_i64(tcg_rn
);
4217 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4218 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4220 /* Half to single */
4221 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4222 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4223 write_fp_sreg(s
, rd
, tcg_rd
);
4224 tcg_temp_free_i32(tcg_rd
);
4226 /* Half to double */
4227 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4228 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4229 write_fp_dreg(s
, rd
, tcg_rd
);
4230 tcg_temp_free_i64(tcg_rd
);
4232 tcg_temp_free_i32(tcg_rn
);
4240 /* C3.6.25 Floating point data-processing (1 source)
4241 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4242 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4243 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4244 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4246 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4248 int type
= extract32(insn
, 22, 2);
4249 int opcode
= extract32(insn
, 15, 6);
4250 int rn
= extract32(insn
, 5, 5);
4251 int rd
= extract32(insn
, 0, 5);
4254 case 0x4: case 0x5: case 0x7:
4256 /* FCVT between half, single and double precision */
4257 int dtype
= extract32(opcode
, 0, 2);
4258 if (type
== 2 || dtype
== type
) {
4259 unallocated_encoding(s
);
4262 if (!fp_access_check(s
)) {
4266 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4272 /* 32-to-32 and 64-to-64 ops */
4275 if (!fp_access_check(s
)) {
4279 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4282 if (!fp_access_check(s
)) {
4286 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4289 unallocated_encoding(s
);
4293 unallocated_encoding(s
);
4298 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4299 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4300 int rd
, int rn
, int rm
)
4307 tcg_res
= tcg_temp_new_i32();
4308 fpst
= get_fpstatus_ptr();
4309 tcg_op1
= read_fp_sreg(s
, rn
);
4310 tcg_op2
= read_fp_sreg(s
, rm
);
4313 case 0x0: /* FMUL */
4314 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4316 case 0x1: /* FDIV */
4317 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4319 case 0x2: /* FADD */
4320 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4322 case 0x3: /* FSUB */
4323 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4325 case 0x4: /* FMAX */
4326 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4328 case 0x5: /* FMIN */
4329 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4331 case 0x6: /* FMAXNM */
4332 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4334 case 0x7: /* FMINNM */
4335 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4337 case 0x8: /* FNMUL */
4338 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4339 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4343 write_fp_sreg(s
, rd
, tcg_res
);
4345 tcg_temp_free_ptr(fpst
);
4346 tcg_temp_free_i32(tcg_op1
);
4347 tcg_temp_free_i32(tcg_op2
);
4348 tcg_temp_free_i32(tcg_res
);
4351 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4352 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4353 int rd
, int rn
, int rm
)
4360 tcg_res
= tcg_temp_new_i64();
4361 fpst
= get_fpstatus_ptr();
4362 tcg_op1
= read_fp_dreg(s
, rn
);
4363 tcg_op2
= read_fp_dreg(s
, rm
);
4366 case 0x0: /* FMUL */
4367 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4369 case 0x1: /* FDIV */
4370 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4372 case 0x2: /* FADD */
4373 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4375 case 0x3: /* FSUB */
4376 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4378 case 0x4: /* FMAX */
4379 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4381 case 0x5: /* FMIN */
4382 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4384 case 0x6: /* FMAXNM */
4385 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4387 case 0x7: /* FMINNM */
4388 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4390 case 0x8: /* FNMUL */
4391 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4392 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4396 write_fp_dreg(s
, rd
, tcg_res
);
4398 tcg_temp_free_ptr(fpst
);
4399 tcg_temp_free_i64(tcg_op1
);
4400 tcg_temp_free_i64(tcg_op2
);
4401 tcg_temp_free_i64(tcg_res
);
4404 /* C3.6.26 Floating point data-processing (2 source)
4405 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4406 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4407 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4408 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4410 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4412 int type
= extract32(insn
, 22, 2);
4413 int rd
= extract32(insn
, 0, 5);
4414 int rn
= extract32(insn
, 5, 5);
4415 int rm
= extract32(insn
, 16, 5);
4416 int opcode
= extract32(insn
, 12, 4);
4419 unallocated_encoding(s
);
4425 if (!fp_access_check(s
)) {
4428 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4431 if (!fp_access_check(s
)) {
4434 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4437 unallocated_encoding(s
);
4441 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4442 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4443 int rd
, int rn
, int rm
, int ra
)
4445 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4446 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4447 TCGv_ptr fpst
= get_fpstatus_ptr();
4449 tcg_op1
= read_fp_sreg(s
, rn
);
4450 tcg_op2
= read_fp_sreg(s
, rm
);
4451 tcg_op3
= read_fp_sreg(s
, ra
);
4453 /* These are fused multiply-add, and must be done as one
4454 * floating point operation with no rounding between the
4455 * multiplication and addition steps.
4456 * NB that doing the negations here as separate steps is
4457 * correct : an input NaN should come out with its sign bit
4458 * flipped if it is a negated-input.
4461 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4465 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4468 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4470 write_fp_sreg(s
, rd
, tcg_res
);
4472 tcg_temp_free_ptr(fpst
);
4473 tcg_temp_free_i32(tcg_op1
);
4474 tcg_temp_free_i32(tcg_op2
);
4475 tcg_temp_free_i32(tcg_op3
);
4476 tcg_temp_free_i32(tcg_res
);
4479 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4480 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4481 int rd
, int rn
, int rm
, int ra
)
4483 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4484 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4485 TCGv_ptr fpst
= get_fpstatus_ptr();
4487 tcg_op1
= read_fp_dreg(s
, rn
);
4488 tcg_op2
= read_fp_dreg(s
, rm
);
4489 tcg_op3
= read_fp_dreg(s
, ra
);
4491 /* These are fused multiply-add, and must be done as one
4492 * floating point operation with no rounding between the
4493 * multiplication and addition steps.
4494 * NB that doing the negations here as separate steps is
4495 * correct : an input NaN should come out with its sign bit
4496 * flipped if it is a negated-input.
4499 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4503 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4506 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4508 write_fp_dreg(s
, rd
, tcg_res
);
4510 tcg_temp_free_ptr(fpst
);
4511 tcg_temp_free_i64(tcg_op1
);
4512 tcg_temp_free_i64(tcg_op2
);
4513 tcg_temp_free_i64(tcg_op3
);
4514 tcg_temp_free_i64(tcg_res
);
4517 /* C3.6.27 Floating point data-processing (3 source)
4518 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4519 * +---+---+---+-----------+------+----+------+----+------+------+------+
4520 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4521 * +---+---+---+-----------+------+----+------+----+------+------+------+
4523 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4525 int type
= extract32(insn
, 22, 2);
4526 int rd
= extract32(insn
, 0, 5);
4527 int rn
= extract32(insn
, 5, 5);
4528 int ra
= extract32(insn
, 10, 5);
4529 int rm
= extract32(insn
, 16, 5);
4530 bool o0
= extract32(insn
, 15, 1);
4531 bool o1
= extract32(insn
, 21, 1);
4535 if (!fp_access_check(s
)) {
4538 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4541 if (!fp_access_check(s
)) {
4544 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4547 unallocated_encoding(s
);
4551 /* C3.6.28 Floating point immediate
4552 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4553 * +---+---+---+-----------+------+---+------------+-------+------+------+
4554 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4555 * +---+---+---+-----------+------+---+------------+-------+------+------+
4557 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4559 int rd
= extract32(insn
, 0, 5);
4560 int imm8
= extract32(insn
, 13, 8);
4561 int is_double
= extract32(insn
, 22, 2);
4565 if (is_double
> 1) {
4566 unallocated_encoding(s
);
4570 if (!fp_access_check(s
)) {
4574 /* The imm8 encodes the sign bit, enough bits to represent
4575 * an exponent in the range 01....1xx to 10....0xx,
4576 * and the most significant 4 bits of the mantissa; see
4577 * VFPExpandImm() in the v8 ARM ARM.
4580 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4581 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4582 extract32(imm8
, 0, 6);
4585 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4586 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4587 (extract32(imm8
, 0, 6) << 3);
4591 tcg_res
= tcg_const_i64(imm
);
4592 write_fp_dreg(s
, rd
, tcg_res
);
4593 tcg_temp_free_i64(tcg_res
);
4596 /* Handle floating point <=> fixed point conversions. Note that we can
4597 * also deal with fp <=> integer conversions as a special case (scale == 64)
4598 * OPTME: consider handling that special case specially or at least skipping
4599 * the call to scalbn in the helpers for zero shifts.
4601 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4602 bool itof
, int rmode
, int scale
, int sf
, int type
)
4604 bool is_signed
= !(opcode
& 1);
4605 bool is_double
= type
;
4606 TCGv_ptr tcg_fpstatus
;
4609 tcg_fpstatus
= get_fpstatus_ptr();
4611 tcg_shift
= tcg_const_i32(64 - scale
);
4614 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4616 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4619 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4621 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4624 tcg_int
= tcg_extend
;
4628 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4630 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4631 tcg_shift
, tcg_fpstatus
);
4633 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4634 tcg_shift
, tcg_fpstatus
);
4636 write_fp_dreg(s
, rd
, tcg_double
);
4637 tcg_temp_free_i64(tcg_double
);
4639 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4641 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4642 tcg_shift
, tcg_fpstatus
);
4644 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4645 tcg_shift
, tcg_fpstatus
);
4647 write_fp_sreg(s
, rd
, tcg_single
);
4648 tcg_temp_free_i32(tcg_single
);
4651 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4654 if (extract32(opcode
, 2, 1)) {
4655 /* There are too many rounding modes to all fit into rmode,
4656 * so FCVTA[US] is a special case.
4658 rmode
= FPROUNDING_TIEAWAY
;
4661 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4663 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4666 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4669 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4670 tcg_shift
, tcg_fpstatus
);
4672 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4673 tcg_shift
, tcg_fpstatus
);
4677 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4678 tcg_shift
, tcg_fpstatus
);
4680 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4681 tcg_shift
, tcg_fpstatus
);
4684 tcg_temp_free_i64(tcg_double
);
4686 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4689 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4690 tcg_shift
, tcg_fpstatus
);
4692 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4693 tcg_shift
, tcg_fpstatus
);
4696 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4698 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4699 tcg_shift
, tcg_fpstatus
);
4701 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4702 tcg_shift
, tcg_fpstatus
);
4704 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4705 tcg_temp_free_i32(tcg_dest
);
4707 tcg_temp_free_i32(tcg_single
);
4710 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4711 tcg_temp_free_i32(tcg_rmode
);
4714 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4718 tcg_temp_free_ptr(tcg_fpstatus
);
4719 tcg_temp_free_i32(tcg_shift
);
4722 /* C3.6.29 Floating point <-> fixed point conversions
4723 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4724 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4725 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4726 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4728 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4730 int rd
= extract32(insn
, 0, 5);
4731 int rn
= extract32(insn
, 5, 5);
4732 int scale
= extract32(insn
, 10, 6);
4733 int opcode
= extract32(insn
, 16, 3);
4734 int rmode
= extract32(insn
, 19, 2);
4735 int type
= extract32(insn
, 22, 2);
4736 bool sbit
= extract32(insn
, 29, 1);
4737 bool sf
= extract32(insn
, 31, 1);
4740 if (sbit
|| (type
> 1)
4741 || (!sf
&& scale
< 32)) {
4742 unallocated_encoding(s
);
4746 switch ((rmode
<< 3) | opcode
) {
4747 case 0x2: /* SCVTF */
4748 case 0x3: /* UCVTF */
4751 case 0x18: /* FCVTZS */
4752 case 0x19: /* FCVTZU */
4756 unallocated_encoding(s
);
4760 if (!fp_access_check(s
)) {
4764 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4767 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4769 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4770 * without conversion.
4774 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4780 TCGv_i64 tmp
= tcg_temp_new_i64();
4781 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4782 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4783 tcg_gen_movi_i64(tmp
, 0);
4784 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4785 tcg_temp_free_i64(tmp
);
4791 TCGv_i64 tmp
= tcg_const_i64(0);
4792 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4793 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4794 tcg_temp_free_i64(tmp
);
4798 /* 64 bit to top half. */
4799 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4803 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4808 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
4812 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
4815 /* 64 bits from top half */
4816 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
4822 /* C3.6.30 Floating point <-> integer conversions
4823 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4824 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4825 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4826 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4828 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4830 int rd
= extract32(insn
, 0, 5);
4831 int rn
= extract32(insn
, 5, 5);
4832 int opcode
= extract32(insn
, 16, 3);
4833 int rmode
= extract32(insn
, 19, 2);
4834 int type
= extract32(insn
, 22, 2);
4835 bool sbit
= extract32(insn
, 29, 1);
4836 bool sf
= extract32(insn
, 31, 1);
4839 unallocated_encoding(s
);
4845 bool itof
= opcode
& 1;
4848 unallocated_encoding(s
);
4852 switch (sf
<< 3 | type
<< 1 | rmode
) {
4853 case 0x0: /* 32 bit */
4854 case 0xa: /* 64 bit */
4855 case 0xd: /* 64 bit to top half of quad */
4858 /* all other sf/type/rmode combinations are invalid */
4859 unallocated_encoding(s
);
4863 if (!fp_access_check(s
)) {
4866 handle_fmov(s
, rd
, rn
, type
, itof
);
4868 /* actual FP conversions */
4869 bool itof
= extract32(opcode
, 1, 1);
4871 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
4872 unallocated_encoding(s
);
4876 if (!fp_access_check(s
)) {
4879 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
4883 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
4884 * 31 30 29 28 25 24 0
4885 * +---+---+---+---------+-----------------------------+
4886 * | | 0 | | 1 1 1 1 | |
4887 * +---+---+---+---------+-----------------------------+
4889 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
4891 if (extract32(insn
, 24, 1)) {
4892 /* Floating point data-processing (3 source) */
4893 disas_fp_3src(s
, insn
);
4894 } else if (extract32(insn
, 21, 1) == 0) {
4895 /* Floating point to fixed point conversions */
4896 disas_fp_fixed_conv(s
, insn
);
4898 switch (extract32(insn
, 10, 2)) {
4900 /* Floating point conditional compare */
4901 disas_fp_ccomp(s
, insn
);
4904 /* Floating point data-processing (2 source) */
4905 disas_fp_2src(s
, insn
);
4908 /* Floating point conditional select */
4909 disas_fp_csel(s
, insn
);
4912 switch (ctz32(extract32(insn
, 12, 4))) {
4913 case 0: /* [15:12] == xxx1 */
4914 /* Floating point immediate */
4915 disas_fp_imm(s
, insn
);
4917 case 1: /* [15:12] == xx10 */
4918 /* Floating point compare */
4919 disas_fp_compare(s
, insn
);
4921 case 2: /* [15:12] == x100 */
4922 /* Floating point data-processing (1 source) */
4923 disas_fp_1src(s
, insn
);
4925 case 3: /* [15:12] == 1000 */
4926 unallocated_encoding(s
);
4928 default: /* [15:12] == 0000 */
4929 /* Floating point <-> integer conversions */
4930 disas_fp_int_conv(s
, insn
);
4938 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
4941 /* Extract 64 bits from the middle of two concatenated 64 bit
4942 * vector register slices left:right. The extracted bits start
4943 * at 'pos' bits into the right (least significant) side.
4944 * We return the result in tcg_right, and guarantee not to
4947 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4948 assert(pos
> 0 && pos
< 64);
4950 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
4951 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
4952 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
4954 tcg_temp_free_i64(tcg_tmp
);
4958 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
4959 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4960 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
4961 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4963 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
4965 int is_q
= extract32(insn
, 30, 1);
4966 int op2
= extract32(insn
, 22, 2);
4967 int imm4
= extract32(insn
, 11, 4);
4968 int rm
= extract32(insn
, 16, 5);
4969 int rn
= extract32(insn
, 5, 5);
4970 int rd
= extract32(insn
, 0, 5);
4971 int pos
= imm4
<< 3;
4972 TCGv_i64 tcg_resl
, tcg_resh
;
4974 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
4975 unallocated_encoding(s
);
4979 if (!fp_access_check(s
)) {
4983 tcg_resh
= tcg_temp_new_i64();
4984 tcg_resl
= tcg_temp_new_i64();
4986 /* Vd gets bits starting at pos bits into Vm:Vn. This is
4987 * either extracting 128 bits from a 128:128 concatenation, or
4988 * extracting 64 bits from a 64:64 concatenation.
4991 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
4993 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
4994 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
4996 tcg_gen_movi_i64(tcg_resh
, 0);
5003 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5004 EltPosns
*elt
= eltposns
;
5011 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5013 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5016 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5017 tcg_hh
= tcg_temp_new_i64();
5018 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5019 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5020 tcg_temp_free_i64(tcg_hh
);
5024 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5025 tcg_temp_free_i64(tcg_resl
);
5026 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5027 tcg_temp_free_i64(tcg_resh
);
5031 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5032 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5033 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5034 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5036 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5038 int op2
= extract32(insn
, 22, 2);
5039 int is_q
= extract32(insn
, 30, 1);
5040 int rm
= extract32(insn
, 16, 5);
5041 int rn
= extract32(insn
, 5, 5);
5042 int rd
= extract32(insn
, 0, 5);
5043 int is_tblx
= extract32(insn
, 12, 1);
5044 int len
= extract32(insn
, 13, 2);
5045 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5046 TCGv_i32 tcg_regno
, tcg_numregs
;
5049 unallocated_encoding(s
);
5053 if (!fp_access_check(s
)) {
5057 /* This does a table lookup: for every byte element in the input
5058 * we index into a table formed from up to four vector registers,
5059 * and then the output is the result of the lookups. Our helper
5060 * function does the lookup operation for a single 64 bit part of
5063 tcg_resl
= tcg_temp_new_i64();
5064 tcg_resh
= tcg_temp_new_i64();
5067 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5069 tcg_gen_movi_i64(tcg_resl
, 0);
5071 if (is_tblx
&& is_q
) {
5072 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5074 tcg_gen_movi_i64(tcg_resh
, 0);
5077 tcg_idx
= tcg_temp_new_i64();
5078 tcg_regno
= tcg_const_i32(rn
);
5079 tcg_numregs
= tcg_const_i32(len
+ 1);
5080 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5081 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5082 tcg_regno
, tcg_numregs
);
5084 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5085 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5086 tcg_regno
, tcg_numregs
);
5088 tcg_temp_free_i64(tcg_idx
);
5089 tcg_temp_free_i32(tcg_regno
);
5090 tcg_temp_free_i32(tcg_numregs
);
5092 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5093 tcg_temp_free_i64(tcg_resl
);
5094 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5095 tcg_temp_free_i64(tcg_resh
);
5098 /* C3.6.3 ZIP/UZP/TRN
5099 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5100 * +---+---+-------------+------+---+------+---+------------------+------+
5101 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5102 * +---+---+-------------+------+---+------+---+------------------+------+
5104 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5106 int rd
= extract32(insn
, 0, 5);
5107 int rn
= extract32(insn
, 5, 5);
5108 int rm
= extract32(insn
, 16, 5);
5109 int size
= extract32(insn
, 22, 2);
5110 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5111 * bit 2 indicates 1 vs 2 variant of the insn.
5113 int opcode
= extract32(insn
, 12, 2);
5114 bool part
= extract32(insn
, 14, 1);
5115 bool is_q
= extract32(insn
, 30, 1);
5116 int esize
= 8 << size
;
5118 int datasize
= is_q
? 128 : 64;
5119 int elements
= datasize
/ esize
;
5120 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5122 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5123 unallocated_encoding(s
);
5127 if (!fp_access_check(s
)) {
5131 tcg_resl
= tcg_const_i64(0);
5132 tcg_resh
= tcg_const_i64(0);
5133 tcg_res
= tcg_temp_new_i64();
5135 for (i
= 0; i
< elements
; i
++) {
5137 case 1: /* UZP1/2 */
5139 int midpoint
= elements
/ 2;
5141 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5143 read_vec_element(s
, tcg_res
, rm
,
5144 2 * (i
- midpoint
) + part
, size
);
5148 case 2: /* TRN1/2 */
5150 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5152 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5155 case 3: /* ZIP1/2 */
5157 int base
= part
* elements
/ 2;
5159 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5161 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5166 g_assert_not_reached();
5171 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5172 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5174 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5175 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5179 tcg_temp_free_i64(tcg_res
);
5181 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5182 tcg_temp_free_i64(tcg_resl
);
5183 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5184 tcg_temp_free_i64(tcg_resh
);
5187 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5188 int opc
, bool is_min
, TCGv_ptr fpst
)
5190 /* Helper function for disas_simd_across_lanes: do a single precision
5191 * min/max operation on the specified two inputs,
5192 * and return the result in tcg_elt1.
5196 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5198 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5203 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5205 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5210 /* C3.6.4 AdvSIMD across lanes
5211 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5212 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5213 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5214 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5216 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5218 int rd
= extract32(insn
, 0, 5);
5219 int rn
= extract32(insn
, 5, 5);
5220 int size
= extract32(insn
, 22, 2);
5221 int opcode
= extract32(insn
, 12, 5);
5222 bool is_q
= extract32(insn
, 30, 1);
5223 bool is_u
= extract32(insn
, 29, 1);
5225 bool is_min
= false;
5229 TCGv_i64 tcg_res
, tcg_elt
;
5232 case 0x1b: /* ADDV */
5234 unallocated_encoding(s
);
5238 case 0x3: /* SADDLV, UADDLV */
5239 case 0xa: /* SMAXV, UMAXV */
5240 case 0x1a: /* SMINV, UMINV */
5241 if (size
== 3 || (size
== 2 && !is_q
)) {
5242 unallocated_encoding(s
);
5246 case 0xc: /* FMAXNMV, FMINNMV */
5247 case 0xf: /* FMAXV, FMINV */
5248 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5249 unallocated_encoding(s
);
5252 /* Bit 1 of size field encodes min vs max, and actual size is always
5253 * 32 bits: adjust the size variable so following code can rely on it
5255 is_min
= extract32(size
, 1, 1);
5260 unallocated_encoding(s
);
5264 if (!fp_access_check(s
)) {
5269 elements
= (is_q
? 128 : 64) / esize
;
5271 tcg_res
= tcg_temp_new_i64();
5272 tcg_elt
= tcg_temp_new_i64();
5274 /* These instructions operate across all lanes of a vector
5275 * to produce a single result. We can guarantee that a 64
5276 * bit intermediate is sufficient:
5277 * + for [US]ADDLV the maximum element size is 32 bits, and
5278 * the result type is 64 bits
5279 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5280 * same as the element size, which is 32 bits at most
5281 * For the integer operations we can choose to work at 64
5282 * or 32 bits and truncate at the end; for simplicity
5283 * we use 64 bits always. The floating point
5284 * ops do require 32 bit intermediates, though.
5287 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5289 for (i
= 1; i
< elements
; i
++) {
5290 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5293 case 0x03: /* SADDLV / UADDLV */
5294 case 0x1b: /* ADDV */
5295 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5297 case 0x0a: /* SMAXV / UMAXV */
5298 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5300 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5302 case 0x1a: /* SMINV / UMINV */
5303 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5305 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5309 g_assert_not_reached();
5314 /* Floating point ops which work on 32 bit (single) intermediates.
5315 * Note that correct NaN propagation requires that we do these
5316 * operations in exactly the order specified by the pseudocode.
5318 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5319 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5320 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5321 TCGv_ptr fpst
= get_fpstatus_ptr();
5323 assert(esize
== 32);
5324 assert(elements
== 4);
5326 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5327 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5328 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5329 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5331 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5333 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5334 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5335 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5336 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5338 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5340 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5342 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5343 tcg_temp_free_i32(tcg_elt1
);
5344 tcg_temp_free_i32(tcg_elt2
);
5345 tcg_temp_free_i32(tcg_elt3
);
5346 tcg_temp_free_ptr(fpst
);
5349 tcg_temp_free_i64(tcg_elt
);
5351 /* Now truncate the result to the width required for the final output */
5352 if (opcode
== 0x03) {
5353 /* SADDLV, UADDLV: result is 2*esize */
5359 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5362 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5365 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5370 g_assert_not_reached();
5373 write_fp_dreg(s
, rd
, tcg_res
);
5374 tcg_temp_free_i64(tcg_res
);
5377 /* C6.3.31 DUP (Element, Vector)
5379 * 31 30 29 21 20 16 15 10 9 5 4 0
5380 * +---+---+-------------------+--------+-------------+------+------+
5381 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5382 * +---+---+-------------------+--------+-------------+------+------+
5384 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5386 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5389 int size
= ctz32(imm5
);
5390 int esize
= 8 << size
;
5391 int elements
= (is_q
? 128 : 64) / esize
;
5395 if (size
> 3 || (size
== 3 && !is_q
)) {
5396 unallocated_encoding(s
);
5400 if (!fp_access_check(s
)) {
5404 index
= imm5
>> (size
+ 1);
5406 tmp
= tcg_temp_new_i64();
5407 read_vec_element(s
, tmp
, rn
, index
, size
);
5409 for (i
= 0; i
< elements
; i
++) {
5410 write_vec_element(s
, tmp
, rd
, i
, size
);
5414 clear_vec_high(s
, rd
);
5417 tcg_temp_free_i64(tmp
);
5420 /* C6.3.31 DUP (element, scalar)
5421 * 31 21 20 16 15 10 9 5 4 0
5422 * +-----------------------+--------+-------------+------+------+
5423 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5424 * +-----------------------+--------+-------------+------+------+
5426 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5429 int size
= ctz32(imm5
);
5434 unallocated_encoding(s
);
5438 if (!fp_access_check(s
)) {
5442 index
= imm5
>> (size
+ 1);
5444 /* This instruction just extracts the specified element and
5445 * zero-extends it into the bottom of the destination register.
5447 tmp
= tcg_temp_new_i64();
5448 read_vec_element(s
, tmp
, rn
, index
, size
);
5449 write_fp_dreg(s
, rd
, tmp
);
5450 tcg_temp_free_i64(tmp
);
5453 /* C6.3.32 DUP (General)
5455 * 31 30 29 21 20 16 15 10 9 5 4 0
5456 * +---+---+-------------------+--------+-------------+------+------+
5457 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5458 * +---+---+-------------------+--------+-------------+------+------+
5460 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5462 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5465 int size
= ctz32(imm5
);
5466 int esize
= 8 << size
;
5467 int elements
= (is_q
? 128 : 64)/esize
;
5470 if (size
> 3 || ((size
== 3) && !is_q
)) {
5471 unallocated_encoding(s
);
5475 if (!fp_access_check(s
)) {
5479 for (i
= 0; i
< elements
; i
++) {
5480 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5483 clear_vec_high(s
, rd
);
5487 /* C6.3.150 INS (Element)
5489 * 31 21 20 16 15 14 11 10 9 5 4 0
5490 * +-----------------------+--------+------------+---+------+------+
5491 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5492 * +-----------------------+--------+------------+---+------+------+
5494 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5495 * index: encoded in imm5<4:size+1>
5497 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5500 int size
= ctz32(imm5
);
5501 int src_index
, dst_index
;
5505 unallocated_encoding(s
);
5509 if (!fp_access_check(s
)) {
5513 dst_index
= extract32(imm5
, 1+size
, 5);
5514 src_index
= extract32(imm4
, size
, 4);
5516 tmp
= tcg_temp_new_i64();
5518 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5519 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5521 tcg_temp_free_i64(tmp
);
5525 /* C6.3.151 INS (General)
5527 * 31 21 20 16 15 10 9 5 4 0
5528 * +-----------------------+--------+-------------+------+------+
5529 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5530 * +-----------------------+--------+-------------+------+------+
5532 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5533 * index: encoded in imm5<4:size+1>
5535 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5537 int size
= ctz32(imm5
);
5541 unallocated_encoding(s
);
5545 if (!fp_access_check(s
)) {
5549 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5550 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5554 * C6.3.321 UMOV (General)
5555 * C6.3.237 SMOV (General)
5557 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5558 * +---+---+-------------------+--------+-------------+------+------+
5559 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5560 * +---+---+-------------------+--------+-------------+------+------+
5562 * U: unsigned when set
5563 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5565 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5566 int rn
, int rd
, int imm5
)
5568 int size
= ctz32(imm5
);
5572 /* Check for UnallocatedEncodings */
5574 if (size
> 2 || (size
== 2 && !is_q
)) {
5575 unallocated_encoding(s
);
5580 || (size
< 3 && is_q
)
5581 || (size
== 3 && !is_q
)) {
5582 unallocated_encoding(s
);
5587 if (!fp_access_check(s
)) {
5591 element
= extract32(imm5
, 1+size
, 4);
5593 tcg_rd
= cpu_reg(s
, rd
);
5594 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5595 if (is_signed
&& !is_q
) {
5596 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5600 /* C3.6.5 AdvSIMD copy
5601 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5602 * +---+---+----+-----------------+------+---+------+---+------+------+
5603 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5604 * +---+---+----+-----------------+------+---+------+---+------+------+
5606 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5608 int rd
= extract32(insn
, 0, 5);
5609 int rn
= extract32(insn
, 5, 5);
5610 int imm4
= extract32(insn
, 11, 4);
5611 int op
= extract32(insn
, 29, 1);
5612 int is_q
= extract32(insn
, 30, 1);
5613 int imm5
= extract32(insn
, 16, 5);
5618 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5620 unallocated_encoding(s
);
5625 /* DUP (element - vector) */
5626 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5630 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5635 handle_simd_insg(s
, rd
, rn
, imm5
);
5637 unallocated_encoding(s
);
5642 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5643 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5646 unallocated_encoding(s
);
5652 /* C3.6.6 AdvSIMD modified immediate
5653 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5654 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5655 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5656 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5658 * There are a number of operations that can be carried out here:
5659 * MOVI - move (shifted) imm into register
5660 * MVNI - move inverted (shifted) imm into register
5661 * ORR - bitwise OR of (shifted) imm with register
5662 * BIC - bitwise clear of (shifted) imm with register
5664 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5666 int rd
= extract32(insn
, 0, 5);
5667 int cmode
= extract32(insn
, 12, 4);
5668 int cmode_3_1
= extract32(cmode
, 1, 3);
5669 int cmode_0
= extract32(cmode
, 0, 1);
5670 int o2
= extract32(insn
, 11, 1);
5671 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5672 bool is_neg
= extract32(insn
, 29, 1);
5673 bool is_q
= extract32(insn
, 30, 1);
5675 TCGv_i64 tcg_rd
, tcg_imm
;
5678 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5679 unallocated_encoding(s
);
5683 if (!fp_access_check(s
)) {
5687 /* See AdvSIMDExpandImm() in ARM ARM */
5688 switch (cmode_3_1
) {
5689 case 0: /* Replicate(Zeros(24):imm8, 2) */
5690 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5691 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5692 case 3: /* Replicate(imm8:Zeros(24), 2) */
5694 int shift
= cmode_3_1
* 8;
5695 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5698 case 4: /* Replicate(Zeros(8):imm8, 4) */
5699 case 5: /* Replicate(imm8:Zeros(8), 4) */
5701 int shift
= (cmode_3_1
& 0x1) * 8;
5702 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5707 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5708 imm
= (abcdefgh
<< 16) | 0xffff;
5710 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5711 imm
= (abcdefgh
<< 8) | 0xff;
5713 imm
= bitfield_replicate(imm
, 32);
5716 if (!cmode_0
&& !is_neg
) {
5717 imm
= bitfield_replicate(abcdefgh
, 8);
5718 } else if (!cmode_0
&& is_neg
) {
5721 for (i
= 0; i
< 8; i
++) {
5722 if ((abcdefgh
) & (1 << i
)) {
5723 imm
|= 0xffULL
<< (i
* 8);
5726 } else if (cmode_0
) {
5728 imm
= (abcdefgh
& 0x3f) << 48;
5729 if (abcdefgh
& 0x80) {
5730 imm
|= 0x8000000000000000ULL
;
5732 if (abcdefgh
& 0x40) {
5733 imm
|= 0x3fc0000000000000ULL
;
5735 imm
|= 0x4000000000000000ULL
;
5738 imm
= (abcdefgh
& 0x3f) << 19;
5739 if (abcdefgh
& 0x80) {
5742 if (abcdefgh
& 0x40) {
5753 if (cmode_3_1
!= 7 && is_neg
) {
5757 tcg_imm
= tcg_const_i64(imm
);
5758 tcg_rd
= new_tmp_a64(s
);
5760 for (i
= 0; i
< 2; i
++) {
5761 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
5763 if (i
== 1 && !is_q
) {
5764 /* non-quad ops clear high half of vector */
5765 tcg_gen_movi_i64(tcg_rd
, 0);
5766 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5767 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5770 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5773 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5777 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5779 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5782 tcg_temp_free_i64(tcg_imm
);
5785 /* C3.6.7 AdvSIMD scalar copy
5786 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5787 * +-----+----+-----------------+------+---+------+---+------+------+
5788 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5789 * +-----+----+-----------------+------+---+------+---+------+------+
5791 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5793 int rd
= extract32(insn
, 0, 5);
5794 int rn
= extract32(insn
, 5, 5);
5795 int imm4
= extract32(insn
, 11, 4);
5796 int imm5
= extract32(insn
, 16, 5);
5797 int op
= extract32(insn
, 29, 1);
5799 if (op
!= 0 || imm4
!= 0) {
5800 unallocated_encoding(s
);
5804 /* DUP (element, scalar) */
5805 handle_simd_dupes(s
, rd
, rn
, imm5
);
5808 /* C3.6.8 AdvSIMD scalar pairwise
5809 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5810 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5811 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5812 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5814 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5816 int u
= extract32(insn
, 29, 1);
5817 int size
= extract32(insn
, 22, 2);
5818 int opcode
= extract32(insn
, 12, 5);
5819 int rn
= extract32(insn
, 5, 5);
5820 int rd
= extract32(insn
, 0, 5);
5823 /* For some ops (the FP ones), size[1] is part of the encoding.
5824 * For ADDP strictly it is not but size[1] is always 1 for valid
5827 opcode
|= (extract32(size
, 1, 1) << 5);
5830 case 0x3b: /* ADDP */
5831 if (u
|| size
!= 3) {
5832 unallocated_encoding(s
);
5835 if (!fp_access_check(s
)) {
5839 TCGV_UNUSED_PTR(fpst
);
5841 case 0xc: /* FMAXNMP */
5842 case 0xd: /* FADDP */
5843 case 0xf: /* FMAXP */
5844 case 0x2c: /* FMINNMP */
5845 case 0x2f: /* FMINP */
5846 /* FP op, size[0] is 32 or 64 bit */
5848 unallocated_encoding(s
);
5851 if (!fp_access_check(s
)) {
5855 size
= extract32(size
, 0, 1) ? 3 : 2;
5856 fpst
= get_fpstatus_ptr();
5859 unallocated_encoding(s
);
5864 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5865 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5866 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5868 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
5869 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
5872 case 0x3b: /* ADDP */
5873 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
5875 case 0xc: /* FMAXNMP */
5876 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5878 case 0xd: /* FADDP */
5879 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5881 case 0xf: /* FMAXP */
5882 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5884 case 0x2c: /* FMINNMP */
5885 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5887 case 0x2f: /* FMINP */
5888 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5891 g_assert_not_reached();
5894 write_fp_dreg(s
, rd
, tcg_res
);
5896 tcg_temp_free_i64(tcg_op1
);
5897 tcg_temp_free_i64(tcg_op2
);
5898 tcg_temp_free_i64(tcg_res
);
5900 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
5901 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
5902 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5904 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
5905 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
5908 case 0xc: /* FMAXNMP */
5909 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5911 case 0xd: /* FADDP */
5912 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5914 case 0xf: /* FMAXP */
5915 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5917 case 0x2c: /* FMINNMP */
5918 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5920 case 0x2f: /* FMINP */
5921 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5924 g_assert_not_reached();
5927 write_fp_sreg(s
, rd
, tcg_res
);
5929 tcg_temp_free_i32(tcg_op1
);
5930 tcg_temp_free_i32(tcg_op2
);
5931 tcg_temp_free_i32(tcg_res
);
5934 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
5935 tcg_temp_free_ptr(fpst
);
5940 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
5942 * This code is handles the common shifting code and is used by both
5943 * the vector and scalar code.
5945 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5946 TCGv_i64 tcg_rnd
, bool accumulate
,
5947 bool is_u
, int size
, int shift
)
5949 bool extended_result
= false;
5950 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
5952 TCGv_i64 tcg_src_hi
;
5954 if (round
&& size
== 3) {
5955 extended_result
= true;
5956 ext_lshift
= 64 - shift
;
5957 tcg_src_hi
= tcg_temp_new_i64();
5958 } else if (shift
== 64) {
5959 if (!accumulate
&& is_u
) {
5960 /* result is zero */
5961 tcg_gen_movi_i64(tcg_res
, 0);
5966 /* Deal with the rounding step */
5968 if (extended_result
) {
5969 TCGv_i64 tcg_zero
= tcg_const_i64(0);
5971 /* take care of sign extending tcg_res */
5972 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
5973 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5974 tcg_src
, tcg_src_hi
,
5977 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5981 tcg_temp_free_i64(tcg_zero
);
5983 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
5987 /* Now do the shift right */
5988 if (round
&& extended_result
) {
5989 /* extended case, >64 bit precision required */
5990 if (ext_lshift
== 0) {
5991 /* special case, only high bits matter */
5992 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
5994 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5995 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
5996 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6001 /* essentially shifting in 64 zeros */
6002 tcg_gen_movi_i64(tcg_src
, 0);
6004 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6008 /* effectively extending the sign-bit */
6009 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6011 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6017 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6019 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6022 if (extended_result
) {
6023 tcg_temp_free_i64(tcg_src_hi
);
6027 /* Common SHL/SLI - Shift left with an optional insert */
6028 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6029 bool insert
, int shift
)
6031 if (insert
) { /* SLI */
6032 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6034 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6038 /* SRI: shift right with insert */
6039 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6040 int size
, int shift
)
6042 int esize
= 8 << size
;
6044 /* shift count same as element size is valid but does nothing;
6045 * special case to avoid potential shift by 64.
6047 if (shift
!= esize
) {
6048 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6049 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6053 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6054 static void handle_scalar_simd_shri(DisasContext
*s
,
6055 bool is_u
, int immh
, int immb
,
6056 int opcode
, int rn
, int rd
)
6059 int immhb
= immh
<< 3 | immb
;
6060 int shift
= 2 * (8 << size
) - immhb
;
6061 bool accumulate
= false;
6063 bool insert
= false;
6068 if (!extract32(immh
, 3, 1)) {
6069 unallocated_encoding(s
);
6073 if (!fp_access_check(s
)) {
6078 case 0x02: /* SSRA / USRA (accumulate) */
6081 case 0x04: /* SRSHR / URSHR (rounding) */
6084 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6085 accumulate
= round
= true;
6087 case 0x08: /* SRI */
6093 uint64_t round_const
= 1ULL << (shift
- 1);
6094 tcg_round
= tcg_const_i64(round_const
);
6096 TCGV_UNUSED_I64(tcg_round
);
6099 tcg_rn
= read_fp_dreg(s
, rn
);
6100 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6103 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6105 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6106 accumulate
, is_u
, size
, shift
);
6109 write_fp_dreg(s
, rd
, tcg_rd
);
6111 tcg_temp_free_i64(tcg_rn
);
6112 tcg_temp_free_i64(tcg_rd
);
6114 tcg_temp_free_i64(tcg_round
);
6118 /* SHL/SLI - Scalar shift left */
6119 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6120 int immh
, int immb
, int opcode
,
6123 int size
= 32 - clz32(immh
) - 1;
6124 int immhb
= immh
<< 3 | immb
;
6125 int shift
= immhb
- (8 << size
);
6126 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6127 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6129 if (!extract32(immh
, 3, 1)) {
6130 unallocated_encoding(s
);
6134 if (!fp_access_check(s
)) {
6138 tcg_rn
= read_fp_dreg(s
, rn
);
6139 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6141 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6143 write_fp_dreg(s
, rd
, tcg_rd
);
6145 tcg_temp_free_i64(tcg_rn
);
6146 tcg_temp_free_i64(tcg_rd
);
6149 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6150 * (signed/unsigned) narrowing */
6151 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6152 bool is_u_shift
, bool is_u_narrow
,
6153 int immh
, int immb
, int opcode
,
6156 int immhb
= immh
<< 3 | immb
;
6157 int size
= 32 - clz32(immh
) - 1;
6158 int esize
= 8 << size
;
6159 int shift
= (2 * esize
) - immhb
;
6160 int elements
= is_scalar
? 1 : (64 / esize
);
6161 bool round
= extract32(opcode
, 0, 1);
6162 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6163 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6164 TCGv_i32 tcg_rd_narrowed
;
6167 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6168 { gen_helper_neon_narrow_sat_s8
,
6169 gen_helper_neon_unarrow_sat8
},
6170 { gen_helper_neon_narrow_sat_s16
,
6171 gen_helper_neon_unarrow_sat16
},
6172 { gen_helper_neon_narrow_sat_s32
,
6173 gen_helper_neon_unarrow_sat32
},
6176 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6177 gen_helper_neon_narrow_sat_u8
,
6178 gen_helper_neon_narrow_sat_u16
,
6179 gen_helper_neon_narrow_sat_u32
,
6182 NeonGenNarrowEnvFn
*narrowfn
;
6188 if (extract32(immh
, 3, 1)) {
6189 unallocated_encoding(s
);
6193 if (!fp_access_check(s
)) {
6198 narrowfn
= unsigned_narrow_fns
[size
];
6200 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6203 tcg_rn
= tcg_temp_new_i64();
6204 tcg_rd
= tcg_temp_new_i64();
6205 tcg_rd_narrowed
= tcg_temp_new_i32();
6206 tcg_final
= tcg_const_i64(0);
6209 uint64_t round_const
= 1ULL << (shift
- 1);
6210 tcg_round
= tcg_const_i64(round_const
);
6212 TCGV_UNUSED_I64(tcg_round
);
6215 for (i
= 0; i
< elements
; i
++) {
6216 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6217 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6218 false, is_u_shift
, size
+1, shift
);
6219 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6220 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6221 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6225 clear_vec_high(s
, rd
);
6226 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6228 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6232 tcg_temp_free_i64(tcg_round
);
6234 tcg_temp_free_i64(tcg_rn
);
6235 tcg_temp_free_i64(tcg_rd
);
6236 tcg_temp_free_i32(tcg_rd_narrowed
);
6237 tcg_temp_free_i64(tcg_final
);
6241 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6242 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6243 bool src_unsigned
, bool dst_unsigned
,
6244 int immh
, int immb
, int rn
, int rd
)
6246 int immhb
= immh
<< 3 | immb
;
6247 int size
= 32 - clz32(immh
) - 1;
6248 int shift
= immhb
- (8 << size
);
6252 assert(!(scalar
&& is_q
));
6255 if (!is_q
&& extract32(immh
, 3, 1)) {
6256 unallocated_encoding(s
);
6260 /* Since we use the variable-shift helpers we must
6261 * replicate the shift count into each element of
6262 * the tcg_shift value.
6266 shift
|= shift
<< 8;
6269 shift
|= shift
<< 16;
6275 g_assert_not_reached();
6279 if (!fp_access_check(s
)) {
6284 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6285 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6286 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6287 { NULL
, gen_helper_neon_qshl_u64
},
6289 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6290 int maxpass
= is_q
? 2 : 1;
6292 for (pass
= 0; pass
< maxpass
; pass
++) {
6293 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6295 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6296 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6297 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6299 tcg_temp_free_i64(tcg_op
);
6301 tcg_temp_free_i64(tcg_shift
);
6304 clear_vec_high(s
, rd
);
6307 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6308 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6310 { gen_helper_neon_qshl_s8
,
6311 gen_helper_neon_qshl_s16
,
6312 gen_helper_neon_qshl_s32
},
6313 { gen_helper_neon_qshlu_s8
,
6314 gen_helper_neon_qshlu_s16
,
6315 gen_helper_neon_qshlu_s32
}
6317 { NULL
, NULL
, NULL
},
6318 { gen_helper_neon_qshl_u8
,
6319 gen_helper_neon_qshl_u16
,
6320 gen_helper_neon_qshl_u32
}
6323 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6324 TCGMemOp memop
= scalar
? size
: MO_32
;
6325 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6327 for (pass
= 0; pass
< maxpass
; pass
++) {
6328 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6330 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6331 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6335 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6338 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6343 g_assert_not_reached();
6345 write_fp_sreg(s
, rd
, tcg_op
);
6347 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6350 tcg_temp_free_i32(tcg_op
);
6352 tcg_temp_free_i32(tcg_shift
);
6354 if (!is_q
&& !scalar
) {
6355 clear_vec_high(s
, rd
);
6360 /* Common vector code for handling integer to FP conversion */
6361 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6362 int elements
, int is_signed
,
6363 int fracbits
, int size
)
6365 bool is_double
= size
== 3 ? true : false;
6366 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6367 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6368 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6369 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6372 for (pass
= 0; pass
< elements
; pass
++) {
6373 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6376 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6378 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6379 tcg_shift
, tcg_fpst
);
6381 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6382 tcg_shift
, tcg_fpst
);
6384 if (elements
== 1) {
6385 write_fp_dreg(s
, rd
, tcg_double
);
6387 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6389 tcg_temp_free_i64(tcg_double
);
6391 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6393 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6394 tcg_shift
, tcg_fpst
);
6396 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6397 tcg_shift
, tcg_fpst
);
6399 if (elements
== 1) {
6400 write_fp_sreg(s
, rd
, tcg_single
);
6402 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6404 tcg_temp_free_i32(tcg_single
);
6408 if (!is_double
&& elements
== 2) {
6409 clear_vec_high(s
, rd
);
6412 tcg_temp_free_i64(tcg_int
);
6413 tcg_temp_free_ptr(tcg_fpst
);
6414 tcg_temp_free_i32(tcg_shift
);
6417 /* UCVTF/SCVTF - Integer to FP conversion */
6418 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6419 bool is_q
, bool is_u
,
6420 int immh
, int immb
, int opcode
,
6423 bool is_double
= extract32(immh
, 3, 1);
6424 int size
= is_double
? MO_64
: MO_32
;
6426 int immhb
= immh
<< 3 | immb
;
6427 int fracbits
= (is_double
? 128 : 64) - immhb
;
6429 if (!extract32(immh
, 2, 2)) {
6430 unallocated_encoding(s
);
6437 elements
= is_double
? 2 : is_q
? 4 : 2;
6438 if (is_double
&& !is_q
) {
6439 unallocated_encoding(s
);
6444 if (!fp_access_check(s
)) {
6448 /* immh == 0 would be a failure of the decode logic */
6451 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6454 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6455 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6456 bool is_q
, bool is_u
,
6457 int immh
, int immb
, int rn
, int rd
)
6459 bool is_double
= extract32(immh
, 3, 1);
6460 int immhb
= immh
<< 3 | immb
;
6461 int fracbits
= (is_double
? 128 : 64) - immhb
;
6463 TCGv_ptr tcg_fpstatus
;
6464 TCGv_i32 tcg_rmode
, tcg_shift
;
6466 if (!extract32(immh
, 2, 2)) {
6467 unallocated_encoding(s
);
6471 if (!is_scalar
&& !is_q
&& is_double
) {
6472 unallocated_encoding(s
);
6476 if (!fp_access_check(s
)) {
6480 assert(!(is_scalar
&& is_q
));
6482 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6483 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6484 tcg_fpstatus
= get_fpstatus_ptr();
6485 tcg_shift
= tcg_const_i32(fracbits
);
6488 int maxpass
= is_scalar
? 1 : is_q
? 2 : 1;
6490 for (pass
= 0; pass
< maxpass
; pass
++) {
6491 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6493 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6495 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6497 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6499 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6500 tcg_temp_free_i64(tcg_op
);
6503 clear_vec_high(s
, rd
);
6506 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6507 for (pass
= 0; pass
< maxpass
; pass
++) {
6508 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6510 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6512 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6514 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6517 write_fp_sreg(s
, rd
, tcg_op
);
6519 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6521 tcg_temp_free_i32(tcg_op
);
6523 if (!is_q
&& !is_scalar
) {
6524 clear_vec_high(s
, rd
);
6528 tcg_temp_free_ptr(tcg_fpstatus
);
6529 tcg_temp_free_i32(tcg_shift
);
6530 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6531 tcg_temp_free_i32(tcg_rmode
);
6534 /* C3.6.9 AdvSIMD scalar shift by immediate
6535 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6536 * +-----+---+-------------+------+------+--------+---+------+------+
6537 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6538 * +-----+---+-------------+------+------+--------+---+------+------+
6540 * This is the scalar version so it works on a fixed sized registers
6542 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6544 int rd
= extract32(insn
, 0, 5);
6545 int rn
= extract32(insn
, 5, 5);
6546 int opcode
= extract32(insn
, 11, 5);
6547 int immb
= extract32(insn
, 16, 3);
6548 int immh
= extract32(insn
, 19, 4);
6549 bool is_u
= extract32(insn
, 29, 1);
6552 unallocated_encoding(s
);
6557 case 0x08: /* SRI */
6559 unallocated_encoding(s
);
6563 case 0x00: /* SSHR / USHR */
6564 case 0x02: /* SSRA / USRA */
6565 case 0x04: /* SRSHR / URSHR */
6566 case 0x06: /* SRSRA / URSRA */
6567 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6569 case 0x0a: /* SHL / SLI */
6570 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6572 case 0x1c: /* SCVTF, UCVTF */
6573 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6576 case 0x10: /* SQSHRUN, SQSHRUN2 */
6577 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6579 unallocated_encoding(s
);
6582 handle_vec_simd_sqshrn(s
, true, false, false, true,
6583 immh
, immb
, opcode
, rn
, rd
);
6585 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6586 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6587 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6588 immh
, immb
, opcode
, rn
, rd
);
6590 case 0xc: /* SQSHLU */
6592 unallocated_encoding(s
);
6595 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6597 case 0xe: /* SQSHL, UQSHL */
6598 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6600 case 0x1f: /* FCVTZS, FCVTZU */
6601 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6604 unallocated_encoding(s
);
6609 /* C3.6.10 AdvSIMD scalar three different
6610 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6611 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6612 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6613 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6615 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6617 bool is_u
= extract32(insn
, 29, 1);
6618 int size
= extract32(insn
, 22, 2);
6619 int opcode
= extract32(insn
, 12, 4);
6620 int rm
= extract32(insn
, 16, 5);
6621 int rn
= extract32(insn
, 5, 5);
6622 int rd
= extract32(insn
, 0, 5);
6625 unallocated_encoding(s
);
6630 case 0x9: /* SQDMLAL, SQDMLAL2 */
6631 case 0xb: /* SQDMLSL, SQDMLSL2 */
6632 case 0xd: /* SQDMULL, SQDMULL2 */
6633 if (size
== 0 || size
== 3) {
6634 unallocated_encoding(s
);
6639 unallocated_encoding(s
);
6643 if (!fp_access_check(s
)) {
6648 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6649 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6650 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6652 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6653 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6655 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6656 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6659 case 0xd: /* SQDMULL, SQDMULL2 */
6661 case 0xb: /* SQDMLSL, SQDMLSL2 */
6662 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6664 case 0x9: /* SQDMLAL, SQDMLAL2 */
6665 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6666 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6670 g_assert_not_reached();
6673 write_fp_dreg(s
, rd
, tcg_res
);
6675 tcg_temp_free_i64(tcg_op1
);
6676 tcg_temp_free_i64(tcg_op2
);
6677 tcg_temp_free_i64(tcg_res
);
6679 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6680 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6681 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6683 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6684 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6686 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6687 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6690 case 0xd: /* SQDMULL, SQDMULL2 */
6692 case 0xb: /* SQDMLSL, SQDMLSL2 */
6693 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6695 case 0x9: /* SQDMLAL, SQDMLAL2 */
6697 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6698 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6699 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6701 tcg_temp_free_i64(tcg_op3
);
6705 g_assert_not_reached();
6708 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6709 write_fp_dreg(s
, rd
, tcg_res
);
6711 tcg_temp_free_i32(tcg_op1
);
6712 tcg_temp_free_i32(tcg_op2
);
6713 tcg_temp_free_i64(tcg_res
);
6717 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6718 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6720 /* Handle 64x64->64 opcodes which are shared between the scalar
6721 * and vector 3-same groups. We cover every opcode where size == 3
6722 * is valid in either the three-reg-same (integer, not pairwise)
6723 * or scalar-three-reg-same groups. (Some opcodes are not yet
6729 case 0x1: /* SQADD */
6731 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6733 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6736 case 0x5: /* SQSUB */
6738 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6740 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6743 case 0x6: /* CMGT, CMHI */
6744 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6745 * We implement this using setcond (test) and then negating.
6747 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6749 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6750 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6752 case 0x7: /* CMGE, CMHS */
6753 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6755 case 0x11: /* CMTST, CMEQ */
6760 /* CMTST : test is "if (X & Y != 0)". */
6761 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6762 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6763 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6765 case 0x8: /* SSHL, USHL */
6767 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6769 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6772 case 0x9: /* SQSHL, UQSHL */
6774 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6776 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6779 case 0xa: /* SRSHL, URSHL */
6781 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6783 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6786 case 0xb: /* SQRSHL, UQRSHL */
6788 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6790 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6793 case 0x10: /* ADD, SUB */
6795 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6797 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6801 g_assert_not_reached();
6805 /* Handle the 3-same-operands float operations; shared by the scalar
6806 * and vector encodings. The caller must filter out any encodings
6807 * not allocated for the encoding it is dealing with.
6809 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6810 int fpopcode
, int rd
, int rn
, int rm
)
6813 TCGv_ptr fpst
= get_fpstatus_ptr();
6815 for (pass
= 0; pass
< elements
; pass
++) {
6818 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6819 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6820 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6822 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6823 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6826 case 0x39: /* FMLS */
6827 /* As usual for ARM, separate negation for fused multiply-add */
6828 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6830 case 0x19: /* FMLA */
6831 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6832 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6835 case 0x18: /* FMAXNM */
6836 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6838 case 0x1a: /* FADD */
6839 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6841 case 0x1b: /* FMULX */
6842 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6844 case 0x1c: /* FCMEQ */
6845 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6847 case 0x1e: /* FMAX */
6848 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6850 case 0x1f: /* FRECPS */
6851 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6853 case 0x38: /* FMINNM */
6854 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6856 case 0x3a: /* FSUB */
6857 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6859 case 0x3e: /* FMIN */
6860 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6862 case 0x3f: /* FRSQRTS */
6863 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6865 case 0x5b: /* FMUL */
6866 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6868 case 0x5c: /* FCMGE */
6869 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6871 case 0x5d: /* FACGE */
6872 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6874 case 0x5f: /* FDIV */
6875 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6877 case 0x7a: /* FABD */
6878 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6879 gen_helper_vfp_absd(tcg_res
, tcg_res
);
6881 case 0x7c: /* FCMGT */
6882 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6884 case 0x7d: /* FACGT */
6885 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6888 g_assert_not_reached();
6891 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6893 tcg_temp_free_i64(tcg_res
);
6894 tcg_temp_free_i64(tcg_op1
);
6895 tcg_temp_free_i64(tcg_op2
);
6898 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6899 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6900 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6902 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
6903 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
6906 case 0x39: /* FMLS */
6907 /* As usual for ARM, separate negation for fused multiply-add */
6908 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6910 case 0x19: /* FMLA */
6911 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6912 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
6915 case 0x1a: /* FADD */
6916 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6918 case 0x1b: /* FMULX */
6919 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6921 case 0x1c: /* FCMEQ */
6922 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6924 case 0x1e: /* FMAX */
6925 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6927 case 0x1f: /* FRECPS */
6928 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6930 case 0x18: /* FMAXNM */
6931 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6933 case 0x38: /* FMINNM */
6934 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6936 case 0x3a: /* FSUB */
6937 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6939 case 0x3e: /* FMIN */
6940 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6942 case 0x3f: /* FRSQRTS */
6943 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6945 case 0x5b: /* FMUL */
6946 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6948 case 0x5c: /* FCMGE */
6949 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6951 case 0x5d: /* FACGE */
6952 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6954 case 0x5f: /* FDIV */
6955 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6957 case 0x7a: /* FABD */
6958 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6959 gen_helper_vfp_abss(tcg_res
, tcg_res
);
6961 case 0x7c: /* FCMGT */
6962 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6964 case 0x7d: /* FACGT */
6965 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6968 g_assert_not_reached();
6971 if (elements
== 1) {
6972 /* scalar single so clear high part */
6973 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6975 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
6976 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
6977 tcg_temp_free_i64(tcg_tmp
);
6979 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6982 tcg_temp_free_i32(tcg_res
);
6983 tcg_temp_free_i32(tcg_op1
);
6984 tcg_temp_free_i32(tcg_op2
);
6988 tcg_temp_free_ptr(fpst
);
6990 if ((elements
<< size
) < 4) {
6991 /* scalar, or non-quad vector op */
6992 clear_vec_high(s
, rd
);
6996 /* C3.6.11 AdvSIMD scalar three same
6997 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
6998 * +-----+---+-----------+------+---+------+--------+---+------+------+
6999 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7000 * +-----+---+-----------+------+---+------+--------+---+------+------+
7002 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7004 int rd
= extract32(insn
, 0, 5);
7005 int rn
= extract32(insn
, 5, 5);
7006 int opcode
= extract32(insn
, 11, 5);
7007 int rm
= extract32(insn
, 16, 5);
7008 int size
= extract32(insn
, 22, 2);
7009 bool u
= extract32(insn
, 29, 1);
7012 if (opcode
>= 0x18) {
7013 /* Floating point: U, size[1] and opcode indicate operation */
7014 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7016 case 0x1b: /* FMULX */
7017 case 0x1f: /* FRECPS */
7018 case 0x3f: /* FRSQRTS */
7019 case 0x5d: /* FACGE */
7020 case 0x7d: /* FACGT */
7021 case 0x1c: /* FCMEQ */
7022 case 0x5c: /* FCMGE */
7023 case 0x7c: /* FCMGT */
7024 case 0x7a: /* FABD */
7027 unallocated_encoding(s
);
7031 if (!fp_access_check(s
)) {
7035 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7040 case 0x1: /* SQADD, UQADD */
7041 case 0x5: /* SQSUB, UQSUB */
7042 case 0x9: /* SQSHL, UQSHL */
7043 case 0xb: /* SQRSHL, UQRSHL */
7045 case 0x8: /* SSHL, USHL */
7046 case 0xa: /* SRSHL, URSHL */
7047 case 0x6: /* CMGT, CMHI */
7048 case 0x7: /* CMGE, CMHS */
7049 case 0x11: /* CMTST, CMEQ */
7050 case 0x10: /* ADD, SUB (vector) */
7052 unallocated_encoding(s
);
7056 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7057 if (size
!= 1 && size
!= 2) {
7058 unallocated_encoding(s
);
7063 unallocated_encoding(s
);
7067 if (!fp_access_check(s
)) {
7071 tcg_rd
= tcg_temp_new_i64();
7074 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7075 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7077 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7078 tcg_temp_free_i64(tcg_rn
);
7079 tcg_temp_free_i64(tcg_rm
);
7081 /* Do a single operation on the lowest element in the vector.
7082 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7083 * no side effects for all these operations.
7084 * OPTME: special-purpose helpers would avoid doing some
7085 * unnecessary work in the helper for the 8 and 16 bit cases.
7087 NeonGenTwoOpEnvFn
*genenvfn
;
7088 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7089 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7090 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7092 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7093 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7096 case 0x1: /* SQADD, UQADD */
7098 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7099 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7100 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7101 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7103 genenvfn
= fns
[size
][u
];
7106 case 0x5: /* SQSUB, UQSUB */
7108 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7109 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7110 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7111 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7113 genenvfn
= fns
[size
][u
];
7116 case 0x9: /* SQSHL, UQSHL */
7118 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7119 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7120 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7121 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7123 genenvfn
= fns
[size
][u
];
7126 case 0xb: /* SQRSHL, UQRSHL */
7128 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7129 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7130 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7131 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7133 genenvfn
= fns
[size
][u
];
7136 case 0x16: /* SQDMULH, SQRDMULH */
7138 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7139 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7140 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7142 assert(size
== 1 || size
== 2);
7143 genenvfn
= fns
[size
- 1][u
];
7147 g_assert_not_reached();
7150 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7151 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7152 tcg_temp_free_i32(tcg_rd32
);
7153 tcg_temp_free_i32(tcg_rn
);
7154 tcg_temp_free_i32(tcg_rm
);
7157 write_fp_dreg(s
, rd
, tcg_rd
);
7159 tcg_temp_free_i64(tcg_rd
);
7162 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7163 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7164 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7166 /* Handle 64->64 opcodes which are shared between the scalar and
7167 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7168 * is valid in either group and also the double-precision fp ops.
7169 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7175 case 0x4: /* CLS, CLZ */
7177 gen_helper_clz64(tcg_rd
, tcg_rn
);
7179 gen_helper_cls64(tcg_rd
, tcg_rn
);
7183 /* This opcode is shared with CNT and RBIT but we have earlier
7184 * enforced that size == 3 if and only if this is the NOT insn.
7186 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7188 case 0x7: /* SQABS, SQNEG */
7190 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7192 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7195 case 0xa: /* CMLT */
7196 /* 64 bit integer comparison against zero, result is
7197 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7202 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7203 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7205 case 0x8: /* CMGT, CMGE */
7206 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7208 case 0x9: /* CMEQ, CMLE */
7209 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7211 case 0xb: /* ABS, NEG */
7213 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7215 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7216 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7217 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7219 tcg_temp_free_i64(tcg_zero
);
7222 case 0x2f: /* FABS */
7223 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7225 case 0x6f: /* FNEG */
7226 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7228 case 0x7f: /* FSQRT */
7229 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7231 case 0x1a: /* FCVTNS */
7232 case 0x1b: /* FCVTMS */
7233 case 0x1c: /* FCVTAS */
7234 case 0x3a: /* FCVTPS */
7235 case 0x3b: /* FCVTZS */
7237 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7238 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7239 tcg_temp_free_i32(tcg_shift
);
7242 case 0x5a: /* FCVTNU */
7243 case 0x5b: /* FCVTMU */
7244 case 0x5c: /* FCVTAU */
7245 case 0x7a: /* FCVTPU */
7246 case 0x7b: /* FCVTZU */
7248 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7249 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7250 tcg_temp_free_i32(tcg_shift
);
7253 case 0x18: /* FRINTN */
7254 case 0x19: /* FRINTM */
7255 case 0x38: /* FRINTP */
7256 case 0x39: /* FRINTZ */
7257 case 0x58: /* FRINTA */
7258 case 0x79: /* FRINTI */
7259 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7261 case 0x59: /* FRINTX */
7262 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7265 g_assert_not_reached();
7269 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7270 bool is_scalar
, bool is_u
, bool is_q
,
7271 int size
, int rn
, int rd
)
7273 bool is_double
= (size
== 3);
7276 if (!fp_access_check(s
)) {
7280 fpst
= get_fpstatus_ptr();
7283 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7284 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7285 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7286 NeonGenTwoDoubleOPFn
*genfn
;
7291 case 0x2e: /* FCMLT (zero) */
7294 case 0x2c: /* FCMGT (zero) */
7295 genfn
= gen_helper_neon_cgt_f64
;
7297 case 0x2d: /* FCMEQ (zero) */
7298 genfn
= gen_helper_neon_ceq_f64
;
7300 case 0x6d: /* FCMLE (zero) */
7303 case 0x6c: /* FCMGE (zero) */
7304 genfn
= gen_helper_neon_cge_f64
;
7307 g_assert_not_reached();
7310 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7311 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7313 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7315 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7317 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7320 clear_vec_high(s
, rd
);
7323 tcg_temp_free_i64(tcg_res
);
7324 tcg_temp_free_i64(tcg_zero
);
7325 tcg_temp_free_i64(tcg_op
);
7327 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7328 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7329 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7330 NeonGenTwoSingleOPFn
*genfn
;
7332 int pass
, maxpasses
;
7335 case 0x2e: /* FCMLT (zero) */
7338 case 0x2c: /* FCMGT (zero) */
7339 genfn
= gen_helper_neon_cgt_f32
;
7341 case 0x2d: /* FCMEQ (zero) */
7342 genfn
= gen_helper_neon_ceq_f32
;
7344 case 0x6d: /* FCMLE (zero) */
7347 case 0x6c: /* FCMGE (zero) */
7348 genfn
= gen_helper_neon_cge_f32
;
7351 g_assert_not_reached();
7357 maxpasses
= is_q
? 4 : 2;
7360 for (pass
= 0; pass
< maxpasses
; pass
++) {
7361 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7363 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7365 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7368 write_fp_sreg(s
, rd
, tcg_res
);
7370 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7373 tcg_temp_free_i32(tcg_res
);
7374 tcg_temp_free_i32(tcg_zero
);
7375 tcg_temp_free_i32(tcg_op
);
7376 if (!is_q
&& !is_scalar
) {
7377 clear_vec_high(s
, rd
);
7381 tcg_temp_free_ptr(fpst
);
7384 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7385 bool is_scalar
, bool is_u
, bool is_q
,
7386 int size
, int rn
, int rd
)
7388 bool is_double
= (size
== 3);
7389 TCGv_ptr fpst
= get_fpstatus_ptr();
7392 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7393 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7396 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7397 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7399 case 0x3d: /* FRECPE */
7400 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7402 case 0x3f: /* FRECPX */
7403 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7405 case 0x7d: /* FRSQRTE */
7406 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7409 g_assert_not_reached();
7411 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7414 clear_vec_high(s
, rd
);
7417 tcg_temp_free_i64(tcg_res
);
7418 tcg_temp_free_i64(tcg_op
);
7420 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7421 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7422 int pass
, maxpasses
;
7427 maxpasses
= is_q
? 4 : 2;
7430 for (pass
= 0; pass
< maxpasses
; pass
++) {
7431 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7434 case 0x3c: /* URECPE */
7435 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7437 case 0x3d: /* FRECPE */
7438 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7440 case 0x3f: /* FRECPX */
7441 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7443 case 0x7d: /* FRSQRTE */
7444 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7447 g_assert_not_reached();
7451 write_fp_sreg(s
, rd
, tcg_res
);
7453 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7456 tcg_temp_free_i32(tcg_res
);
7457 tcg_temp_free_i32(tcg_op
);
7458 if (!is_q
&& !is_scalar
) {
7459 clear_vec_high(s
, rd
);
7462 tcg_temp_free_ptr(fpst
);
7465 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7466 int opcode
, bool u
, bool is_q
,
7467 int size
, int rn
, int rd
)
7469 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7470 * in the source becomes a size element in the destination).
7473 TCGv_i32 tcg_res
[2];
7474 int destelt
= is_q
? 2 : 0;
7475 int passes
= scalar
? 1 : 2;
7478 tcg_res
[1] = tcg_const_i32(0);
7481 for (pass
= 0; pass
< passes
; pass
++) {
7482 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7483 NeonGenNarrowFn
*genfn
= NULL
;
7484 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7487 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7489 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7491 tcg_res
[pass
] = tcg_temp_new_i32();
7494 case 0x12: /* XTN, SQXTUN */
7496 static NeonGenNarrowFn
* const xtnfns
[3] = {
7497 gen_helper_neon_narrow_u8
,
7498 gen_helper_neon_narrow_u16
,
7499 tcg_gen_trunc_i64_i32
,
7501 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7502 gen_helper_neon_unarrow_sat8
,
7503 gen_helper_neon_unarrow_sat16
,
7504 gen_helper_neon_unarrow_sat32
,
7507 genenvfn
= sqxtunfns
[size
];
7509 genfn
= xtnfns
[size
];
7513 case 0x14: /* SQXTN, UQXTN */
7515 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7516 { gen_helper_neon_narrow_sat_s8
,
7517 gen_helper_neon_narrow_sat_u8
},
7518 { gen_helper_neon_narrow_sat_s16
,
7519 gen_helper_neon_narrow_sat_u16
},
7520 { gen_helper_neon_narrow_sat_s32
,
7521 gen_helper_neon_narrow_sat_u32
},
7523 genenvfn
= fns
[size
][u
];
7526 case 0x16: /* FCVTN, FCVTN2 */
7527 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7529 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7531 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7532 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7533 tcg_gen_trunc_i64_i32(tcg_lo
, tcg_op
);
7534 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7535 tcg_gen_shri_i64(tcg_op
, tcg_op
, 32);
7536 tcg_gen_trunc_i64_i32(tcg_hi
, tcg_op
);
7537 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7538 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7539 tcg_temp_free_i32(tcg_lo
);
7540 tcg_temp_free_i32(tcg_hi
);
7543 case 0x56: /* FCVTXN, FCVTXN2 */
7544 /* 64 bit to 32 bit float conversion
7545 * with von Neumann rounding (round to odd)
7548 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7551 g_assert_not_reached();
7555 genfn(tcg_res
[pass
], tcg_op
);
7556 } else if (genenvfn
) {
7557 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7560 tcg_temp_free_i64(tcg_op
);
7563 for (pass
= 0; pass
< 2; pass
++) {
7564 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7565 tcg_temp_free_i32(tcg_res
[pass
]);
7568 clear_vec_high(s
, rd
);
7572 /* Remaining saturating accumulating ops */
7573 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7574 bool is_q
, int size
, int rn
, int rd
)
7576 bool is_double
= (size
== 3);
7579 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7580 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7583 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7584 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7585 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7587 if (is_u
) { /* USQADD */
7588 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7589 } else { /* SUQADD */
7590 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7592 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7595 clear_vec_high(s
, rd
);
7598 tcg_temp_free_i64(tcg_rd
);
7599 tcg_temp_free_i64(tcg_rn
);
7601 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7602 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7603 int pass
, maxpasses
;
7608 maxpasses
= is_q
? 4 : 2;
7611 for (pass
= 0; pass
< maxpasses
; pass
++) {
7613 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7614 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7616 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7617 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7620 if (is_u
) { /* USQADD */
7623 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7626 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7629 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7632 g_assert_not_reached();
7634 } else { /* SUQADD */
7637 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7640 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7643 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7646 g_assert_not_reached();
7651 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7652 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7653 tcg_temp_free_i64(tcg_zero
);
7655 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7659 clear_vec_high(s
, rd
);
7662 tcg_temp_free_i32(tcg_rd
);
7663 tcg_temp_free_i32(tcg_rn
);
7667 /* C3.6.12 AdvSIMD scalar two reg misc
7668 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7669 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7670 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7671 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7673 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7675 int rd
= extract32(insn
, 0, 5);
7676 int rn
= extract32(insn
, 5, 5);
7677 int opcode
= extract32(insn
, 12, 5);
7678 int size
= extract32(insn
, 22, 2);
7679 bool u
= extract32(insn
, 29, 1);
7680 bool is_fcvt
= false;
7683 TCGv_ptr tcg_fpstatus
;
7686 case 0x3: /* USQADD / SUQADD*/
7687 if (!fp_access_check(s
)) {
7690 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7692 case 0x7: /* SQABS / SQNEG */
7694 case 0xa: /* CMLT */
7696 unallocated_encoding(s
);
7700 case 0x8: /* CMGT, CMGE */
7701 case 0x9: /* CMEQ, CMLE */
7702 case 0xb: /* ABS, NEG */
7704 unallocated_encoding(s
);
7708 case 0x12: /* SQXTUN */
7710 unallocated_encoding(s
);
7714 case 0x14: /* SQXTN, UQXTN */
7716 unallocated_encoding(s
);
7719 if (!fp_access_check(s
)) {
7722 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7727 /* Floating point: U, size[1] and opcode indicate operation;
7728 * size[0] indicates single or double precision.
7730 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7731 size
= extract32(size
, 0, 1) ? 3 : 2;
7733 case 0x2c: /* FCMGT (zero) */
7734 case 0x2d: /* FCMEQ (zero) */
7735 case 0x2e: /* FCMLT (zero) */
7736 case 0x6c: /* FCMGE (zero) */
7737 case 0x6d: /* FCMLE (zero) */
7738 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7740 case 0x1d: /* SCVTF */
7741 case 0x5d: /* UCVTF */
7743 bool is_signed
= (opcode
== 0x1d);
7744 if (!fp_access_check(s
)) {
7747 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7750 case 0x3d: /* FRECPE */
7751 case 0x3f: /* FRECPX */
7752 case 0x7d: /* FRSQRTE */
7753 if (!fp_access_check(s
)) {
7756 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7758 case 0x1a: /* FCVTNS */
7759 case 0x1b: /* FCVTMS */
7760 case 0x3a: /* FCVTPS */
7761 case 0x3b: /* FCVTZS */
7762 case 0x5a: /* FCVTNU */
7763 case 0x5b: /* FCVTMU */
7764 case 0x7a: /* FCVTPU */
7765 case 0x7b: /* FCVTZU */
7767 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
7769 case 0x1c: /* FCVTAS */
7770 case 0x5c: /* FCVTAU */
7771 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7773 rmode
= FPROUNDING_TIEAWAY
;
7775 case 0x56: /* FCVTXN, FCVTXN2 */
7777 unallocated_encoding(s
);
7780 if (!fp_access_check(s
)) {
7783 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
7786 unallocated_encoding(s
);
7791 unallocated_encoding(s
);
7795 if (!fp_access_check(s
)) {
7800 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7801 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7802 tcg_fpstatus
= get_fpstatus_ptr();
7804 TCGV_UNUSED_I32(tcg_rmode
);
7805 TCGV_UNUSED_PTR(tcg_fpstatus
);
7809 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7810 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7812 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
7813 write_fp_dreg(s
, rd
, tcg_rd
);
7814 tcg_temp_free_i64(tcg_rd
);
7815 tcg_temp_free_i64(tcg_rn
);
7817 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7818 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7820 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7823 case 0x7: /* SQABS, SQNEG */
7825 NeonGenOneOpEnvFn
*genfn
;
7826 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
7827 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
7828 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
7829 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
7831 genfn
= fns
[size
][u
];
7832 genfn(tcg_rd
, cpu_env
, tcg_rn
);
7835 case 0x1a: /* FCVTNS */
7836 case 0x1b: /* FCVTMS */
7837 case 0x1c: /* FCVTAS */
7838 case 0x3a: /* FCVTPS */
7839 case 0x3b: /* FCVTZS */
7841 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7842 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7843 tcg_temp_free_i32(tcg_shift
);
7846 case 0x5a: /* FCVTNU */
7847 case 0x5b: /* FCVTMU */
7848 case 0x5c: /* FCVTAU */
7849 case 0x7a: /* FCVTPU */
7850 case 0x7b: /* FCVTZU */
7852 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7853 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7854 tcg_temp_free_i32(tcg_shift
);
7858 g_assert_not_reached();
7861 write_fp_sreg(s
, rd
, tcg_rd
);
7862 tcg_temp_free_i32(tcg_rd
);
7863 tcg_temp_free_i32(tcg_rn
);
7867 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7868 tcg_temp_free_i32(tcg_rmode
);
7869 tcg_temp_free_ptr(tcg_fpstatus
);
7873 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
7874 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
7875 int immh
, int immb
, int opcode
, int rn
, int rd
)
7877 int size
= 32 - clz32(immh
) - 1;
7878 int immhb
= immh
<< 3 | immb
;
7879 int shift
= 2 * (8 << size
) - immhb
;
7880 bool accumulate
= false;
7882 bool insert
= false;
7883 int dsize
= is_q
? 128 : 64;
7884 int esize
= 8 << size
;
7885 int elements
= dsize
/esize
;
7886 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
7887 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7888 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7892 if (extract32(immh
, 3, 1) && !is_q
) {
7893 unallocated_encoding(s
);
7897 if (size
> 3 && !is_q
) {
7898 unallocated_encoding(s
);
7902 if (!fp_access_check(s
)) {
7907 case 0x02: /* SSRA / USRA (accumulate) */
7910 case 0x04: /* SRSHR / URSHR (rounding) */
7913 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7914 accumulate
= round
= true;
7916 case 0x08: /* SRI */
7922 uint64_t round_const
= 1ULL << (shift
- 1);
7923 tcg_round
= tcg_const_i64(round_const
);
7925 TCGV_UNUSED_I64(tcg_round
);
7928 for (i
= 0; i
< elements
; i
++) {
7929 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
7930 if (accumulate
|| insert
) {
7931 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
7935 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
7937 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7938 accumulate
, is_u
, size
, shift
);
7941 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
7945 clear_vec_high(s
, rd
);
7949 tcg_temp_free_i64(tcg_round
);
7953 /* SHL/SLI - Vector shift left */
7954 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
7955 int immh
, int immb
, int opcode
, int rn
, int rd
)
7957 int size
= 32 - clz32(immh
) - 1;
7958 int immhb
= immh
<< 3 | immb
;
7959 int shift
= immhb
- (8 << size
);
7960 int dsize
= is_q
? 128 : 64;
7961 int esize
= 8 << size
;
7962 int elements
= dsize
/esize
;
7963 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7964 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7967 if (extract32(immh
, 3, 1) && !is_q
) {
7968 unallocated_encoding(s
);
7972 if (size
> 3 && !is_q
) {
7973 unallocated_encoding(s
);
7977 if (!fp_access_check(s
)) {
7981 for (i
= 0; i
< elements
; i
++) {
7982 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
7984 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
7987 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
7989 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
7993 clear_vec_high(s
, rd
);
7997 /* USHLL/SHLL - Vector shift left with widening */
7998 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
7999 int immh
, int immb
, int opcode
, int rn
, int rd
)
8001 int size
= 32 - clz32(immh
) - 1;
8002 int immhb
= immh
<< 3 | immb
;
8003 int shift
= immhb
- (8 << size
);
8005 int esize
= 8 << size
;
8006 int elements
= dsize
/esize
;
8007 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8008 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8012 unallocated_encoding(s
);
8016 if (!fp_access_check(s
)) {
8020 /* For the LL variants the store is larger than the load,
8021 * so if rd == rn we would overwrite parts of our input.
8022 * So load everything right now and use shifts in the main loop.
8024 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8026 for (i
= 0; i
< elements
; i
++) {
8027 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8028 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8029 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8030 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8034 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8035 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8036 int immh
, int immb
, int opcode
, int rn
, int rd
)
8038 int immhb
= immh
<< 3 | immb
;
8039 int size
= 32 - clz32(immh
) - 1;
8041 int esize
= 8 << size
;
8042 int elements
= dsize
/esize
;
8043 int shift
= (2 * esize
) - immhb
;
8044 bool round
= extract32(opcode
, 0, 1);
8045 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8049 if (extract32(immh
, 3, 1)) {
8050 unallocated_encoding(s
);
8054 if (!fp_access_check(s
)) {
8058 tcg_rn
= tcg_temp_new_i64();
8059 tcg_rd
= tcg_temp_new_i64();
8060 tcg_final
= tcg_temp_new_i64();
8061 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8064 uint64_t round_const
= 1ULL << (shift
- 1);
8065 tcg_round
= tcg_const_i64(round_const
);
8067 TCGV_UNUSED_I64(tcg_round
);
8070 for (i
= 0; i
< elements
; i
++) {
8071 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8072 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8073 false, true, size
+1, shift
);
8075 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8079 clear_vec_high(s
, rd
);
8080 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8082 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8086 tcg_temp_free_i64(tcg_round
);
8088 tcg_temp_free_i64(tcg_rn
);
8089 tcg_temp_free_i64(tcg_rd
);
8090 tcg_temp_free_i64(tcg_final
);
8095 /* C3.6.14 AdvSIMD shift by immediate
8096 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8097 * +---+---+---+-------------+------+------+--------+---+------+------+
8098 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8099 * +---+---+---+-------------+------+------+--------+---+------+------+
8101 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8103 int rd
= extract32(insn
, 0, 5);
8104 int rn
= extract32(insn
, 5, 5);
8105 int opcode
= extract32(insn
, 11, 5);
8106 int immb
= extract32(insn
, 16, 3);
8107 int immh
= extract32(insn
, 19, 4);
8108 bool is_u
= extract32(insn
, 29, 1);
8109 bool is_q
= extract32(insn
, 30, 1);
8112 case 0x08: /* SRI */
8114 unallocated_encoding(s
);
8118 case 0x00: /* SSHR / USHR */
8119 case 0x02: /* SSRA / USRA (accumulate) */
8120 case 0x04: /* SRSHR / URSHR (rounding) */
8121 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8122 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8124 case 0x0a: /* SHL / SLI */
8125 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8127 case 0x10: /* SHRN */
8128 case 0x11: /* RSHRN / SQRSHRUN */
8130 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8133 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8136 case 0x12: /* SQSHRN / UQSHRN */
8137 case 0x13: /* SQRSHRN / UQRSHRN */
8138 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8141 case 0x14: /* SSHLL / USHLL */
8142 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8144 case 0x1c: /* SCVTF / UCVTF */
8145 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8148 case 0xc: /* SQSHLU */
8150 unallocated_encoding(s
);
8153 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8155 case 0xe: /* SQSHL, UQSHL */
8156 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8158 case 0x1f: /* FCVTZS/ FCVTZU */
8159 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8162 unallocated_encoding(s
);
8167 /* Generate code to do a "long" addition or subtraction, ie one done in
8168 * TCGv_i64 on vector lanes twice the width specified by size.
8170 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8171 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8173 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8174 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8175 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8176 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8178 NeonGenTwo64OpFn
*genfn
;
8181 genfn
= fns
[size
][is_sub
];
8182 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8185 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8186 int opcode
, int rd
, int rn
, int rm
)
8188 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8189 TCGv_i64 tcg_res
[2];
8192 tcg_res
[0] = tcg_temp_new_i64();
8193 tcg_res
[1] = tcg_temp_new_i64();
8195 /* Does this op do an adding accumulate, a subtracting accumulate,
8196 * or no accumulate at all?
8214 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8215 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8218 /* size == 2 means two 32x32->64 operations; this is worth special
8219 * casing because we can generally handle it inline.
8222 for (pass
= 0; pass
< 2; pass
++) {
8223 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8224 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8225 TCGv_i64 tcg_passres
;
8226 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8228 int elt
= pass
+ is_q
* 2;
8230 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8231 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8234 tcg_passres
= tcg_res
[pass
];
8236 tcg_passres
= tcg_temp_new_i64();
8240 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8241 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8243 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8244 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8246 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8247 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8249 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8250 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8252 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8253 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8254 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8256 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8257 tcg_temp_free_i64(tcg_tmp1
);
8258 tcg_temp_free_i64(tcg_tmp2
);
8261 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8262 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8263 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8264 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8266 case 9: /* SQDMLAL, SQDMLAL2 */
8267 case 11: /* SQDMLSL, SQDMLSL2 */
8268 case 13: /* SQDMULL, SQDMULL2 */
8269 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8270 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8271 tcg_passres
, tcg_passres
);
8274 g_assert_not_reached();
8277 if (opcode
== 9 || opcode
== 11) {
8278 /* saturating accumulate ops */
8280 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8282 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8283 tcg_res
[pass
], tcg_passres
);
8284 } else if (accop
> 0) {
8285 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8286 } else if (accop
< 0) {
8287 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8291 tcg_temp_free_i64(tcg_passres
);
8294 tcg_temp_free_i64(tcg_op1
);
8295 tcg_temp_free_i64(tcg_op2
);
8298 /* size 0 or 1, generally helper functions */
8299 for (pass
= 0; pass
< 2; pass
++) {
8300 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8301 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8302 TCGv_i64 tcg_passres
;
8303 int elt
= pass
+ is_q
* 2;
8305 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8306 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8309 tcg_passres
= tcg_res
[pass
];
8311 tcg_passres
= tcg_temp_new_i64();
8315 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8316 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8318 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8319 static NeonGenWidenFn
* const widenfns
[2][2] = {
8320 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8321 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8323 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8325 widenfn(tcg_op2_64
, tcg_op2
);
8326 widenfn(tcg_passres
, tcg_op1
);
8327 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8328 tcg_passres
, tcg_op2_64
);
8329 tcg_temp_free_i64(tcg_op2_64
);
8332 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8333 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8336 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8338 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8342 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8344 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8348 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8349 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8350 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8353 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8355 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8359 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8361 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8365 case 9: /* SQDMLAL, SQDMLAL2 */
8366 case 11: /* SQDMLSL, SQDMLSL2 */
8367 case 13: /* SQDMULL, SQDMULL2 */
8369 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8370 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8371 tcg_passres
, tcg_passres
);
8373 case 14: /* PMULL */
8375 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8378 g_assert_not_reached();
8380 tcg_temp_free_i32(tcg_op1
);
8381 tcg_temp_free_i32(tcg_op2
);
8384 if (opcode
== 9 || opcode
== 11) {
8385 /* saturating accumulate ops */
8387 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8389 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8393 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8394 tcg_res
[pass
], tcg_passres
);
8396 tcg_temp_free_i64(tcg_passres
);
8401 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8402 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8403 tcg_temp_free_i64(tcg_res
[0]);
8404 tcg_temp_free_i64(tcg_res
[1]);
8407 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8408 int opcode
, int rd
, int rn
, int rm
)
8410 TCGv_i64 tcg_res
[2];
8411 int part
= is_q
? 2 : 0;
8414 for (pass
= 0; pass
< 2; pass
++) {
8415 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8416 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8417 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8418 static NeonGenWidenFn
* const widenfns
[3][2] = {
8419 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8420 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8421 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8423 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8425 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8426 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8427 widenfn(tcg_op2_wide
, tcg_op2
);
8428 tcg_temp_free_i32(tcg_op2
);
8429 tcg_res
[pass
] = tcg_temp_new_i64();
8430 gen_neon_addl(size
, (opcode
== 3),
8431 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8432 tcg_temp_free_i64(tcg_op1
);
8433 tcg_temp_free_i64(tcg_op2_wide
);
8436 for (pass
= 0; pass
< 2; pass
++) {
8437 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8438 tcg_temp_free_i64(tcg_res
[pass
]);
8442 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8444 tcg_gen_shri_i64(in
, in
, 32);
8445 tcg_gen_trunc_i64_i32(res
, in
);
8448 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8450 tcg_gen_addi_i64(in
, in
, 1U << 31);
8451 do_narrow_high_u32(res
, in
);
8454 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8455 int opcode
, int rd
, int rn
, int rm
)
8457 TCGv_i32 tcg_res
[2];
8458 int part
= is_q
? 2 : 0;
8461 for (pass
= 0; pass
< 2; pass
++) {
8462 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8463 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8464 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8465 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8466 { gen_helper_neon_narrow_high_u8
,
8467 gen_helper_neon_narrow_round_high_u8
},
8468 { gen_helper_neon_narrow_high_u16
,
8469 gen_helper_neon_narrow_round_high_u16
},
8470 { do_narrow_high_u32
, do_narrow_round_high_u32
},
8472 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8474 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8475 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8477 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8479 tcg_temp_free_i64(tcg_op1
);
8480 tcg_temp_free_i64(tcg_op2
);
8482 tcg_res
[pass
] = tcg_temp_new_i32();
8483 gennarrow(tcg_res
[pass
], tcg_wideres
);
8484 tcg_temp_free_i64(tcg_wideres
);
8487 for (pass
= 0; pass
< 2; pass
++) {
8488 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8489 tcg_temp_free_i32(tcg_res
[pass
]);
8492 clear_vec_high(s
, rd
);
8496 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8498 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8499 * is the only three-reg-diff instruction which produces a
8500 * 128-bit wide result from a single operation. However since
8501 * it's possible to calculate the two halves more or less
8502 * separately we just use two helper calls.
8504 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8505 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8506 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8508 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8509 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8510 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8511 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8512 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8513 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8515 tcg_temp_free_i64(tcg_op1
);
8516 tcg_temp_free_i64(tcg_op2
);
8517 tcg_temp_free_i64(tcg_res
);
8520 /* C3.6.15 AdvSIMD three different
8521 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8522 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8523 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8524 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8526 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8528 /* Instructions in this group fall into three basic classes
8529 * (in each case with the operation working on each element in
8530 * the input vectors):
8531 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8533 * (2) wide 64 x 128 -> 128
8534 * (3) narrowing 128 x 128 -> 64
8535 * Here we do initial decode, catch unallocated cases and
8536 * dispatch to separate functions for each class.
8538 int is_q
= extract32(insn
, 30, 1);
8539 int is_u
= extract32(insn
, 29, 1);
8540 int size
= extract32(insn
, 22, 2);
8541 int opcode
= extract32(insn
, 12, 4);
8542 int rm
= extract32(insn
, 16, 5);
8543 int rn
= extract32(insn
, 5, 5);
8544 int rd
= extract32(insn
, 0, 5);
8547 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8548 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8549 /* 64 x 128 -> 128 */
8551 unallocated_encoding(s
);
8554 if (!fp_access_check(s
)) {
8557 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8559 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8560 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8561 /* 128 x 128 -> 64 */
8563 unallocated_encoding(s
);
8566 if (!fp_access_check(s
)) {
8569 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8571 case 14: /* PMULL, PMULL2 */
8572 if (is_u
|| size
== 1 || size
== 2) {
8573 unallocated_encoding(s
);
8577 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8578 unallocated_encoding(s
);
8581 if (!fp_access_check(s
)) {
8584 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8588 case 9: /* SQDMLAL, SQDMLAL2 */
8589 case 11: /* SQDMLSL, SQDMLSL2 */
8590 case 13: /* SQDMULL, SQDMULL2 */
8591 if (is_u
|| size
== 0) {
8592 unallocated_encoding(s
);
8596 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8597 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8598 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8599 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8600 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8601 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8602 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8603 /* 64 x 64 -> 128 */
8605 unallocated_encoding(s
);
8609 if (!fp_access_check(s
)) {
8613 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8616 /* opcode 15 not allocated */
8617 unallocated_encoding(s
);
8622 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8623 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8625 int rd
= extract32(insn
, 0, 5);
8626 int rn
= extract32(insn
, 5, 5);
8627 int rm
= extract32(insn
, 16, 5);
8628 int size
= extract32(insn
, 22, 2);
8629 bool is_u
= extract32(insn
, 29, 1);
8630 bool is_q
= extract32(insn
, 30, 1);
8631 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8634 if (!fp_access_check(s
)) {
8638 tcg_op1
= tcg_temp_new_i64();
8639 tcg_op2
= tcg_temp_new_i64();
8640 tcg_res
[0] = tcg_temp_new_i64();
8641 tcg_res
[1] = tcg_temp_new_i64();
8643 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8644 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8645 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8650 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8653 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8656 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8659 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8664 /* B* ops need res loaded to operate on */
8665 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8670 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8672 case 1: /* BSL bitwise select */
8673 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8674 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8675 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8677 case 2: /* BIT, bitwise insert if true */
8678 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8679 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8680 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8682 case 3: /* BIF, bitwise insert if false */
8683 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8684 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8685 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8691 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8693 tcg_gen_movi_i64(tcg_res
[1], 0);
8695 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8697 tcg_temp_free_i64(tcg_op1
);
8698 tcg_temp_free_i64(tcg_op2
);
8699 tcg_temp_free_i64(tcg_res
[0]);
8700 tcg_temp_free_i64(tcg_res
[1]);
8703 /* Helper functions for 32 bit comparisons */
8704 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8706 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8709 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8711 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8714 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8716 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8719 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8721 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8724 /* Pairwise op subgroup of C3.6.16.
8726 * This is called directly or via the handle_3same_float for float pairwise
8727 * operations where the opcode and size are calculated differently.
8729 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8730 int size
, int rn
, int rm
, int rd
)
8735 /* Floating point operations need fpst */
8736 if (opcode
>= 0x58) {
8737 fpst
= get_fpstatus_ptr();
8739 TCGV_UNUSED_PTR(fpst
);
8742 if (!fp_access_check(s
)) {
8746 /* These operations work on the concatenated rm:rn, with each pair of
8747 * adjacent elements being operated on to produce an element in the result.
8750 TCGv_i64 tcg_res
[2];
8752 for (pass
= 0; pass
< 2; pass
++) {
8753 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8754 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8755 int passreg
= (pass
== 0) ? rn
: rm
;
8757 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8758 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8759 tcg_res
[pass
] = tcg_temp_new_i64();
8762 case 0x17: /* ADDP */
8763 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8765 case 0x58: /* FMAXNMP */
8766 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8768 case 0x5a: /* FADDP */
8769 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8771 case 0x5e: /* FMAXP */
8772 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8774 case 0x78: /* FMINNMP */
8775 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8777 case 0x7e: /* FMINP */
8778 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8781 g_assert_not_reached();
8784 tcg_temp_free_i64(tcg_op1
);
8785 tcg_temp_free_i64(tcg_op2
);
8788 for (pass
= 0; pass
< 2; pass
++) {
8789 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8790 tcg_temp_free_i64(tcg_res
[pass
]);
8793 int maxpass
= is_q
? 4 : 2;
8794 TCGv_i32 tcg_res
[4];
8796 for (pass
= 0; pass
< maxpass
; pass
++) {
8797 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8798 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8799 NeonGenTwoOpFn
*genfn
= NULL
;
8800 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
8801 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
8803 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
8804 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
8805 tcg_res
[pass
] = tcg_temp_new_i32();
8808 case 0x17: /* ADDP */
8810 static NeonGenTwoOpFn
* const fns
[3] = {
8811 gen_helper_neon_padd_u8
,
8812 gen_helper_neon_padd_u16
,
8818 case 0x14: /* SMAXP, UMAXP */
8820 static NeonGenTwoOpFn
* const fns
[3][2] = {
8821 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
8822 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
8823 { gen_max_s32
, gen_max_u32
},
8825 genfn
= fns
[size
][u
];
8828 case 0x15: /* SMINP, UMINP */
8830 static NeonGenTwoOpFn
* const fns
[3][2] = {
8831 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
8832 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
8833 { gen_min_s32
, gen_min_u32
},
8835 genfn
= fns
[size
][u
];
8838 /* The FP operations are all on single floats (32 bit) */
8839 case 0x58: /* FMAXNMP */
8840 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8842 case 0x5a: /* FADDP */
8843 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8845 case 0x5e: /* FMAXP */
8846 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8848 case 0x78: /* FMINNMP */
8849 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8851 case 0x7e: /* FMINP */
8852 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8855 g_assert_not_reached();
8858 /* FP ops called directly, otherwise call now */
8860 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8863 tcg_temp_free_i32(tcg_op1
);
8864 tcg_temp_free_i32(tcg_op2
);
8867 for (pass
= 0; pass
< maxpass
; pass
++) {
8868 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8869 tcg_temp_free_i32(tcg_res
[pass
]);
8872 clear_vec_high(s
, rd
);
8876 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
8877 tcg_temp_free_ptr(fpst
);
8881 /* Floating point op subgroup of C3.6.16. */
8882 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
8884 /* For floating point ops, the U, size[1] and opcode bits
8885 * together indicate the operation. size[0] indicates single
8888 int fpopcode
= extract32(insn
, 11, 5)
8889 | (extract32(insn
, 23, 1) << 5)
8890 | (extract32(insn
, 29, 1) << 6);
8891 int is_q
= extract32(insn
, 30, 1);
8892 int size
= extract32(insn
, 22, 1);
8893 int rm
= extract32(insn
, 16, 5);
8894 int rn
= extract32(insn
, 5, 5);
8895 int rd
= extract32(insn
, 0, 5);
8897 int datasize
= is_q
? 128 : 64;
8898 int esize
= 32 << size
;
8899 int elements
= datasize
/ esize
;
8901 if (size
== 1 && !is_q
) {
8902 unallocated_encoding(s
);
8907 case 0x58: /* FMAXNMP */
8908 case 0x5a: /* FADDP */
8909 case 0x5e: /* FMAXP */
8910 case 0x78: /* FMINNMP */
8911 case 0x7e: /* FMINP */
8912 if (size
&& !is_q
) {
8913 unallocated_encoding(s
);
8916 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
8919 case 0x1b: /* FMULX */
8920 case 0x1f: /* FRECPS */
8921 case 0x3f: /* FRSQRTS */
8922 case 0x5d: /* FACGE */
8923 case 0x7d: /* FACGT */
8924 case 0x19: /* FMLA */
8925 case 0x39: /* FMLS */
8926 case 0x18: /* FMAXNM */
8927 case 0x1a: /* FADD */
8928 case 0x1c: /* FCMEQ */
8929 case 0x1e: /* FMAX */
8930 case 0x38: /* FMINNM */
8931 case 0x3a: /* FSUB */
8932 case 0x3e: /* FMIN */
8933 case 0x5b: /* FMUL */
8934 case 0x5c: /* FCMGE */
8935 case 0x5f: /* FDIV */
8936 case 0x7a: /* FABD */
8937 case 0x7c: /* FCMGT */
8938 if (!fp_access_check(s
)) {
8942 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
8945 unallocated_encoding(s
);
8950 /* Integer op subgroup of C3.6.16. */
8951 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
8953 int is_q
= extract32(insn
, 30, 1);
8954 int u
= extract32(insn
, 29, 1);
8955 int size
= extract32(insn
, 22, 2);
8956 int opcode
= extract32(insn
, 11, 5);
8957 int rm
= extract32(insn
, 16, 5);
8958 int rn
= extract32(insn
, 5, 5);
8959 int rd
= extract32(insn
, 0, 5);
8963 case 0x13: /* MUL, PMUL */
8964 if (u
&& size
!= 0) {
8965 unallocated_encoding(s
);
8969 case 0x0: /* SHADD, UHADD */
8970 case 0x2: /* SRHADD, URHADD */
8971 case 0x4: /* SHSUB, UHSUB */
8972 case 0xc: /* SMAX, UMAX */
8973 case 0xd: /* SMIN, UMIN */
8974 case 0xe: /* SABD, UABD */
8975 case 0xf: /* SABA, UABA */
8976 case 0x12: /* MLA, MLS */
8978 unallocated_encoding(s
);
8982 case 0x16: /* SQDMULH, SQRDMULH */
8983 if (size
== 0 || size
== 3) {
8984 unallocated_encoding(s
);
8989 if (size
== 3 && !is_q
) {
8990 unallocated_encoding(s
);
8996 if (!fp_access_check(s
)) {
9001 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9002 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9003 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9004 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9006 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9007 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9009 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9011 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9013 tcg_temp_free_i64(tcg_res
);
9014 tcg_temp_free_i64(tcg_op1
);
9015 tcg_temp_free_i64(tcg_op2
);
9018 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9019 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9020 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9021 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9022 NeonGenTwoOpFn
*genfn
= NULL
;
9023 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9025 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9026 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9029 case 0x0: /* SHADD, UHADD */
9031 static NeonGenTwoOpFn
* const fns
[3][2] = {
9032 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9033 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9034 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9036 genfn
= fns
[size
][u
];
9039 case 0x1: /* SQADD, UQADD */
9041 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9042 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9043 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9044 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9046 genenvfn
= fns
[size
][u
];
9049 case 0x2: /* SRHADD, URHADD */
9051 static NeonGenTwoOpFn
* const fns
[3][2] = {
9052 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9053 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9054 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9056 genfn
= fns
[size
][u
];
9059 case 0x4: /* SHSUB, UHSUB */
9061 static NeonGenTwoOpFn
* const fns
[3][2] = {
9062 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9063 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9064 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9066 genfn
= fns
[size
][u
];
9069 case 0x5: /* SQSUB, UQSUB */
9071 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9072 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9073 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9074 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9076 genenvfn
= fns
[size
][u
];
9079 case 0x6: /* CMGT, CMHI */
9081 static NeonGenTwoOpFn
* const fns
[3][2] = {
9082 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9083 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9084 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9086 genfn
= fns
[size
][u
];
9089 case 0x7: /* CMGE, CMHS */
9091 static NeonGenTwoOpFn
* const fns
[3][2] = {
9092 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9093 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9094 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9096 genfn
= fns
[size
][u
];
9099 case 0x8: /* SSHL, USHL */
9101 static NeonGenTwoOpFn
* const fns
[3][2] = {
9102 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9103 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9104 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9106 genfn
= fns
[size
][u
];
9109 case 0x9: /* SQSHL, UQSHL */
9111 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9112 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9113 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9114 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9116 genenvfn
= fns
[size
][u
];
9119 case 0xa: /* SRSHL, URSHL */
9121 static NeonGenTwoOpFn
* const fns
[3][2] = {
9122 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9123 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9124 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9126 genfn
= fns
[size
][u
];
9129 case 0xb: /* SQRSHL, UQRSHL */
9131 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9132 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9133 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9134 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9136 genenvfn
= fns
[size
][u
];
9139 case 0xc: /* SMAX, UMAX */
9141 static NeonGenTwoOpFn
* const fns
[3][2] = {
9142 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9143 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9144 { gen_max_s32
, gen_max_u32
},
9146 genfn
= fns
[size
][u
];
9150 case 0xd: /* SMIN, UMIN */
9152 static NeonGenTwoOpFn
* const fns
[3][2] = {
9153 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9154 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9155 { gen_min_s32
, gen_min_u32
},
9157 genfn
= fns
[size
][u
];
9160 case 0xe: /* SABD, UABD */
9161 case 0xf: /* SABA, UABA */
9163 static NeonGenTwoOpFn
* const fns
[3][2] = {
9164 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9165 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9166 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9168 genfn
= fns
[size
][u
];
9171 case 0x10: /* ADD, SUB */
9173 static NeonGenTwoOpFn
* const fns
[3][2] = {
9174 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9175 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9176 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9178 genfn
= fns
[size
][u
];
9181 case 0x11: /* CMTST, CMEQ */
9183 static NeonGenTwoOpFn
* const fns
[3][2] = {
9184 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9185 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9186 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9188 genfn
= fns
[size
][u
];
9191 case 0x13: /* MUL, PMUL */
9195 genfn
= gen_helper_neon_mul_p8
;
9198 /* fall through : MUL */
9199 case 0x12: /* MLA, MLS */
9201 static NeonGenTwoOpFn
* const fns
[3] = {
9202 gen_helper_neon_mul_u8
,
9203 gen_helper_neon_mul_u16
,
9209 case 0x16: /* SQDMULH, SQRDMULH */
9211 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9212 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9213 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9215 assert(size
== 1 || size
== 2);
9216 genenvfn
= fns
[size
- 1][u
];
9220 g_assert_not_reached();
9224 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9226 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9229 if (opcode
== 0xf || opcode
== 0x12) {
9230 /* SABA, UABA, MLA, MLS: accumulating ops */
9231 static NeonGenTwoOpFn
* const fns
[3][2] = {
9232 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9233 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9234 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9236 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9238 genfn
= fns
[size
][is_sub
];
9239 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9240 genfn(tcg_res
, tcg_op1
, tcg_res
);
9243 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9245 tcg_temp_free_i32(tcg_res
);
9246 tcg_temp_free_i32(tcg_op1
);
9247 tcg_temp_free_i32(tcg_op2
);
9252 clear_vec_high(s
, rd
);
9256 /* C3.6.16 AdvSIMD three same
9257 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9258 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9259 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9260 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9262 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9264 int opcode
= extract32(insn
, 11, 5);
9267 case 0x3: /* logic ops */
9268 disas_simd_3same_logic(s
, insn
);
9270 case 0x17: /* ADDP */
9271 case 0x14: /* SMAXP, UMAXP */
9272 case 0x15: /* SMINP, UMINP */
9274 /* Pairwise operations */
9275 int is_q
= extract32(insn
, 30, 1);
9276 int u
= extract32(insn
, 29, 1);
9277 int size
= extract32(insn
, 22, 2);
9278 int rm
= extract32(insn
, 16, 5);
9279 int rn
= extract32(insn
, 5, 5);
9280 int rd
= extract32(insn
, 0, 5);
9281 if (opcode
== 0x17) {
9282 if (u
|| (size
== 3 && !is_q
)) {
9283 unallocated_encoding(s
);
9288 unallocated_encoding(s
);
9292 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9296 /* floating point ops, sz[1] and U are part of opcode */
9297 disas_simd_3same_float(s
, insn
);
9300 disas_simd_3same_int(s
, insn
);
9305 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9306 int size
, int rn
, int rd
)
9308 /* Handle 2-reg-misc ops which are widening (so each size element
9309 * in the source becomes a 2*size element in the destination.
9310 * The only instruction like this is FCVTL.
9315 /* 32 -> 64 bit fp conversion */
9316 TCGv_i64 tcg_res
[2];
9317 int srcelt
= is_q
? 2 : 0;
9319 for (pass
= 0; pass
< 2; pass
++) {
9320 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9321 tcg_res
[pass
] = tcg_temp_new_i64();
9323 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9324 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9325 tcg_temp_free_i32(tcg_op
);
9327 for (pass
= 0; pass
< 2; pass
++) {
9328 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9329 tcg_temp_free_i64(tcg_res
[pass
]);
9332 /* 16 -> 32 bit fp conversion */
9333 int srcelt
= is_q
? 4 : 0;
9334 TCGv_i32 tcg_res
[4];
9336 for (pass
= 0; pass
< 4; pass
++) {
9337 tcg_res
[pass
] = tcg_temp_new_i32();
9339 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9340 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9343 for (pass
= 0; pass
< 4; pass
++) {
9344 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9345 tcg_temp_free_i32(tcg_res
[pass
]);
9350 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9351 bool is_q
, int size
, int rn
, int rd
)
9353 int op
= (opcode
<< 1) | u
;
9354 int opsz
= op
+ size
;
9355 int grp_size
= 3 - opsz
;
9356 int dsize
= is_q
? 128 : 64;
9360 unallocated_encoding(s
);
9364 if (!fp_access_check(s
)) {
9369 /* Special case bytes, use bswap op on each group of elements */
9370 int groups
= dsize
/ (8 << grp_size
);
9372 for (i
= 0; i
< groups
; i
++) {
9373 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9375 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9378 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9381 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9384 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9387 g_assert_not_reached();
9389 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9390 tcg_temp_free_i64(tcg_tmp
);
9393 clear_vec_high(s
, rd
);
9396 int revmask
= (1 << grp_size
) - 1;
9397 int esize
= 8 << size
;
9398 int elements
= dsize
/ esize
;
9399 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9400 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9401 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9403 for (i
= 0; i
< elements
; i
++) {
9404 int e_rev
= (i
& 0xf) ^ revmask
;
9405 int off
= e_rev
* esize
;
9406 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9408 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9409 tcg_rn
, off
- 64, esize
);
9411 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9414 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9415 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9417 tcg_temp_free_i64(tcg_rd_hi
);
9418 tcg_temp_free_i64(tcg_rd
);
9419 tcg_temp_free_i64(tcg_rn
);
9423 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9424 bool is_q
, int size
, int rn
, int rd
)
9426 /* Implement the pairwise operations from 2-misc:
9427 * SADDLP, UADDLP, SADALP, UADALP.
9428 * These all add pairs of elements in the input to produce a
9429 * double-width result element in the output (possibly accumulating).
9431 bool accum
= (opcode
== 0x6);
9432 int maxpass
= is_q
? 2 : 1;
9434 TCGv_i64 tcg_res
[2];
9437 /* 32 + 32 -> 64 op */
9438 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9440 for (pass
= 0; pass
< maxpass
; pass
++) {
9441 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9442 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9444 tcg_res
[pass
] = tcg_temp_new_i64();
9446 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9447 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9448 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9450 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9451 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9454 tcg_temp_free_i64(tcg_op1
);
9455 tcg_temp_free_i64(tcg_op2
);
9458 for (pass
= 0; pass
< maxpass
; pass
++) {
9459 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9460 NeonGenOneOpFn
*genfn
;
9461 static NeonGenOneOpFn
* const fns
[2][2] = {
9462 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9463 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9466 genfn
= fns
[size
][u
];
9468 tcg_res
[pass
] = tcg_temp_new_i64();
9470 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9471 genfn(tcg_res
[pass
], tcg_op
);
9474 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9476 gen_helper_neon_addl_u16(tcg_res
[pass
],
9477 tcg_res
[pass
], tcg_op
);
9479 gen_helper_neon_addl_u32(tcg_res
[pass
],
9480 tcg_res
[pass
], tcg_op
);
9483 tcg_temp_free_i64(tcg_op
);
9487 tcg_res
[1] = tcg_const_i64(0);
9489 for (pass
= 0; pass
< 2; pass
++) {
9490 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9491 tcg_temp_free_i64(tcg_res
[pass
]);
9495 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9497 /* Implement SHLL and SHLL2 */
9499 int part
= is_q
? 2 : 0;
9500 TCGv_i64 tcg_res
[2];
9502 for (pass
= 0; pass
< 2; pass
++) {
9503 static NeonGenWidenFn
* const widenfns
[3] = {
9504 gen_helper_neon_widen_u8
,
9505 gen_helper_neon_widen_u16
,
9506 tcg_gen_extu_i32_i64
,
9508 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9509 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9511 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9512 tcg_res
[pass
] = tcg_temp_new_i64();
9513 widenfn(tcg_res
[pass
], tcg_op
);
9514 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9516 tcg_temp_free_i32(tcg_op
);
9519 for (pass
= 0; pass
< 2; pass
++) {
9520 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9521 tcg_temp_free_i64(tcg_res
[pass
]);
9525 /* C3.6.17 AdvSIMD two reg misc
9526 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9527 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9528 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9529 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9531 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9533 int size
= extract32(insn
, 22, 2);
9534 int opcode
= extract32(insn
, 12, 5);
9535 bool u
= extract32(insn
, 29, 1);
9536 bool is_q
= extract32(insn
, 30, 1);
9537 int rn
= extract32(insn
, 5, 5);
9538 int rd
= extract32(insn
, 0, 5);
9539 bool need_fpstatus
= false;
9540 bool need_rmode
= false;
9543 TCGv_ptr tcg_fpstatus
;
9546 case 0x0: /* REV64, REV32 */
9547 case 0x1: /* REV16 */
9548 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9550 case 0x5: /* CNT, NOT, RBIT */
9551 if (u
&& size
== 0) {
9552 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9555 } else if (u
&& size
== 1) {
9558 } else if (!u
&& size
== 0) {
9562 unallocated_encoding(s
);
9564 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9565 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9567 unallocated_encoding(s
);
9570 if (!fp_access_check(s
)) {
9574 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9576 case 0x4: /* CLS, CLZ */
9578 unallocated_encoding(s
);
9582 case 0x2: /* SADDLP, UADDLP */
9583 case 0x6: /* SADALP, UADALP */
9585 unallocated_encoding(s
);
9588 if (!fp_access_check(s
)) {
9591 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9593 case 0x13: /* SHLL, SHLL2 */
9594 if (u
== 0 || size
== 3) {
9595 unallocated_encoding(s
);
9598 if (!fp_access_check(s
)) {
9601 handle_shll(s
, is_q
, size
, rn
, rd
);
9603 case 0xa: /* CMLT */
9605 unallocated_encoding(s
);
9609 case 0x8: /* CMGT, CMGE */
9610 case 0x9: /* CMEQ, CMLE */
9611 case 0xb: /* ABS, NEG */
9612 if (size
== 3 && !is_q
) {
9613 unallocated_encoding(s
);
9617 case 0x3: /* SUQADD, USQADD */
9618 if (size
== 3 && !is_q
) {
9619 unallocated_encoding(s
);
9622 if (!fp_access_check(s
)) {
9625 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9627 case 0x7: /* SQABS, SQNEG */
9628 if (size
== 3 && !is_q
) {
9629 unallocated_encoding(s
);
9637 /* Floating point: U, size[1] and opcode indicate operation;
9638 * size[0] indicates single or double precision.
9640 int is_double
= extract32(size
, 0, 1);
9641 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9642 size
= is_double
? 3 : 2;
9644 case 0x2f: /* FABS */
9645 case 0x6f: /* FNEG */
9646 if (size
== 3 && !is_q
) {
9647 unallocated_encoding(s
);
9651 case 0x1d: /* SCVTF */
9652 case 0x5d: /* UCVTF */
9654 bool is_signed
= (opcode
== 0x1d) ? true : false;
9655 int elements
= is_double
? 2 : is_q
? 4 : 2;
9656 if (is_double
&& !is_q
) {
9657 unallocated_encoding(s
);
9660 if (!fp_access_check(s
)) {
9663 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9666 case 0x2c: /* FCMGT (zero) */
9667 case 0x2d: /* FCMEQ (zero) */
9668 case 0x2e: /* FCMLT (zero) */
9669 case 0x6c: /* FCMGE (zero) */
9670 case 0x6d: /* FCMLE (zero) */
9671 if (size
== 3 && !is_q
) {
9672 unallocated_encoding(s
);
9675 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9677 case 0x7f: /* FSQRT */
9678 if (size
== 3 && !is_q
) {
9679 unallocated_encoding(s
);
9683 case 0x1a: /* FCVTNS */
9684 case 0x1b: /* FCVTMS */
9685 case 0x3a: /* FCVTPS */
9686 case 0x3b: /* FCVTZS */
9687 case 0x5a: /* FCVTNU */
9688 case 0x5b: /* FCVTMU */
9689 case 0x7a: /* FCVTPU */
9690 case 0x7b: /* FCVTZU */
9691 need_fpstatus
= true;
9693 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9694 if (size
== 3 && !is_q
) {
9695 unallocated_encoding(s
);
9699 case 0x5c: /* FCVTAU */
9700 case 0x1c: /* FCVTAS */
9701 need_fpstatus
= true;
9703 rmode
= FPROUNDING_TIEAWAY
;
9704 if (size
== 3 && !is_q
) {
9705 unallocated_encoding(s
);
9709 case 0x3c: /* URECPE */
9711 unallocated_encoding(s
);
9715 case 0x3d: /* FRECPE */
9716 case 0x7d: /* FRSQRTE */
9717 if (size
== 3 && !is_q
) {
9718 unallocated_encoding(s
);
9721 if (!fp_access_check(s
)) {
9724 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9726 case 0x56: /* FCVTXN, FCVTXN2 */
9728 unallocated_encoding(s
);
9732 case 0x16: /* FCVTN, FCVTN2 */
9733 /* handle_2misc_narrow does a 2*size -> size operation, but these
9734 * instructions encode the source size rather than dest size.
9736 if (!fp_access_check(s
)) {
9739 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9741 case 0x17: /* FCVTL, FCVTL2 */
9742 if (!fp_access_check(s
)) {
9745 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9747 case 0x18: /* FRINTN */
9748 case 0x19: /* FRINTM */
9749 case 0x38: /* FRINTP */
9750 case 0x39: /* FRINTZ */
9752 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9754 case 0x59: /* FRINTX */
9755 case 0x79: /* FRINTI */
9756 need_fpstatus
= true;
9757 if (size
== 3 && !is_q
) {
9758 unallocated_encoding(s
);
9762 case 0x58: /* FRINTA */
9764 rmode
= FPROUNDING_TIEAWAY
;
9765 need_fpstatus
= true;
9766 if (size
== 3 && !is_q
) {
9767 unallocated_encoding(s
);
9771 case 0x7c: /* URSQRTE */
9773 unallocated_encoding(s
);
9776 need_fpstatus
= true;
9779 unallocated_encoding(s
);
9785 unallocated_encoding(s
);
9789 if (!fp_access_check(s
)) {
9793 if (need_fpstatus
) {
9794 tcg_fpstatus
= get_fpstatus_ptr();
9796 TCGV_UNUSED_PTR(tcg_fpstatus
);
9799 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9800 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9802 TCGV_UNUSED_I32(tcg_rmode
);
9806 /* All 64-bit element operations can be shared with scalar 2misc */
9809 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9810 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9811 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9813 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9815 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
9816 tcg_rmode
, tcg_fpstatus
);
9818 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9820 tcg_temp_free_i64(tcg_res
);
9821 tcg_temp_free_i64(tcg_op
);
9826 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9827 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9828 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9831 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9834 /* Special cases for 32 bit elements */
9836 case 0xa: /* CMLT */
9837 /* 32 bit integer comparison against zero, result is
9838 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9843 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
9844 tcg_gen_neg_i32(tcg_res
, tcg_res
);
9846 case 0x8: /* CMGT, CMGE */
9847 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9849 case 0x9: /* CMEQ, CMLE */
9850 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9854 gen_helper_clz32(tcg_res
, tcg_op
);
9856 gen_helper_cls32(tcg_res
, tcg_op
);
9859 case 0x7: /* SQABS, SQNEG */
9861 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
9863 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
9866 case 0xb: /* ABS, NEG */
9868 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9870 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9871 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9872 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
9873 tcg_zero
, tcg_op
, tcg_res
);
9874 tcg_temp_free_i32(tcg_zero
);
9877 case 0x2f: /* FABS */
9878 gen_helper_vfp_abss(tcg_res
, tcg_op
);
9880 case 0x6f: /* FNEG */
9881 gen_helper_vfp_negs(tcg_res
, tcg_op
);
9883 case 0x7f: /* FSQRT */
9884 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
9886 case 0x1a: /* FCVTNS */
9887 case 0x1b: /* FCVTMS */
9888 case 0x1c: /* FCVTAS */
9889 case 0x3a: /* FCVTPS */
9890 case 0x3b: /* FCVTZS */
9892 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9893 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
9894 tcg_shift
, tcg_fpstatus
);
9895 tcg_temp_free_i32(tcg_shift
);
9898 case 0x5a: /* FCVTNU */
9899 case 0x5b: /* FCVTMU */
9900 case 0x5c: /* FCVTAU */
9901 case 0x7a: /* FCVTPU */
9902 case 0x7b: /* FCVTZU */
9904 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9905 gen_helper_vfp_touls(tcg_res
, tcg_op
,
9906 tcg_shift
, tcg_fpstatus
);
9907 tcg_temp_free_i32(tcg_shift
);
9910 case 0x18: /* FRINTN */
9911 case 0x19: /* FRINTM */
9912 case 0x38: /* FRINTP */
9913 case 0x39: /* FRINTZ */
9914 case 0x58: /* FRINTA */
9915 case 0x79: /* FRINTI */
9916 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
9918 case 0x59: /* FRINTX */
9919 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
9921 case 0x7c: /* URSQRTE */
9922 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
9925 g_assert_not_reached();
9928 /* Use helpers for 8 and 16 bit elements */
9930 case 0x5: /* CNT, RBIT */
9931 /* For these two insns size is part of the opcode specifier
9932 * (handled earlier); they always operate on byte elements.
9935 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
9937 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
9940 case 0x7: /* SQABS, SQNEG */
9942 NeonGenOneOpEnvFn
*genfn
;
9943 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
9944 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9945 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9947 genfn
= fns
[size
][u
];
9948 genfn(tcg_res
, cpu_env
, tcg_op
);
9951 case 0x8: /* CMGT, CMGE */
9952 case 0x9: /* CMEQ, CMLE */
9953 case 0xa: /* CMLT */
9955 static NeonGenTwoOpFn
* const fns
[3][2] = {
9956 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
9957 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
9958 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
9960 NeonGenTwoOpFn
*genfn
;
9963 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9965 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
9966 comp
= (opcode
- 0x8) * 2 + u
;
9967 /* ...but LE, LT are implemented as reverse GE, GT */
9968 reverse
= (comp
> 2);
9972 genfn
= fns
[comp
][size
];
9974 genfn(tcg_res
, tcg_zero
, tcg_op
);
9976 genfn(tcg_res
, tcg_op
, tcg_zero
);
9978 tcg_temp_free_i32(tcg_zero
);
9981 case 0xb: /* ABS, NEG */
9983 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9985 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
9987 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
9989 tcg_temp_free_i32(tcg_zero
);
9992 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
9994 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
9998 case 0x4: /* CLS, CLZ */
10001 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10003 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10007 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10009 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10014 g_assert_not_reached();
10018 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10020 tcg_temp_free_i32(tcg_res
);
10021 tcg_temp_free_i32(tcg_op
);
10025 clear_vec_high(s
, rd
);
10029 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10030 tcg_temp_free_i32(tcg_rmode
);
10032 if (need_fpstatus
) {
10033 tcg_temp_free_ptr(tcg_fpstatus
);
10037 /* C3.6.13 AdvSIMD scalar x indexed element
10038 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10039 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10040 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10041 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10042 * C3.6.18 AdvSIMD vector x indexed element
10043 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10044 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10045 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10046 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10048 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10050 /* This encoding has two kinds of instruction:
10051 * normal, where we perform elt x idxelt => elt for each
10052 * element in the vector
10053 * long, where we perform elt x idxelt and generate a result of
10054 * double the width of the input element
10055 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10057 bool is_scalar
= extract32(insn
, 28, 1);
10058 bool is_q
= extract32(insn
, 30, 1);
10059 bool u
= extract32(insn
, 29, 1);
10060 int size
= extract32(insn
, 22, 2);
10061 int l
= extract32(insn
, 21, 1);
10062 int m
= extract32(insn
, 20, 1);
10063 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10064 int rm
= extract32(insn
, 16, 4);
10065 int opcode
= extract32(insn
, 12, 4);
10066 int h
= extract32(insn
, 11, 1);
10067 int rn
= extract32(insn
, 5, 5);
10068 int rd
= extract32(insn
, 0, 5);
10069 bool is_long
= false;
10070 bool is_fp
= false;
10075 case 0x0: /* MLA */
10076 case 0x4: /* MLS */
10077 if (!u
|| is_scalar
) {
10078 unallocated_encoding(s
);
10082 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10083 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10084 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10086 unallocated_encoding(s
);
10091 case 0x3: /* SQDMLAL, SQDMLAL2 */
10092 case 0x7: /* SQDMLSL, SQDMLSL2 */
10093 case 0xb: /* SQDMULL, SQDMULL2 */
10096 case 0xc: /* SQDMULH */
10097 case 0xd: /* SQRDMULH */
10099 unallocated_encoding(s
);
10103 case 0x8: /* MUL */
10104 if (u
|| is_scalar
) {
10105 unallocated_encoding(s
);
10109 case 0x1: /* FMLA */
10110 case 0x5: /* FMLS */
10112 unallocated_encoding(s
);
10116 case 0x9: /* FMUL, FMULX */
10117 if (!extract32(size
, 1, 1)) {
10118 unallocated_encoding(s
);
10124 unallocated_encoding(s
);
10129 /* low bit of size indicates single/double */
10130 size
= extract32(size
, 0, 1) ? 3 : 2;
10132 index
= h
<< 1 | l
;
10135 unallocated_encoding(s
);
10144 index
= h
<< 2 | l
<< 1 | m
;
10147 index
= h
<< 1 | l
;
10151 unallocated_encoding(s
);
10156 if (!fp_access_check(s
)) {
10161 fpst
= get_fpstatus_ptr();
10163 TCGV_UNUSED_PTR(fpst
);
10167 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10170 assert(is_fp
&& is_q
&& !is_long
);
10172 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10174 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10175 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10176 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10178 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10181 case 0x5: /* FMLS */
10182 /* As usual for ARM, separate negation for fused multiply-add */
10183 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10185 case 0x1: /* FMLA */
10186 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10187 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10189 case 0x9: /* FMUL, FMULX */
10191 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10193 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10197 g_assert_not_reached();
10200 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10201 tcg_temp_free_i64(tcg_op
);
10202 tcg_temp_free_i64(tcg_res
);
10206 clear_vec_high(s
, rd
);
10209 tcg_temp_free_i64(tcg_idx
);
10210 } else if (!is_long
) {
10211 /* 32 bit floating point, or 16 or 32 bit integer.
10212 * For the 16 bit scalar case we use the usual Neon helpers and
10213 * rely on the fact that 0 op 0 == 0 with no side effects.
10215 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10216 int pass
, maxpasses
;
10221 maxpasses
= is_q
? 4 : 2;
10224 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10226 if (size
== 1 && !is_scalar
) {
10227 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10228 * the index into both halves of the 32 bit tcg_idx and then use
10229 * the usual Neon helpers.
10231 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10234 for (pass
= 0; pass
< maxpasses
; pass
++) {
10235 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10236 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10238 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10241 case 0x0: /* MLA */
10242 case 0x4: /* MLS */
10243 case 0x8: /* MUL */
10245 static NeonGenTwoOpFn
* const fns
[2][2] = {
10246 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10247 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10249 NeonGenTwoOpFn
*genfn
;
10250 bool is_sub
= opcode
== 0x4;
10253 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10255 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10257 if (opcode
== 0x8) {
10260 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10261 genfn
= fns
[size
- 1][is_sub
];
10262 genfn(tcg_res
, tcg_op
, tcg_res
);
10265 case 0x5: /* FMLS */
10266 /* As usual for ARM, separate negation for fused multiply-add */
10267 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10269 case 0x1: /* FMLA */
10270 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10271 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10273 case 0x9: /* FMUL, FMULX */
10275 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10277 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10280 case 0xc: /* SQDMULH */
10282 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10285 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10289 case 0xd: /* SQRDMULH */
10291 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10294 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10299 g_assert_not_reached();
10303 write_fp_sreg(s
, rd
, tcg_res
);
10305 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10308 tcg_temp_free_i32(tcg_op
);
10309 tcg_temp_free_i32(tcg_res
);
10312 tcg_temp_free_i32(tcg_idx
);
10315 clear_vec_high(s
, rd
);
10318 /* long ops: 16x16->32 or 32x32->64 */
10319 TCGv_i64 tcg_res
[2];
10321 bool satop
= extract32(opcode
, 0, 1);
10322 TCGMemOp memop
= MO_32
;
10329 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10331 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10333 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10334 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10335 TCGv_i64 tcg_passres
;
10341 passelt
= pass
+ (is_q
* 2);
10344 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10346 tcg_res
[pass
] = tcg_temp_new_i64();
10348 if (opcode
== 0xa || opcode
== 0xb) {
10349 /* Non-accumulating ops */
10350 tcg_passres
= tcg_res
[pass
];
10352 tcg_passres
= tcg_temp_new_i64();
10355 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10356 tcg_temp_free_i64(tcg_op
);
10359 /* saturating, doubling */
10360 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10361 tcg_passres
, tcg_passres
);
10364 if (opcode
== 0xa || opcode
== 0xb) {
10368 /* Accumulating op: handle accumulate step */
10369 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10372 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10373 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10375 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10376 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10378 case 0x7: /* SQDMLSL, SQDMLSL2 */
10379 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10381 case 0x3: /* SQDMLAL, SQDMLAL2 */
10382 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10387 g_assert_not_reached();
10389 tcg_temp_free_i64(tcg_passres
);
10391 tcg_temp_free_i64(tcg_idx
);
10394 clear_vec_high(s
, rd
);
10397 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10400 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10403 /* The simplest way to handle the 16x16 indexed ops is to
10404 * duplicate the index into both halves of the 32 bit tcg_idx
10405 * and then use the usual Neon helpers.
10407 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10410 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10411 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10412 TCGv_i64 tcg_passres
;
10415 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10417 read_vec_element_i32(s
, tcg_op
, rn
,
10418 pass
+ (is_q
* 2), MO_32
);
10421 tcg_res
[pass
] = tcg_temp_new_i64();
10423 if (opcode
== 0xa || opcode
== 0xb) {
10424 /* Non-accumulating ops */
10425 tcg_passres
= tcg_res
[pass
];
10427 tcg_passres
= tcg_temp_new_i64();
10430 if (memop
& MO_SIGN
) {
10431 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10433 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10436 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10437 tcg_passres
, tcg_passres
);
10439 tcg_temp_free_i32(tcg_op
);
10441 if (opcode
== 0xa || opcode
== 0xb) {
10445 /* Accumulating op: handle accumulate step */
10446 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10449 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10450 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10453 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10454 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10457 case 0x7: /* SQDMLSL, SQDMLSL2 */
10458 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10460 case 0x3: /* SQDMLAL, SQDMLAL2 */
10461 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10466 g_assert_not_reached();
10468 tcg_temp_free_i64(tcg_passres
);
10470 tcg_temp_free_i32(tcg_idx
);
10473 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10478 tcg_res
[1] = tcg_const_i64(0);
10481 for (pass
= 0; pass
< 2; pass
++) {
10482 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10483 tcg_temp_free_i64(tcg_res
[pass
]);
10487 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10488 tcg_temp_free_ptr(fpst
);
10492 /* C3.6.19 Crypto AES
10493 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10494 * +-----------------+------+-----------+--------+-----+------+------+
10495 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10496 * +-----------------+------+-----------+--------+-----+------+------+
10498 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10500 unsupported_encoding(s
, insn
);
10503 /* C3.6.20 Crypto three-reg SHA
10504 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10505 * +-----------------+------+---+------+---+--------+-----+------+------+
10506 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10507 * +-----------------+------+---+------+---+--------+-----+------+------+
10509 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10511 unsupported_encoding(s
, insn
);
10514 /* C3.6.21 Crypto two-reg SHA
10515 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10516 * +-----------------+------+-----------+--------+-----+------+------+
10517 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10518 * +-----------------+------+-----------+--------+-----+------+------+
10520 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10522 unsupported_encoding(s
, insn
);
10525 /* C3.6 Data processing - SIMD, inc Crypto
10527 * As the decode gets a little complex we are using a table based
10528 * approach for this part of the decode.
10530 static const AArch64DecodeTable data_proc_simd
[] = {
10531 /* pattern , mask , fn */
10532 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10533 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10534 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10535 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10536 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10537 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10538 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10539 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10540 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10541 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10542 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10543 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10544 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10545 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10546 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10547 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10548 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10549 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10550 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10551 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10552 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10553 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10554 { 0x00000000, 0x00000000, NULL
}
10557 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10559 /* Note that this is called with all non-FP cases from
10560 * table C3-6 so it must UNDEF for entries not specifically
10561 * allocated to instructions in that table.
10563 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10567 unallocated_encoding(s
);
10571 /* C3.6 Data processing - SIMD and floating point */
10572 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10574 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10575 disas_data_proc_fp(s
, insn
);
10577 /* SIMD, including crypto */
10578 disas_data_proc_simd(s
, insn
);
10582 /* C3.1 A64 instruction index by encoding */
10583 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10587 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10591 s
->fp_access_checked
= false;
10593 switch (extract32(insn
, 25, 4)) {
10594 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10595 unallocated_encoding(s
);
10597 case 0x8: case 0x9: /* Data processing - immediate */
10598 disas_data_proc_imm(s
, insn
);
10600 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10601 disas_b_exc_sys(s
, insn
);
10606 case 0xe: /* Loads and stores */
10607 disas_ldst(s
, insn
);
10610 case 0xd: /* Data processing - register */
10611 disas_data_proc_reg(s
, insn
);
10614 case 0xf: /* Data processing - SIMD and floating point */
10615 disas_data_proc_simd_fp(s
, insn
);
10618 assert(FALSE
); /* all 15 cases should be handled above */
10622 /* if we allocated any temporaries, free them here */
10626 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
10627 TranslationBlock
*tb
,
10630 CPUState
*cs
= CPU(cpu
);
10631 CPUARMState
*env
= &cpu
->env
;
10632 DisasContext dc1
, *dc
= &dc1
;
10634 uint16_t *gen_opc_end
;
10636 target_ulong pc_start
;
10637 target_ulong next_page_start
;
10645 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
10647 dc
->is_jmp
= DISAS_NEXT
;
10649 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
10654 dc
->bswap_code
= 0;
10655 dc
->condexec_mask
= 0;
10656 dc
->condexec_cond
= 0;
10657 #if !defined(CONFIG_USER_ONLY)
10658 dc
->user
= (ARM_TBFLAG_AA64_EL(tb
->flags
) == 0);
10660 dc
->cpacr_fpen
= ARM_TBFLAG_AA64_FPEN(tb
->flags
);
10662 dc
->vec_stride
= 0;
10663 dc
->cp_regs
= cpu
->cp_regs
;
10664 dc
->current_pl
= arm_current_pl(env
);
10665 dc
->features
= env
->features
;
10667 init_tmp_a64_array(dc
);
10669 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
10672 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10673 if (max_insns
== 0) {
10674 max_insns
= CF_COUNT_MASK
;
10679 tcg_clear_temp_count();
10682 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
10683 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
10684 if (bp
->pc
== dc
->pc
) {
10685 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
10686 /* Advance PC so that clearing the breakpoint will
10687 invalidate this TB. */
10689 goto done_generating
;
10695 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10699 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10702 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
10703 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
10704 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
10707 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
10711 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
10712 tcg_gen_debug_insn_start(dc
->pc
);
10715 disas_a64_insn(env
, dc
);
10717 if (tcg_check_temp_count()) {
10718 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
10722 /* Translation stops when a conditional branch is encountered.
10723 * Otherwise the subsequent code could get translated several times.
10724 * Also stop translation when a page boundary is reached. This
10725 * ensures prefetch aborts occur at the right place.
10728 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
10729 !cs
->singlestep_enabled
&&
10731 dc
->pc
< next_page_start
&&
10732 num_insns
< max_insns
);
10734 if (tb
->cflags
& CF_LAST_IO
) {
10738 if (unlikely(cs
->singlestep_enabled
) && dc
->is_jmp
!= DISAS_EXC
) {
10739 /* Note that this means single stepping WFI doesn't halt the CPU.
10740 * For conditional branch insns this is harmless unreachable code as
10741 * gen_goto_tb() has already handled emitting the debug exception
10742 * (and thus a tb-jump is not possible when singlestepping).
10744 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
10745 if (dc
->is_jmp
!= DISAS_JUMP
) {
10746 gen_a64_set_pc_im(dc
->pc
);
10748 gen_exception_internal(EXCP_DEBUG
);
10750 switch (dc
->is_jmp
) {
10752 gen_goto_tb(dc
, 1, dc
->pc
);
10756 gen_a64_set_pc_im(dc
->pc
);
10759 /* indicate that the hash table must be used to find the next TB */
10760 tcg_gen_exit_tb(0);
10762 case DISAS_TB_JUMP
:
10767 gen_a64_set_pc_im(dc
->pc
);
10768 gen_helper_wfe(cpu_env
);
10771 /* This is a special case because we don't want to just halt the CPU
10772 * if trying to debug across a WFI.
10774 gen_a64_set_pc_im(dc
->pc
);
10775 gen_helper_wfi(cpu_env
);
10781 gen_tb_end(tb
, num_insns
);
10782 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
10785 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
10786 qemu_log("----------------\n");
10787 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
10788 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
10789 4 | (dc
->bswap_code
<< 1));
10794 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10797 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10800 tb
->size
= dc
->pc
- pc_start
;
10801 tb
->icount
= num_insns
;