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target-arm: fix decoding of Neon 64 bit shifts.
[mirror_qemu.git] / target-arm / translate.c
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <stdarg.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <string.h>
25 #include <inttypes.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "qemu-log.h"
32
33 #include "helpers.h"
34 #define GEN_HELPER 1
35 #include "helpers.h"
36
37 #define ENABLE_ARCH_5J 0
38 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
42
43 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
44
45 /* internal defines */
46 typedef struct DisasContext {
47 target_ulong pc;
48 int is_jmp;
49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
56 struct TranslationBlock *tb;
57 int singlestep_enabled;
58 int thumb;
59 #if !defined(CONFIG_USER_ONLY)
60 int user;
61 #endif
62 int vfp_enabled;
63 int vec_len;
64 int vec_stride;
65 } DisasContext;
66
67 static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
68
69 #if defined(CONFIG_USER_ONLY)
70 #define IS_USER(s) 1
71 #else
72 #define IS_USER(s) (s->user)
73 #endif
74
75 /* These instructions trap after executing, so defer them until after the
76 conditional executions state has been updated. */
77 #define DISAS_WFI 4
78 #define DISAS_SWI 5
79
80 static TCGv_ptr cpu_env;
81 /* We reuse the same 64-bit temporaries for efficiency. */
82 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
83 static TCGv_i32 cpu_R[16];
84 static TCGv_i32 cpu_exclusive_addr;
85 static TCGv_i32 cpu_exclusive_val;
86 static TCGv_i32 cpu_exclusive_high;
87 #ifdef CONFIG_USER_ONLY
88 static TCGv_i32 cpu_exclusive_test;
89 static TCGv_i32 cpu_exclusive_info;
90 #endif
91
92 /* FIXME: These should be removed. */
93 static TCGv cpu_F0s, cpu_F1s;
94 static TCGv_i64 cpu_F0d, cpu_F1d;
95
96 #include "gen-icount.h"
97
98 static const char *regnames[] =
99 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
101
102 /* initialize TCG globals. */
103 void arm_translate_init(void)
104 {
105 int i;
106
107 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
108
109 for (i = 0; i < 16; i++) {
110 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, regs[i]),
112 regnames[i]);
113 }
114 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, exclusive_addr), "exclusive_addr");
116 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_val), "exclusive_val");
118 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_high), "exclusive_high");
120 #ifdef CONFIG_USER_ONLY
121 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, exclusive_test), "exclusive_test");
123 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
124 offsetof(CPUState, exclusive_info), "exclusive_info");
125 #endif
126
127 #define GEN_HELPER 2
128 #include "helpers.h"
129 }
130
131 static int num_temps;
132
133 /* Allocate a temporary variable. */
134 static TCGv_i32 new_tmp(void)
135 {
136 num_temps++;
137 return tcg_temp_new_i32();
138 }
139
140 /* Release a temporary variable. */
141 static void dead_tmp(TCGv tmp)
142 {
143 tcg_temp_free(tmp);
144 num_temps--;
145 }
146
147 static inline TCGv load_cpu_offset(int offset)
148 {
149 TCGv tmp = new_tmp();
150 tcg_gen_ld_i32(tmp, cpu_env, offset);
151 return tmp;
152 }
153
154 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
155
156 static inline void store_cpu_offset(TCGv var, int offset)
157 {
158 tcg_gen_st_i32(var, cpu_env, offset);
159 dead_tmp(var);
160 }
161
162 #define store_cpu_field(var, name) \
163 store_cpu_offset(var, offsetof(CPUState, name))
164
165 /* Set a variable to the value of a CPU register. */
166 static void load_reg_var(DisasContext *s, TCGv var, int reg)
167 {
168 if (reg == 15) {
169 uint32_t addr;
170 /* normaly, since we updated PC, we need only to add one insn */
171 if (s->thumb)
172 addr = (long)s->pc + 2;
173 else
174 addr = (long)s->pc + 4;
175 tcg_gen_movi_i32(var, addr);
176 } else {
177 tcg_gen_mov_i32(var, cpu_R[reg]);
178 }
179 }
180
181 /* Create a new temporary and set it to the value of a CPU register. */
182 static inline TCGv load_reg(DisasContext *s, int reg)
183 {
184 TCGv tmp = new_tmp();
185 load_reg_var(s, tmp, reg);
186 return tmp;
187 }
188
189 /* Set a CPU register. The source must be a temporary and will be
190 marked as dead. */
191 static void store_reg(DisasContext *s, int reg, TCGv var)
192 {
193 if (reg == 15) {
194 tcg_gen_andi_i32(var, var, ~1);
195 s->is_jmp = DISAS_JUMP;
196 }
197 tcg_gen_mov_i32(cpu_R[reg], var);
198 dead_tmp(var);
199 }
200
201 /* Value extensions. */
202 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
203 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
204 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
205 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
206
207 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
208 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
209
210
211 static inline void gen_set_cpsr(TCGv var, uint32_t mask)
212 {
213 TCGv tmp_mask = tcg_const_i32(mask);
214 gen_helper_cpsr_write(var, tmp_mask);
215 tcg_temp_free_i32(tmp_mask);
216 }
217 /* Set NZCV flags from the high 4 bits of var. */
218 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
219
220 static void gen_exception(int excp)
221 {
222 TCGv tmp = new_tmp();
223 tcg_gen_movi_i32(tmp, excp);
224 gen_helper_exception(tmp);
225 dead_tmp(tmp);
226 }
227
228 static void gen_smul_dual(TCGv a, TCGv b)
229 {
230 TCGv tmp1 = new_tmp();
231 TCGv tmp2 = new_tmp();
232 tcg_gen_ext16s_i32(tmp1, a);
233 tcg_gen_ext16s_i32(tmp2, b);
234 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
235 dead_tmp(tmp2);
236 tcg_gen_sari_i32(a, a, 16);
237 tcg_gen_sari_i32(b, b, 16);
238 tcg_gen_mul_i32(b, b, a);
239 tcg_gen_mov_i32(a, tmp1);
240 dead_tmp(tmp1);
241 }
242
243 /* Byteswap each halfword. */
244 static void gen_rev16(TCGv var)
245 {
246 TCGv tmp = new_tmp();
247 tcg_gen_shri_i32(tmp, var, 8);
248 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
249 tcg_gen_shli_i32(var, var, 8);
250 tcg_gen_andi_i32(var, var, 0xff00ff00);
251 tcg_gen_or_i32(var, var, tmp);
252 dead_tmp(tmp);
253 }
254
255 /* Byteswap low halfword and sign extend. */
256 static void gen_revsh(TCGv var)
257 {
258 tcg_gen_ext16u_i32(var, var);
259 tcg_gen_bswap16_i32(var, var);
260 tcg_gen_ext16s_i32(var, var);
261 }
262
263 /* Unsigned bitfield extract. */
264 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
265 {
266 if (shift)
267 tcg_gen_shri_i32(var, var, shift);
268 tcg_gen_andi_i32(var, var, mask);
269 }
270
271 /* Signed bitfield extract. */
272 static void gen_sbfx(TCGv var, int shift, int width)
273 {
274 uint32_t signbit;
275
276 if (shift)
277 tcg_gen_sari_i32(var, var, shift);
278 if (shift + width < 32) {
279 signbit = 1u << (width - 1);
280 tcg_gen_andi_i32(var, var, (1u << width) - 1);
281 tcg_gen_xori_i32(var, var, signbit);
282 tcg_gen_subi_i32(var, var, signbit);
283 }
284 }
285
286 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
287 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
288 {
289 tcg_gen_andi_i32(val, val, mask);
290 tcg_gen_shli_i32(val, val, shift);
291 tcg_gen_andi_i32(base, base, ~(mask << shift));
292 tcg_gen_or_i32(dest, base, val);
293 }
294
295 /* Return (b << 32) + a. Mark inputs as dead */
296 static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
297 {
298 TCGv_i64 tmp64 = tcg_temp_new_i64();
299
300 tcg_gen_extu_i32_i64(tmp64, b);
301 dead_tmp(b);
302 tcg_gen_shli_i64(tmp64, tmp64, 32);
303 tcg_gen_add_i64(a, tmp64, a);
304
305 tcg_temp_free_i64(tmp64);
306 return a;
307 }
308
309 /* Return (b << 32) - a. Mark inputs as dead. */
310 static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
311 {
312 TCGv_i64 tmp64 = tcg_temp_new_i64();
313
314 tcg_gen_extu_i32_i64(tmp64, b);
315 dead_tmp(b);
316 tcg_gen_shli_i64(tmp64, tmp64, 32);
317 tcg_gen_sub_i64(a, tmp64, a);
318
319 tcg_temp_free_i64(tmp64);
320 return a;
321 }
322
323 /* FIXME: Most targets have native widening multiplication.
324 It would be good to use that instead of a full wide multiply. */
325 /* 32x32->64 multiply. Marks inputs as dead. */
326 static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
327 {
328 TCGv_i64 tmp1 = tcg_temp_new_i64();
329 TCGv_i64 tmp2 = tcg_temp_new_i64();
330
331 tcg_gen_extu_i32_i64(tmp1, a);
332 dead_tmp(a);
333 tcg_gen_extu_i32_i64(tmp2, b);
334 dead_tmp(b);
335 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
336 tcg_temp_free_i64(tmp2);
337 return tmp1;
338 }
339
340 static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
341 {
342 TCGv_i64 tmp1 = tcg_temp_new_i64();
343 TCGv_i64 tmp2 = tcg_temp_new_i64();
344
345 tcg_gen_ext_i32_i64(tmp1, a);
346 dead_tmp(a);
347 tcg_gen_ext_i32_i64(tmp2, b);
348 dead_tmp(b);
349 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
350 tcg_temp_free_i64(tmp2);
351 return tmp1;
352 }
353
354 /* Swap low and high halfwords. */
355 static void gen_swap_half(TCGv var)
356 {
357 TCGv tmp = new_tmp();
358 tcg_gen_shri_i32(tmp, var, 16);
359 tcg_gen_shli_i32(var, var, 16);
360 tcg_gen_or_i32(var, var, tmp);
361 dead_tmp(tmp);
362 }
363
364 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
365 tmp = (t0 ^ t1) & 0x8000;
366 t0 &= ~0x8000;
367 t1 &= ~0x8000;
368 t0 = (t0 + t1) ^ tmp;
369 */
370
371 static void gen_add16(TCGv t0, TCGv t1)
372 {
373 TCGv tmp = new_tmp();
374 tcg_gen_xor_i32(tmp, t0, t1);
375 tcg_gen_andi_i32(tmp, tmp, 0x8000);
376 tcg_gen_andi_i32(t0, t0, ~0x8000);
377 tcg_gen_andi_i32(t1, t1, ~0x8000);
378 tcg_gen_add_i32(t0, t0, t1);
379 tcg_gen_xor_i32(t0, t0, tmp);
380 dead_tmp(tmp);
381 dead_tmp(t1);
382 }
383
384 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
385
386 /* Set CF to the top bit of var. */
387 static void gen_set_CF_bit31(TCGv var)
388 {
389 TCGv tmp = new_tmp();
390 tcg_gen_shri_i32(tmp, var, 31);
391 gen_set_CF(tmp);
392 dead_tmp(tmp);
393 }
394
395 /* Set N and Z flags from var. */
396 static inline void gen_logic_CC(TCGv var)
397 {
398 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
399 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
400 }
401
402 /* T0 += T1 + CF. */
403 static void gen_adc(TCGv t0, TCGv t1)
404 {
405 TCGv tmp;
406 tcg_gen_add_i32(t0, t0, t1);
407 tmp = load_cpu_field(CF);
408 tcg_gen_add_i32(t0, t0, tmp);
409 dead_tmp(tmp);
410 }
411
412 /* dest = T0 + T1 + CF. */
413 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
414 {
415 TCGv tmp;
416 tcg_gen_add_i32(dest, t0, t1);
417 tmp = load_cpu_field(CF);
418 tcg_gen_add_i32(dest, dest, tmp);
419 dead_tmp(tmp);
420 }
421
422 /* dest = T0 - T1 + CF - 1. */
423 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
424 {
425 TCGv tmp;
426 tcg_gen_sub_i32(dest, t0, t1);
427 tmp = load_cpu_field(CF);
428 tcg_gen_add_i32(dest, dest, tmp);
429 tcg_gen_subi_i32(dest, dest, 1);
430 dead_tmp(tmp);
431 }
432
433 /* FIXME: Implement this natively. */
434 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
435
436 static void shifter_out_im(TCGv var, int shift)
437 {
438 TCGv tmp = new_tmp();
439 if (shift == 0) {
440 tcg_gen_andi_i32(tmp, var, 1);
441 } else {
442 tcg_gen_shri_i32(tmp, var, shift);
443 if (shift != 31)
444 tcg_gen_andi_i32(tmp, tmp, 1);
445 }
446 gen_set_CF(tmp);
447 dead_tmp(tmp);
448 }
449
450 /* Shift by immediate. Includes special handling for shift == 0. */
451 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
452 {
453 switch (shiftop) {
454 case 0: /* LSL */
455 if (shift != 0) {
456 if (flags)
457 shifter_out_im(var, 32 - shift);
458 tcg_gen_shli_i32(var, var, shift);
459 }
460 break;
461 case 1: /* LSR */
462 if (shift == 0) {
463 if (flags) {
464 tcg_gen_shri_i32(var, var, 31);
465 gen_set_CF(var);
466 }
467 tcg_gen_movi_i32(var, 0);
468 } else {
469 if (flags)
470 shifter_out_im(var, shift - 1);
471 tcg_gen_shri_i32(var, var, shift);
472 }
473 break;
474 case 2: /* ASR */
475 if (shift == 0)
476 shift = 32;
477 if (flags)
478 shifter_out_im(var, shift - 1);
479 if (shift == 32)
480 shift = 31;
481 tcg_gen_sari_i32(var, var, shift);
482 break;
483 case 3: /* ROR/RRX */
484 if (shift != 0) {
485 if (flags)
486 shifter_out_im(var, shift - 1);
487 tcg_gen_rotri_i32(var, var, shift); break;
488 } else {
489 TCGv tmp = load_cpu_field(CF);
490 if (flags)
491 shifter_out_im(var, 0);
492 tcg_gen_shri_i32(var, var, 1);
493 tcg_gen_shli_i32(tmp, tmp, 31);
494 tcg_gen_or_i32(var, var, tmp);
495 dead_tmp(tmp);
496 }
497 }
498 };
499
500 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
501 TCGv shift, int flags)
502 {
503 if (flags) {
504 switch (shiftop) {
505 case 0: gen_helper_shl_cc(var, var, shift); break;
506 case 1: gen_helper_shr_cc(var, var, shift); break;
507 case 2: gen_helper_sar_cc(var, var, shift); break;
508 case 3: gen_helper_ror_cc(var, var, shift); break;
509 }
510 } else {
511 switch (shiftop) {
512 case 0: gen_helper_shl(var, var, shift); break;
513 case 1: gen_helper_shr(var, var, shift); break;
514 case 2: gen_helper_sar(var, var, shift); break;
515 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
516 tcg_gen_rotr_i32(var, var, shift); break;
517 }
518 }
519 dead_tmp(shift);
520 }
521
522 #define PAS_OP(pfx) \
523 switch (op2) { \
524 case 0: gen_pas_helper(glue(pfx,add16)); break; \
525 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
526 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
527 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
528 case 4: gen_pas_helper(glue(pfx,add8)); break; \
529 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
530 }
531 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
532 {
533 TCGv_ptr tmp;
534
535 switch (op1) {
536 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
537 case 1:
538 tmp = tcg_temp_new_ptr();
539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(s)
541 tcg_temp_free_ptr(tmp);
542 break;
543 case 5:
544 tmp = tcg_temp_new_ptr();
545 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
546 PAS_OP(u)
547 tcg_temp_free_ptr(tmp);
548 break;
549 #undef gen_pas_helper
550 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
551 case 2:
552 PAS_OP(q);
553 break;
554 case 3:
555 PAS_OP(sh);
556 break;
557 case 6:
558 PAS_OP(uq);
559 break;
560 case 7:
561 PAS_OP(uh);
562 break;
563 #undef gen_pas_helper
564 }
565 }
566 #undef PAS_OP
567
568 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
569 #define PAS_OP(pfx) \
570 switch (op1) { \
571 case 0: gen_pas_helper(glue(pfx,add8)); break; \
572 case 1: gen_pas_helper(glue(pfx,add16)); break; \
573 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
574 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
575 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
576 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
577 }
578 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
579 {
580 TCGv_ptr tmp;
581
582 switch (op2) {
583 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
584 case 0:
585 tmp = tcg_temp_new_ptr();
586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(s)
588 tcg_temp_free_ptr(tmp);
589 break;
590 case 4:
591 tmp = tcg_temp_new_ptr();
592 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
593 PAS_OP(u)
594 tcg_temp_free_ptr(tmp);
595 break;
596 #undef gen_pas_helper
597 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 case 1:
599 PAS_OP(q);
600 break;
601 case 2:
602 PAS_OP(sh);
603 break;
604 case 5:
605 PAS_OP(uq);
606 break;
607 case 6:
608 PAS_OP(uh);
609 break;
610 #undef gen_pas_helper
611 }
612 }
613 #undef PAS_OP
614
615 static void gen_test_cc(int cc, int label)
616 {
617 TCGv tmp;
618 TCGv tmp2;
619 int inv;
620
621 switch (cc) {
622 case 0: /* eq: Z */
623 tmp = load_cpu_field(ZF);
624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
625 break;
626 case 1: /* ne: !Z */
627 tmp = load_cpu_field(ZF);
628 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
629 break;
630 case 2: /* cs: C */
631 tmp = load_cpu_field(CF);
632 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
633 break;
634 case 3: /* cc: !C */
635 tmp = load_cpu_field(CF);
636 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
637 break;
638 case 4: /* mi: N */
639 tmp = load_cpu_field(NF);
640 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
641 break;
642 case 5: /* pl: !N */
643 tmp = load_cpu_field(NF);
644 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
645 break;
646 case 6: /* vs: V */
647 tmp = load_cpu_field(VF);
648 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
649 break;
650 case 7: /* vc: !V */
651 tmp = load_cpu_field(VF);
652 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
653 break;
654 case 8: /* hi: C && !Z */
655 inv = gen_new_label();
656 tmp = load_cpu_field(CF);
657 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
658 dead_tmp(tmp);
659 tmp = load_cpu_field(ZF);
660 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
661 gen_set_label(inv);
662 break;
663 case 9: /* ls: !C || Z */
664 tmp = load_cpu_field(CF);
665 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
666 dead_tmp(tmp);
667 tmp = load_cpu_field(ZF);
668 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
669 break;
670 case 10: /* ge: N == V -> N ^ V == 0 */
671 tmp = load_cpu_field(VF);
672 tmp2 = load_cpu_field(NF);
673 tcg_gen_xor_i32(tmp, tmp, tmp2);
674 dead_tmp(tmp2);
675 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
676 break;
677 case 11: /* lt: N != V -> N ^ V != 0 */
678 tmp = load_cpu_field(VF);
679 tmp2 = load_cpu_field(NF);
680 tcg_gen_xor_i32(tmp, tmp, tmp2);
681 dead_tmp(tmp2);
682 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
683 break;
684 case 12: /* gt: !Z && N == V */
685 inv = gen_new_label();
686 tmp = load_cpu_field(ZF);
687 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
688 dead_tmp(tmp);
689 tmp = load_cpu_field(VF);
690 tmp2 = load_cpu_field(NF);
691 tcg_gen_xor_i32(tmp, tmp, tmp2);
692 dead_tmp(tmp2);
693 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
694 gen_set_label(inv);
695 break;
696 case 13: /* le: Z || N != V */
697 tmp = load_cpu_field(ZF);
698 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
699 dead_tmp(tmp);
700 tmp = load_cpu_field(VF);
701 tmp2 = load_cpu_field(NF);
702 tcg_gen_xor_i32(tmp, tmp, tmp2);
703 dead_tmp(tmp2);
704 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
705 break;
706 default:
707 fprintf(stderr, "Bad condition code 0x%x\n", cc);
708 abort();
709 }
710 dead_tmp(tmp);
711 }
712
713 static const uint8_t table_logic_cc[16] = {
714 1, /* and */
715 1, /* xor */
716 0, /* sub */
717 0, /* rsb */
718 0, /* add */
719 0, /* adc */
720 0, /* sbc */
721 0, /* rsc */
722 1, /* andl */
723 1, /* xorl */
724 0, /* cmp */
725 0, /* cmn */
726 1, /* orr */
727 1, /* mov */
728 1, /* bic */
729 1, /* mvn */
730 };
731
732 /* Set PC and Thumb state from an immediate address. */
733 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
734 {
735 TCGv tmp;
736
737 s->is_jmp = DISAS_UPDATE;
738 if (s->thumb != (addr & 1)) {
739 tmp = new_tmp();
740 tcg_gen_movi_i32(tmp, addr & 1);
741 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
742 dead_tmp(tmp);
743 }
744 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
745 }
746
747 /* Set PC and Thumb state from var. var is marked as dead. */
748 static inline void gen_bx(DisasContext *s, TCGv var)
749 {
750 s->is_jmp = DISAS_UPDATE;
751 tcg_gen_andi_i32(cpu_R[15], var, ~1);
752 tcg_gen_andi_i32(var, var, 1);
753 store_cpu_field(var, thumb);
754 }
755
756 /* Variant of store_reg which uses branch&exchange logic when storing
757 to r15 in ARM architecture v7 and above. The source must be a temporary
758 and will be marked as dead. */
759 static inline void store_reg_bx(CPUState *env, DisasContext *s,
760 int reg, TCGv var)
761 {
762 if (reg == 15 && ENABLE_ARCH_7) {
763 gen_bx(s, var);
764 } else {
765 store_reg(s, reg, var);
766 }
767 }
768
769 static inline TCGv gen_ld8s(TCGv addr, int index)
770 {
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8s(tmp, addr, index);
773 return tmp;
774 }
775 static inline TCGv gen_ld8u(TCGv addr, int index)
776 {
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld8u(tmp, addr, index);
779 return tmp;
780 }
781 static inline TCGv gen_ld16s(TCGv addr, int index)
782 {
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16s(tmp, addr, index);
785 return tmp;
786 }
787 static inline TCGv gen_ld16u(TCGv addr, int index)
788 {
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld16u(tmp, addr, index);
791 return tmp;
792 }
793 static inline TCGv gen_ld32(TCGv addr, int index)
794 {
795 TCGv tmp = new_tmp();
796 tcg_gen_qemu_ld32u(tmp, addr, index);
797 return tmp;
798 }
799 static inline TCGv_i64 gen_ld64(TCGv addr, int index)
800 {
801 TCGv_i64 tmp = tcg_temp_new_i64();
802 tcg_gen_qemu_ld64(tmp, addr, index);
803 return tmp;
804 }
805 static inline void gen_st8(TCGv val, TCGv addr, int index)
806 {
807 tcg_gen_qemu_st8(val, addr, index);
808 dead_tmp(val);
809 }
810 static inline void gen_st16(TCGv val, TCGv addr, int index)
811 {
812 tcg_gen_qemu_st16(val, addr, index);
813 dead_tmp(val);
814 }
815 static inline void gen_st32(TCGv val, TCGv addr, int index)
816 {
817 tcg_gen_qemu_st32(val, addr, index);
818 dead_tmp(val);
819 }
820 static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
821 {
822 tcg_gen_qemu_st64(val, addr, index);
823 tcg_temp_free_i64(val);
824 }
825
826 static inline void gen_set_pc_im(uint32_t val)
827 {
828 tcg_gen_movi_i32(cpu_R[15], val);
829 }
830
831 /* Force a TB lookup after an instruction that changes the CPU state. */
832 static inline void gen_lookup_tb(DisasContext *s)
833 {
834 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
835 s->is_jmp = DISAS_UPDATE;
836 }
837
838 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
839 TCGv var)
840 {
841 int val, rm, shift, shiftop;
842 TCGv offset;
843
844 if (!(insn & (1 << 25))) {
845 /* immediate */
846 val = insn & 0xfff;
847 if (!(insn & (1 << 23)))
848 val = -val;
849 if (val != 0)
850 tcg_gen_addi_i32(var, var, val);
851 } else {
852 /* shift/register */
853 rm = (insn) & 0xf;
854 shift = (insn >> 7) & 0x1f;
855 shiftop = (insn >> 5) & 3;
856 offset = load_reg(s, rm);
857 gen_arm_shift_im(offset, shiftop, shift, 0);
858 if (!(insn & (1 << 23)))
859 tcg_gen_sub_i32(var, var, offset);
860 else
861 tcg_gen_add_i32(var, var, offset);
862 dead_tmp(offset);
863 }
864 }
865
866 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
867 int extra, TCGv var)
868 {
869 int val, rm;
870 TCGv offset;
871
872 if (insn & (1 << 22)) {
873 /* immediate */
874 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
875 if (!(insn & (1 << 23)))
876 val = -val;
877 val += extra;
878 if (val != 0)
879 tcg_gen_addi_i32(var, var, val);
880 } else {
881 /* register */
882 if (extra)
883 tcg_gen_addi_i32(var, var, extra);
884 rm = (insn) & 0xf;
885 offset = load_reg(s, rm);
886 if (!(insn & (1 << 23)))
887 tcg_gen_sub_i32(var, var, offset);
888 else
889 tcg_gen_add_i32(var, var, offset);
890 dead_tmp(offset);
891 }
892 }
893
894 #define VFP_OP2(name) \
895 static inline void gen_vfp_##name(int dp) \
896 { \
897 if (dp) \
898 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
899 else \
900 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
901 }
902
903 VFP_OP2(add)
904 VFP_OP2(sub)
905 VFP_OP2(mul)
906 VFP_OP2(div)
907
908 #undef VFP_OP2
909
910 static inline void gen_vfp_abs(int dp)
911 {
912 if (dp)
913 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
914 else
915 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
916 }
917
918 static inline void gen_vfp_neg(int dp)
919 {
920 if (dp)
921 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
922 else
923 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
924 }
925
926 static inline void gen_vfp_sqrt(int dp)
927 {
928 if (dp)
929 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
930 else
931 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
932 }
933
934 static inline void gen_vfp_cmp(int dp)
935 {
936 if (dp)
937 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
938 else
939 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
940 }
941
942 static inline void gen_vfp_cmpe(int dp)
943 {
944 if (dp)
945 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
946 else
947 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
948 }
949
950 static inline void gen_vfp_F1_ld0(int dp)
951 {
952 if (dp)
953 tcg_gen_movi_i64(cpu_F1d, 0);
954 else
955 tcg_gen_movi_i32(cpu_F1s, 0);
956 }
957
958 static inline void gen_vfp_uito(int dp)
959 {
960 if (dp)
961 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
962 else
963 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
964 }
965
966 static inline void gen_vfp_sito(int dp)
967 {
968 if (dp)
969 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
970 else
971 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
972 }
973
974 static inline void gen_vfp_toui(int dp)
975 {
976 if (dp)
977 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
978 else
979 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
980 }
981
982 static inline void gen_vfp_touiz(int dp)
983 {
984 if (dp)
985 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
986 else
987 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
988 }
989
990 static inline void gen_vfp_tosi(int dp)
991 {
992 if (dp)
993 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
994 else
995 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
996 }
997
998 static inline void gen_vfp_tosiz(int dp)
999 {
1000 if (dp)
1001 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
1002 else
1003 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1004 }
1005
1006 #define VFP_GEN_FIX(name) \
1007 static inline void gen_vfp_##name(int dp, int shift) \
1008 { \
1009 TCGv tmp_shift = tcg_const_i32(shift); \
1010 if (dp) \
1011 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1012 else \
1013 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1014 tcg_temp_free_i32(tmp_shift); \
1015 }
1016 VFP_GEN_FIX(tosh)
1017 VFP_GEN_FIX(tosl)
1018 VFP_GEN_FIX(touh)
1019 VFP_GEN_FIX(toul)
1020 VFP_GEN_FIX(shto)
1021 VFP_GEN_FIX(slto)
1022 VFP_GEN_FIX(uhto)
1023 VFP_GEN_FIX(ulto)
1024 #undef VFP_GEN_FIX
1025
1026 static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
1027 {
1028 if (dp)
1029 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
1030 else
1031 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
1032 }
1033
1034 static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
1035 {
1036 if (dp)
1037 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
1038 else
1039 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
1040 }
1041
1042 static inline long
1043 vfp_reg_offset (int dp, int reg)
1044 {
1045 if (dp)
1046 return offsetof(CPUARMState, vfp.regs[reg]);
1047 else if (reg & 1) {
1048 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1049 + offsetof(CPU_DoubleU, l.upper);
1050 } else {
1051 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1052 + offsetof(CPU_DoubleU, l.lower);
1053 }
1054 }
1055
1056 /* Return the offset of a 32-bit piece of a NEON register.
1057 zero is the least significant end of the register. */
1058 static inline long
1059 neon_reg_offset (int reg, int n)
1060 {
1061 int sreg;
1062 sreg = reg * 2 + n;
1063 return vfp_reg_offset(0, sreg);
1064 }
1065
1066 static TCGv neon_load_reg(int reg, int pass)
1067 {
1068 TCGv tmp = new_tmp();
1069 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1070 return tmp;
1071 }
1072
1073 static void neon_store_reg(int reg, int pass, TCGv var)
1074 {
1075 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1076 dead_tmp(var);
1077 }
1078
1079 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1080 {
1081 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1082 }
1083
1084 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1085 {
1086 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1087 }
1088
1089 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1090 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1091 #define tcg_gen_st_f32 tcg_gen_st_i32
1092 #define tcg_gen_st_f64 tcg_gen_st_i64
1093
1094 static inline void gen_mov_F0_vreg(int dp, int reg)
1095 {
1096 if (dp)
1097 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1098 else
1099 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1100 }
1101
1102 static inline void gen_mov_F1_vreg(int dp, int reg)
1103 {
1104 if (dp)
1105 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1106 else
1107 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1108 }
1109
1110 static inline void gen_mov_vreg_F0(int dp, int reg)
1111 {
1112 if (dp)
1113 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1114 else
1115 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1116 }
1117
1118 #define ARM_CP_RW_BIT (1 << 20)
1119
1120 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1121 {
1122 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1123 }
1124
1125 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1126 {
1127 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1128 }
1129
1130 static inline TCGv iwmmxt_load_creg(int reg)
1131 {
1132 TCGv var = new_tmp();
1133 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1134 return var;
1135 }
1136
1137 static inline void iwmmxt_store_creg(int reg, TCGv var)
1138 {
1139 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1140 dead_tmp(var);
1141 }
1142
1143 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1144 {
1145 iwmmxt_store_reg(cpu_M0, rn);
1146 }
1147
1148 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1149 {
1150 iwmmxt_load_reg(cpu_M0, rn);
1151 }
1152
1153 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1154 {
1155 iwmmxt_load_reg(cpu_V1, rn);
1156 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1157 }
1158
1159 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1160 {
1161 iwmmxt_load_reg(cpu_V1, rn);
1162 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1163 }
1164
1165 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1166 {
1167 iwmmxt_load_reg(cpu_V1, rn);
1168 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1169 }
1170
1171 #define IWMMXT_OP(name) \
1172 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1173 { \
1174 iwmmxt_load_reg(cpu_V1, rn); \
1175 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1176 }
1177
1178 #define IWMMXT_OP_ENV(name) \
1179 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1180 { \
1181 iwmmxt_load_reg(cpu_V1, rn); \
1182 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1183 }
1184
1185 #define IWMMXT_OP_ENV_SIZE(name) \
1186 IWMMXT_OP_ENV(name##b) \
1187 IWMMXT_OP_ENV(name##w) \
1188 IWMMXT_OP_ENV(name##l)
1189
1190 #define IWMMXT_OP_ENV1(name) \
1191 static inline void gen_op_iwmmxt_##name##_M0(void) \
1192 { \
1193 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1194 }
1195
1196 IWMMXT_OP(maddsq)
1197 IWMMXT_OP(madduq)
1198 IWMMXT_OP(sadb)
1199 IWMMXT_OP(sadw)
1200 IWMMXT_OP(mulslw)
1201 IWMMXT_OP(mulshw)
1202 IWMMXT_OP(mululw)
1203 IWMMXT_OP(muluhw)
1204 IWMMXT_OP(macsw)
1205 IWMMXT_OP(macuw)
1206
1207 IWMMXT_OP_ENV_SIZE(unpackl)
1208 IWMMXT_OP_ENV_SIZE(unpackh)
1209
1210 IWMMXT_OP_ENV1(unpacklub)
1211 IWMMXT_OP_ENV1(unpackluw)
1212 IWMMXT_OP_ENV1(unpacklul)
1213 IWMMXT_OP_ENV1(unpackhub)
1214 IWMMXT_OP_ENV1(unpackhuw)
1215 IWMMXT_OP_ENV1(unpackhul)
1216 IWMMXT_OP_ENV1(unpacklsb)
1217 IWMMXT_OP_ENV1(unpacklsw)
1218 IWMMXT_OP_ENV1(unpacklsl)
1219 IWMMXT_OP_ENV1(unpackhsb)
1220 IWMMXT_OP_ENV1(unpackhsw)
1221 IWMMXT_OP_ENV1(unpackhsl)
1222
1223 IWMMXT_OP_ENV_SIZE(cmpeq)
1224 IWMMXT_OP_ENV_SIZE(cmpgtu)
1225 IWMMXT_OP_ENV_SIZE(cmpgts)
1226
1227 IWMMXT_OP_ENV_SIZE(mins)
1228 IWMMXT_OP_ENV_SIZE(minu)
1229 IWMMXT_OP_ENV_SIZE(maxs)
1230 IWMMXT_OP_ENV_SIZE(maxu)
1231
1232 IWMMXT_OP_ENV_SIZE(subn)
1233 IWMMXT_OP_ENV_SIZE(addn)
1234 IWMMXT_OP_ENV_SIZE(subu)
1235 IWMMXT_OP_ENV_SIZE(addu)
1236 IWMMXT_OP_ENV_SIZE(subs)
1237 IWMMXT_OP_ENV_SIZE(adds)
1238
1239 IWMMXT_OP_ENV(avgb0)
1240 IWMMXT_OP_ENV(avgb1)
1241 IWMMXT_OP_ENV(avgw0)
1242 IWMMXT_OP_ENV(avgw1)
1243
1244 IWMMXT_OP(msadb)
1245
1246 IWMMXT_OP_ENV(packuw)
1247 IWMMXT_OP_ENV(packul)
1248 IWMMXT_OP_ENV(packuq)
1249 IWMMXT_OP_ENV(packsw)
1250 IWMMXT_OP_ENV(packsl)
1251 IWMMXT_OP_ENV(packsq)
1252
1253 static void gen_op_iwmmxt_set_mup(void)
1254 {
1255 TCGv tmp;
1256 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1257 tcg_gen_ori_i32(tmp, tmp, 2);
1258 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1259 }
1260
1261 static void gen_op_iwmmxt_set_cup(void)
1262 {
1263 TCGv tmp;
1264 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1265 tcg_gen_ori_i32(tmp, tmp, 1);
1266 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1267 }
1268
1269 static void gen_op_iwmmxt_setpsr_nz(void)
1270 {
1271 TCGv tmp = new_tmp();
1272 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1273 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1274 }
1275
1276 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1277 {
1278 iwmmxt_load_reg(cpu_V1, rn);
1279 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1280 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1281 }
1282
1283 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
1284 {
1285 int rd;
1286 uint32_t offset;
1287 TCGv tmp;
1288
1289 rd = (insn >> 16) & 0xf;
1290 tmp = load_reg(s, rd);
1291
1292 offset = (insn & 0xff) << ((insn >> 7) & 2);
1293 if (insn & (1 << 24)) {
1294 /* Pre indexed */
1295 if (insn & (1 << 23))
1296 tcg_gen_addi_i32(tmp, tmp, offset);
1297 else
1298 tcg_gen_addi_i32(tmp, tmp, -offset);
1299 tcg_gen_mov_i32(dest, tmp);
1300 if (insn & (1 << 21))
1301 store_reg(s, rd, tmp);
1302 else
1303 dead_tmp(tmp);
1304 } else if (insn & (1 << 21)) {
1305 /* Post indexed */
1306 tcg_gen_mov_i32(dest, tmp);
1307 if (insn & (1 << 23))
1308 tcg_gen_addi_i32(tmp, tmp, offset);
1309 else
1310 tcg_gen_addi_i32(tmp, tmp, -offset);
1311 store_reg(s, rd, tmp);
1312 } else if (!(insn & (1 << 23)))
1313 return 1;
1314 return 0;
1315 }
1316
1317 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
1318 {
1319 int rd = (insn >> 0) & 0xf;
1320 TCGv tmp;
1321
1322 if (insn & (1 << 8)) {
1323 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1324 return 1;
1325 } else {
1326 tmp = iwmmxt_load_creg(rd);
1327 }
1328 } else {
1329 tmp = new_tmp();
1330 iwmmxt_load_reg(cpu_V0, rd);
1331 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1332 }
1333 tcg_gen_andi_i32(tmp, tmp, mask);
1334 tcg_gen_mov_i32(dest, tmp);
1335 dead_tmp(tmp);
1336 return 0;
1337 }
1338
1339 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1340 (ie. an undefined instruction). */
1341 static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1342 {
1343 int rd, wrd;
1344 int rdhi, rdlo, rd0, rd1, i;
1345 TCGv addr;
1346 TCGv tmp, tmp2, tmp3;
1347
1348 if ((insn & 0x0e000e00) == 0x0c000000) {
1349 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1350 wrd = insn & 0xf;
1351 rdlo = (insn >> 12) & 0xf;
1352 rdhi = (insn >> 16) & 0xf;
1353 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1354 iwmmxt_load_reg(cpu_V0, wrd);
1355 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1356 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1357 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
1358 } else { /* TMCRR */
1359 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1360 iwmmxt_store_reg(cpu_V0, wrd);
1361 gen_op_iwmmxt_set_mup();
1362 }
1363 return 0;
1364 }
1365
1366 wrd = (insn >> 12) & 0xf;
1367 addr = new_tmp();
1368 if (gen_iwmmxt_address(s, insn, addr)) {
1369 dead_tmp(addr);
1370 return 1;
1371 }
1372 if (insn & ARM_CP_RW_BIT) {
1373 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1374 tmp = new_tmp();
1375 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1376 iwmmxt_store_creg(wrd, tmp);
1377 } else {
1378 i = 1;
1379 if (insn & (1 << 8)) {
1380 if (insn & (1 << 22)) { /* WLDRD */
1381 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
1382 i = 0;
1383 } else { /* WLDRW wRd */
1384 tmp = gen_ld32(addr, IS_USER(s));
1385 }
1386 } else {
1387 if (insn & (1 << 22)) { /* WLDRH */
1388 tmp = gen_ld16u(addr, IS_USER(s));
1389 } else { /* WLDRB */
1390 tmp = gen_ld8u(addr, IS_USER(s));
1391 }
1392 }
1393 if (i) {
1394 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1395 dead_tmp(tmp);
1396 }
1397 gen_op_iwmmxt_movq_wRn_M0(wrd);
1398 }
1399 } else {
1400 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1401 tmp = iwmmxt_load_creg(wrd);
1402 gen_st32(tmp, addr, IS_USER(s));
1403 } else {
1404 gen_op_iwmmxt_movq_M0_wRn(wrd);
1405 tmp = new_tmp();
1406 if (insn & (1 << 8)) {
1407 if (insn & (1 << 22)) { /* WSTRD */
1408 dead_tmp(tmp);
1409 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
1410 } else { /* WSTRW wRd */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1412 gen_st32(tmp, addr, IS_USER(s));
1413 }
1414 } else {
1415 if (insn & (1 << 22)) { /* WSTRH */
1416 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1417 gen_st16(tmp, addr, IS_USER(s));
1418 } else { /* WSTRB */
1419 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1420 gen_st8(tmp, addr, IS_USER(s));
1421 }
1422 }
1423 }
1424 }
1425 dead_tmp(addr);
1426 return 0;
1427 }
1428
1429 if ((insn & 0x0f000000) != 0x0e000000)
1430 return 1;
1431
1432 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1433 case 0x000: /* WOR */
1434 wrd = (insn >> 12) & 0xf;
1435 rd0 = (insn >> 0) & 0xf;
1436 rd1 = (insn >> 16) & 0xf;
1437 gen_op_iwmmxt_movq_M0_wRn(rd0);
1438 gen_op_iwmmxt_orq_M0_wRn(rd1);
1439 gen_op_iwmmxt_setpsr_nz();
1440 gen_op_iwmmxt_movq_wRn_M0(wrd);
1441 gen_op_iwmmxt_set_mup();
1442 gen_op_iwmmxt_set_cup();
1443 break;
1444 case 0x011: /* TMCR */
1445 if (insn & 0xf)
1446 return 1;
1447 rd = (insn >> 12) & 0xf;
1448 wrd = (insn >> 16) & 0xf;
1449 switch (wrd) {
1450 case ARM_IWMMXT_wCID:
1451 case ARM_IWMMXT_wCASF:
1452 break;
1453 case ARM_IWMMXT_wCon:
1454 gen_op_iwmmxt_set_cup();
1455 /* Fall through. */
1456 case ARM_IWMMXT_wCSSF:
1457 tmp = iwmmxt_load_creg(wrd);
1458 tmp2 = load_reg(s, rd);
1459 tcg_gen_andc_i32(tmp, tmp, tmp2);
1460 dead_tmp(tmp2);
1461 iwmmxt_store_creg(wrd, tmp);
1462 break;
1463 case ARM_IWMMXT_wCGR0:
1464 case ARM_IWMMXT_wCGR1:
1465 case ARM_IWMMXT_wCGR2:
1466 case ARM_IWMMXT_wCGR3:
1467 gen_op_iwmmxt_set_cup();
1468 tmp = load_reg(s, rd);
1469 iwmmxt_store_creg(wrd, tmp);
1470 break;
1471 default:
1472 return 1;
1473 }
1474 break;
1475 case 0x100: /* WXOR */
1476 wrd = (insn >> 12) & 0xf;
1477 rd0 = (insn >> 0) & 0xf;
1478 rd1 = (insn >> 16) & 0xf;
1479 gen_op_iwmmxt_movq_M0_wRn(rd0);
1480 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1481 gen_op_iwmmxt_setpsr_nz();
1482 gen_op_iwmmxt_movq_wRn_M0(wrd);
1483 gen_op_iwmmxt_set_mup();
1484 gen_op_iwmmxt_set_cup();
1485 break;
1486 case 0x111: /* TMRC */
1487 if (insn & 0xf)
1488 return 1;
1489 rd = (insn >> 12) & 0xf;
1490 wrd = (insn >> 16) & 0xf;
1491 tmp = iwmmxt_load_creg(wrd);
1492 store_reg(s, rd, tmp);
1493 break;
1494 case 0x300: /* WANDN */
1495 wrd = (insn >> 12) & 0xf;
1496 rd0 = (insn >> 0) & 0xf;
1497 rd1 = (insn >> 16) & 0xf;
1498 gen_op_iwmmxt_movq_M0_wRn(rd0);
1499 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1500 gen_op_iwmmxt_andq_M0_wRn(rd1);
1501 gen_op_iwmmxt_setpsr_nz();
1502 gen_op_iwmmxt_movq_wRn_M0(wrd);
1503 gen_op_iwmmxt_set_mup();
1504 gen_op_iwmmxt_set_cup();
1505 break;
1506 case 0x200: /* WAND */
1507 wrd = (insn >> 12) & 0xf;
1508 rd0 = (insn >> 0) & 0xf;
1509 rd1 = (insn >> 16) & 0xf;
1510 gen_op_iwmmxt_movq_M0_wRn(rd0);
1511 gen_op_iwmmxt_andq_M0_wRn(rd1);
1512 gen_op_iwmmxt_setpsr_nz();
1513 gen_op_iwmmxt_movq_wRn_M0(wrd);
1514 gen_op_iwmmxt_set_mup();
1515 gen_op_iwmmxt_set_cup();
1516 break;
1517 case 0x810: case 0xa10: /* WMADD */
1518 wrd = (insn >> 12) & 0xf;
1519 rd0 = (insn >> 0) & 0xf;
1520 rd1 = (insn >> 16) & 0xf;
1521 gen_op_iwmmxt_movq_M0_wRn(rd0);
1522 if (insn & (1 << 21))
1523 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1524 else
1525 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1526 gen_op_iwmmxt_movq_wRn_M0(wrd);
1527 gen_op_iwmmxt_set_mup();
1528 break;
1529 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1530 wrd = (insn >> 12) & 0xf;
1531 rd0 = (insn >> 16) & 0xf;
1532 rd1 = (insn >> 0) & 0xf;
1533 gen_op_iwmmxt_movq_M0_wRn(rd0);
1534 switch ((insn >> 22) & 3) {
1535 case 0:
1536 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1537 break;
1538 case 1:
1539 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1540 break;
1541 case 2:
1542 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1543 break;
1544 case 3:
1545 return 1;
1546 }
1547 gen_op_iwmmxt_movq_wRn_M0(wrd);
1548 gen_op_iwmmxt_set_mup();
1549 gen_op_iwmmxt_set_cup();
1550 break;
1551 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1552 wrd = (insn >> 12) & 0xf;
1553 rd0 = (insn >> 16) & 0xf;
1554 rd1 = (insn >> 0) & 0xf;
1555 gen_op_iwmmxt_movq_M0_wRn(rd0);
1556 switch ((insn >> 22) & 3) {
1557 case 0:
1558 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1559 break;
1560 case 1:
1561 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1562 break;
1563 case 2:
1564 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1565 break;
1566 case 3:
1567 return 1;
1568 }
1569 gen_op_iwmmxt_movq_wRn_M0(wrd);
1570 gen_op_iwmmxt_set_mup();
1571 gen_op_iwmmxt_set_cup();
1572 break;
1573 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1574 wrd = (insn >> 12) & 0xf;
1575 rd0 = (insn >> 16) & 0xf;
1576 rd1 = (insn >> 0) & 0xf;
1577 gen_op_iwmmxt_movq_M0_wRn(rd0);
1578 if (insn & (1 << 22))
1579 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1580 else
1581 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1582 if (!(insn & (1 << 20)))
1583 gen_op_iwmmxt_addl_M0_wRn(wrd);
1584 gen_op_iwmmxt_movq_wRn_M0(wrd);
1585 gen_op_iwmmxt_set_mup();
1586 break;
1587 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1588 wrd = (insn >> 12) & 0xf;
1589 rd0 = (insn >> 16) & 0xf;
1590 rd1 = (insn >> 0) & 0xf;
1591 gen_op_iwmmxt_movq_M0_wRn(rd0);
1592 if (insn & (1 << 21)) {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1597 } else {
1598 if (insn & (1 << 20))
1599 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1600 else
1601 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1602 }
1603 gen_op_iwmmxt_movq_wRn_M0(wrd);
1604 gen_op_iwmmxt_set_mup();
1605 break;
1606 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1607 wrd = (insn >> 12) & 0xf;
1608 rd0 = (insn >> 16) & 0xf;
1609 rd1 = (insn >> 0) & 0xf;
1610 gen_op_iwmmxt_movq_M0_wRn(rd0);
1611 if (insn & (1 << 21))
1612 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1613 else
1614 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1615 if (!(insn & (1 << 20))) {
1616 iwmmxt_load_reg(cpu_V1, wrd);
1617 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1618 }
1619 gen_op_iwmmxt_movq_wRn_M0(wrd);
1620 gen_op_iwmmxt_set_mup();
1621 break;
1622 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1623 wrd = (insn >> 12) & 0xf;
1624 rd0 = (insn >> 16) & 0xf;
1625 rd1 = (insn >> 0) & 0xf;
1626 gen_op_iwmmxt_movq_M0_wRn(rd0);
1627 switch ((insn >> 22) & 3) {
1628 case 0:
1629 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1630 break;
1631 case 1:
1632 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1633 break;
1634 case 2:
1635 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1636 break;
1637 case 3:
1638 return 1;
1639 }
1640 gen_op_iwmmxt_movq_wRn_M0(wrd);
1641 gen_op_iwmmxt_set_mup();
1642 gen_op_iwmmxt_set_cup();
1643 break;
1644 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1645 wrd = (insn >> 12) & 0xf;
1646 rd0 = (insn >> 16) & 0xf;
1647 rd1 = (insn >> 0) & 0xf;
1648 gen_op_iwmmxt_movq_M0_wRn(rd0);
1649 if (insn & (1 << 22)) {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1654 } else {
1655 if (insn & (1 << 20))
1656 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1657 else
1658 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1659 }
1660 gen_op_iwmmxt_movq_wRn_M0(wrd);
1661 gen_op_iwmmxt_set_mup();
1662 gen_op_iwmmxt_set_cup();
1663 break;
1664 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1665 wrd = (insn >> 12) & 0xf;
1666 rd0 = (insn >> 16) & 0xf;
1667 rd1 = (insn >> 0) & 0xf;
1668 gen_op_iwmmxt_movq_M0_wRn(rd0);
1669 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1670 tcg_gen_andi_i32(tmp, tmp, 7);
1671 iwmmxt_load_reg(cpu_V1, rd1);
1672 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1673 dead_tmp(tmp);
1674 gen_op_iwmmxt_movq_wRn_M0(wrd);
1675 gen_op_iwmmxt_set_mup();
1676 break;
1677 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1678 if (((insn >> 6) & 3) == 3)
1679 return 1;
1680 rd = (insn >> 12) & 0xf;
1681 wrd = (insn >> 16) & 0xf;
1682 tmp = load_reg(s, rd);
1683 gen_op_iwmmxt_movq_M0_wRn(wrd);
1684 switch ((insn >> 6) & 3) {
1685 case 0:
1686 tmp2 = tcg_const_i32(0xff);
1687 tmp3 = tcg_const_i32((insn & 7) << 3);
1688 break;
1689 case 1:
1690 tmp2 = tcg_const_i32(0xffff);
1691 tmp3 = tcg_const_i32((insn & 3) << 4);
1692 break;
1693 case 2:
1694 tmp2 = tcg_const_i32(0xffffffff);
1695 tmp3 = tcg_const_i32((insn & 1) << 5);
1696 break;
1697 default:
1698 TCGV_UNUSED(tmp2);
1699 TCGV_UNUSED(tmp3);
1700 }
1701 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1702 tcg_temp_free(tmp3);
1703 tcg_temp_free(tmp2);
1704 dead_tmp(tmp);
1705 gen_op_iwmmxt_movq_wRn_M0(wrd);
1706 gen_op_iwmmxt_set_mup();
1707 break;
1708 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1709 rd = (insn >> 12) & 0xf;
1710 wrd = (insn >> 16) & 0xf;
1711 if (rd == 15 || ((insn >> 22) & 3) == 3)
1712 return 1;
1713 gen_op_iwmmxt_movq_M0_wRn(wrd);
1714 tmp = new_tmp();
1715 switch ((insn >> 22) & 3) {
1716 case 0:
1717 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1718 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1719 if (insn & 8) {
1720 tcg_gen_ext8s_i32(tmp, tmp);
1721 } else {
1722 tcg_gen_andi_i32(tmp, tmp, 0xff);
1723 }
1724 break;
1725 case 1:
1726 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1727 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1728 if (insn & 8) {
1729 tcg_gen_ext16s_i32(tmp, tmp);
1730 } else {
1731 tcg_gen_andi_i32(tmp, tmp, 0xffff);
1732 }
1733 break;
1734 case 2:
1735 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1736 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1737 break;
1738 }
1739 store_reg(s, rd, tmp);
1740 break;
1741 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1742 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1743 return 1;
1744 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1745 switch ((insn >> 22) & 3) {
1746 case 0:
1747 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
1748 break;
1749 case 1:
1750 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
1751 break;
1752 case 2:
1753 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
1754 break;
1755 }
1756 tcg_gen_shli_i32(tmp, tmp, 28);
1757 gen_set_nzcv(tmp);
1758 dead_tmp(tmp);
1759 break;
1760 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1761 if (((insn >> 6) & 3) == 3)
1762 return 1;
1763 rd = (insn >> 12) & 0xf;
1764 wrd = (insn >> 16) & 0xf;
1765 tmp = load_reg(s, rd);
1766 switch ((insn >> 6) & 3) {
1767 case 0:
1768 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
1769 break;
1770 case 1:
1771 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
1772 break;
1773 case 2:
1774 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
1775 break;
1776 }
1777 dead_tmp(tmp);
1778 gen_op_iwmmxt_movq_wRn_M0(wrd);
1779 gen_op_iwmmxt_set_mup();
1780 break;
1781 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1782 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1783 return 1;
1784 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1785 tmp2 = new_tmp();
1786 tcg_gen_mov_i32(tmp2, tmp);
1787 switch ((insn >> 22) & 3) {
1788 case 0:
1789 for (i = 0; i < 7; i ++) {
1790 tcg_gen_shli_i32(tmp2, tmp2, 4);
1791 tcg_gen_and_i32(tmp, tmp, tmp2);
1792 }
1793 break;
1794 case 1:
1795 for (i = 0; i < 3; i ++) {
1796 tcg_gen_shli_i32(tmp2, tmp2, 8);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
1798 }
1799 break;
1800 case 2:
1801 tcg_gen_shli_i32(tmp2, tmp2, 16);
1802 tcg_gen_and_i32(tmp, tmp, tmp2);
1803 break;
1804 }
1805 gen_set_nzcv(tmp);
1806 dead_tmp(tmp2);
1807 dead_tmp(tmp);
1808 break;
1809 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1810 wrd = (insn >> 12) & 0xf;
1811 rd0 = (insn >> 16) & 0xf;
1812 gen_op_iwmmxt_movq_M0_wRn(rd0);
1813 switch ((insn >> 22) & 3) {
1814 case 0:
1815 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1816 break;
1817 case 1:
1818 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1819 break;
1820 case 2:
1821 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1822 break;
1823 case 3:
1824 return 1;
1825 }
1826 gen_op_iwmmxt_movq_wRn_M0(wrd);
1827 gen_op_iwmmxt_set_mup();
1828 break;
1829 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1830 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1831 return 1;
1832 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1833 tmp2 = new_tmp();
1834 tcg_gen_mov_i32(tmp2, tmp);
1835 switch ((insn >> 22) & 3) {
1836 case 0:
1837 for (i = 0; i < 7; i ++) {
1838 tcg_gen_shli_i32(tmp2, tmp2, 4);
1839 tcg_gen_or_i32(tmp, tmp, tmp2);
1840 }
1841 break;
1842 case 1:
1843 for (i = 0; i < 3; i ++) {
1844 tcg_gen_shli_i32(tmp2, tmp2, 8);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
1846 }
1847 break;
1848 case 2:
1849 tcg_gen_shli_i32(tmp2, tmp2, 16);
1850 tcg_gen_or_i32(tmp, tmp, tmp2);
1851 break;
1852 }
1853 gen_set_nzcv(tmp);
1854 dead_tmp(tmp2);
1855 dead_tmp(tmp);
1856 break;
1857 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1858 rd = (insn >> 12) & 0xf;
1859 rd0 = (insn >> 16) & 0xf;
1860 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
1861 return 1;
1862 gen_op_iwmmxt_movq_M0_wRn(rd0);
1863 tmp = new_tmp();
1864 switch ((insn >> 22) & 3) {
1865 case 0:
1866 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
1867 break;
1868 case 1:
1869 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
1870 break;
1871 case 2:
1872 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
1873 break;
1874 }
1875 store_reg(s, rd, tmp);
1876 break;
1877 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1878 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1879 wrd = (insn >> 12) & 0xf;
1880 rd0 = (insn >> 16) & 0xf;
1881 rd1 = (insn >> 0) & 0xf;
1882 gen_op_iwmmxt_movq_M0_wRn(rd0);
1883 switch ((insn >> 22) & 3) {
1884 case 0:
1885 if (insn & (1 << 21))
1886 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1887 else
1888 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1889 break;
1890 case 1:
1891 if (insn & (1 << 21))
1892 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1893 else
1894 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1895 break;
1896 case 2:
1897 if (insn & (1 << 21))
1898 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1899 else
1900 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1901 break;
1902 case 3:
1903 return 1;
1904 }
1905 gen_op_iwmmxt_movq_wRn_M0(wrd);
1906 gen_op_iwmmxt_set_mup();
1907 gen_op_iwmmxt_set_cup();
1908 break;
1909 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1910 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1911 wrd = (insn >> 12) & 0xf;
1912 rd0 = (insn >> 16) & 0xf;
1913 gen_op_iwmmxt_movq_M0_wRn(rd0);
1914 switch ((insn >> 22) & 3) {
1915 case 0:
1916 if (insn & (1 << 21))
1917 gen_op_iwmmxt_unpacklsb_M0();
1918 else
1919 gen_op_iwmmxt_unpacklub_M0();
1920 break;
1921 case 1:
1922 if (insn & (1 << 21))
1923 gen_op_iwmmxt_unpacklsw_M0();
1924 else
1925 gen_op_iwmmxt_unpackluw_M0();
1926 break;
1927 case 2:
1928 if (insn & (1 << 21))
1929 gen_op_iwmmxt_unpacklsl_M0();
1930 else
1931 gen_op_iwmmxt_unpacklul_M0();
1932 break;
1933 case 3:
1934 return 1;
1935 }
1936 gen_op_iwmmxt_movq_wRn_M0(wrd);
1937 gen_op_iwmmxt_set_mup();
1938 gen_op_iwmmxt_set_cup();
1939 break;
1940 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1941 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1942 wrd = (insn >> 12) & 0xf;
1943 rd0 = (insn >> 16) & 0xf;
1944 gen_op_iwmmxt_movq_M0_wRn(rd0);
1945 switch ((insn >> 22) & 3) {
1946 case 0:
1947 if (insn & (1 << 21))
1948 gen_op_iwmmxt_unpackhsb_M0();
1949 else
1950 gen_op_iwmmxt_unpackhub_M0();
1951 break;
1952 case 1:
1953 if (insn & (1 << 21))
1954 gen_op_iwmmxt_unpackhsw_M0();
1955 else
1956 gen_op_iwmmxt_unpackhuw_M0();
1957 break;
1958 case 2:
1959 if (insn & (1 << 21))
1960 gen_op_iwmmxt_unpackhsl_M0();
1961 else
1962 gen_op_iwmmxt_unpackhul_M0();
1963 break;
1964 case 3:
1965 return 1;
1966 }
1967 gen_op_iwmmxt_movq_wRn_M0(wrd);
1968 gen_op_iwmmxt_set_mup();
1969 gen_op_iwmmxt_set_cup();
1970 break;
1971 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1972 case 0x214: case 0x614: case 0xa14: case 0xe14:
1973 if (((insn >> 22) & 3) == 0)
1974 return 1;
1975 wrd = (insn >> 12) & 0xf;
1976 rd0 = (insn >> 16) & 0xf;
1977 gen_op_iwmmxt_movq_M0_wRn(rd0);
1978 tmp = new_tmp();
1979 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1980 dead_tmp(tmp);
1981 return 1;
1982 }
1983 switch ((insn >> 22) & 3) {
1984 case 1:
1985 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
1986 break;
1987 case 2:
1988 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
1989 break;
1990 case 3:
1991 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
1992 break;
1993 }
1994 dead_tmp(tmp);
1995 gen_op_iwmmxt_movq_wRn_M0(wrd);
1996 gen_op_iwmmxt_set_mup();
1997 gen_op_iwmmxt_set_cup();
1998 break;
1999 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2000 case 0x014: case 0x414: case 0x814: case 0xc14:
2001 if (((insn >> 22) & 3) == 0)
2002 return 1;
2003 wrd = (insn >> 12) & 0xf;
2004 rd0 = (insn >> 16) & 0xf;
2005 gen_op_iwmmxt_movq_M0_wRn(rd0);
2006 tmp = new_tmp();
2007 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2008 dead_tmp(tmp);
2009 return 1;
2010 }
2011 switch ((insn >> 22) & 3) {
2012 case 1:
2013 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
2014 break;
2015 case 2:
2016 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
2017 break;
2018 case 3:
2019 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
2020 break;
2021 }
2022 dead_tmp(tmp);
2023 gen_op_iwmmxt_movq_wRn_M0(wrd);
2024 gen_op_iwmmxt_set_mup();
2025 gen_op_iwmmxt_set_cup();
2026 break;
2027 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2028 case 0x114: case 0x514: case 0x914: case 0xd14:
2029 if (((insn >> 22) & 3) == 0)
2030 return 1;
2031 wrd = (insn >> 12) & 0xf;
2032 rd0 = (insn >> 16) & 0xf;
2033 gen_op_iwmmxt_movq_M0_wRn(rd0);
2034 tmp = new_tmp();
2035 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2036 dead_tmp(tmp);
2037 return 1;
2038 }
2039 switch ((insn >> 22) & 3) {
2040 case 1:
2041 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
2042 break;
2043 case 2:
2044 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
2045 break;
2046 case 3:
2047 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
2048 break;
2049 }
2050 dead_tmp(tmp);
2051 gen_op_iwmmxt_movq_wRn_M0(wrd);
2052 gen_op_iwmmxt_set_mup();
2053 gen_op_iwmmxt_set_cup();
2054 break;
2055 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2056 case 0x314: case 0x714: case 0xb14: case 0xf14:
2057 if (((insn >> 22) & 3) == 0)
2058 return 1;
2059 wrd = (insn >> 12) & 0xf;
2060 rd0 = (insn >> 16) & 0xf;
2061 gen_op_iwmmxt_movq_M0_wRn(rd0);
2062 tmp = new_tmp();
2063 switch ((insn >> 22) & 3) {
2064 case 1:
2065 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2066 dead_tmp(tmp);
2067 return 1;
2068 }
2069 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
2070 break;
2071 case 2:
2072 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2073 dead_tmp(tmp);
2074 return 1;
2075 }
2076 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
2077 break;
2078 case 3:
2079 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2080 dead_tmp(tmp);
2081 return 1;
2082 }
2083 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
2084 break;
2085 }
2086 dead_tmp(tmp);
2087 gen_op_iwmmxt_movq_wRn_M0(wrd);
2088 gen_op_iwmmxt_set_mup();
2089 gen_op_iwmmxt_set_cup();
2090 break;
2091 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2092 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2093 wrd = (insn >> 12) & 0xf;
2094 rd0 = (insn >> 16) & 0xf;
2095 rd1 = (insn >> 0) & 0xf;
2096 gen_op_iwmmxt_movq_M0_wRn(rd0);
2097 switch ((insn >> 22) & 3) {
2098 case 0:
2099 if (insn & (1 << 21))
2100 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2101 else
2102 gen_op_iwmmxt_minub_M0_wRn(rd1);
2103 break;
2104 case 1:
2105 if (insn & (1 << 21))
2106 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2107 else
2108 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2109 break;
2110 case 2:
2111 if (insn & (1 << 21))
2112 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2113 else
2114 gen_op_iwmmxt_minul_M0_wRn(rd1);
2115 break;
2116 case 3:
2117 return 1;
2118 }
2119 gen_op_iwmmxt_movq_wRn_M0(wrd);
2120 gen_op_iwmmxt_set_mup();
2121 break;
2122 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2123 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2124 wrd = (insn >> 12) & 0xf;
2125 rd0 = (insn >> 16) & 0xf;
2126 rd1 = (insn >> 0) & 0xf;
2127 gen_op_iwmmxt_movq_M0_wRn(rd0);
2128 switch ((insn >> 22) & 3) {
2129 case 0:
2130 if (insn & (1 << 21))
2131 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2132 else
2133 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2134 break;
2135 case 1:
2136 if (insn & (1 << 21))
2137 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2138 else
2139 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2140 break;
2141 case 2:
2142 if (insn & (1 << 21))
2143 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2144 else
2145 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2146 break;
2147 case 3:
2148 return 1;
2149 }
2150 gen_op_iwmmxt_movq_wRn_M0(wrd);
2151 gen_op_iwmmxt_set_mup();
2152 break;
2153 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2154 case 0x402: case 0x502: case 0x602: case 0x702:
2155 wrd = (insn >> 12) & 0xf;
2156 rd0 = (insn >> 16) & 0xf;
2157 rd1 = (insn >> 0) & 0xf;
2158 gen_op_iwmmxt_movq_M0_wRn(rd0);
2159 tmp = tcg_const_i32((insn >> 20) & 3);
2160 iwmmxt_load_reg(cpu_V1, rd1);
2161 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2162 tcg_temp_free(tmp);
2163 gen_op_iwmmxt_movq_wRn_M0(wrd);
2164 gen_op_iwmmxt_set_mup();
2165 break;
2166 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2167 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2168 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2169 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2170 wrd = (insn >> 12) & 0xf;
2171 rd0 = (insn >> 16) & 0xf;
2172 rd1 = (insn >> 0) & 0xf;
2173 gen_op_iwmmxt_movq_M0_wRn(rd0);
2174 switch ((insn >> 20) & 0xf) {
2175 case 0x0:
2176 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2177 break;
2178 case 0x1:
2179 gen_op_iwmmxt_subub_M0_wRn(rd1);
2180 break;
2181 case 0x3:
2182 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2183 break;
2184 case 0x4:
2185 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2186 break;
2187 case 0x5:
2188 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2189 break;
2190 case 0x7:
2191 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2192 break;
2193 case 0x8:
2194 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2195 break;
2196 case 0x9:
2197 gen_op_iwmmxt_subul_M0_wRn(rd1);
2198 break;
2199 case 0xb:
2200 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2201 break;
2202 default:
2203 return 1;
2204 }
2205 gen_op_iwmmxt_movq_wRn_M0(wrd);
2206 gen_op_iwmmxt_set_mup();
2207 gen_op_iwmmxt_set_cup();
2208 break;
2209 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2210 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2211 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2212 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2213 wrd = (insn >> 12) & 0xf;
2214 rd0 = (insn >> 16) & 0xf;
2215 gen_op_iwmmxt_movq_M0_wRn(rd0);
2216 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2217 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2218 tcg_temp_free(tmp);
2219 gen_op_iwmmxt_movq_wRn_M0(wrd);
2220 gen_op_iwmmxt_set_mup();
2221 gen_op_iwmmxt_set_cup();
2222 break;
2223 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2224 case 0x418: case 0x518: case 0x618: case 0x718:
2225 case 0x818: case 0x918: case 0xa18: case 0xb18:
2226 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2227 wrd = (insn >> 12) & 0xf;
2228 rd0 = (insn >> 16) & 0xf;
2229 rd1 = (insn >> 0) & 0xf;
2230 gen_op_iwmmxt_movq_M0_wRn(rd0);
2231 switch ((insn >> 20) & 0xf) {
2232 case 0x0:
2233 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2234 break;
2235 case 0x1:
2236 gen_op_iwmmxt_addub_M0_wRn(rd1);
2237 break;
2238 case 0x3:
2239 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2240 break;
2241 case 0x4:
2242 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2243 break;
2244 case 0x5:
2245 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2246 break;
2247 case 0x7:
2248 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2249 break;
2250 case 0x8:
2251 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2252 break;
2253 case 0x9:
2254 gen_op_iwmmxt_addul_M0_wRn(rd1);
2255 break;
2256 case 0xb:
2257 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2258 break;
2259 default:
2260 return 1;
2261 }
2262 gen_op_iwmmxt_movq_wRn_M0(wrd);
2263 gen_op_iwmmxt_set_mup();
2264 gen_op_iwmmxt_set_cup();
2265 break;
2266 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2267 case 0x408: case 0x508: case 0x608: case 0x708:
2268 case 0x808: case 0x908: case 0xa08: case 0xb08:
2269 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2270 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2271 return 1;
2272 wrd = (insn >> 12) & 0xf;
2273 rd0 = (insn >> 16) & 0xf;
2274 rd1 = (insn >> 0) & 0xf;
2275 gen_op_iwmmxt_movq_M0_wRn(rd0);
2276 switch ((insn >> 22) & 3) {
2277 case 1:
2278 if (insn & (1 << 21))
2279 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2280 else
2281 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2282 break;
2283 case 2:
2284 if (insn & (1 << 21))
2285 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2286 else
2287 gen_op_iwmmxt_packul_M0_wRn(rd1);
2288 break;
2289 case 3:
2290 if (insn & (1 << 21))
2291 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2292 else
2293 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2294 break;
2295 }
2296 gen_op_iwmmxt_movq_wRn_M0(wrd);
2297 gen_op_iwmmxt_set_mup();
2298 gen_op_iwmmxt_set_cup();
2299 break;
2300 case 0x201: case 0x203: case 0x205: case 0x207:
2301 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2302 case 0x211: case 0x213: case 0x215: case 0x217:
2303 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2304 wrd = (insn >> 5) & 0xf;
2305 rd0 = (insn >> 12) & 0xf;
2306 rd1 = (insn >> 0) & 0xf;
2307 if (rd0 == 0xf || rd1 == 0xf)
2308 return 1;
2309 gen_op_iwmmxt_movq_M0_wRn(wrd);
2310 tmp = load_reg(s, rd0);
2311 tmp2 = load_reg(s, rd1);
2312 switch ((insn >> 16) & 0xf) {
2313 case 0x0: /* TMIA */
2314 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2315 break;
2316 case 0x8: /* TMIAPH */
2317 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2318 break;
2319 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2320 if (insn & (1 << 16))
2321 tcg_gen_shri_i32(tmp, tmp, 16);
2322 if (insn & (1 << 17))
2323 tcg_gen_shri_i32(tmp2, tmp2, 16);
2324 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2325 break;
2326 default:
2327 dead_tmp(tmp2);
2328 dead_tmp(tmp);
2329 return 1;
2330 }
2331 dead_tmp(tmp2);
2332 dead_tmp(tmp);
2333 gen_op_iwmmxt_movq_wRn_M0(wrd);
2334 gen_op_iwmmxt_set_mup();
2335 break;
2336 default:
2337 return 1;
2338 }
2339
2340 return 0;
2341 }
2342
2343 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2344 (ie. an undefined instruction). */
2345 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2346 {
2347 int acc, rd0, rd1, rdhi, rdlo;
2348 TCGv tmp, tmp2;
2349
2350 if ((insn & 0x0ff00f10) == 0x0e200010) {
2351 /* Multiply with Internal Accumulate Format */
2352 rd0 = (insn >> 12) & 0xf;
2353 rd1 = insn & 0xf;
2354 acc = (insn >> 5) & 7;
2355
2356 if (acc != 0)
2357 return 1;
2358
2359 tmp = load_reg(s, rd0);
2360 tmp2 = load_reg(s, rd1);
2361 switch ((insn >> 16) & 0xf) {
2362 case 0x0: /* MIA */
2363 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2364 break;
2365 case 0x8: /* MIAPH */
2366 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2367 break;
2368 case 0xc: /* MIABB */
2369 case 0xd: /* MIABT */
2370 case 0xe: /* MIATB */
2371 case 0xf: /* MIATT */
2372 if (insn & (1 << 16))
2373 tcg_gen_shri_i32(tmp, tmp, 16);
2374 if (insn & (1 << 17))
2375 tcg_gen_shri_i32(tmp2, tmp2, 16);
2376 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2377 break;
2378 default:
2379 return 1;
2380 }
2381 dead_tmp(tmp2);
2382 dead_tmp(tmp);
2383
2384 gen_op_iwmmxt_movq_wRn_M0(acc);
2385 return 0;
2386 }
2387
2388 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2389 /* Internal Accumulator Access Format */
2390 rdhi = (insn >> 16) & 0xf;
2391 rdlo = (insn >> 12) & 0xf;
2392 acc = insn & 7;
2393
2394 if (acc != 0)
2395 return 1;
2396
2397 if (insn & ARM_CP_RW_BIT) { /* MRA */
2398 iwmmxt_load_reg(cpu_V0, acc);
2399 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2400 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2401 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2402 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2403 } else { /* MAR */
2404 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2405 iwmmxt_store_reg(cpu_V0, acc);
2406 }
2407 return 0;
2408 }
2409
2410 return 1;
2411 }
2412
2413 /* Disassemble system coprocessor instruction. Return nonzero if
2414 instruction is not defined. */
2415 static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2416 {
2417 TCGv tmp, tmp2;
2418 uint32_t rd = (insn >> 12) & 0xf;
2419 uint32_t cp = (insn >> 8) & 0xf;
2420 if (IS_USER(s)) {
2421 return 1;
2422 }
2423
2424 if (insn & ARM_CP_RW_BIT) {
2425 if (!env->cp[cp].cp_read)
2426 return 1;
2427 gen_set_pc_im(s->pc);
2428 tmp = new_tmp();
2429 tmp2 = tcg_const_i32(insn);
2430 gen_helper_get_cp(tmp, cpu_env, tmp2);
2431 tcg_temp_free(tmp2);
2432 store_reg(s, rd, tmp);
2433 } else {
2434 if (!env->cp[cp].cp_write)
2435 return 1;
2436 gen_set_pc_im(s->pc);
2437 tmp = load_reg(s, rd);
2438 tmp2 = tcg_const_i32(insn);
2439 gen_helper_set_cp(cpu_env, tmp2, tmp);
2440 tcg_temp_free(tmp2);
2441 dead_tmp(tmp);
2442 }
2443 return 0;
2444 }
2445
2446 static int cp15_user_ok(uint32_t insn)
2447 {
2448 int cpn = (insn >> 16) & 0xf;
2449 int cpm = insn & 0xf;
2450 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2451
2452 if (cpn == 13 && cpm == 0) {
2453 /* TLS register. */
2454 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2455 return 1;
2456 }
2457 if (cpn == 7) {
2458 /* ISB, DSB, DMB. */
2459 if ((cpm == 5 && op == 4)
2460 || (cpm == 10 && (op == 4 || op == 5)))
2461 return 1;
2462 }
2463 return 0;
2464 }
2465
2466 static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2467 {
2468 TCGv tmp;
2469 int cpn = (insn >> 16) & 0xf;
2470 int cpm = insn & 0xf;
2471 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2472
2473 if (!arm_feature(env, ARM_FEATURE_V6K))
2474 return 0;
2475
2476 if (!(cpn == 13 && cpm == 0))
2477 return 0;
2478
2479 if (insn & ARM_CP_RW_BIT) {
2480 switch (op) {
2481 case 2:
2482 tmp = load_cpu_field(cp15.c13_tls1);
2483 break;
2484 case 3:
2485 tmp = load_cpu_field(cp15.c13_tls2);
2486 break;
2487 case 4:
2488 tmp = load_cpu_field(cp15.c13_tls3);
2489 break;
2490 default:
2491 return 0;
2492 }
2493 store_reg(s, rd, tmp);
2494
2495 } else {
2496 tmp = load_reg(s, rd);
2497 switch (op) {
2498 case 2:
2499 store_cpu_field(tmp, cp15.c13_tls1);
2500 break;
2501 case 3:
2502 store_cpu_field(tmp, cp15.c13_tls2);
2503 break;
2504 case 4:
2505 store_cpu_field(tmp, cp15.c13_tls3);
2506 break;
2507 default:
2508 dead_tmp(tmp);
2509 return 0;
2510 }
2511 }
2512 return 1;
2513 }
2514
2515 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2516 instruction is not defined. */
2517 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
2518 {
2519 uint32_t rd;
2520 TCGv tmp, tmp2;
2521
2522 /* M profile cores use memory mapped registers instead of cp15. */
2523 if (arm_feature(env, ARM_FEATURE_M))
2524 return 1;
2525
2526 if ((insn & (1 << 25)) == 0) {
2527 if (insn & (1 << 20)) {
2528 /* mrrc */
2529 return 1;
2530 }
2531 /* mcrr. Used for block cache operations, so implement as no-op. */
2532 return 0;
2533 }
2534 if ((insn & (1 << 4)) == 0) {
2535 /* cdp */
2536 return 1;
2537 }
2538 if (IS_USER(s) && !cp15_user_ok(insn)) {
2539 return 1;
2540 }
2541 if ((insn & 0x0fff0fff) == 0x0e070f90
2542 || (insn & 0x0fff0fff) == 0x0e070f58) {
2543 /* Wait for interrupt. */
2544 gen_set_pc_im(s->pc);
2545 s->is_jmp = DISAS_WFI;
2546 return 0;
2547 }
2548 rd = (insn >> 12) & 0xf;
2549
2550 if (cp15_tls_load_store(env, s, insn, rd))
2551 return 0;
2552
2553 tmp2 = tcg_const_i32(insn);
2554 if (insn & ARM_CP_RW_BIT) {
2555 tmp = new_tmp();
2556 gen_helper_get_cp15(tmp, cpu_env, tmp2);
2557 /* If the destination register is r15 then sets condition codes. */
2558 if (rd != 15)
2559 store_reg(s, rd, tmp);
2560 else
2561 dead_tmp(tmp);
2562 } else {
2563 tmp = load_reg(s, rd);
2564 gen_helper_set_cp15(cpu_env, tmp2, tmp);
2565 dead_tmp(tmp);
2566 /* Normally we would always end the TB here, but Linux
2567 * arch/arm/mach-pxa/sleep.S expects two instructions following
2568 * an MMU enable to execute from cache. Imitate this behaviour. */
2569 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2570 (insn & 0x0fff0fff) != 0x0e010f10)
2571 gen_lookup_tb(s);
2572 }
2573 tcg_temp_free_i32(tmp2);
2574 return 0;
2575 }
2576
2577 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2578 #define VFP_SREG(insn, bigbit, smallbit) \
2579 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2580 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2581 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2582 reg = (((insn) >> (bigbit)) & 0x0f) \
2583 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2584 } else { \
2585 if (insn & (1 << (smallbit))) \
2586 return 1; \
2587 reg = ((insn) >> (bigbit)) & 0x0f; \
2588 }} while (0)
2589
2590 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2591 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2592 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2593 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2594 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2595 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2596
2597 /* Move between integer and VFP cores. */
2598 static TCGv gen_vfp_mrs(void)
2599 {
2600 TCGv tmp = new_tmp();
2601 tcg_gen_mov_i32(tmp, cpu_F0s);
2602 return tmp;
2603 }
2604
2605 static void gen_vfp_msr(TCGv tmp)
2606 {
2607 tcg_gen_mov_i32(cpu_F0s, tmp);
2608 dead_tmp(tmp);
2609 }
2610
2611 static void gen_neon_dup_u8(TCGv var, int shift)
2612 {
2613 TCGv tmp = new_tmp();
2614 if (shift)
2615 tcg_gen_shri_i32(var, var, shift);
2616 tcg_gen_ext8u_i32(var, var);
2617 tcg_gen_shli_i32(tmp, var, 8);
2618 tcg_gen_or_i32(var, var, tmp);
2619 tcg_gen_shli_i32(tmp, var, 16);
2620 tcg_gen_or_i32(var, var, tmp);
2621 dead_tmp(tmp);
2622 }
2623
2624 static void gen_neon_dup_low16(TCGv var)
2625 {
2626 TCGv tmp = new_tmp();
2627 tcg_gen_ext16u_i32(var, var);
2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
2630 dead_tmp(tmp);
2631 }
2632
2633 static void gen_neon_dup_high16(TCGv var)
2634 {
2635 TCGv tmp = new_tmp();
2636 tcg_gen_andi_i32(var, var, 0xffff0000);
2637 tcg_gen_shri_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
2639 dead_tmp(tmp);
2640 }
2641
2642 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2643 (ie. an undefined instruction). */
2644 static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2645 {
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2647 int dp, veclen;
2648 TCGv addr;
2649 TCGv tmp;
2650 TCGv tmp2;
2651
2652 if (!arm_feature(env, ARM_FEATURE_VFP))
2653 return 1;
2654
2655 if (!s->vfp_enabled) {
2656 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2657 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2658 return 1;
2659 rn = (insn >> 16) & 0xf;
2660 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2661 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2662 return 1;
2663 }
2664 dp = ((insn & 0xf00) == 0xb00);
2665 switch ((insn >> 24) & 0xf) {
2666 case 0xe:
2667 if (insn & (1 << 4)) {
2668 /* single register transfer */
2669 rd = (insn >> 12) & 0xf;
2670 if (dp) {
2671 int size;
2672 int pass;
2673
2674 VFP_DREG_N(rn, insn);
2675 if (insn & 0xf)
2676 return 1;
2677 if (insn & 0x00c00060
2678 && !arm_feature(env, ARM_FEATURE_NEON))
2679 return 1;
2680
2681 pass = (insn >> 21) & 1;
2682 if (insn & (1 << 22)) {
2683 size = 0;
2684 offset = ((insn >> 5) & 3) * 8;
2685 } else if (insn & (1 << 5)) {
2686 size = 1;
2687 offset = (insn & (1 << 6)) ? 16 : 0;
2688 } else {
2689 size = 2;
2690 offset = 0;
2691 }
2692 if (insn & ARM_CP_RW_BIT) {
2693 /* vfp->arm */
2694 tmp = neon_load_reg(rn, pass);
2695 switch (size) {
2696 case 0:
2697 if (offset)
2698 tcg_gen_shri_i32(tmp, tmp, offset);
2699 if (insn & (1 << 23))
2700 gen_uxtb(tmp);
2701 else
2702 gen_sxtb(tmp);
2703 break;
2704 case 1:
2705 if (insn & (1 << 23)) {
2706 if (offset) {
2707 tcg_gen_shri_i32(tmp, tmp, 16);
2708 } else {
2709 gen_uxth(tmp);
2710 }
2711 } else {
2712 if (offset) {
2713 tcg_gen_sari_i32(tmp, tmp, 16);
2714 } else {
2715 gen_sxth(tmp);
2716 }
2717 }
2718 break;
2719 case 2:
2720 break;
2721 }
2722 store_reg(s, rd, tmp);
2723 } else {
2724 /* arm->vfp */
2725 tmp = load_reg(s, rd);
2726 if (insn & (1 << 23)) {
2727 /* VDUP */
2728 if (size == 0) {
2729 gen_neon_dup_u8(tmp, 0);
2730 } else if (size == 1) {
2731 gen_neon_dup_low16(tmp);
2732 }
2733 for (n = 0; n <= pass * 2; n++) {
2734 tmp2 = new_tmp();
2735 tcg_gen_mov_i32(tmp2, tmp);
2736 neon_store_reg(rn, n, tmp2);
2737 }
2738 neon_store_reg(rn, n, tmp);
2739 } else {
2740 /* VMOV */
2741 switch (size) {
2742 case 0:
2743 tmp2 = neon_load_reg(rn, pass);
2744 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2745 dead_tmp(tmp2);
2746 break;
2747 case 1:
2748 tmp2 = neon_load_reg(rn, pass);
2749 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2750 dead_tmp(tmp2);
2751 break;
2752 case 2:
2753 break;
2754 }
2755 neon_store_reg(rn, pass, tmp);
2756 }
2757 }
2758 } else { /* !dp */
2759 if ((insn & 0x6f) != 0x00)
2760 return 1;
2761 rn = VFP_SREG_N(insn);
2762 if (insn & ARM_CP_RW_BIT) {
2763 /* vfp->arm */
2764 if (insn & (1 << 21)) {
2765 /* system register */
2766 rn >>= 1;
2767
2768 switch (rn) {
2769 case ARM_VFP_FPSID:
2770 /* VFP2 allows access to FSID from userspace.
2771 VFP3 restricts all id registers to privileged
2772 accesses. */
2773 if (IS_USER(s)
2774 && arm_feature(env, ARM_FEATURE_VFP3))
2775 return 1;
2776 tmp = load_cpu_field(vfp.xregs[rn]);
2777 break;
2778 case ARM_VFP_FPEXC:
2779 if (IS_USER(s))
2780 return 1;
2781 tmp = load_cpu_field(vfp.xregs[rn]);
2782 break;
2783 case ARM_VFP_FPINST:
2784 case ARM_VFP_FPINST2:
2785 /* Not present in VFP3. */
2786 if (IS_USER(s)
2787 || arm_feature(env, ARM_FEATURE_VFP3))
2788 return 1;
2789 tmp = load_cpu_field(vfp.xregs[rn]);
2790 break;
2791 case ARM_VFP_FPSCR:
2792 if (rd == 15) {
2793 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2794 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2795 } else {
2796 tmp = new_tmp();
2797 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2798 }
2799 break;
2800 case ARM_VFP_MVFR0:
2801 case ARM_VFP_MVFR1:
2802 if (IS_USER(s)
2803 || !arm_feature(env, ARM_FEATURE_VFP3))
2804 return 1;
2805 tmp = load_cpu_field(vfp.xregs[rn]);
2806 break;
2807 default:
2808 return 1;
2809 }
2810 } else {
2811 gen_mov_F0_vreg(0, rn);
2812 tmp = gen_vfp_mrs();
2813 }
2814 if (rd == 15) {
2815 /* Set the 4 flag bits in the CPSR. */
2816 gen_set_nzcv(tmp);
2817 dead_tmp(tmp);
2818 } else {
2819 store_reg(s, rd, tmp);
2820 }
2821 } else {
2822 /* arm->vfp */
2823 tmp = load_reg(s, rd);
2824 if (insn & (1 << 21)) {
2825 rn >>= 1;
2826 /* system register */
2827 switch (rn) {
2828 case ARM_VFP_FPSID:
2829 case ARM_VFP_MVFR0:
2830 case ARM_VFP_MVFR1:
2831 /* Writes are ignored. */
2832 break;
2833 case ARM_VFP_FPSCR:
2834 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2835 dead_tmp(tmp);
2836 gen_lookup_tb(s);
2837 break;
2838 case ARM_VFP_FPEXC:
2839 if (IS_USER(s))
2840 return 1;
2841 /* TODO: VFP subarchitecture support.
2842 * For now, keep the EN bit only */
2843 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
2844 store_cpu_field(tmp, vfp.xregs[rn]);
2845 gen_lookup_tb(s);
2846 break;
2847 case ARM_VFP_FPINST:
2848 case ARM_VFP_FPINST2:
2849 store_cpu_field(tmp, vfp.xregs[rn]);
2850 break;
2851 default:
2852 return 1;
2853 }
2854 } else {
2855 gen_vfp_msr(tmp);
2856 gen_mov_vreg_F0(0, rn);
2857 }
2858 }
2859 }
2860 } else {
2861 /* data processing */
2862 /* The opcode is in bits 23, 21, 20 and 6. */
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2864 if (dp) {
2865 if (op == 15) {
2866 /* rn is opcode */
2867 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2868 } else {
2869 /* rn is register number */
2870 VFP_DREG_N(rn, insn);
2871 }
2872
2873 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2874 /* Integer or single precision destination. */
2875 rd = VFP_SREG_D(insn);
2876 } else {
2877 VFP_DREG_D(rd, insn);
2878 }
2879 if (op == 15 &&
2880 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2881 /* VCVT from int is always from S reg regardless of dp bit.
2882 * VCVT with immediate frac_bits has same format as SREG_M
2883 */
2884 rm = VFP_SREG_M(insn);
2885 } else {
2886 VFP_DREG_M(rm, insn);
2887 }
2888 } else {
2889 rn = VFP_SREG_N(insn);
2890 if (op == 15 && rn == 15) {
2891 /* Double precision destination. */
2892 VFP_DREG_D(rd, insn);
2893 } else {
2894 rd = VFP_SREG_D(insn);
2895 }
2896 /* NB that we implicitly rely on the encoding for the frac_bits
2897 * in VCVT of fixed to float being the same as that of an SREG_M
2898 */
2899 rm = VFP_SREG_M(insn);
2900 }
2901
2902 veclen = s->vec_len;
2903 if (op == 15 && rn > 3)
2904 veclen = 0;
2905
2906 /* Shut up compiler warnings. */
2907 delta_m = 0;
2908 delta_d = 0;
2909 bank_mask = 0;
2910
2911 if (veclen > 0) {
2912 if (dp)
2913 bank_mask = 0xc;
2914 else
2915 bank_mask = 0x18;
2916
2917 /* Figure out what type of vector operation this is. */
2918 if ((rd & bank_mask) == 0) {
2919 /* scalar */
2920 veclen = 0;
2921 } else {
2922 if (dp)
2923 delta_d = (s->vec_stride >> 1) + 1;
2924 else
2925 delta_d = s->vec_stride + 1;
2926
2927 if ((rm & bank_mask) == 0) {
2928 /* mixed scalar/vector */
2929 delta_m = 0;
2930 } else {
2931 /* vector */
2932 delta_m = delta_d;
2933 }
2934 }
2935 }
2936
2937 /* Load the initial operands. */
2938 if (op == 15) {
2939 switch (rn) {
2940 case 16:
2941 case 17:
2942 /* Integer source */
2943 gen_mov_F0_vreg(0, rm);
2944 break;
2945 case 8:
2946 case 9:
2947 /* Compare */
2948 gen_mov_F0_vreg(dp, rd);
2949 gen_mov_F1_vreg(dp, rm);
2950 break;
2951 case 10:
2952 case 11:
2953 /* Compare with zero */
2954 gen_mov_F0_vreg(dp, rd);
2955 gen_vfp_F1_ld0(dp);
2956 break;
2957 case 20:
2958 case 21:
2959 case 22:
2960 case 23:
2961 case 28:
2962 case 29:
2963 case 30:
2964 case 31:
2965 /* Source and destination the same. */
2966 gen_mov_F0_vreg(dp, rd);
2967 break;
2968 default:
2969 /* One source operand. */
2970 gen_mov_F0_vreg(dp, rm);
2971 break;
2972 }
2973 } else {
2974 /* Two source operands. */
2975 gen_mov_F0_vreg(dp, rn);
2976 gen_mov_F1_vreg(dp, rm);
2977 }
2978
2979 for (;;) {
2980 /* Perform the calculation. */
2981 switch (op) {
2982 case 0: /* mac: fd + (fn * fm) */
2983 gen_vfp_mul(dp);
2984 gen_mov_F1_vreg(dp, rd);
2985 gen_vfp_add(dp);
2986 break;
2987 case 1: /* nmac: fd - (fn * fm) */
2988 gen_vfp_mul(dp);
2989 gen_vfp_neg(dp);
2990 gen_mov_F1_vreg(dp, rd);
2991 gen_vfp_add(dp);
2992 break;
2993 case 2: /* msc: -fd + (fn * fm) */
2994 gen_vfp_mul(dp);
2995 gen_mov_F1_vreg(dp, rd);
2996 gen_vfp_sub(dp);
2997 break;
2998 case 3: /* nmsc: -fd - (fn * fm) */
2999 gen_vfp_mul(dp);
3000 gen_vfp_neg(dp);
3001 gen_mov_F1_vreg(dp, rd);
3002 gen_vfp_sub(dp);
3003 break;
3004 case 4: /* mul: fn * fm */
3005 gen_vfp_mul(dp);
3006 break;
3007 case 5: /* nmul: -(fn * fm) */
3008 gen_vfp_mul(dp);
3009 gen_vfp_neg(dp);
3010 break;
3011 case 6: /* add: fn + fm */
3012 gen_vfp_add(dp);
3013 break;
3014 case 7: /* sub: fn - fm */
3015 gen_vfp_sub(dp);
3016 break;
3017 case 8: /* div: fn / fm */
3018 gen_vfp_div(dp);
3019 break;
3020 case 14: /* fconst */
3021 if (!arm_feature(env, ARM_FEATURE_VFP3))
3022 return 1;
3023
3024 n = (insn << 12) & 0x80000000;
3025 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3026 if (dp) {
3027 if (i & 0x40)
3028 i |= 0x3f80;
3029 else
3030 i |= 0x4000;
3031 n |= i << 16;
3032 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3033 } else {
3034 if (i & 0x40)
3035 i |= 0x780;
3036 else
3037 i |= 0x800;
3038 n |= i << 19;
3039 tcg_gen_movi_i32(cpu_F0s, n);
3040 }
3041 break;
3042 case 15: /* extension space */
3043 switch (rn) {
3044 case 0: /* cpy */
3045 /* no-op */
3046 break;
3047 case 1: /* abs */
3048 gen_vfp_abs(dp);
3049 break;
3050 case 2: /* neg */
3051 gen_vfp_neg(dp);
3052 break;
3053 case 3: /* sqrt */
3054 gen_vfp_sqrt(dp);
3055 break;
3056 case 4: /* vcvtb.f32.f16 */
3057 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3058 return 1;
3059 tmp = gen_vfp_mrs();
3060 tcg_gen_ext16u_i32(tmp, tmp);
3061 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3062 dead_tmp(tmp);
3063 break;
3064 case 5: /* vcvtt.f32.f16 */
3065 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3066 return 1;
3067 tmp = gen_vfp_mrs();
3068 tcg_gen_shri_i32(tmp, tmp, 16);
3069 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3070 dead_tmp(tmp);
3071 break;
3072 case 6: /* vcvtb.f16.f32 */
3073 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3074 return 1;
3075 tmp = new_tmp();
3076 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3077 gen_mov_F0_vreg(0, rd);
3078 tmp2 = gen_vfp_mrs();
3079 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3080 tcg_gen_or_i32(tmp, tmp, tmp2);
3081 dead_tmp(tmp2);
3082 gen_vfp_msr(tmp);
3083 break;
3084 case 7: /* vcvtt.f16.f32 */
3085 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3086 return 1;
3087 tmp = new_tmp();
3088 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3089 tcg_gen_shli_i32(tmp, tmp, 16);
3090 gen_mov_F0_vreg(0, rd);
3091 tmp2 = gen_vfp_mrs();
3092 tcg_gen_ext16u_i32(tmp2, tmp2);
3093 tcg_gen_or_i32(tmp, tmp, tmp2);
3094 dead_tmp(tmp2);
3095 gen_vfp_msr(tmp);
3096 break;
3097 case 8: /* cmp */
3098 gen_vfp_cmp(dp);
3099 break;
3100 case 9: /* cmpe */
3101 gen_vfp_cmpe(dp);
3102 break;
3103 case 10: /* cmpz */
3104 gen_vfp_cmp(dp);
3105 break;
3106 case 11: /* cmpez */
3107 gen_vfp_F1_ld0(dp);
3108 gen_vfp_cmpe(dp);
3109 break;
3110 case 15: /* single<->double conversion */
3111 if (dp)
3112 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3113 else
3114 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3115 break;
3116 case 16: /* fuito */
3117 gen_vfp_uito(dp);
3118 break;
3119 case 17: /* fsito */
3120 gen_vfp_sito(dp);
3121 break;
3122 case 20: /* fshto */
3123 if (!arm_feature(env, ARM_FEATURE_VFP3))
3124 return 1;
3125 gen_vfp_shto(dp, 16 - rm);
3126 break;
3127 case 21: /* fslto */
3128 if (!arm_feature(env, ARM_FEATURE_VFP3))
3129 return 1;
3130 gen_vfp_slto(dp, 32 - rm);
3131 break;
3132 case 22: /* fuhto */
3133 if (!arm_feature(env, ARM_FEATURE_VFP3))
3134 return 1;
3135 gen_vfp_uhto(dp, 16 - rm);
3136 break;
3137 case 23: /* fulto */
3138 if (!arm_feature(env, ARM_FEATURE_VFP3))
3139 return 1;
3140 gen_vfp_ulto(dp, 32 - rm);
3141 break;
3142 case 24: /* ftoui */
3143 gen_vfp_toui(dp);
3144 break;
3145 case 25: /* ftouiz */
3146 gen_vfp_touiz(dp);
3147 break;
3148 case 26: /* ftosi */
3149 gen_vfp_tosi(dp);
3150 break;
3151 case 27: /* ftosiz */
3152 gen_vfp_tosiz(dp);
3153 break;
3154 case 28: /* ftosh */
3155 if (!arm_feature(env, ARM_FEATURE_VFP3))
3156 return 1;
3157 gen_vfp_tosh(dp, 16 - rm);
3158 break;
3159 case 29: /* ftosl */
3160 if (!arm_feature(env, ARM_FEATURE_VFP3))
3161 return 1;
3162 gen_vfp_tosl(dp, 32 - rm);
3163 break;
3164 case 30: /* ftouh */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
3167 gen_vfp_touh(dp, 16 - rm);
3168 break;
3169 case 31: /* ftoul */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
3172 gen_vfp_toul(dp, 32 - rm);
3173 break;
3174 default: /* undefined */
3175 printf ("rn:%d\n", rn);
3176 return 1;
3177 }
3178 break;
3179 default: /* undefined */
3180 printf ("op:%d\n", op);
3181 return 1;
3182 }
3183
3184 /* Write back the result. */
3185 if (op == 15 && (rn >= 8 && rn <= 11))
3186 ; /* Comparison, do nothing. */
3187 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3188 /* VCVT double to int: always integer result. */
3189 gen_mov_vreg_F0(0, rd);
3190 else if (op == 15 && rn == 15)
3191 /* conversion */
3192 gen_mov_vreg_F0(!dp, rd);
3193 else
3194 gen_mov_vreg_F0(dp, rd);
3195
3196 /* break out of the loop if we have finished */
3197 if (veclen == 0)
3198 break;
3199
3200 if (op == 15 && delta_m == 0) {
3201 /* single source one-many */
3202 while (veclen--) {
3203 rd = ((rd + delta_d) & (bank_mask - 1))
3204 | (rd & bank_mask);
3205 gen_mov_vreg_F0(dp, rd);
3206 }
3207 break;
3208 }
3209 /* Setup the next operands. */
3210 veclen--;
3211 rd = ((rd + delta_d) & (bank_mask - 1))
3212 | (rd & bank_mask);
3213
3214 if (op == 15) {
3215 /* One source operand. */
3216 rm = ((rm + delta_m) & (bank_mask - 1))
3217 | (rm & bank_mask);
3218 gen_mov_F0_vreg(dp, rm);
3219 } else {
3220 /* Two source operands. */
3221 rn = ((rn + delta_d) & (bank_mask - 1))
3222 | (rn & bank_mask);
3223 gen_mov_F0_vreg(dp, rn);
3224 if (delta_m) {
3225 rm = ((rm + delta_m) & (bank_mask - 1))
3226 | (rm & bank_mask);
3227 gen_mov_F1_vreg(dp, rm);
3228 }
3229 }
3230 }
3231 }
3232 break;
3233 case 0xc:
3234 case 0xd:
3235 if (dp && (insn & 0x03e00000) == 0x00400000) {
3236 /* two-register transfer */
3237 rn = (insn >> 16) & 0xf;
3238 rd = (insn >> 12) & 0xf;
3239 if (dp) {
3240 VFP_DREG_M(rm, insn);
3241 } else {
3242 rm = VFP_SREG_M(insn);
3243 }
3244
3245 if (insn & ARM_CP_RW_BIT) {
3246 /* vfp->arm */
3247 if (dp) {
3248 gen_mov_F0_vreg(0, rm * 2);
3249 tmp = gen_vfp_mrs();
3250 store_reg(s, rd, tmp);
3251 gen_mov_F0_vreg(0, rm * 2 + 1);
3252 tmp = gen_vfp_mrs();
3253 store_reg(s, rn, tmp);
3254 } else {
3255 gen_mov_F0_vreg(0, rm);
3256 tmp = gen_vfp_mrs();
3257 store_reg(s, rn, tmp);
3258 gen_mov_F0_vreg(0, rm + 1);
3259 tmp = gen_vfp_mrs();
3260 store_reg(s, rd, tmp);
3261 }
3262 } else {
3263 /* arm->vfp */
3264 if (dp) {
3265 tmp = load_reg(s, rd);
3266 gen_vfp_msr(tmp);
3267 gen_mov_vreg_F0(0, rm * 2);
3268 tmp = load_reg(s, rn);
3269 gen_vfp_msr(tmp);
3270 gen_mov_vreg_F0(0, rm * 2 + 1);
3271 } else {
3272 tmp = load_reg(s, rn);
3273 gen_vfp_msr(tmp);
3274 gen_mov_vreg_F0(0, rm);
3275 tmp = load_reg(s, rd);
3276 gen_vfp_msr(tmp);
3277 gen_mov_vreg_F0(0, rm + 1);
3278 }
3279 }
3280 } else {
3281 /* Load/store */
3282 rn = (insn >> 16) & 0xf;
3283 if (dp)
3284 VFP_DREG_D(rd, insn);
3285 else
3286 rd = VFP_SREG_D(insn);
3287 if (s->thumb && rn == 15) {
3288 addr = new_tmp();
3289 tcg_gen_movi_i32(addr, s->pc & ~2);
3290 } else {
3291 addr = load_reg(s, rn);
3292 }
3293 if ((insn & 0x01200000) == 0x01000000) {
3294 /* Single load/store */
3295 offset = (insn & 0xff) << 2;
3296 if ((insn & (1 << 23)) == 0)
3297 offset = -offset;
3298 tcg_gen_addi_i32(addr, addr, offset);
3299 if (insn & (1 << 20)) {
3300 gen_vfp_ld(s, dp, addr);
3301 gen_mov_vreg_F0(dp, rd);
3302 } else {
3303 gen_mov_F0_vreg(dp, rd);
3304 gen_vfp_st(s, dp, addr);
3305 }
3306 dead_tmp(addr);
3307 } else {
3308 /* load/store multiple */
3309 if (dp)
3310 n = (insn >> 1) & 0x7f;
3311 else
3312 n = insn & 0xff;
3313
3314 if (insn & (1 << 24)) /* pre-decrement */
3315 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
3316
3317 if (dp)
3318 offset = 8;
3319 else
3320 offset = 4;
3321 for (i = 0; i < n; i++) {
3322 if (insn & ARM_CP_RW_BIT) {
3323 /* load */
3324 gen_vfp_ld(s, dp, addr);
3325 gen_mov_vreg_F0(dp, rd + i);
3326 } else {
3327 /* store */
3328 gen_mov_F0_vreg(dp, rd + i);
3329 gen_vfp_st(s, dp, addr);
3330 }
3331 tcg_gen_addi_i32(addr, addr, offset);
3332 }
3333 if (insn & (1 << 21)) {
3334 /* writeback */
3335 if (insn & (1 << 24))
3336 offset = -offset * n;
3337 else if (dp && (insn & 1))
3338 offset = 4;
3339 else
3340 offset = 0;
3341
3342 if (offset != 0)
3343 tcg_gen_addi_i32(addr, addr, offset);
3344 store_reg(s, rn, addr);
3345 } else {
3346 dead_tmp(addr);
3347 }
3348 }
3349 }
3350 break;
3351 default:
3352 /* Should never happen. */
3353 return 1;
3354 }
3355 return 0;
3356 }
3357
3358 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
3359 {
3360 TranslationBlock *tb;
3361
3362 tb = s->tb;
3363 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3364 tcg_gen_goto_tb(n);
3365 gen_set_pc_im(dest);
3366 tcg_gen_exit_tb((long)tb + n);
3367 } else {
3368 gen_set_pc_im(dest);
3369 tcg_gen_exit_tb(0);
3370 }
3371 }
3372
3373 static inline void gen_jmp (DisasContext *s, uint32_t dest)
3374 {
3375 if (unlikely(s->singlestep_enabled)) {
3376 /* An indirect jump so that we still trigger the debug exception. */
3377 if (s->thumb)
3378 dest |= 1;
3379 gen_bx_im(s, dest);
3380 } else {
3381 gen_goto_tb(s, 0, dest);
3382 s->is_jmp = DISAS_TB_JUMP;
3383 }
3384 }
3385
3386 static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
3387 {
3388 if (x)
3389 tcg_gen_sari_i32(t0, t0, 16);
3390 else
3391 gen_sxth(t0);
3392 if (y)
3393 tcg_gen_sari_i32(t1, t1, 16);
3394 else
3395 gen_sxth(t1);
3396 tcg_gen_mul_i32(t0, t0, t1);
3397 }
3398
3399 /* Return the mask of PSR bits set by a MSR instruction. */
3400 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
3401 uint32_t mask;
3402
3403 mask = 0;
3404 if (flags & (1 << 0))
3405 mask |= 0xff;
3406 if (flags & (1 << 1))
3407 mask |= 0xff00;
3408 if (flags & (1 << 2))
3409 mask |= 0xff0000;
3410 if (flags & (1 << 3))
3411 mask |= 0xff000000;
3412
3413 /* Mask out undefined bits. */
3414 mask &= ~CPSR_RESERVED;
3415 if (!arm_feature(env, ARM_FEATURE_V6))
3416 mask &= ~(CPSR_E | CPSR_GE);
3417 if (!arm_feature(env, ARM_FEATURE_THUMB2))
3418 mask &= ~CPSR_IT;
3419 /* Mask out execution state bits. */
3420 if (!spsr)
3421 mask &= ~CPSR_EXEC;
3422 /* Mask out privileged bits. */
3423 if (IS_USER(s))
3424 mask &= CPSR_USER;
3425 return mask;
3426 }
3427
3428 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3429 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
3430 {
3431 TCGv tmp;
3432 if (spsr) {
3433 /* ??? This is also undefined in system mode. */
3434 if (IS_USER(s))
3435 return 1;
3436
3437 tmp = load_cpu_field(spsr);
3438 tcg_gen_andi_i32(tmp, tmp, ~mask);
3439 tcg_gen_andi_i32(t0, t0, mask);
3440 tcg_gen_or_i32(tmp, tmp, t0);
3441 store_cpu_field(tmp, spsr);
3442 } else {
3443 gen_set_cpsr(t0, mask);
3444 }
3445 dead_tmp(t0);
3446 gen_lookup_tb(s);
3447 return 0;
3448 }
3449
3450 /* Returns nonzero if access to the PSR is not permitted. */
3451 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3452 {
3453 TCGv tmp;
3454 tmp = new_tmp();
3455 tcg_gen_movi_i32(tmp, val);
3456 return gen_set_psr(s, mask, spsr, tmp);
3457 }
3458
3459 /* Generate an old-style exception return. Marks pc as dead. */
3460 static void gen_exception_return(DisasContext *s, TCGv pc)
3461 {
3462 TCGv tmp;
3463 store_reg(s, 15, pc);
3464 tmp = load_cpu_field(spsr);
3465 gen_set_cpsr(tmp, 0xffffffff);
3466 dead_tmp(tmp);
3467 s->is_jmp = DISAS_UPDATE;
3468 }
3469
3470 /* Generate a v6 exception return. Marks both values as dead. */
3471 static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
3472 {
3473 gen_set_cpsr(cpsr, 0xffffffff);
3474 dead_tmp(cpsr);
3475 store_reg(s, 15, pc);
3476 s->is_jmp = DISAS_UPDATE;
3477 }
3478
3479 static inline void
3480 gen_set_condexec (DisasContext *s)
3481 {
3482 if (s->condexec_mask) {
3483 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3484 TCGv tmp = new_tmp();
3485 tcg_gen_movi_i32(tmp, val);
3486 store_cpu_field(tmp, condexec_bits);
3487 }
3488 }
3489
3490 static void gen_exception_insn(DisasContext *s, int offset, int excp)
3491 {
3492 gen_set_condexec(s);
3493 gen_set_pc_im(s->pc - offset);
3494 gen_exception(excp);
3495 s->is_jmp = DISAS_JUMP;
3496 }
3497
3498 static void gen_nop_hint(DisasContext *s, int val)
3499 {
3500 switch (val) {
3501 case 3: /* wfi */
3502 gen_set_pc_im(s->pc);
3503 s->is_jmp = DISAS_WFI;
3504 break;
3505 case 2: /* wfe */
3506 case 4: /* sev */
3507 /* TODO: Implement SEV and WFE. May help SMP performance. */
3508 default: /* nop */
3509 break;
3510 }
3511 }
3512
3513 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3514
3515 static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
3516 {
3517 switch (size) {
3518 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3519 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3520 case 2: tcg_gen_add_i32(t0, t0, t1); break;
3521 default: return 1;
3522 }
3523 return 0;
3524 }
3525
3526 static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
3527 {
3528 switch (size) {
3529 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3530 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3531 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
3532 default: return;
3533 }
3534 }
3535
3536 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3537 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3538 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3539 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3540 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3541
3542 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3543 switch ((size << 1) | u) { \
3544 case 0: \
3545 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3546 break; \
3547 case 1: \
3548 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3549 break; \
3550 case 2: \
3551 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3552 break; \
3553 case 3: \
3554 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3555 break; \
3556 case 4: \
3557 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3558 break; \
3559 case 5: \
3560 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3561 break; \
3562 default: return 1; \
3563 }} while (0)
3564
3565 #define GEN_NEON_INTEGER_OP(name) do { \
3566 switch ((size << 1) | u) { \
3567 case 0: \
3568 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3569 break; \
3570 case 1: \
3571 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3572 break; \
3573 case 2: \
3574 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3575 break; \
3576 case 3: \
3577 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3578 break; \
3579 case 4: \
3580 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3581 break; \
3582 case 5: \
3583 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3584 break; \
3585 default: return 1; \
3586 }} while (0)
3587
3588 static TCGv neon_load_scratch(int scratch)
3589 {
3590 TCGv tmp = new_tmp();
3591 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3592 return tmp;
3593 }
3594
3595 static void neon_store_scratch(int scratch, TCGv var)
3596 {
3597 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3598 dead_tmp(var);
3599 }
3600
3601 static inline TCGv neon_get_scalar(int size, int reg)
3602 {
3603 TCGv tmp;
3604 if (size == 1) {
3605 tmp = neon_load_reg(reg & 7, reg >> 4);
3606 if (reg & 8) {
3607 gen_neon_dup_high16(tmp);
3608 } else {
3609 gen_neon_dup_low16(tmp);
3610 }
3611 } else {
3612 tmp = neon_load_reg(reg & 15, reg >> 4);
3613 }
3614 return tmp;
3615 }
3616
3617 static int gen_neon_unzip(int rd, int rm, int size, int q)
3618 {
3619 TCGv tmp, tmp2;
3620 if (size == 3 || (!q && size == 2)) {
3621 return 1;
3622 }
3623 tmp = tcg_const_i32(rd);
3624 tmp2 = tcg_const_i32(rm);
3625 if (q) {
3626 switch (size) {
3627 case 0:
3628 gen_helper_neon_qunzip8(cpu_env, tmp, tmp2);
3629 break;
3630 case 1:
3631 gen_helper_neon_qunzip16(cpu_env, tmp, tmp2);
3632 break;
3633 case 2:
3634 gen_helper_neon_qunzip32(cpu_env, tmp, tmp2);
3635 break;
3636 default:
3637 abort();
3638 }
3639 } else {
3640 switch (size) {
3641 case 0:
3642 gen_helper_neon_unzip8(cpu_env, tmp, tmp2);
3643 break;
3644 case 1:
3645 gen_helper_neon_unzip16(cpu_env, tmp, tmp2);
3646 break;
3647 default:
3648 abort();
3649 }
3650 }
3651 tcg_temp_free_i32(tmp);
3652 tcg_temp_free_i32(tmp2);
3653 return 0;
3654 }
3655
3656 static int gen_neon_zip(int rd, int rm, int size, int q)
3657 {
3658 TCGv tmp, tmp2;
3659 if (size == 3 || (!q && size == 2)) {
3660 return 1;
3661 }
3662 tmp = tcg_const_i32(rd);
3663 tmp2 = tcg_const_i32(rm);
3664 if (q) {
3665 switch (size) {
3666 case 0:
3667 gen_helper_neon_qzip8(cpu_env, tmp, tmp2);
3668 break;
3669 case 1:
3670 gen_helper_neon_qzip16(cpu_env, tmp, tmp2);
3671 break;
3672 case 2:
3673 gen_helper_neon_qzip32(cpu_env, tmp, tmp2);
3674 break;
3675 default:
3676 abort();
3677 }
3678 } else {
3679 switch (size) {
3680 case 0:
3681 gen_helper_neon_zip8(cpu_env, tmp, tmp2);
3682 break;
3683 case 1:
3684 gen_helper_neon_zip16(cpu_env, tmp, tmp2);
3685 break;
3686 default:
3687 abort();
3688 }
3689 }
3690 tcg_temp_free_i32(tmp);
3691 tcg_temp_free_i32(tmp2);
3692 return 0;
3693 }
3694
3695 static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3696 {
3697 TCGv rd, tmp;
3698
3699 rd = new_tmp();
3700 tmp = new_tmp();
3701
3702 tcg_gen_shli_i32(rd, t0, 8);
3703 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3704 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3705 tcg_gen_or_i32(rd, rd, tmp);
3706
3707 tcg_gen_shri_i32(t1, t1, 8);
3708 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3709 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3710 tcg_gen_or_i32(t1, t1, tmp);
3711 tcg_gen_mov_i32(t0, rd);
3712
3713 dead_tmp(tmp);
3714 dead_tmp(rd);
3715 }
3716
3717 static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3718 {
3719 TCGv rd, tmp;
3720
3721 rd = new_tmp();
3722 tmp = new_tmp();
3723
3724 tcg_gen_shli_i32(rd, t0, 16);
3725 tcg_gen_andi_i32(tmp, t1, 0xffff);
3726 tcg_gen_or_i32(rd, rd, tmp);
3727 tcg_gen_shri_i32(t1, t1, 16);
3728 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3729 tcg_gen_or_i32(t1, t1, tmp);
3730 tcg_gen_mov_i32(t0, rd);
3731
3732 dead_tmp(tmp);
3733 dead_tmp(rd);
3734 }
3735
3736
3737 static struct {
3738 int nregs;
3739 int interleave;
3740 int spacing;
3741 } neon_ls_element_type[11] = {
3742 {4, 4, 1},
3743 {4, 4, 2},
3744 {4, 1, 1},
3745 {4, 2, 1},
3746 {3, 3, 1},
3747 {3, 3, 2},
3748 {3, 1, 1},
3749 {1, 1, 1},
3750 {2, 2, 1},
3751 {2, 2, 2},
3752 {2, 1, 1}
3753 };
3754
3755 /* Translate a NEON load/store element instruction. Return nonzero if the
3756 instruction is invalid. */
3757 static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3758 {
3759 int rd, rn, rm;
3760 int op;
3761 int nregs;
3762 int interleave;
3763 int spacing;
3764 int stride;
3765 int size;
3766 int reg;
3767 int pass;
3768 int load;
3769 int shift;
3770 int n;
3771 TCGv addr;
3772 TCGv tmp;
3773 TCGv tmp2;
3774 TCGv_i64 tmp64;
3775
3776 if (!s->vfp_enabled)
3777 return 1;
3778 VFP_DREG_D(rd, insn);
3779 rn = (insn >> 16) & 0xf;
3780 rm = insn & 0xf;
3781 load = (insn & (1 << 21)) != 0;
3782 addr = new_tmp();
3783 if ((insn & (1 << 23)) == 0) {
3784 /* Load store all elements. */
3785 op = (insn >> 8) & 0xf;
3786 size = (insn >> 6) & 3;
3787 if (op > 10)
3788 return 1;
3789 nregs = neon_ls_element_type[op].nregs;
3790 interleave = neon_ls_element_type[op].interleave;
3791 spacing = neon_ls_element_type[op].spacing;
3792 if (size == 3 && (interleave | spacing) != 1)
3793 return 1;
3794 load_reg_var(s, addr, rn);
3795 stride = (1 << size) * interleave;
3796 for (reg = 0; reg < nregs; reg++) {
3797 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3798 load_reg_var(s, addr, rn);
3799 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
3800 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3801 load_reg_var(s, addr, rn);
3802 tcg_gen_addi_i32(addr, addr, 1 << size);
3803 }
3804 if (size == 3) {
3805 if (load) {
3806 tmp64 = gen_ld64(addr, IS_USER(s));
3807 neon_store_reg64(tmp64, rd);
3808 tcg_temp_free_i64(tmp64);
3809 } else {
3810 tmp64 = tcg_temp_new_i64();
3811 neon_load_reg64(tmp64, rd);
3812 gen_st64(tmp64, addr, IS_USER(s));
3813 }
3814 tcg_gen_addi_i32(addr, addr, stride);
3815 } else {
3816 for (pass = 0; pass < 2; pass++) {
3817 if (size == 2) {
3818 if (load) {
3819 tmp = gen_ld32(addr, IS_USER(s));
3820 neon_store_reg(rd, pass, tmp);
3821 } else {
3822 tmp = neon_load_reg(rd, pass);
3823 gen_st32(tmp, addr, IS_USER(s));
3824 }
3825 tcg_gen_addi_i32(addr, addr, stride);
3826 } else if (size == 1) {
3827 if (load) {
3828 tmp = gen_ld16u(addr, IS_USER(s));
3829 tcg_gen_addi_i32(addr, addr, stride);
3830 tmp2 = gen_ld16u(addr, IS_USER(s));
3831 tcg_gen_addi_i32(addr, addr, stride);
3832 tcg_gen_shli_i32(tmp2, tmp2, 16);
3833 tcg_gen_or_i32(tmp, tmp, tmp2);
3834 dead_tmp(tmp2);
3835 neon_store_reg(rd, pass, tmp);
3836 } else {
3837 tmp = neon_load_reg(rd, pass);
3838 tmp2 = new_tmp();
3839 tcg_gen_shri_i32(tmp2, tmp, 16);
3840 gen_st16(tmp, addr, IS_USER(s));
3841 tcg_gen_addi_i32(addr, addr, stride);
3842 gen_st16(tmp2, addr, IS_USER(s));
3843 tcg_gen_addi_i32(addr, addr, stride);
3844 }
3845 } else /* size == 0 */ {
3846 if (load) {
3847 TCGV_UNUSED(tmp2);
3848 for (n = 0; n < 4; n++) {
3849 tmp = gen_ld8u(addr, IS_USER(s));
3850 tcg_gen_addi_i32(addr, addr, stride);
3851 if (n == 0) {
3852 tmp2 = tmp;
3853 } else {
3854 tcg_gen_shli_i32(tmp, tmp, n * 8);
3855 tcg_gen_or_i32(tmp2, tmp2, tmp);
3856 dead_tmp(tmp);
3857 }
3858 }
3859 neon_store_reg(rd, pass, tmp2);
3860 } else {
3861 tmp2 = neon_load_reg(rd, pass);
3862 for (n = 0; n < 4; n++) {
3863 tmp = new_tmp();
3864 if (n == 0) {
3865 tcg_gen_mov_i32(tmp, tmp2);
3866 } else {
3867 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3868 }
3869 gen_st8(tmp, addr, IS_USER(s));
3870 tcg_gen_addi_i32(addr, addr, stride);
3871 }
3872 dead_tmp(tmp2);
3873 }
3874 }
3875 }
3876 }
3877 rd += spacing;
3878 }
3879 stride = nregs * 8;
3880 } else {
3881 size = (insn >> 10) & 3;
3882 if (size == 3) {
3883 /* Load single element to all lanes. */
3884 if (!load)
3885 return 1;
3886 size = (insn >> 6) & 3;
3887 nregs = ((insn >> 8) & 3) + 1;
3888 stride = (insn & (1 << 5)) ? 2 : 1;
3889 load_reg_var(s, addr, rn);
3890 for (reg = 0; reg < nregs; reg++) {
3891 switch (size) {
3892 case 0:
3893 tmp = gen_ld8u(addr, IS_USER(s));
3894 gen_neon_dup_u8(tmp, 0);
3895 break;
3896 case 1:
3897 tmp = gen_ld16u(addr, IS_USER(s));
3898 gen_neon_dup_low16(tmp);
3899 break;
3900 case 2:
3901 tmp = gen_ld32(addr, IS_USER(s));
3902 break;
3903 case 3:
3904 return 1;
3905 default: /* Avoid compiler warnings. */
3906 abort();
3907 }
3908 tcg_gen_addi_i32(addr, addr, 1 << size);
3909 tmp2 = new_tmp();
3910 tcg_gen_mov_i32(tmp2, tmp);
3911 neon_store_reg(rd, 0, tmp2);
3912 neon_store_reg(rd, 1, tmp);
3913 rd += stride;
3914 }
3915 stride = (1 << size) * nregs;
3916 } else {
3917 /* Single element. */
3918 pass = (insn >> 7) & 1;
3919 switch (size) {
3920 case 0:
3921 shift = ((insn >> 5) & 3) * 8;
3922 stride = 1;
3923 break;
3924 case 1:
3925 shift = ((insn >> 6) & 1) * 16;
3926 stride = (insn & (1 << 5)) ? 2 : 1;
3927 break;
3928 case 2:
3929 shift = 0;
3930 stride = (insn & (1 << 6)) ? 2 : 1;
3931 break;
3932 default:
3933 abort();
3934 }
3935 nregs = ((insn >> 8) & 3) + 1;
3936 load_reg_var(s, addr, rn);
3937 for (reg = 0; reg < nregs; reg++) {
3938 if (load) {
3939 switch (size) {
3940 case 0:
3941 tmp = gen_ld8u(addr, IS_USER(s));
3942 break;
3943 case 1:
3944 tmp = gen_ld16u(addr, IS_USER(s));
3945 break;
3946 case 2:
3947 tmp = gen_ld32(addr, IS_USER(s));
3948 break;
3949 default: /* Avoid compiler warnings. */
3950 abort();
3951 }
3952 if (size != 2) {
3953 tmp2 = neon_load_reg(rd, pass);
3954 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3955 dead_tmp(tmp2);
3956 }
3957 neon_store_reg(rd, pass, tmp);
3958 } else { /* Store */
3959 tmp = neon_load_reg(rd, pass);
3960 if (shift)
3961 tcg_gen_shri_i32(tmp, tmp, shift);
3962 switch (size) {
3963 case 0:
3964 gen_st8(tmp, addr, IS_USER(s));
3965 break;
3966 case 1:
3967 gen_st16(tmp, addr, IS_USER(s));
3968 break;
3969 case 2:
3970 gen_st32(tmp, addr, IS_USER(s));
3971 break;
3972 }
3973 }
3974 rd += stride;
3975 tcg_gen_addi_i32(addr, addr, 1 << size);
3976 }
3977 stride = nregs * (1 << size);
3978 }
3979 }
3980 dead_tmp(addr);
3981 if (rm != 15) {
3982 TCGv base;
3983
3984 base = load_reg(s, rn);
3985 if (rm == 13) {
3986 tcg_gen_addi_i32(base, base, stride);
3987 } else {
3988 TCGv index;
3989 index = load_reg(s, rm);
3990 tcg_gen_add_i32(base, base, index);
3991 dead_tmp(index);
3992 }
3993 store_reg(s, rn, base);
3994 }
3995 return 0;
3996 }
3997
3998 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
3999 static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4000 {
4001 tcg_gen_and_i32(t, t, c);
4002 tcg_gen_andc_i32(f, f, c);
4003 tcg_gen_or_i32(dest, t, f);
4004 }
4005
4006 static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
4007 {
4008 switch (size) {
4009 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4010 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4011 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4012 default: abort();
4013 }
4014 }
4015
4016 static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
4017 {
4018 switch (size) {
4019 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4020 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4021 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4022 default: abort();
4023 }
4024 }
4025
4026 static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
4027 {
4028 switch (size) {
4029 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4030 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4031 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4032 default: abort();
4033 }
4034 }
4035
4036 static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src)
4037 {
4038 switch (size) {
4039 case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break;
4040 case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break;
4041 case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break;
4042 default: abort();
4043 }
4044 }
4045
4046 static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4047 int q, int u)
4048 {
4049 if (q) {
4050 if (u) {
4051 switch (size) {
4052 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4053 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4054 default: abort();
4055 }
4056 } else {
4057 switch (size) {
4058 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4059 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4060 default: abort();
4061 }
4062 }
4063 } else {
4064 if (u) {
4065 switch (size) {
4066 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4067 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
4068 default: abort();
4069 }
4070 } else {
4071 switch (size) {
4072 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4073 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4074 default: abort();
4075 }
4076 }
4077 }
4078 }
4079
4080 static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
4081 {
4082 if (u) {
4083 switch (size) {
4084 case 0: gen_helper_neon_widen_u8(dest, src); break;
4085 case 1: gen_helper_neon_widen_u16(dest, src); break;
4086 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4087 default: abort();
4088 }
4089 } else {
4090 switch (size) {
4091 case 0: gen_helper_neon_widen_s8(dest, src); break;
4092 case 1: gen_helper_neon_widen_s16(dest, src); break;
4093 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4094 default: abort();
4095 }
4096 }
4097 dead_tmp(src);
4098 }
4099
4100 static inline void gen_neon_addl(int size)
4101 {
4102 switch (size) {
4103 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4104 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4105 case 2: tcg_gen_add_i64(CPU_V001); break;
4106 default: abort();
4107 }
4108 }
4109
4110 static inline void gen_neon_subl(int size)
4111 {
4112 switch (size) {
4113 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4114 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4115 case 2: tcg_gen_sub_i64(CPU_V001); break;
4116 default: abort();
4117 }
4118 }
4119
4120 static inline void gen_neon_negl(TCGv_i64 var, int size)
4121 {
4122 switch (size) {
4123 case 0: gen_helper_neon_negl_u16(var, var); break;
4124 case 1: gen_helper_neon_negl_u32(var, var); break;
4125 case 2: gen_helper_neon_negl_u64(var, var); break;
4126 default: abort();
4127 }
4128 }
4129
4130 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4131 {
4132 switch (size) {
4133 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4134 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4135 default: abort();
4136 }
4137 }
4138
4139 static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
4140 {
4141 TCGv_i64 tmp;
4142
4143 switch ((size << 1) | u) {
4144 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4145 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4146 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4147 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4148 case 4:
4149 tmp = gen_muls_i64_i32(a, b);
4150 tcg_gen_mov_i64(dest, tmp);
4151 break;
4152 case 5:
4153 tmp = gen_mulu_i64_i32(a, b);
4154 tcg_gen_mov_i64(dest, tmp);
4155 break;
4156 default: abort();
4157 }
4158
4159 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4160 Don't forget to clean them now. */
4161 if (size < 2) {
4162 dead_tmp(a);
4163 dead_tmp(b);
4164 }
4165 }
4166
4167 /* Translate a NEON data processing instruction. Return nonzero if the
4168 instruction is invalid.
4169 We process data in a mixture of 32-bit and 64-bit chunks.
4170 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4171
4172 static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4173 {
4174 int op;
4175 int q;
4176 int rd, rn, rm;
4177 int size;
4178 int shift;
4179 int pass;
4180 int count;
4181 int pairwise;
4182 int u;
4183 int n;
4184 uint32_t imm, mask;
4185 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
4186 TCGv_i64 tmp64;
4187
4188 if (!s->vfp_enabled)
4189 return 1;
4190 q = (insn & (1 << 6)) != 0;
4191 u = (insn >> 24) & 1;
4192 VFP_DREG_D(rd, insn);
4193 VFP_DREG_N(rn, insn);
4194 VFP_DREG_M(rm, insn);
4195 size = (insn >> 20) & 3;
4196 if ((insn & (1 << 23)) == 0) {
4197 /* Three register same length. */
4198 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4199 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4200 || op == 10 || op == 11 || op == 16)) {
4201 /* 64-bit element instructions. */
4202 for (pass = 0; pass < (q ? 2 : 1); pass++) {
4203 neon_load_reg64(cpu_V0, rn + pass);
4204 neon_load_reg64(cpu_V1, rm + pass);
4205 switch (op) {
4206 case 1: /* VQADD */
4207 if (u) {
4208 gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
4209 cpu_V0, cpu_V1);
4210 } else {
4211 gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
4212 cpu_V0, cpu_V1);
4213 }
4214 break;
4215 case 5: /* VQSUB */
4216 if (u) {
4217 gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
4218 cpu_V0, cpu_V1);
4219 } else {
4220 gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
4221 cpu_V0, cpu_V1);
4222 }
4223 break;
4224 case 8: /* VSHL */
4225 if (u) {
4226 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4227 } else {
4228 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4229 }
4230 break;
4231 case 9: /* VQSHL */
4232 if (u) {
4233 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4234 cpu_V1, cpu_V0);
4235 } else {
4236 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4237 cpu_V1, cpu_V0);
4238 }
4239 break;
4240 case 10: /* VRSHL */
4241 if (u) {
4242 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
4243 } else {
4244 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4245 }
4246 break;
4247 case 11: /* VQRSHL */
4248 if (u) {
4249 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4250 cpu_V1, cpu_V0);
4251 } else {
4252 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4253 cpu_V1, cpu_V0);
4254 }
4255 break;
4256 case 16:
4257 if (u) {
4258 tcg_gen_sub_i64(CPU_V001);
4259 } else {
4260 tcg_gen_add_i64(CPU_V001);
4261 }
4262 break;
4263 default:
4264 abort();
4265 }
4266 neon_store_reg64(cpu_V0, rd + pass);
4267 }
4268 return 0;
4269 }
4270 switch (op) {
4271 case 8: /* VSHL */
4272 case 9: /* VQSHL */
4273 case 10: /* VRSHL */
4274 case 11: /* VQRSHL */
4275 {
4276 int rtmp;
4277 /* Shift instruction operands are reversed. */
4278 rtmp = rn;
4279 rn = rm;
4280 rm = rtmp;
4281 pairwise = 0;
4282 }
4283 break;
4284 case 20: /* VPMAX */
4285 case 21: /* VPMIN */
4286 case 23: /* VPADD */
4287 pairwise = 1;
4288 break;
4289 case 26: /* VPADD (float) */
4290 pairwise = (u && size < 2);
4291 break;
4292 case 30: /* VPMIN/VPMAX (float) */
4293 pairwise = u;
4294 break;
4295 default:
4296 pairwise = 0;
4297 break;
4298 }
4299
4300 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4301
4302 if (pairwise) {
4303 /* Pairwise. */
4304 if (q)
4305 n = (pass & 1) * 2;
4306 else
4307 n = 0;
4308 if (pass < q + 1) {
4309 tmp = neon_load_reg(rn, n);
4310 tmp2 = neon_load_reg(rn, n + 1);
4311 } else {
4312 tmp = neon_load_reg(rm, n);
4313 tmp2 = neon_load_reg(rm, n + 1);
4314 }
4315 } else {
4316 /* Elementwise. */
4317 tmp = neon_load_reg(rn, pass);
4318 tmp2 = neon_load_reg(rm, pass);
4319 }
4320 switch (op) {
4321 case 0: /* VHADD */
4322 GEN_NEON_INTEGER_OP(hadd);
4323 break;
4324 case 1: /* VQADD */
4325 GEN_NEON_INTEGER_OP_ENV(qadd);
4326 break;
4327 case 2: /* VRHADD */
4328 GEN_NEON_INTEGER_OP(rhadd);
4329 break;
4330 case 3: /* Logic ops. */
4331 switch ((u << 2) | size) {
4332 case 0: /* VAND */
4333 tcg_gen_and_i32(tmp, tmp, tmp2);
4334 break;
4335 case 1: /* BIC */
4336 tcg_gen_andc_i32(tmp, tmp, tmp2);
4337 break;
4338 case 2: /* VORR */
4339 tcg_gen_or_i32(tmp, tmp, tmp2);
4340 break;
4341 case 3: /* VORN */
4342 tcg_gen_orc_i32(tmp, tmp, tmp2);
4343 break;
4344 case 4: /* VEOR */
4345 tcg_gen_xor_i32(tmp, tmp, tmp2);
4346 break;
4347 case 5: /* VBSL */
4348 tmp3 = neon_load_reg(rd, pass);
4349 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4350 dead_tmp(tmp3);
4351 break;
4352 case 6: /* VBIT */
4353 tmp3 = neon_load_reg(rd, pass);
4354 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4355 dead_tmp(tmp3);
4356 break;
4357 case 7: /* VBIF */
4358 tmp3 = neon_load_reg(rd, pass);
4359 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4360 dead_tmp(tmp3);
4361 break;
4362 }
4363 break;
4364 case 4: /* VHSUB */
4365 GEN_NEON_INTEGER_OP(hsub);
4366 break;
4367 case 5: /* VQSUB */
4368 GEN_NEON_INTEGER_OP_ENV(qsub);
4369 break;
4370 case 6: /* VCGT */
4371 GEN_NEON_INTEGER_OP(cgt);
4372 break;
4373 case 7: /* VCGE */
4374 GEN_NEON_INTEGER_OP(cge);
4375 break;
4376 case 8: /* VSHL */
4377 GEN_NEON_INTEGER_OP(shl);
4378 break;
4379 case 9: /* VQSHL */
4380 GEN_NEON_INTEGER_OP_ENV(qshl);
4381 break;
4382 case 10: /* VRSHL */
4383 GEN_NEON_INTEGER_OP(rshl);
4384 break;
4385 case 11: /* VQRSHL */
4386 GEN_NEON_INTEGER_OP_ENV(qrshl);
4387 break;
4388 case 12: /* VMAX */
4389 GEN_NEON_INTEGER_OP(max);
4390 break;
4391 case 13: /* VMIN */
4392 GEN_NEON_INTEGER_OP(min);
4393 break;
4394 case 14: /* VABD */
4395 GEN_NEON_INTEGER_OP(abd);
4396 break;
4397 case 15: /* VABA */
4398 GEN_NEON_INTEGER_OP(abd);
4399 dead_tmp(tmp2);
4400 tmp2 = neon_load_reg(rd, pass);
4401 gen_neon_add(size, tmp, tmp2);
4402 break;
4403 case 16:
4404 if (!u) { /* VADD */
4405 if (gen_neon_add(size, tmp, tmp2))
4406 return 1;
4407 } else { /* VSUB */
4408 switch (size) {
4409 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4410 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4411 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
4412 default: return 1;
4413 }
4414 }
4415 break;
4416 case 17:
4417 if (!u) { /* VTST */
4418 switch (size) {
4419 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4420 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4421 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
4422 default: return 1;
4423 }
4424 } else { /* VCEQ */
4425 switch (size) {
4426 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4427 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4428 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
4429 default: return 1;
4430 }
4431 }
4432 break;
4433 case 18: /* Multiply. */
4434 switch (size) {
4435 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4436 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4437 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4438 default: return 1;
4439 }
4440 dead_tmp(tmp2);
4441 tmp2 = neon_load_reg(rd, pass);
4442 if (u) { /* VMLS */
4443 gen_neon_rsb(size, tmp, tmp2);
4444 } else { /* VMLA */
4445 gen_neon_add(size, tmp, tmp2);
4446 }
4447 break;
4448 case 19: /* VMUL */
4449 if (u) { /* polynomial */
4450 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
4451 } else { /* Integer */
4452 switch (size) {
4453 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4454 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4455 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4456 default: return 1;
4457 }
4458 }
4459 break;
4460 case 20: /* VPMAX */
4461 GEN_NEON_INTEGER_OP(pmax);
4462 break;
4463 case 21: /* VPMIN */
4464 GEN_NEON_INTEGER_OP(pmin);
4465 break;
4466 case 22: /* Hultiply high. */
4467 if (!u) { /* VQDMULH */
4468 switch (size) {
4469 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4470 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
4471 default: return 1;
4472 }
4473 } else { /* VQRDHMUL */
4474 switch (size) {
4475 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4476 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
4477 default: return 1;
4478 }
4479 }
4480 break;
4481 case 23: /* VPADD */
4482 if (u)
4483 return 1;
4484 switch (size) {
4485 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4486 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4487 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
4488 default: return 1;
4489 }
4490 break;
4491 case 26: /* Floating point arithnetic. */
4492 switch ((u << 2) | size) {
4493 case 0: /* VADD */
4494 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4495 break;
4496 case 2: /* VSUB */
4497 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
4498 break;
4499 case 4: /* VPADD */
4500 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4501 break;
4502 case 6: /* VABD */
4503 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
4504 break;
4505 default:
4506 return 1;
4507 }
4508 break;
4509 case 27: /* Float multiply. */
4510 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
4511 if (!u) {
4512 dead_tmp(tmp2);
4513 tmp2 = neon_load_reg(rd, pass);
4514 if (size == 0) {
4515 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4516 } else {
4517 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
4518 }
4519 }
4520 break;
4521 case 28: /* Float compare. */
4522 if (!u) {
4523 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
4524 } else {
4525 if (size == 0)
4526 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
4527 else
4528 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
4529 }
4530 break;
4531 case 29: /* Float compare absolute. */
4532 if (!u)
4533 return 1;
4534 if (size == 0)
4535 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
4536 else
4537 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
4538 break;
4539 case 30: /* Float min/max. */
4540 if (size == 0)
4541 gen_helper_neon_max_f32(tmp, tmp, tmp2);
4542 else
4543 gen_helper_neon_min_f32(tmp, tmp, tmp2);
4544 break;
4545 case 31:
4546 if (size == 0)
4547 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
4548 else
4549 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
4550 break;
4551 default:
4552 abort();
4553 }
4554 dead_tmp(tmp2);
4555
4556 /* Save the result. For elementwise operations we can put it
4557 straight into the destination register. For pairwise operations
4558 we have to be careful to avoid clobbering the source operands. */
4559 if (pairwise && rd == rm) {
4560 neon_store_scratch(pass, tmp);
4561 } else {
4562 neon_store_reg(rd, pass, tmp);
4563 }
4564
4565 } /* for pass */
4566 if (pairwise && rd == rm) {
4567 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4568 tmp = neon_load_scratch(pass);
4569 neon_store_reg(rd, pass, tmp);
4570 }
4571 }
4572 /* End of 3 register same size operations. */
4573 } else if (insn & (1 << 4)) {
4574 if ((insn & 0x00380080) != 0) {
4575 /* Two registers and shift. */
4576 op = (insn >> 8) & 0xf;
4577 if (insn & (1 << 7)) {
4578 /* 64-bit shift. */
4579 size = 3;
4580 } else {
4581 size = 2;
4582 while ((insn & (1 << (size + 19))) == 0)
4583 size--;
4584 }
4585 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4586 /* To avoid excessive dumplication of ops we implement shift
4587 by immediate using the variable shift operations. */
4588 if (op < 8) {
4589 /* Shift by immediate:
4590 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4591 /* Right shifts are encoded as N - shift, where N is the
4592 element size in bits. */
4593 if (op <= 4)
4594 shift = shift - (1 << (size + 3));
4595 if (size == 3) {
4596 count = q + 1;
4597 } else {
4598 count = q ? 4: 2;
4599 }
4600 switch (size) {
4601 case 0:
4602 imm = (uint8_t) shift;
4603 imm |= imm << 8;
4604 imm |= imm << 16;
4605 break;
4606 case 1:
4607 imm = (uint16_t) shift;
4608 imm |= imm << 16;
4609 break;
4610 case 2:
4611 case 3:
4612 imm = shift;
4613 break;
4614 default:
4615 abort();
4616 }
4617
4618 for (pass = 0; pass < count; pass++) {
4619 if (size == 3) {
4620 neon_load_reg64(cpu_V0, rm + pass);
4621 tcg_gen_movi_i64(cpu_V1, imm);
4622 switch (op) {
4623 case 0: /* VSHR */
4624 case 1: /* VSRA */
4625 if (u)
4626 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4627 else
4628 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
4629 break;
4630 case 2: /* VRSHR */
4631 case 3: /* VRSRA */
4632 if (u)
4633 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
4634 else
4635 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
4636 break;
4637 case 4: /* VSRI */
4638 if (!u)
4639 return 1;
4640 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4641 break;
4642 case 5: /* VSHL, VSLI */
4643 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4644 break;
4645 case 6: /* VQSHLU */
4646 if (u) {
4647 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
4648 cpu_V0, cpu_V1);
4649 } else {
4650 return 1;
4651 }
4652 break;
4653 case 7: /* VQSHL */
4654 if (u) {
4655 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4656 cpu_V0, cpu_V1);
4657 } else {
4658 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4659 cpu_V0, cpu_V1);
4660 }
4661 break;
4662 }
4663 if (op == 1 || op == 3) {
4664 /* Accumulate. */
4665 neon_load_reg64(cpu_V1, rd + pass);
4666 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4667 } else if (op == 4 || (op == 5 && u)) {
4668 /* Insert */
4669 neon_load_reg64(cpu_V1, rd + pass);
4670 uint64_t mask;
4671 if (shift < -63 || shift > 63) {
4672 mask = 0;
4673 } else {
4674 if (op == 4) {
4675 mask = 0xffffffffffffffffull >> -shift;
4676 } else {
4677 mask = 0xffffffffffffffffull << shift;
4678 }
4679 }
4680 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
4681 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
4682 }
4683 neon_store_reg64(cpu_V0, rd + pass);
4684 } else { /* size < 3 */
4685 /* Operands in T0 and T1. */
4686 tmp = neon_load_reg(rm, pass);
4687 tmp2 = new_tmp();
4688 tcg_gen_movi_i32(tmp2, imm);
4689 switch (op) {
4690 case 0: /* VSHR */
4691 case 1: /* VSRA */
4692 GEN_NEON_INTEGER_OP(shl);
4693 break;
4694 case 2: /* VRSHR */
4695 case 3: /* VRSRA */
4696 GEN_NEON_INTEGER_OP(rshl);
4697 break;
4698 case 4: /* VSRI */
4699 if (!u)
4700 return 1;
4701 GEN_NEON_INTEGER_OP(shl);
4702 break;
4703 case 5: /* VSHL, VSLI */
4704 switch (size) {
4705 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4706 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4707 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
4708 default: return 1;
4709 }
4710 break;
4711 case 6: /* VQSHLU */
4712 if (!u) {
4713 return 1;
4714 }
4715 switch (size) {
4716 case 0:
4717 gen_helper_neon_qshlu_s8(tmp, cpu_env,
4718 tmp, tmp2);
4719 break;
4720 case 1:
4721 gen_helper_neon_qshlu_s16(tmp, cpu_env,
4722 tmp, tmp2);
4723 break;
4724 case 2:
4725 gen_helper_neon_qshlu_s32(tmp, cpu_env,
4726 tmp, tmp2);
4727 break;
4728 default:
4729 return 1;
4730 }
4731 break;
4732 case 7: /* VQSHL */
4733 GEN_NEON_INTEGER_OP_ENV(qshl);
4734 break;
4735 }
4736 dead_tmp(tmp2);
4737
4738 if (op == 1 || op == 3) {
4739 /* Accumulate. */
4740 tmp2 = neon_load_reg(rd, pass);
4741 gen_neon_add(size, tmp, tmp2);
4742 dead_tmp(tmp2);
4743 } else if (op == 4 || (op == 5 && u)) {
4744 /* Insert */
4745 switch (size) {
4746 case 0:
4747 if (op == 4)
4748 mask = 0xff >> -shift;
4749 else
4750 mask = (uint8_t)(0xff << shift);
4751 mask |= mask << 8;
4752 mask |= mask << 16;
4753 break;
4754 case 1:
4755 if (op == 4)
4756 mask = 0xffff >> -shift;
4757 else
4758 mask = (uint16_t)(0xffff << shift);
4759 mask |= mask << 16;
4760 break;
4761 case 2:
4762 if (shift < -31 || shift > 31) {
4763 mask = 0;
4764 } else {
4765 if (op == 4)
4766 mask = 0xffffffffu >> -shift;
4767 else
4768 mask = 0xffffffffu << shift;
4769 }
4770 break;
4771 default:
4772 abort();
4773 }
4774 tmp2 = neon_load_reg(rd, pass);
4775 tcg_gen_andi_i32(tmp, tmp, mask);
4776 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
4777 tcg_gen_or_i32(tmp, tmp, tmp2);
4778 dead_tmp(tmp2);
4779 }
4780 neon_store_reg(rd, pass, tmp);
4781 }
4782 } /* for pass */
4783 } else if (op < 10) {
4784 /* Shift by immediate and narrow:
4785 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4786 int input_unsigned = (op == 8) ? !u : u;
4787
4788 shift = shift - (1 << (size + 3));
4789 size++;
4790 switch (size) {
4791 case 1:
4792 imm = (uint16_t)shift;
4793 imm |= imm << 16;
4794 tmp2 = tcg_const_i32(imm);
4795 TCGV_UNUSED_I64(tmp64);
4796 break;
4797 case 2:
4798 imm = (uint32_t)shift;
4799 tmp2 = tcg_const_i32(imm);
4800 TCGV_UNUSED_I64(tmp64);
4801 break;
4802 case 3:
4803 tmp64 = tcg_const_i64(shift);
4804 TCGV_UNUSED(tmp2);
4805 break;
4806 default:
4807 abort();
4808 }
4809
4810 for (pass = 0; pass < 2; pass++) {
4811 if (size == 3) {
4812 neon_load_reg64(cpu_V0, rm + pass);
4813 if (q) {
4814 if (input_unsigned) {
4815 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0,
4816 tmp64);
4817 } else {
4818 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0,
4819 tmp64);
4820 }
4821 } else {
4822 if (input_unsigned) {
4823 gen_helper_neon_shl_u64(cpu_V0, cpu_V0,
4824 tmp64);
4825 } else {
4826 gen_helper_neon_shl_s64(cpu_V0, cpu_V0,
4827 tmp64);
4828 }
4829 }
4830 } else {
4831 tmp = neon_load_reg(rm + pass, 0);
4832 gen_neon_shift_narrow(size, tmp, tmp2, q,
4833 input_unsigned);
4834 tmp3 = neon_load_reg(rm + pass, 1);
4835 gen_neon_shift_narrow(size, tmp3, tmp2, q,
4836 input_unsigned);
4837 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
4838 dead_tmp(tmp);
4839 dead_tmp(tmp3);
4840 }
4841 tmp = new_tmp();
4842 if (op == 8) {
4843 if (u) { /* VQSHRUN / VQRSHRUN */
4844 gen_neon_unarrow_sats(size - 1, tmp, cpu_V0);
4845 } else { /* VSHRN / VRSHRN */
4846 gen_neon_narrow(size - 1, tmp, cpu_V0);
4847 }
4848 } else {
4849 if (u) { /* VQSHRN / VQRSHRN */
4850 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4851 } else { /* VQSHRN / VQRSHRN */
4852 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
4853 }
4854 }
4855 neon_store_reg(rd, pass, tmp);
4856 } /* for pass */
4857 if (size == 3) {
4858 tcg_temp_free_i64(tmp64);
4859 } else {
4860 tcg_temp_free_i32(tmp2);
4861 }
4862 } else if (op == 10) {
4863 /* VSHLL */
4864 if (q || size == 3)
4865 return 1;
4866 tmp = neon_load_reg(rm, 0);
4867 tmp2 = neon_load_reg(rm, 1);
4868 for (pass = 0; pass < 2; pass++) {
4869 if (pass == 1)
4870 tmp = tmp2;
4871
4872 gen_neon_widen(cpu_V0, tmp, size, u);
4873
4874 if (shift != 0) {
4875 /* The shift is less than the width of the source
4876 type, so we can just shift the whole register. */
4877 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4878 /* Widen the result of shift: we need to clear
4879 * the potential overflow bits resulting from
4880 * left bits of the narrow input appearing as
4881 * right bits of left the neighbour narrow
4882 * input. */
4883 if (size < 2 || !u) {
4884 uint64_t imm64;
4885 if (size == 0) {
4886 imm = (0xffu >> (8 - shift));
4887 imm |= imm << 16;
4888 } else if (size == 1) {
4889 imm = 0xffff >> (16 - shift);
4890 } else {
4891 /* size == 2 */
4892 imm = 0xffffffff >> (32 - shift);
4893 }
4894 if (size < 2) {
4895 imm64 = imm | (((uint64_t)imm) << 32);
4896 } else {
4897 imm64 = imm;
4898 }
4899 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
4900 }
4901 }
4902 neon_store_reg64(cpu_V0, rd + pass);
4903 }
4904 } else if (op >= 14) {
4905 /* VCVT fixed-point. */
4906 /* We have already masked out the must-be-1 top bit of imm6,
4907 * hence this 32-shift where the ARM ARM has 64-imm6.
4908 */
4909 shift = 32 - shift;
4910 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4911 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
4912 if (!(op & 1)) {
4913 if (u)
4914 gen_vfp_ulto(0, shift);
4915 else
4916 gen_vfp_slto(0, shift);
4917 } else {
4918 if (u)
4919 gen_vfp_toul(0, shift);
4920 else
4921 gen_vfp_tosl(0, shift);
4922 }
4923 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
4924 }
4925 } else {
4926 return 1;
4927 }
4928 } else { /* (insn & 0x00380080) == 0 */
4929 int invert;
4930
4931 op = (insn >> 8) & 0xf;
4932 /* One register and immediate. */
4933 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4934 invert = (insn & (1 << 5)) != 0;
4935 switch (op) {
4936 case 0: case 1:
4937 /* no-op */
4938 break;
4939 case 2: case 3:
4940 imm <<= 8;
4941 break;
4942 case 4: case 5:
4943 imm <<= 16;
4944 break;
4945 case 6: case 7:
4946 imm <<= 24;
4947 break;
4948 case 8: case 9:
4949 imm |= imm << 16;
4950 break;
4951 case 10: case 11:
4952 imm = (imm << 8) | (imm << 24);
4953 break;
4954 case 12:
4955 imm = (imm << 8) | 0xff;
4956 break;
4957 case 13:
4958 imm = (imm << 16) | 0xffff;
4959 break;
4960 case 14:
4961 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4962 if (invert)
4963 imm = ~imm;
4964 break;
4965 case 15:
4966 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4967 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4968 break;
4969 }
4970 if (invert)
4971 imm = ~imm;
4972
4973 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4974 if (op & 1 && op < 12) {
4975 tmp = neon_load_reg(rd, pass);
4976 if (invert) {
4977 /* The immediate value has already been inverted, so
4978 BIC becomes AND. */
4979 tcg_gen_andi_i32(tmp, tmp, imm);
4980 } else {
4981 tcg_gen_ori_i32(tmp, tmp, imm);
4982 }
4983 } else {
4984 /* VMOV, VMVN. */
4985 tmp = new_tmp();
4986 if (op == 14 && invert) {
4987 uint32_t val;
4988 val = 0;
4989 for (n = 0; n < 4; n++) {
4990 if (imm & (1 << (n + (pass & 1) * 4)))
4991 val |= 0xff << (n * 8);
4992 }
4993 tcg_gen_movi_i32(tmp, val);
4994 } else {
4995 tcg_gen_movi_i32(tmp, imm);
4996 }
4997 }
4998 neon_store_reg(rd, pass, tmp);
4999 }
5000 }
5001 } else { /* (insn & 0x00800010 == 0x00800000) */
5002 if (size != 3) {
5003 op = (insn >> 8) & 0xf;
5004 if ((insn & (1 << 6)) == 0) {
5005 /* Three registers of different lengths. */
5006 int src1_wide;
5007 int src2_wide;
5008 int prewiden;
5009 /* prewiden, src1_wide, src2_wide */
5010 static const int neon_3reg_wide[16][3] = {
5011 {1, 0, 0}, /* VADDL */
5012 {1, 1, 0}, /* VADDW */
5013 {1, 0, 0}, /* VSUBL */
5014 {1, 1, 0}, /* VSUBW */
5015 {0, 1, 1}, /* VADDHN */
5016 {0, 0, 0}, /* VABAL */
5017 {0, 1, 1}, /* VSUBHN */
5018 {0, 0, 0}, /* VABDL */
5019 {0, 0, 0}, /* VMLAL */
5020 {0, 0, 0}, /* VQDMLAL */
5021 {0, 0, 0}, /* VMLSL */
5022 {0, 0, 0}, /* VQDMLSL */
5023 {0, 0, 0}, /* Integer VMULL */
5024 {0, 0, 0}, /* VQDMULL */
5025 {0, 0, 0} /* Polynomial VMULL */
5026 };
5027
5028 prewiden = neon_3reg_wide[op][0];
5029 src1_wide = neon_3reg_wide[op][1];
5030 src2_wide = neon_3reg_wide[op][2];
5031
5032 if (size == 0 && (op == 9 || op == 11 || op == 13))
5033 return 1;
5034
5035 /* Avoid overlapping operands. Wide source operands are
5036 always aligned so will never overlap with wide
5037 destinations in problematic ways. */
5038 if (rd == rm && !src2_wide) {
5039 tmp = neon_load_reg(rm, 1);
5040 neon_store_scratch(2, tmp);
5041 } else if (rd == rn && !src1_wide) {
5042 tmp = neon_load_reg(rn, 1);
5043 neon_store_scratch(2, tmp);
5044 }
5045 TCGV_UNUSED(tmp3);
5046 for (pass = 0; pass < 2; pass++) {
5047 if (src1_wide) {
5048 neon_load_reg64(cpu_V0, rn + pass);
5049 TCGV_UNUSED(tmp);
5050 } else {
5051 if (pass == 1 && rd == rn) {
5052 tmp = neon_load_scratch(2);
5053 } else {
5054 tmp = neon_load_reg(rn, pass);
5055 }
5056 if (prewiden) {
5057 gen_neon_widen(cpu_V0, tmp, size, u);
5058 }
5059 }
5060 if (src2_wide) {
5061 neon_load_reg64(cpu_V1, rm + pass);
5062 TCGV_UNUSED(tmp2);
5063 } else {
5064 if (pass == 1 && rd == rm) {
5065 tmp2 = neon_load_scratch(2);
5066 } else {
5067 tmp2 = neon_load_reg(rm, pass);
5068 }
5069 if (prewiden) {
5070 gen_neon_widen(cpu_V1, tmp2, size, u);
5071 }
5072 }
5073 switch (op) {
5074 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5075 gen_neon_addl(size);
5076 break;
5077 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5078 gen_neon_subl(size);
5079 break;
5080 case 5: case 7: /* VABAL, VABDL */
5081 switch ((size << 1) | u) {
5082 case 0:
5083 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5084 break;
5085 case 1:
5086 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5087 break;
5088 case 2:
5089 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5090 break;
5091 case 3:
5092 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5093 break;
5094 case 4:
5095 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5096 break;
5097 case 5:
5098 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5099 break;
5100 default: abort();
5101 }
5102 dead_tmp(tmp2);
5103 dead_tmp(tmp);
5104 break;
5105 case 8: case 9: case 10: case 11: case 12: case 13:
5106 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5107 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5108 break;
5109 case 14: /* Polynomial VMULL */
5110 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
5111 dead_tmp(tmp2);
5112 dead_tmp(tmp);
5113 break;
5114 default: /* 15 is RESERVED. */
5115 return 1;
5116 }
5117 if (op == 13) {
5118 /* VQDMULL */
5119 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5120 neon_store_reg64(cpu_V0, rd + pass);
5121 } else if (op == 5 || (op >= 8 && op <= 11)) {
5122 /* Accumulate. */
5123 neon_load_reg64(cpu_V1, rd + pass);
5124 switch (op) {
5125 case 10: /* VMLSL */
5126 gen_neon_negl(cpu_V0, size);
5127 /* Fall through */
5128 case 5: case 8: /* VABAL, VMLAL */
5129 gen_neon_addl(size);
5130 break;
5131 case 9: case 11: /* VQDMLAL, VQDMLSL */
5132 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5133 if (op == 11) {
5134 gen_neon_negl(cpu_V0, size);
5135 }
5136 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5137 break;
5138 default:
5139 abort();
5140 }
5141 neon_store_reg64(cpu_V0, rd + pass);
5142 } else if (op == 4 || op == 6) {
5143 /* Narrowing operation. */
5144 tmp = new_tmp();
5145 if (!u) {
5146 switch (size) {
5147 case 0:
5148 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5149 break;
5150 case 1:
5151 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5152 break;
5153 case 2:
5154 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5155 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5156 break;
5157 default: abort();
5158 }
5159 } else {
5160 switch (size) {
5161 case 0:
5162 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5163 break;
5164 case 1:
5165 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5166 break;
5167 case 2:
5168 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5169 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5170 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5171 break;
5172 default: abort();
5173 }
5174 }
5175 if (pass == 0) {
5176 tmp3 = tmp;
5177 } else {
5178 neon_store_reg(rd, 0, tmp3);
5179 neon_store_reg(rd, 1, tmp);
5180 }
5181 } else {
5182 /* Write back the result. */
5183 neon_store_reg64(cpu_V0, rd + pass);
5184 }
5185 }
5186 } else {
5187 /* Two registers and a scalar. */
5188 switch (op) {
5189 case 0: /* Integer VMLA scalar */
5190 case 1: /* Float VMLA scalar */
5191 case 4: /* Integer VMLS scalar */
5192 case 5: /* Floating point VMLS scalar */
5193 case 8: /* Integer VMUL scalar */
5194 case 9: /* Floating point VMUL scalar */
5195 case 12: /* VQDMULH scalar */
5196 case 13: /* VQRDMULH scalar */
5197 tmp = neon_get_scalar(size, rm);
5198 neon_store_scratch(0, tmp);
5199 for (pass = 0; pass < (u ? 4 : 2); pass++) {
5200 tmp = neon_load_scratch(0);
5201 tmp2 = neon_load_reg(rn, pass);
5202 if (op == 12) {
5203 if (size == 1) {
5204 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
5205 } else {
5206 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
5207 }
5208 } else if (op == 13) {
5209 if (size == 1) {
5210 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
5211 } else {
5212 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
5213 }
5214 } else if (op & 1) {
5215 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
5216 } else {
5217 switch (size) {
5218 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5219 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5220 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5221 default: return 1;
5222 }
5223 }
5224 dead_tmp(tmp2);
5225 if (op < 8) {
5226 /* Accumulate. */
5227 tmp2 = neon_load_reg(rd, pass);
5228 switch (op) {
5229 case 0:
5230 gen_neon_add(size, tmp, tmp2);
5231 break;
5232 case 1:
5233 gen_helper_neon_add_f32(tmp, tmp, tmp2);
5234 break;
5235 case 4:
5236 gen_neon_rsb(size, tmp, tmp2);
5237 break;
5238 case 5:
5239 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
5240 break;
5241 default:
5242 abort();
5243 }
5244 dead_tmp(tmp2);
5245 }
5246 neon_store_reg(rd, pass, tmp);
5247 }
5248 break;
5249 case 2: /* VMLAL sclar */
5250 case 3: /* VQDMLAL scalar */
5251 case 6: /* VMLSL scalar */
5252 case 7: /* VQDMLSL scalar */
5253 case 10: /* VMULL scalar */
5254 case 11: /* VQDMULL scalar */
5255 if (size == 0 && (op == 3 || op == 7 || op == 11))
5256 return 1;
5257
5258 tmp2 = neon_get_scalar(size, rm);
5259 /* We need a copy of tmp2 because gen_neon_mull
5260 * deletes it during pass 0. */
5261 tmp4 = new_tmp();
5262 tcg_gen_mov_i32(tmp4, tmp2);
5263 tmp3 = neon_load_reg(rn, 1);
5264
5265 for (pass = 0; pass < 2; pass++) {
5266 if (pass == 0) {
5267 tmp = neon_load_reg(rn, 0);
5268 } else {
5269 tmp = tmp3;
5270 tmp2 = tmp4;
5271 }
5272 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5273 if (op != 11) {
5274 neon_load_reg64(cpu_V1, rd + pass);
5275 }
5276 switch (op) {
5277 case 6:
5278 gen_neon_negl(cpu_V0, size);
5279 /* Fall through */
5280 case 2:
5281 gen_neon_addl(size);
5282 break;
5283 case 3: case 7:
5284 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5285 if (op == 7) {
5286 gen_neon_negl(cpu_V0, size);
5287 }
5288 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5289 break;
5290 case 10:
5291 /* no-op */
5292 break;
5293 case 11:
5294 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5295 break;
5296 default:
5297 abort();
5298 }
5299 neon_store_reg64(cpu_V0, rd + pass);
5300 }
5301
5302
5303 break;
5304 default: /* 14 and 15 are RESERVED */
5305 return 1;
5306 }
5307 }
5308 } else { /* size == 3 */
5309 if (!u) {
5310 /* Extract. */
5311 imm = (insn >> 8) & 0xf;
5312
5313 if (imm > 7 && !q)
5314 return 1;
5315
5316 if (imm == 0) {
5317 neon_load_reg64(cpu_V0, rn);
5318 if (q) {
5319 neon_load_reg64(cpu_V1, rn + 1);
5320 }
5321 } else if (imm == 8) {
5322 neon_load_reg64(cpu_V0, rn + 1);
5323 if (q) {
5324 neon_load_reg64(cpu_V1, rm);
5325 }
5326 } else if (q) {
5327 tmp64 = tcg_temp_new_i64();
5328 if (imm < 8) {
5329 neon_load_reg64(cpu_V0, rn);
5330 neon_load_reg64(tmp64, rn + 1);
5331 } else {
5332 neon_load_reg64(cpu_V0, rn + 1);
5333 neon_load_reg64(tmp64, rm);
5334 }
5335 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
5336 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
5337 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5338 if (imm < 8) {
5339 neon_load_reg64(cpu_V1, rm);
5340 } else {
5341 neon_load_reg64(cpu_V1, rm + 1);
5342 imm -= 8;
5343 }
5344 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5345 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5346 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
5347 tcg_temp_free_i64(tmp64);
5348 } else {
5349 /* BUGFIX */
5350 neon_load_reg64(cpu_V0, rn);
5351 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
5352 neon_load_reg64(cpu_V1, rm);
5353 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5354 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5355 }
5356 neon_store_reg64(cpu_V0, rd);
5357 if (q) {
5358 neon_store_reg64(cpu_V1, rd + 1);
5359 }
5360 } else if ((insn & (1 << 11)) == 0) {
5361 /* Two register misc. */
5362 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5363 size = (insn >> 18) & 3;
5364 switch (op) {
5365 case 0: /* VREV64 */
5366 if (size == 3)
5367 return 1;
5368 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5369 tmp = neon_load_reg(rm, pass * 2);
5370 tmp2 = neon_load_reg(rm, pass * 2 + 1);
5371 switch (size) {
5372 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5373 case 1: gen_swap_half(tmp); break;
5374 case 2: /* no-op */ break;
5375 default: abort();
5376 }
5377 neon_store_reg(rd, pass * 2 + 1, tmp);
5378 if (size == 2) {
5379 neon_store_reg(rd, pass * 2, tmp2);
5380 } else {
5381 switch (size) {
5382 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5383 case 1: gen_swap_half(tmp2); break;
5384 default: abort();
5385 }
5386 neon_store_reg(rd, pass * 2, tmp2);
5387 }
5388 }
5389 break;
5390 case 4: case 5: /* VPADDL */
5391 case 12: case 13: /* VPADAL */
5392 if (size == 3)
5393 return 1;
5394 for (pass = 0; pass < q + 1; pass++) {
5395 tmp = neon_load_reg(rm, pass * 2);
5396 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5397 tmp = neon_load_reg(rm, pass * 2 + 1);
5398 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5399 switch (size) {
5400 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5401 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5402 case 2: tcg_gen_add_i64(CPU_V001); break;
5403 default: abort();
5404 }
5405 if (op >= 12) {
5406 /* Accumulate. */
5407 neon_load_reg64(cpu_V1, rd + pass);
5408 gen_neon_addl(size);
5409 }
5410 neon_store_reg64(cpu_V0, rd + pass);
5411 }
5412 break;
5413 case 33: /* VTRN */
5414 if (size == 2) {
5415 for (n = 0; n < (q ? 4 : 2); n += 2) {
5416 tmp = neon_load_reg(rm, n);
5417 tmp2 = neon_load_reg(rd, n + 1);
5418 neon_store_reg(rm, n, tmp2);
5419 neon_store_reg(rd, n + 1, tmp);
5420 }
5421 } else {
5422 goto elementwise;
5423 }
5424 break;
5425 case 34: /* VUZP */
5426 if (gen_neon_unzip(rd, rm, size, q)) {
5427 return 1;
5428 }
5429 break;
5430 case 35: /* VZIP */
5431 if (gen_neon_zip(rd, rm, size, q)) {
5432 return 1;
5433 }
5434 break;
5435 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5436 if (size == 3)
5437 return 1;
5438 TCGV_UNUSED(tmp2);
5439 for (pass = 0; pass < 2; pass++) {
5440 neon_load_reg64(cpu_V0, rm + pass);
5441 tmp = new_tmp();
5442 if (op == 36) {
5443 if (q) { /* VQMOVUN */
5444 gen_neon_unarrow_sats(size, tmp, cpu_V0);
5445 } else { /* VMOVN */
5446 gen_neon_narrow(size, tmp, cpu_V0);
5447 }
5448 } else { /* VQMOVN */
5449 if (q) {
5450 gen_neon_narrow_satu(size, tmp, cpu_V0);
5451 } else {
5452 gen_neon_narrow_sats(size, tmp, cpu_V0);
5453 }
5454 }
5455 if (pass == 0) {
5456 tmp2 = tmp;
5457 } else {
5458 neon_store_reg(rd, 0, tmp2);
5459 neon_store_reg(rd, 1, tmp);
5460 }
5461 }
5462 break;
5463 case 38: /* VSHLL */
5464 if (q || size == 3)
5465 return 1;
5466 tmp = neon_load_reg(rm, 0);
5467 tmp2 = neon_load_reg(rm, 1);
5468 for (pass = 0; pass < 2; pass++) {
5469 if (pass == 1)
5470 tmp = tmp2;
5471 gen_neon_widen(cpu_V0, tmp, size, 1);
5472 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
5473 neon_store_reg64(cpu_V0, rd + pass);
5474 }
5475 break;
5476 case 44: /* VCVT.F16.F32 */
5477 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5478 return 1;
5479 tmp = new_tmp();
5480 tmp2 = new_tmp();
5481 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5482 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5483 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5484 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5485 tcg_gen_shli_i32(tmp2, tmp2, 16);
5486 tcg_gen_or_i32(tmp2, tmp2, tmp);
5487 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5488 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5489 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5490 neon_store_reg(rd, 0, tmp2);
5491 tmp2 = new_tmp();
5492 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5493 tcg_gen_shli_i32(tmp2, tmp2, 16);
5494 tcg_gen_or_i32(tmp2, tmp2, tmp);
5495 neon_store_reg(rd, 1, tmp2);
5496 dead_tmp(tmp);
5497 break;
5498 case 46: /* VCVT.F32.F16 */
5499 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5500 return 1;
5501 tmp3 = new_tmp();
5502 tmp = neon_load_reg(rm, 0);
5503 tmp2 = neon_load_reg(rm, 1);
5504 tcg_gen_ext16u_i32(tmp3, tmp);
5505 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5506 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5507 tcg_gen_shri_i32(tmp3, tmp, 16);
5508 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5509 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5510 dead_tmp(tmp);
5511 tcg_gen_ext16u_i32(tmp3, tmp2);
5512 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5513 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5514 tcg_gen_shri_i32(tmp3, tmp2, 16);
5515 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5516 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5517 dead_tmp(tmp2);
5518 dead_tmp(tmp3);
5519 break;
5520 default:
5521 elementwise:
5522 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5523 if (op == 30 || op == 31 || op >= 58) {
5524 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5525 neon_reg_offset(rm, pass));
5526 TCGV_UNUSED(tmp);
5527 } else {
5528 tmp = neon_load_reg(rm, pass);
5529 }
5530 switch (op) {
5531 case 1: /* VREV32 */
5532 switch (size) {
5533 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5534 case 1: gen_swap_half(tmp); break;
5535 default: return 1;
5536 }
5537 break;
5538 case 2: /* VREV16 */
5539 if (size != 0)
5540 return 1;
5541 gen_rev16(tmp);
5542 break;
5543 case 8: /* CLS */
5544 switch (size) {
5545 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5546 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5547 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
5548 default: return 1;
5549 }
5550 break;
5551 case 9: /* CLZ */
5552 switch (size) {
5553 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5554 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5555 case 2: gen_helper_clz(tmp, tmp); break;
5556 default: return 1;
5557 }
5558 break;
5559 case 10: /* CNT */
5560 if (size != 0)
5561 return 1;
5562 gen_helper_neon_cnt_u8(tmp, tmp);
5563 break;
5564 case 11: /* VNOT */
5565 if (size != 0)
5566 return 1;
5567 tcg_gen_not_i32(tmp, tmp);
5568 break;
5569 case 14: /* VQABS */
5570 switch (size) {
5571 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5572 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5573 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
5574 default: return 1;
5575 }
5576 break;
5577 case 15: /* VQNEG */
5578 switch (size) {
5579 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5580 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5581 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
5582 default: return 1;
5583 }
5584 break;
5585 case 16: case 19: /* VCGT #0, VCLE #0 */
5586 tmp2 = tcg_const_i32(0);
5587 switch(size) {
5588 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5589 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5590 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
5591 default: return 1;
5592 }
5593 tcg_temp_free(tmp2);
5594 if (op == 19)
5595 tcg_gen_not_i32(tmp, tmp);
5596 break;
5597 case 17: case 20: /* VCGE #0, VCLT #0 */
5598 tmp2 = tcg_const_i32(0);
5599 switch(size) {
5600 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5601 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5602 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
5603 default: return 1;
5604 }
5605 tcg_temp_free(tmp2);
5606 if (op == 20)
5607 tcg_gen_not_i32(tmp, tmp);
5608 break;
5609 case 18: /* VCEQ #0 */
5610 tmp2 = tcg_const_i32(0);
5611 switch(size) {
5612 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5613 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5614 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
5615 default: return 1;
5616 }
5617 tcg_temp_free(tmp2);
5618 break;
5619 case 22: /* VABS */
5620 switch(size) {
5621 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5622 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5623 case 2: tcg_gen_abs_i32(tmp, tmp); break;
5624 default: return 1;
5625 }
5626 break;
5627 case 23: /* VNEG */
5628 if (size == 3)
5629 return 1;
5630 tmp2 = tcg_const_i32(0);
5631 gen_neon_rsb(size, tmp, tmp2);
5632 tcg_temp_free(tmp2);
5633 break;
5634 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5635 tmp2 = tcg_const_i32(0);
5636 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5637 tcg_temp_free(tmp2);
5638 if (op == 27)
5639 tcg_gen_not_i32(tmp, tmp);
5640 break;
5641 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5642 tmp2 = tcg_const_i32(0);
5643 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5644 tcg_temp_free(tmp2);
5645 if (op == 28)
5646 tcg_gen_not_i32(tmp, tmp);
5647 break;
5648 case 26: /* Float VCEQ #0 */
5649 tmp2 = tcg_const_i32(0);
5650 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5651 tcg_temp_free(tmp2);
5652 break;
5653 case 30: /* Float VABS */
5654 gen_vfp_abs(0);
5655 break;
5656 case 31: /* Float VNEG */
5657 gen_vfp_neg(0);
5658 break;
5659 case 32: /* VSWP */
5660 tmp2 = neon_load_reg(rd, pass);
5661 neon_store_reg(rm, pass, tmp2);
5662 break;
5663 case 33: /* VTRN */
5664 tmp2 = neon_load_reg(rd, pass);
5665 switch (size) {
5666 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5667 case 1: gen_neon_trn_u16(tmp, tmp2); break;
5668 case 2: abort();
5669 default: return 1;
5670 }
5671 neon_store_reg(rm, pass, tmp2);
5672 break;
5673 case 56: /* Integer VRECPE */
5674 gen_helper_recpe_u32(tmp, tmp, cpu_env);
5675 break;
5676 case 57: /* Integer VRSQRTE */
5677 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
5678 break;
5679 case 58: /* Float VRECPE */
5680 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
5681 break;
5682 case 59: /* Float VRSQRTE */
5683 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
5684 break;
5685 case 60: /* VCVT.F32.S32 */
5686 gen_vfp_sito(0);
5687 break;
5688 case 61: /* VCVT.F32.U32 */
5689 gen_vfp_uito(0);
5690 break;
5691 case 62: /* VCVT.S32.F32 */
5692 gen_vfp_tosiz(0);
5693 break;
5694 case 63: /* VCVT.U32.F32 */
5695 gen_vfp_touiz(0);
5696 break;
5697 default:
5698 /* Reserved: 21, 29, 39-56 */
5699 return 1;
5700 }
5701 if (op == 30 || op == 31 || op >= 58) {
5702 tcg_gen_st_f32(cpu_F0s, cpu_env,
5703 neon_reg_offset(rd, pass));
5704 } else {
5705 neon_store_reg(rd, pass, tmp);
5706 }
5707 }
5708 break;
5709 }
5710 } else if ((insn & (1 << 10)) == 0) {
5711 /* VTBL, VTBX. */
5712 n = ((insn >> 5) & 0x18) + 8;
5713 if (insn & (1 << 6)) {
5714 tmp = neon_load_reg(rd, 0);
5715 } else {
5716 tmp = new_tmp();
5717 tcg_gen_movi_i32(tmp, 0);
5718 }
5719 tmp2 = neon_load_reg(rm, 0);
5720 tmp4 = tcg_const_i32(rn);
5721 tmp5 = tcg_const_i32(n);
5722 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
5723 dead_tmp(tmp);
5724 if (insn & (1 << 6)) {
5725 tmp = neon_load_reg(rd, 1);
5726 } else {
5727 tmp = new_tmp();
5728 tcg_gen_movi_i32(tmp, 0);
5729 }
5730 tmp3 = neon_load_reg(rm, 1);
5731 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
5732 tcg_temp_free_i32(tmp5);
5733 tcg_temp_free_i32(tmp4);
5734 neon_store_reg(rd, 0, tmp2);
5735 neon_store_reg(rd, 1, tmp3);
5736 dead_tmp(tmp);
5737 } else if ((insn & 0x380) == 0) {
5738 /* VDUP */
5739 if (insn & (1 << 19)) {
5740 tmp = neon_load_reg(rm, 1);
5741 } else {
5742 tmp = neon_load_reg(rm, 0);
5743 }
5744 if (insn & (1 << 16)) {
5745 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
5746 } else if (insn & (1 << 17)) {
5747 if ((insn >> 18) & 1)
5748 gen_neon_dup_high16(tmp);
5749 else
5750 gen_neon_dup_low16(tmp);
5751 }
5752 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5753 tmp2 = new_tmp();
5754 tcg_gen_mov_i32(tmp2, tmp);
5755 neon_store_reg(rd, pass, tmp2);
5756 }
5757 dead_tmp(tmp);
5758 } else {
5759 return 1;
5760 }
5761 }
5762 }
5763 return 0;
5764 }
5765
5766 static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5767 {
5768 int crn = (insn >> 16) & 0xf;
5769 int crm = insn & 0xf;
5770 int op1 = (insn >> 21) & 7;
5771 int op2 = (insn >> 5) & 7;
5772 int rt = (insn >> 12) & 0xf;
5773 TCGv tmp;
5774
5775 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5776 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5777 /* TEECR */
5778 if (IS_USER(s))
5779 return 1;
5780 tmp = load_cpu_field(teecr);
5781 store_reg(s, rt, tmp);
5782 return 0;
5783 }
5784 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5785 /* TEEHBR */
5786 if (IS_USER(s) && (env->teecr & 1))
5787 return 1;
5788 tmp = load_cpu_field(teehbr);
5789 store_reg(s, rt, tmp);
5790 return 0;
5791 }
5792 }
5793 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5794 op1, crn, crm, op2);
5795 return 1;
5796 }
5797
5798 static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5799 {
5800 int crn = (insn >> 16) & 0xf;
5801 int crm = insn & 0xf;
5802 int op1 = (insn >> 21) & 7;
5803 int op2 = (insn >> 5) & 7;
5804 int rt = (insn >> 12) & 0xf;
5805 TCGv tmp;
5806
5807 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5808 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5809 /* TEECR */
5810 if (IS_USER(s))
5811 return 1;
5812 tmp = load_reg(s, rt);
5813 gen_helper_set_teecr(cpu_env, tmp);
5814 dead_tmp(tmp);
5815 return 0;
5816 }
5817 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5818 /* TEEHBR */
5819 if (IS_USER(s) && (env->teecr & 1))
5820 return 1;
5821 tmp = load_reg(s, rt);
5822 store_cpu_field(tmp, teehbr);
5823 return 0;
5824 }
5825 }
5826 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5827 op1, crn, crm, op2);
5828 return 1;
5829 }
5830
5831 static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5832 {
5833 int cpnum;
5834
5835 cpnum = (insn >> 8) & 0xf;
5836 if (arm_feature(env, ARM_FEATURE_XSCALE)
5837 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5838 return 1;
5839
5840 switch (cpnum) {
5841 case 0:
5842 case 1:
5843 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5844 return disas_iwmmxt_insn(env, s, insn);
5845 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5846 return disas_dsp_insn(env, s, insn);
5847 }
5848 return 1;
5849 case 10:
5850 case 11:
5851 return disas_vfp_insn (env, s, insn);
5852 case 14:
5853 /* Coprocessors 7-15 are architecturally reserved by ARM.
5854 Unfortunately Intel decided to ignore this. */
5855 if (arm_feature(env, ARM_FEATURE_XSCALE))
5856 goto board;
5857 if (insn & (1 << 20))
5858 return disas_cp14_read(env, s, insn);
5859 else
5860 return disas_cp14_write(env, s, insn);
5861 case 15:
5862 return disas_cp15_insn (env, s, insn);
5863 default:
5864 board:
5865 /* Unknown coprocessor. See if the board has hooked it. */
5866 return disas_cp_insn (env, s, insn);
5867 }
5868 }
5869
5870
5871 /* Store a 64-bit value to a register pair. Clobbers val. */
5872 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5873 {
5874 TCGv tmp;
5875 tmp = new_tmp();
5876 tcg_gen_trunc_i64_i32(tmp, val);
5877 store_reg(s, rlow, tmp);
5878 tmp = new_tmp();
5879 tcg_gen_shri_i64(val, val, 32);
5880 tcg_gen_trunc_i64_i32(tmp, val);
5881 store_reg(s, rhigh, tmp);
5882 }
5883
5884 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
5885 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5886 {
5887 TCGv_i64 tmp;
5888 TCGv tmp2;
5889
5890 /* Load value and extend to 64 bits. */
5891 tmp = tcg_temp_new_i64();
5892 tmp2 = load_reg(s, rlow);
5893 tcg_gen_extu_i32_i64(tmp, tmp2);
5894 dead_tmp(tmp2);
5895 tcg_gen_add_i64(val, val, tmp);
5896 tcg_temp_free_i64(tmp);
5897 }
5898
5899 /* load and add a 64-bit value from a register pair. */
5900 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5901 {
5902 TCGv_i64 tmp;
5903 TCGv tmpl;
5904 TCGv tmph;
5905
5906 /* Load 64-bit value rd:rn. */
5907 tmpl = load_reg(s, rlow);
5908 tmph = load_reg(s, rhigh);
5909 tmp = tcg_temp_new_i64();
5910 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5911 dead_tmp(tmpl);
5912 dead_tmp(tmph);
5913 tcg_gen_add_i64(val, val, tmp);
5914 tcg_temp_free_i64(tmp);
5915 }
5916
5917 /* Set N and Z flags from a 64-bit value. */
5918 static void gen_logicq_cc(TCGv_i64 val)
5919 {
5920 TCGv tmp = new_tmp();
5921 gen_helper_logicq_cc(tmp, val);
5922 gen_logic_CC(tmp);
5923 dead_tmp(tmp);
5924 }
5925
5926 /* Load/Store exclusive instructions are implemented by remembering
5927 the value/address loaded, and seeing if these are the same
5928 when the store is performed. This should be is sufficient to implement
5929 the architecturally mandated semantics, and avoids having to monitor
5930 regular stores.
5931
5932 In system emulation mode only one CPU will be running at once, so
5933 this sequence is effectively atomic. In user emulation mode we
5934 throw an exception and handle the atomic operation elsewhere. */
5935 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5936 TCGv addr, int size)
5937 {
5938 TCGv tmp;
5939
5940 switch (size) {
5941 case 0:
5942 tmp = gen_ld8u(addr, IS_USER(s));
5943 break;
5944 case 1:
5945 tmp = gen_ld16u(addr, IS_USER(s));
5946 break;
5947 case 2:
5948 case 3:
5949 tmp = gen_ld32(addr, IS_USER(s));
5950 break;
5951 default:
5952 abort();
5953 }
5954 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
5955 store_reg(s, rt, tmp);
5956 if (size == 3) {
5957 TCGv tmp2 = new_tmp();
5958 tcg_gen_addi_i32(tmp2, addr, 4);
5959 tmp = gen_ld32(tmp2, IS_USER(s));
5960 dead_tmp(tmp2);
5961 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
5962 store_reg(s, rt2, tmp);
5963 }
5964 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
5965 }
5966
5967 static void gen_clrex(DisasContext *s)
5968 {
5969 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
5970 }
5971
5972 #ifdef CONFIG_USER_ONLY
5973 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5974 TCGv addr, int size)
5975 {
5976 tcg_gen_mov_i32(cpu_exclusive_test, addr);
5977 tcg_gen_movi_i32(cpu_exclusive_info,
5978 size | (rd << 4) | (rt << 8) | (rt2 << 12));
5979 gen_exception_insn(s, 4, EXCP_STREX);
5980 }
5981 #else
5982 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
5983 TCGv addr, int size)
5984 {
5985 TCGv tmp;
5986 int done_label;
5987 int fail_label;
5988
5989 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
5990 [addr] = {Rt};
5991 {Rd} = 0;
5992 } else {
5993 {Rd} = 1;
5994 } */
5995 fail_label = gen_new_label();
5996 done_label = gen_new_label();
5997 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
5998 switch (size) {
5999 case 0:
6000 tmp = gen_ld8u(addr, IS_USER(s));
6001 break;
6002 case 1:
6003 tmp = gen_ld16u(addr, IS_USER(s));
6004 break;
6005 case 2:
6006 case 3:
6007 tmp = gen_ld32(addr, IS_USER(s));
6008 break;
6009 default:
6010 abort();
6011 }
6012 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
6013 dead_tmp(tmp);
6014 if (size == 3) {
6015 TCGv tmp2 = new_tmp();
6016 tcg_gen_addi_i32(tmp2, addr, 4);
6017 tmp = gen_ld32(tmp2, IS_USER(s));
6018 dead_tmp(tmp2);
6019 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6020 dead_tmp(tmp);
6021 }
6022 tmp = load_reg(s, rt);
6023 switch (size) {
6024 case 0:
6025 gen_st8(tmp, addr, IS_USER(s));
6026 break;
6027 case 1:
6028 gen_st16(tmp, addr, IS_USER(s));
6029 break;
6030 case 2:
6031 case 3:
6032 gen_st32(tmp, addr, IS_USER(s));
6033 break;
6034 default:
6035 abort();
6036 }
6037 if (size == 3) {
6038 tcg_gen_addi_i32(addr, addr, 4);
6039 tmp = load_reg(s, rt2);
6040 gen_st32(tmp, addr, IS_USER(s));
6041 }
6042 tcg_gen_movi_i32(cpu_R[rd], 0);
6043 tcg_gen_br(done_label);
6044 gen_set_label(fail_label);
6045 tcg_gen_movi_i32(cpu_R[rd], 1);
6046 gen_set_label(done_label);
6047 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6048 }
6049 #endif
6050
6051 static void disas_arm_insn(CPUState * env, DisasContext *s)
6052 {
6053 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6054 TCGv tmp;
6055 TCGv tmp2;
6056 TCGv tmp3;
6057 TCGv addr;
6058 TCGv_i64 tmp64;
6059
6060 insn = ldl_code(s->pc);
6061 s->pc += 4;
6062
6063 /* M variants do not implement ARM mode. */
6064 if (IS_M(env))
6065 goto illegal_op;
6066 cond = insn >> 28;
6067 if (cond == 0xf){
6068 /* Unconditional instructions. */
6069 if (((insn >> 25) & 7) == 1) {
6070 /* NEON Data processing. */
6071 if (!arm_feature(env, ARM_FEATURE_NEON))
6072 goto illegal_op;
6073
6074 if (disas_neon_data_insn(env, s, insn))
6075 goto illegal_op;
6076 return;
6077 }
6078 if ((insn & 0x0f100000) == 0x04000000) {
6079 /* NEON load/store. */
6080 if (!arm_feature(env, ARM_FEATURE_NEON))
6081 goto illegal_op;
6082
6083 if (disas_neon_ls_insn(env, s, insn))
6084 goto illegal_op;
6085 return;
6086 }
6087 if (((insn & 0x0f30f000) == 0x0510f000) ||
6088 ((insn & 0x0f30f010) == 0x0710f000)) {
6089 if ((insn & (1 << 22)) == 0) {
6090 /* PLDW; v7MP */
6091 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6092 goto illegal_op;
6093 }
6094 }
6095 /* Otherwise PLD; v5TE+ */
6096 return;
6097 }
6098 if (((insn & 0x0f70f000) == 0x0450f000) ||
6099 ((insn & 0x0f70f010) == 0x0650f000)) {
6100 ARCH(7);
6101 return; /* PLI; V7 */
6102 }
6103 if (((insn & 0x0f700000) == 0x04100000) ||
6104 ((insn & 0x0f700010) == 0x06100000)) {
6105 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6106 goto illegal_op;
6107 }
6108 return; /* v7MP: Unallocated memory hint: must NOP */
6109 }
6110
6111 if ((insn & 0x0ffffdff) == 0x01010000) {
6112 ARCH(6);
6113 /* setend */
6114 if (insn & (1 << 9)) {
6115 /* BE8 mode not implemented. */
6116 goto illegal_op;
6117 }
6118 return;
6119 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6120 switch ((insn >> 4) & 0xf) {
6121 case 1: /* clrex */
6122 ARCH(6K);
6123 gen_clrex(s);
6124 return;
6125 case 4: /* dsb */
6126 case 5: /* dmb */
6127 case 6: /* isb */
6128 ARCH(7);
6129 /* We don't emulate caches so these are a no-op. */
6130 return;
6131 default:
6132 goto illegal_op;
6133 }
6134 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6135 /* srs */
6136 int32_t offset;
6137 if (IS_USER(s))
6138 goto illegal_op;
6139 ARCH(6);
6140 op1 = (insn & 0x1f);
6141 addr = new_tmp();
6142 tmp = tcg_const_i32(op1);
6143 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6144 tcg_temp_free_i32(tmp);
6145 i = (insn >> 23) & 3;
6146 switch (i) {
6147 case 0: offset = -4; break; /* DA */
6148 case 1: offset = 0; break; /* IA */
6149 case 2: offset = -8; break; /* DB */
6150 case 3: offset = 4; break; /* IB */
6151 default: abort();
6152 }
6153 if (offset)
6154 tcg_gen_addi_i32(addr, addr, offset);
6155 tmp = load_reg(s, 14);
6156 gen_st32(tmp, addr, 0);
6157 tmp = load_cpu_field(spsr);
6158 tcg_gen_addi_i32(addr, addr, 4);
6159 gen_st32(tmp, addr, 0);
6160 if (insn & (1 << 21)) {
6161 /* Base writeback. */
6162 switch (i) {
6163 case 0: offset = -8; break;
6164 case 1: offset = 4; break;
6165 case 2: offset = -4; break;
6166 case 3: offset = 0; break;
6167 default: abort();
6168 }
6169 if (offset)
6170 tcg_gen_addi_i32(addr, addr, offset);
6171 tmp = tcg_const_i32(op1);
6172 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6173 tcg_temp_free_i32(tmp);
6174 dead_tmp(addr);
6175 } else {
6176 dead_tmp(addr);
6177 }
6178 return;
6179 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
6180 /* rfe */
6181 int32_t offset;
6182 if (IS_USER(s))
6183 goto illegal_op;
6184 ARCH(6);
6185 rn = (insn >> 16) & 0xf;
6186 addr = load_reg(s, rn);
6187 i = (insn >> 23) & 3;
6188 switch (i) {
6189 case 0: offset = -4; break; /* DA */
6190 case 1: offset = 0; break; /* IA */
6191 case 2: offset = -8; break; /* DB */
6192 case 3: offset = 4; break; /* IB */
6193 default: abort();
6194 }
6195 if (offset)
6196 tcg_gen_addi_i32(addr, addr, offset);
6197 /* Load PC into tmp and CPSR into tmp2. */
6198 tmp = gen_ld32(addr, 0);
6199 tcg_gen_addi_i32(addr, addr, 4);
6200 tmp2 = gen_ld32(addr, 0);
6201 if (insn & (1 << 21)) {
6202 /* Base writeback. */
6203 switch (i) {
6204 case 0: offset = -8; break;
6205 case 1: offset = 4; break;
6206 case 2: offset = -4; break;
6207 case 3: offset = 0; break;
6208 default: abort();
6209 }
6210 if (offset)
6211 tcg_gen_addi_i32(addr, addr, offset);
6212 store_reg(s, rn, addr);
6213 } else {
6214 dead_tmp(addr);
6215 }
6216 gen_rfe(s, tmp, tmp2);
6217 return;
6218 } else if ((insn & 0x0e000000) == 0x0a000000) {
6219 /* branch link and change to thumb (blx <offset>) */
6220 int32_t offset;
6221
6222 val = (uint32_t)s->pc;
6223 tmp = new_tmp();
6224 tcg_gen_movi_i32(tmp, val);
6225 store_reg(s, 14, tmp);
6226 /* Sign-extend the 24-bit offset */
6227 offset = (((int32_t)insn) << 8) >> 8;
6228 /* offset * 4 + bit24 * 2 + (thumb bit) */
6229 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6230 /* pipeline offset */
6231 val += 4;
6232 gen_bx_im(s, val);
6233 return;
6234 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6235 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6236 /* iWMMXt register transfer. */
6237 if (env->cp15.c15_cpar & (1 << 1))
6238 if (!disas_iwmmxt_insn(env, s, insn))
6239 return;
6240 }
6241 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6242 /* Coprocessor double register transfer. */
6243 } else if ((insn & 0x0f000010) == 0x0e000010) {
6244 /* Additional coprocessor register transfer. */
6245 } else if ((insn & 0x0ff10020) == 0x01000000) {
6246 uint32_t mask;
6247 uint32_t val;
6248 /* cps (privileged) */
6249 if (IS_USER(s))
6250 return;
6251 mask = val = 0;
6252 if (insn & (1 << 19)) {
6253 if (insn & (1 << 8))
6254 mask |= CPSR_A;
6255 if (insn & (1 << 7))
6256 mask |= CPSR_I;
6257 if (insn & (1 << 6))
6258 mask |= CPSR_F;
6259 if (insn & (1 << 18))
6260 val |= mask;
6261 }
6262 if (insn & (1 << 17)) {
6263 mask |= CPSR_M;
6264 val |= (insn & 0x1f);
6265 }
6266 if (mask) {
6267 gen_set_psr_im(s, mask, 0, val);
6268 }
6269 return;
6270 }
6271 goto illegal_op;
6272 }
6273 if (cond != 0xe) {
6274 /* if not always execute, we generate a conditional jump to
6275 next instruction */
6276 s->condlabel = gen_new_label();
6277 gen_test_cc(cond ^ 1, s->condlabel);
6278 s->condjmp = 1;
6279 }
6280 if ((insn & 0x0f900000) == 0x03000000) {
6281 if ((insn & (1 << 21)) == 0) {
6282 ARCH(6T2);
6283 rd = (insn >> 12) & 0xf;
6284 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6285 if ((insn & (1 << 22)) == 0) {
6286 /* MOVW */
6287 tmp = new_tmp();
6288 tcg_gen_movi_i32(tmp, val);
6289 } else {
6290 /* MOVT */
6291 tmp = load_reg(s, rd);
6292 tcg_gen_ext16u_i32(tmp, tmp);
6293 tcg_gen_ori_i32(tmp, tmp, val << 16);
6294 }
6295 store_reg(s, rd, tmp);
6296 } else {
6297 if (((insn >> 12) & 0xf) != 0xf)
6298 goto illegal_op;
6299 if (((insn >> 16) & 0xf) == 0) {
6300 gen_nop_hint(s, insn & 0xff);
6301 } else {
6302 /* CPSR = immediate */
6303 val = insn & 0xff;
6304 shift = ((insn >> 8) & 0xf) * 2;
6305 if (shift)
6306 val = (val >> shift) | (val << (32 - shift));
6307 i = ((insn & (1 << 22)) != 0);
6308 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
6309 goto illegal_op;
6310 }
6311 }
6312 } else if ((insn & 0x0f900000) == 0x01000000
6313 && (insn & 0x00000090) != 0x00000090) {
6314 /* miscellaneous instructions */
6315 op1 = (insn >> 21) & 3;
6316 sh = (insn >> 4) & 0xf;
6317 rm = insn & 0xf;
6318 switch (sh) {
6319 case 0x0: /* move program status register */
6320 if (op1 & 1) {
6321 /* PSR = reg */
6322 tmp = load_reg(s, rm);
6323 i = ((op1 & 2) != 0);
6324 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
6325 goto illegal_op;
6326 } else {
6327 /* reg = PSR */
6328 rd = (insn >> 12) & 0xf;
6329 if (op1 & 2) {
6330 if (IS_USER(s))
6331 goto illegal_op;
6332 tmp = load_cpu_field(spsr);
6333 } else {
6334 tmp = new_tmp();
6335 gen_helper_cpsr_read(tmp);
6336 }
6337 store_reg(s, rd, tmp);
6338 }
6339 break;
6340 case 0x1:
6341 if (op1 == 1) {
6342 /* branch/exchange thumb (bx). */
6343 tmp = load_reg(s, rm);
6344 gen_bx(s, tmp);
6345 } else if (op1 == 3) {
6346 /* clz */
6347 rd = (insn >> 12) & 0xf;
6348 tmp = load_reg(s, rm);
6349 gen_helper_clz(tmp, tmp);
6350 store_reg(s, rd, tmp);
6351 } else {
6352 goto illegal_op;
6353 }
6354 break;
6355 case 0x2:
6356 if (op1 == 1) {
6357 ARCH(5J); /* bxj */
6358 /* Trivial implementation equivalent to bx. */
6359 tmp = load_reg(s, rm);
6360 gen_bx(s, tmp);
6361 } else {
6362 goto illegal_op;
6363 }
6364 break;
6365 case 0x3:
6366 if (op1 != 1)
6367 goto illegal_op;
6368
6369 /* branch link/exchange thumb (blx) */
6370 tmp = load_reg(s, rm);
6371 tmp2 = new_tmp();
6372 tcg_gen_movi_i32(tmp2, s->pc);
6373 store_reg(s, 14, tmp2);
6374 gen_bx(s, tmp);
6375 break;
6376 case 0x5: /* saturating add/subtract */
6377 rd = (insn >> 12) & 0xf;
6378 rn = (insn >> 16) & 0xf;
6379 tmp = load_reg(s, rm);
6380 tmp2 = load_reg(s, rn);
6381 if (op1 & 2)
6382 gen_helper_double_saturate(tmp2, tmp2);
6383 if (op1 & 1)
6384 gen_helper_sub_saturate(tmp, tmp, tmp2);
6385 else
6386 gen_helper_add_saturate(tmp, tmp, tmp2);
6387 dead_tmp(tmp2);
6388 store_reg(s, rd, tmp);
6389 break;
6390 case 7:
6391 /* SMC instruction (op1 == 3)
6392 and undefined instructions (op1 == 0 || op1 == 2)
6393 will trap */
6394 if (op1 != 1) {
6395 goto illegal_op;
6396 }
6397 /* bkpt */
6398 gen_exception_insn(s, 4, EXCP_BKPT);
6399 break;
6400 case 0x8: /* signed multiply */
6401 case 0xa:
6402 case 0xc:
6403 case 0xe:
6404 rs = (insn >> 8) & 0xf;
6405 rn = (insn >> 12) & 0xf;
6406 rd = (insn >> 16) & 0xf;
6407 if (op1 == 1) {
6408 /* (32 * 16) >> 16 */
6409 tmp = load_reg(s, rm);
6410 tmp2 = load_reg(s, rs);
6411 if (sh & 4)
6412 tcg_gen_sari_i32(tmp2, tmp2, 16);
6413 else
6414 gen_sxth(tmp2);
6415 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6416 tcg_gen_shri_i64(tmp64, tmp64, 16);
6417 tmp = new_tmp();
6418 tcg_gen_trunc_i64_i32(tmp, tmp64);
6419 tcg_temp_free_i64(tmp64);
6420 if ((sh & 2) == 0) {
6421 tmp2 = load_reg(s, rn);
6422 gen_helper_add_setq(tmp, tmp, tmp2);
6423 dead_tmp(tmp2);
6424 }
6425 store_reg(s, rd, tmp);
6426 } else {
6427 /* 16 * 16 */
6428 tmp = load_reg(s, rm);
6429 tmp2 = load_reg(s, rs);
6430 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6431 dead_tmp(tmp2);
6432 if (op1 == 2) {
6433 tmp64 = tcg_temp_new_i64();
6434 tcg_gen_ext_i32_i64(tmp64, tmp);
6435 dead_tmp(tmp);
6436 gen_addq(s, tmp64, rn, rd);
6437 gen_storeq_reg(s, rn, rd, tmp64);
6438 tcg_temp_free_i64(tmp64);
6439 } else {
6440 if (op1 == 0) {
6441 tmp2 = load_reg(s, rn);
6442 gen_helper_add_setq(tmp, tmp, tmp2);
6443 dead_tmp(tmp2);
6444 }
6445 store_reg(s, rd, tmp);
6446 }
6447 }
6448 break;
6449 default:
6450 goto illegal_op;
6451 }
6452 } else if (((insn & 0x0e000000) == 0 &&
6453 (insn & 0x00000090) != 0x90) ||
6454 ((insn & 0x0e000000) == (1 << 25))) {
6455 int set_cc, logic_cc, shiftop;
6456
6457 op1 = (insn >> 21) & 0xf;
6458 set_cc = (insn >> 20) & 1;
6459 logic_cc = table_logic_cc[op1] & set_cc;
6460
6461 /* data processing instruction */
6462 if (insn & (1 << 25)) {
6463 /* immediate operand */
6464 val = insn & 0xff;
6465 shift = ((insn >> 8) & 0xf) * 2;
6466 if (shift) {
6467 val = (val >> shift) | (val << (32 - shift));
6468 }
6469 tmp2 = new_tmp();
6470 tcg_gen_movi_i32(tmp2, val);
6471 if (logic_cc && shift) {
6472 gen_set_CF_bit31(tmp2);
6473 }
6474 } else {
6475 /* register */
6476 rm = (insn) & 0xf;
6477 tmp2 = load_reg(s, rm);
6478 shiftop = (insn >> 5) & 3;
6479 if (!(insn & (1 << 4))) {
6480 shift = (insn >> 7) & 0x1f;
6481 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
6482 } else {
6483 rs = (insn >> 8) & 0xf;
6484 tmp = load_reg(s, rs);
6485 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
6486 }
6487 }
6488 if (op1 != 0x0f && op1 != 0x0d) {
6489 rn = (insn >> 16) & 0xf;
6490 tmp = load_reg(s, rn);
6491 } else {
6492 TCGV_UNUSED(tmp);
6493 }
6494 rd = (insn >> 12) & 0xf;
6495 switch(op1) {
6496 case 0x00:
6497 tcg_gen_and_i32(tmp, tmp, tmp2);
6498 if (logic_cc) {
6499 gen_logic_CC(tmp);
6500 }
6501 store_reg_bx(env, s, rd, tmp);
6502 break;
6503 case 0x01:
6504 tcg_gen_xor_i32(tmp, tmp, tmp2);
6505 if (logic_cc) {
6506 gen_logic_CC(tmp);
6507 }
6508 store_reg_bx(env, s, rd, tmp);
6509 break;
6510 case 0x02:
6511 if (set_cc && rd == 15) {
6512 /* SUBS r15, ... is used for exception return. */
6513 if (IS_USER(s)) {
6514 goto illegal_op;
6515 }
6516 gen_helper_sub_cc(tmp, tmp, tmp2);
6517 gen_exception_return(s, tmp);
6518 } else {
6519 if (set_cc) {
6520 gen_helper_sub_cc(tmp, tmp, tmp2);
6521 } else {
6522 tcg_gen_sub_i32(tmp, tmp, tmp2);
6523 }
6524 store_reg_bx(env, s, rd, tmp);
6525 }
6526 break;
6527 case 0x03:
6528 if (set_cc) {
6529 gen_helper_sub_cc(tmp, tmp2, tmp);
6530 } else {
6531 tcg_gen_sub_i32(tmp, tmp2, tmp);
6532 }
6533 store_reg_bx(env, s, rd, tmp);
6534 break;
6535 case 0x04:
6536 if (set_cc) {
6537 gen_helper_add_cc(tmp, tmp, tmp2);
6538 } else {
6539 tcg_gen_add_i32(tmp, tmp, tmp2);
6540 }
6541 store_reg_bx(env, s, rd, tmp);
6542 break;
6543 case 0x05:
6544 if (set_cc) {
6545 gen_helper_adc_cc(tmp, tmp, tmp2);
6546 } else {
6547 gen_add_carry(tmp, tmp, tmp2);
6548 }
6549 store_reg_bx(env, s, rd, tmp);
6550 break;
6551 case 0x06:
6552 if (set_cc) {
6553 gen_helper_sbc_cc(tmp, tmp, tmp2);
6554 } else {
6555 gen_sub_carry(tmp, tmp, tmp2);
6556 }
6557 store_reg_bx(env, s, rd, tmp);
6558 break;
6559 case 0x07:
6560 if (set_cc) {
6561 gen_helper_sbc_cc(tmp, tmp2, tmp);
6562 } else {
6563 gen_sub_carry(tmp, tmp2, tmp);
6564 }
6565 store_reg_bx(env, s, rd, tmp);
6566 break;
6567 case 0x08:
6568 if (set_cc) {
6569 tcg_gen_and_i32(tmp, tmp, tmp2);
6570 gen_logic_CC(tmp);
6571 }
6572 dead_tmp(tmp);
6573 break;
6574 case 0x09:
6575 if (set_cc) {
6576 tcg_gen_xor_i32(tmp, tmp, tmp2);
6577 gen_logic_CC(tmp);
6578 }
6579 dead_tmp(tmp);
6580 break;
6581 case 0x0a:
6582 if (set_cc) {
6583 gen_helper_sub_cc(tmp, tmp, tmp2);
6584 }
6585 dead_tmp(tmp);
6586 break;
6587 case 0x0b:
6588 if (set_cc) {
6589 gen_helper_add_cc(tmp, tmp, tmp2);
6590 }
6591 dead_tmp(tmp);
6592 break;
6593 case 0x0c:
6594 tcg_gen_or_i32(tmp, tmp, tmp2);
6595 if (logic_cc) {
6596 gen_logic_CC(tmp);
6597 }
6598 store_reg_bx(env, s, rd, tmp);
6599 break;
6600 case 0x0d:
6601 if (logic_cc && rd == 15) {
6602 /* MOVS r15, ... is used for exception return. */
6603 if (IS_USER(s)) {
6604 goto illegal_op;
6605 }
6606 gen_exception_return(s, tmp2);
6607 } else {
6608 if (logic_cc) {
6609 gen_logic_CC(tmp2);
6610 }
6611 store_reg_bx(env, s, rd, tmp2);
6612 }
6613 break;
6614 case 0x0e:
6615 tcg_gen_andc_i32(tmp, tmp, tmp2);
6616 if (logic_cc) {
6617 gen_logic_CC(tmp);
6618 }
6619 store_reg_bx(env, s, rd, tmp);
6620 break;
6621 default:
6622 case 0x0f:
6623 tcg_gen_not_i32(tmp2, tmp2);
6624 if (logic_cc) {
6625 gen_logic_CC(tmp2);
6626 }
6627 store_reg_bx(env, s, rd, tmp2);
6628 break;
6629 }
6630 if (op1 != 0x0f && op1 != 0x0d) {
6631 dead_tmp(tmp2);
6632 }
6633 } else {
6634 /* other instructions */
6635 op1 = (insn >> 24) & 0xf;
6636 switch(op1) {
6637 case 0x0:
6638 case 0x1:
6639 /* multiplies, extra load/stores */
6640 sh = (insn >> 5) & 3;
6641 if (sh == 0) {
6642 if (op1 == 0x0) {
6643 rd = (insn >> 16) & 0xf;
6644 rn = (insn >> 12) & 0xf;
6645 rs = (insn >> 8) & 0xf;
6646 rm = (insn) & 0xf;
6647 op1 = (insn >> 20) & 0xf;
6648 switch (op1) {
6649 case 0: case 1: case 2: case 3: case 6:
6650 /* 32 bit mul */
6651 tmp = load_reg(s, rs);
6652 tmp2 = load_reg(s, rm);
6653 tcg_gen_mul_i32(tmp, tmp, tmp2);
6654 dead_tmp(tmp2);
6655 if (insn & (1 << 22)) {
6656 /* Subtract (mls) */
6657 ARCH(6T2);
6658 tmp2 = load_reg(s, rn);
6659 tcg_gen_sub_i32(tmp, tmp2, tmp);
6660 dead_tmp(tmp2);
6661 } else if (insn & (1 << 21)) {
6662 /* Add */
6663 tmp2 = load_reg(s, rn);
6664 tcg_gen_add_i32(tmp, tmp, tmp2);
6665 dead_tmp(tmp2);
6666 }
6667 if (insn & (1 << 20))
6668 gen_logic_CC(tmp);
6669 store_reg(s, rd, tmp);
6670 break;
6671 case 4:
6672 /* 64 bit mul double accumulate (UMAAL) */
6673 ARCH(6);
6674 tmp = load_reg(s, rs);
6675 tmp2 = load_reg(s, rm);
6676 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6677 gen_addq_lo(s, tmp64, rn);
6678 gen_addq_lo(s, tmp64, rd);
6679 gen_storeq_reg(s, rn, rd, tmp64);
6680 tcg_temp_free_i64(tmp64);
6681 break;
6682 case 8: case 9: case 10: case 11:
6683 case 12: case 13: case 14: case 15:
6684 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
6685 tmp = load_reg(s, rs);
6686 tmp2 = load_reg(s, rm);
6687 if (insn & (1 << 22)) {
6688 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6689 } else {
6690 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6691 }
6692 if (insn & (1 << 21)) { /* mult accumulate */
6693 gen_addq(s, tmp64, rn, rd);
6694 }
6695 if (insn & (1 << 20)) {
6696 gen_logicq_cc(tmp64);
6697 }
6698 gen_storeq_reg(s, rn, rd, tmp64);
6699 tcg_temp_free_i64(tmp64);
6700 break;
6701 default:
6702 goto illegal_op;
6703 }
6704 } else {
6705 rn = (insn >> 16) & 0xf;
6706 rd = (insn >> 12) & 0xf;
6707 if (insn & (1 << 23)) {
6708 /* load/store exclusive */
6709 op1 = (insn >> 21) & 0x3;
6710 if (op1)
6711 ARCH(6K);
6712 else
6713 ARCH(6);
6714 addr = tcg_temp_local_new_i32();
6715 load_reg_var(s, addr, rn);
6716 if (insn & (1 << 20)) {
6717 switch (op1) {
6718 case 0: /* ldrex */
6719 gen_load_exclusive(s, rd, 15, addr, 2);
6720 break;
6721 case 1: /* ldrexd */
6722 gen_load_exclusive(s, rd, rd + 1, addr, 3);
6723 break;
6724 case 2: /* ldrexb */
6725 gen_load_exclusive(s, rd, 15, addr, 0);
6726 break;
6727 case 3: /* ldrexh */
6728 gen_load_exclusive(s, rd, 15, addr, 1);
6729 break;
6730 default:
6731 abort();
6732 }
6733 } else {
6734 rm = insn & 0xf;
6735 switch (op1) {
6736 case 0: /* strex */
6737 gen_store_exclusive(s, rd, rm, 15, addr, 2);
6738 break;
6739 case 1: /* strexd */
6740 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
6741 break;
6742 case 2: /* strexb */
6743 gen_store_exclusive(s, rd, rm, 15, addr, 0);
6744 break;
6745 case 3: /* strexh */
6746 gen_store_exclusive(s, rd, rm, 15, addr, 1);
6747 break;
6748 default:
6749 abort();
6750 }
6751 }
6752 tcg_temp_free(addr);
6753 } else {
6754 /* SWP instruction */
6755 rm = (insn) & 0xf;
6756
6757 /* ??? This is not really atomic. However we know
6758 we never have multiple CPUs running in parallel,
6759 so it is good enough. */
6760 addr = load_reg(s, rn);
6761 tmp = load_reg(s, rm);
6762 if (insn & (1 << 22)) {
6763 tmp2 = gen_ld8u(addr, IS_USER(s));
6764 gen_st8(tmp, addr, IS_USER(s));
6765 } else {
6766 tmp2 = gen_ld32(addr, IS_USER(s));
6767 gen_st32(tmp, addr, IS_USER(s));
6768 }
6769 dead_tmp(addr);
6770 store_reg(s, rd, tmp2);
6771 }
6772 }
6773 } else {
6774 int address_offset;
6775 int load;
6776 /* Misc load/store */
6777 rn = (insn >> 16) & 0xf;
6778 rd = (insn >> 12) & 0xf;
6779 addr = load_reg(s, rn);
6780 if (insn & (1 << 24))
6781 gen_add_datah_offset(s, insn, 0, addr);
6782 address_offset = 0;
6783 if (insn & (1 << 20)) {
6784 /* load */
6785 switch(sh) {
6786 case 1:
6787 tmp = gen_ld16u(addr, IS_USER(s));
6788 break;
6789 case 2:
6790 tmp = gen_ld8s(addr, IS_USER(s));
6791 break;
6792 default:
6793 case 3:
6794 tmp = gen_ld16s(addr, IS_USER(s));
6795 break;
6796 }
6797 load = 1;
6798 } else if (sh & 2) {
6799 /* doubleword */
6800 if (sh & 1) {
6801 /* store */
6802 tmp = load_reg(s, rd);
6803 gen_st32(tmp, addr, IS_USER(s));
6804 tcg_gen_addi_i32(addr, addr, 4);
6805 tmp = load_reg(s, rd + 1);
6806 gen_st32(tmp, addr, IS_USER(s));
6807 load = 0;
6808 } else {
6809 /* load */
6810 tmp = gen_ld32(addr, IS_USER(s));
6811 store_reg(s, rd, tmp);
6812 tcg_gen_addi_i32(addr, addr, 4);
6813 tmp = gen_ld32(addr, IS_USER(s));
6814 rd++;
6815 load = 1;
6816 }
6817 address_offset = -4;
6818 } else {
6819 /* store */
6820 tmp = load_reg(s, rd);
6821 gen_st16(tmp, addr, IS_USER(s));
6822 load = 0;
6823 }
6824 /* Perform base writeback before the loaded value to
6825 ensure correct behavior with overlapping index registers.
6826 ldrd with base writeback is is undefined if the
6827 destination and index registers overlap. */
6828 if (!(insn & (1 << 24))) {
6829 gen_add_datah_offset(s, insn, address_offset, addr);
6830 store_reg(s, rn, addr);
6831 } else if (insn & (1 << 21)) {
6832 if (address_offset)
6833 tcg_gen_addi_i32(addr, addr, address_offset);
6834 store_reg(s, rn, addr);
6835 } else {
6836 dead_tmp(addr);
6837 }
6838 if (load) {
6839 /* Complete the load. */
6840 store_reg(s, rd, tmp);
6841 }
6842 }
6843 break;
6844 case 0x4:
6845 case 0x5:
6846 goto do_ldst;
6847 case 0x6:
6848 case 0x7:
6849 if (insn & (1 << 4)) {
6850 ARCH(6);
6851 /* Armv6 Media instructions. */
6852 rm = insn & 0xf;
6853 rn = (insn >> 16) & 0xf;
6854 rd = (insn >> 12) & 0xf;
6855 rs = (insn >> 8) & 0xf;
6856 switch ((insn >> 23) & 3) {
6857 case 0: /* Parallel add/subtract. */
6858 op1 = (insn >> 20) & 7;
6859 tmp = load_reg(s, rn);
6860 tmp2 = load_reg(s, rm);
6861 sh = (insn >> 5) & 7;
6862 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6863 goto illegal_op;
6864 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6865 dead_tmp(tmp2);
6866 store_reg(s, rd, tmp);
6867 break;
6868 case 1:
6869 if ((insn & 0x00700020) == 0) {
6870 /* Halfword pack. */
6871 tmp = load_reg(s, rn);
6872 tmp2 = load_reg(s, rm);
6873 shift = (insn >> 7) & 0x1f;
6874 if (insn & (1 << 6)) {
6875 /* pkhtb */
6876 if (shift == 0)
6877 shift = 31;
6878 tcg_gen_sari_i32(tmp2, tmp2, shift);
6879 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
6880 tcg_gen_ext16u_i32(tmp2, tmp2);
6881 } else {
6882 /* pkhbt */
6883 if (shift)
6884 tcg_gen_shli_i32(tmp2, tmp2, shift);
6885 tcg_gen_ext16u_i32(tmp, tmp);
6886 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6887 }
6888 tcg_gen_or_i32(tmp, tmp, tmp2);
6889 dead_tmp(tmp2);
6890 store_reg(s, rd, tmp);
6891 } else if ((insn & 0x00200020) == 0x00200000) {
6892 /* [us]sat */
6893 tmp = load_reg(s, rm);
6894 shift = (insn >> 7) & 0x1f;
6895 if (insn & (1 << 6)) {
6896 if (shift == 0)
6897 shift = 31;
6898 tcg_gen_sari_i32(tmp, tmp, shift);
6899 } else {
6900 tcg_gen_shli_i32(tmp, tmp, shift);
6901 }
6902 sh = (insn >> 16) & 0x1f;
6903 tmp2 = tcg_const_i32(sh);
6904 if (insn & (1 << 22))
6905 gen_helper_usat(tmp, tmp, tmp2);
6906 else
6907 gen_helper_ssat(tmp, tmp, tmp2);
6908 tcg_temp_free_i32(tmp2);
6909 store_reg(s, rd, tmp);
6910 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6911 /* [us]sat16 */
6912 tmp = load_reg(s, rm);
6913 sh = (insn >> 16) & 0x1f;
6914 tmp2 = tcg_const_i32(sh);
6915 if (insn & (1 << 22))
6916 gen_helper_usat16(tmp, tmp, tmp2);
6917 else
6918 gen_helper_ssat16(tmp, tmp, tmp2);
6919 tcg_temp_free_i32(tmp2);
6920 store_reg(s, rd, tmp);
6921 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6922 /* Select bytes. */
6923 tmp = load_reg(s, rn);
6924 tmp2 = load_reg(s, rm);
6925 tmp3 = new_tmp();
6926 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6927 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6928 dead_tmp(tmp3);
6929 dead_tmp(tmp2);
6930 store_reg(s, rd, tmp);
6931 } else if ((insn & 0x000003e0) == 0x00000060) {
6932 tmp = load_reg(s, rm);
6933 shift = (insn >> 10) & 3;
6934 /* ??? In many cases it's not neccessary to do a
6935 rotate, a shift is sufficient. */
6936 if (shift != 0)
6937 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
6938 op1 = (insn >> 20) & 7;
6939 switch (op1) {
6940 case 0: gen_sxtb16(tmp); break;
6941 case 2: gen_sxtb(tmp); break;
6942 case 3: gen_sxth(tmp); break;
6943 case 4: gen_uxtb16(tmp); break;
6944 case 6: gen_uxtb(tmp); break;
6945 case 7: gen_uxth(tmp); break;
6946 default: goto illegal_op;
6947 }
6948 if (rn != 15) {
6949 tmp2 = load_reg(s, rn);
6950 if ((op1 & 3) == 0) {
6951 gen_add16(tmp, tmp2);
6952 } else {
6953 tcg_gen_add_i32(tmp, tmp, tmp2);
6954 dead_tmp(tmp2);
6955 }
6956 }
6957 store_reg(s, rd, tmp);
6958 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6959 /* rev */
6960 tmp = load_reg(s, rm);
6961 if (insn & (1 << 22)) {
6962 if (insn & (1 << 7)) {
6963 gen_revsh(tmp);
6964 } else {
6965 ARCH(6T2);
6966 gen_helper_rbit(tmp, tmp);
6967 }
6968 } else {
6969 if (insn & (1 << 7))
6970 gen_rev16(tmp);
6971 else
6972 tcg_gen_bswap32_i32(tmp, tmp);
6973 }
6974 store_reg(s, rd, tmp);
6975 } else {
6976 goto illegal_op;
6977 }
6978 break;
6979 case 2: /* Multiplies (Type 3). */
6980 tmp = load_reg(s, rm);
6981 tmp2 = load_reg(s, rs);
6982 if (insn & (1 << 20)) {
6983 /* Signed multiply most significant [accumulate].
6984 (SMMUL, SMMLA, SMMLS) */
6985 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6986
6987 if (rd != 15) {
6988 tmp = load_reg(s, rd);
6989 if (insn & (1 << 6)) {
6990 tmp64 = gen_subq_msw(tmp64, tmp);
6991 } else {
6992 tmp64 = gen_addq_msw(tmp64, tmp);
6993 }
6994 }
6995 if (insn & (1 << 5)) {
6996 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
6997 }
6998 tcg_gen_shri_i64(tmp64, tmp64, 32);
6999 tmp = new_tmp();
7000 tcg_gen_trunc_i64_i32(tmp, tmp64);
7001 tcg_temp_free_i64(tmp64);
7002 store_reg(s, rn, tmp);
7003 } else {
7004 if (insn & (1 << 5))
7005 gen_swap_half(tmp2);
7006 gen_smul_dual(tmp, tmp2);
7007 /* This addition cannot overflow. */
7008 if (insn & (1 << 6)) {
7009 tcg_gen_sub_i32(tmp, tmp, tmp2);
7010 } else {
7011 tcg_gen_add_i32(tmp, tmp, tmp2);
7012 }
7013 dead_tmp(tmp2);
7014 if (insn & (1 << 22)) {
7015 /* smlald, smlsld */
7016 tmp64 = tcg_temp_new_i64();
7017 tcg_gen_ext_i32_i64(tmp64, tmp);
7018 dead_tmp(tmp);
7019 gen_addq(s, tmp64, rd, rn);
7020 gen_storeq_reg(s, rd, rn, tmp64);
7021 tcg_temp_free_i64(tmp64);
7022 } else {
7023 /* smuad, smusd, smlad, smlsd */
7024 if (rd != 15)
7025 {
7026 tmp2 = load_reg(s, rd);
7027 gen_helper_add_setq(tmp, tmp, tmp2);
7028 dead_tmp(tmp2);
7029 }
7030 store_reg(s, rn, tmp);
7031 }
7032 }
7033 break;
7034 case 3:
7035 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7036 switch (op1) {
7037 case 0: /* Unsigned sum of absolute differences. */
7038 ARCH(6);
7039 tmp = load_reg(s, rm);
7040 tmp2 = load_reg(s, rs);
7041 gen_helper_usad8(tmp, tmp, tmp2);
7042 dead_tmp(tmp2);
7043 if (rd != 15) {
7044 tmp2 = load_reg(s, rd);
7045 tcg_gen_add_i32(tmp, tmp, tmp2);
7046 dead_tmp(tmp2);
7047 }
7048 store_reg(s, rn, tmp);
7049 break;
7050 case 0x20: case 0x24: case 0x28: case 0x2c:
7051 /* Bitfield insert/clear. */
7052 ARCH(6T2);
7053 shift = (insn >> 7) & 0x1f;
7054 i = (insn >> 16) & 0x1f;
7055 i = i + 1 - shift;
7056 if (rm == 15) {
7057 tmp = new_tmp();
7058 tcg_gen_movi_i32(tmp, 0);
7059 } else {
7060 tmp = load_reg(s, rm);
7061 }
7062 if (i != 32) {
7063 tmp2 = load_reg(s, rd);
7064 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7065 dead_tmp(tmp2);
7066 }
7067 store_reg(s, rd, tmp);
7068 break;
7069 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7070 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7071 ARCH(6T2);
7072 tmp = load_reg(s, rm);
7073 shift = (insn >> 7) & 0x1f;
7074 i = ((insn >> 16) & 0x1f) + 1;
7075 if (shift + i > 32)
7076 goto illegal_op;
7077 if (i < 32) {
7078 if (op1 & 0x20) {
7079 gen_ubfx(tmp, shift, (1u << i) - 1);
7080 } else {
7081 gen_sbfx(tmp, shift, i);
7082 }
7083 }
7084 store_reg(s, rd, tmp);
7085 break;
7086 default:
7087 goto illegal_op;
7088 }
7089 break;
7090 }
7091 break;
7092 }
7093 do_ldst:
7094 /* Check for undefined extension instructions
7095 * per the ARM Bible IE:
7096 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7097 */
7098 sh = (0xf << 20) | (0xf << 4);
7099 if (op1 == 0x7 && ((insn & sh) == sh))
7100 {
7101 goto illegal_op;
7102 }
7103 /* load/store byte/word */
7104 rn = (insn >> 16) & 0xf;
7105 rd = (insn >> 12) & 0xf;
7106 tmp2 = load_reg(s, rn);
7107 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7108 if (insn & (1 << 24))
7109 gen_add_data_offset(s, insn, tmp2);
7110 if (insn & (1 << 20)) {
7111 /* load */
7112 if (insn & (1 << 22)) {
7113 tmp = gen_ld8u(tmp2, i);
7114 } else {
7115 tmp = gen_ld32(tmp2, i);
7116 }
7117 } else {
7118 /* store */
7119 tmp = load_reg(s, rd);
7120 if (insn & (1 << 22))
7121 gen_st8(tmp, tmp2, i);
7122 else
7123 gen_st32(tmp, tmp2, i);
7124 }
7125 if (!(insn & (1 << 24))) {
7126 gen_add_data_offset(s, insn, tmp2);
7127 store_reg(s, rn, tmp2);
7128 } else if (insn & (1 << 21)) {
7129 store_reg(s, rn, tmp2);
7130 } else {
7131 dead_tmp(tmp2);
7132 }
7133 if (insn & (1 << 20)) {
7134 /* Complete the load. */
7135 if (rd == 15)
7136 gen_bx(s, tmp);
7137 else
7138 store_reg(s, rd, tmp);
7139 }
7140 break;
7141 case 0x08:
7142 case 0x09:
7143 {
7144 int j, n, user, loaded_base;
7145 TCGv loaded_var;
7146 /* load/store multiple words */
7147 /* XXX: store correct base if write back */
7148 user = 0;
7149 if (insn & (1 << 22)) {
7150 if (IS_USER(s))
7151 goto illegal_op; /* only usable in supervisor mode */
7152
7153 if ((insn & (1 << 15)) == 0)
7154 user = 1;
7155 }
7156 rn = (insn >> 16) & 0xf;
7157 addr = load_reg(s, rn);
7158
7159 /* compute total size */
7160 loaded_base = 0;
7161 TCGV_UNUSED(loaded_var);
7162 n = 0;
7163 for(i=0;i<16;i++) {
7164 if (insn & (1 << i))
7165 n++;
7166 }
7167 /* XXX: test invalid n == 0 case ? */
7168 if (insn & (1 << 23)) {
7169 if (insn & (1 << 24)) {
7170 /* pre increment */
7171 tcg_gen_addi_i32(addr, addr, 4);
7172 } else {
7173 /* post increment */
7174 }
7175 } else {
7176 if (insn & (1 << 24)) {
7177 /* pre decrement */
7178 tcg_gen_addi_i32(addr, addr, -(n * 4));
7179 } else {
7180 /* post decrement */
7181 if (n != 1)
7182 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7183 }
7184 }
7185 j = 0;
7186 for(i=0;i<16;i++) {
7187 if (insn & (1 << i)) {
7188 if (insn & (1 << 20)) {
7189 /* load */
7190 tmp = gen_ld32(addr, IS_USER(s));
7191 if (i == 15) {
7192 gen_bx(s, tmp);
7193 } else if (user) {
7194 tmp2 = tcg_const_i32(i);
7195 gen_helper_set_user_reg(tmp2, tmp);
7196 tcg_temp_free_i32(tmp2);
7197 dead_tmp(tmp);
7198 } else if (i == rn) {
7199 loaded_var = tmp;
7200 loaded_base = 1;
7201 } else {
7202 store_reg(s, i, tmp);
7203 }
7204 } else {
7205 /* store */
7206 if (i == 15) {
7207 /* special case: r15 = PC + 8 */
7208 val = (long)s->pc + 4;
7209 tmp = new_tmp();
7210 tcg_gen_movi_i32(tmp, val);
7211 } else if (user) {
7212 tmp = new_tmp();
7213 tmp2 = tcg_const_i32(i);
7214 gen_helper_get_user_reg(tmp, tmp2);
7215 tcg_temp_free_i32(tmp2);
7216 } else {
7217 tmp = load_reg(s, i);
7218 }
7219 gen_st32(tmp, addr, IS_USER(s));
7220 }
7221 j++;
7222 /* no need to add after the last transfer */
7223 if (j != n)
7224 tcg_gen_addi_i32(addr, addr, 4);
7225 }
7226 }
7227 if (insn & (1 << 21)) {
7228 /* write back */
7229 if (insn & (1 << 23)) {
7230 if (insn & (1 << 24)) {
7231 /* pre increment */
7232 } else {
7233 /* post increment */
7234 tcg_gen_addi_i32(addr, addr, 4);
7235 }
7236 } else {
7237 if (insn & (1 << 24)) {
7238 /* pre decrement */
7239 if (n != 1)
7240 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7241 } else {
7242 /* post decrement */
7243 tcg_gen_addi_i32(addr, addr, -(n * 4));
7244 }
7245 }
7246 store_reg(s, rn, addr);
7247 } else {
7248 dead_tmp(addr);
7249 }
7250 if (loaded_base) {
7251 store_reg(s, rn, loaded_var);
7252 }
7253 if ((insn & (1 << 22)) && !user) {
7254 /* Restore CPSR from SPSR. */
7255 tmp = load_cpu_field(spsr);
7256 gen_set_cpsr(tmp, 0xffffffff);
7257 dead_tmp(tmp);
7258 s->is_jmp = DISAS_UPDATE;
7259 }
7260 }
7261 break;
7262 case 0xa:
7263 case 0xb:
7264 {
7265 int32_t offset;
7266
7267 /* branch (and link) */
7268 val = (int32_t)s->pc;
7269 if (insn & (1 << 24)) {
7270 tmp = new_tmp();
7271 tcg_gen_movi_i32(tmp, val);
7272 store_reg(s, 14, tmp);
7273 }
7274 offset = (((int32_t)insn << 8) >> 8);
7275 val += (offset << 2) + 4;
7276 gen_jmp(s, val);
7277 }
7278 break;
7279 case 0xc:
7280 case 0xd:
7281 case 0xe:
7282 /* Coprocessor. */
7283 if (disas_coproc_insn(env, s, insn))
7284 goto illegal_op;
7285 break;
7286 case 0xf:
7287 /* swi */
7288 gen_set_pc_im(s->pc);
7289 s->is_jmp = DISAS_SWI;
7290 break;
7291 default:
7292 illegal_op:
7293 gen_exception_insn(s, 4, EXCP_UDEF);
7294 break;
7295 }
7296 }
7297 }
7298
7299 /* Return true if this is a Thumb-2 logical op. */
7300 static int
7301 thumb2_logic_op(int op)
7302 {
7303 return (op < 8);
7304 }
7305
7306 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7307 then set condition code flags based on the result of the operation.
7308 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7309 to the high bit of T1.
7310 Returns zero if the opcode is valid. */
7311
7312 static int
7313 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
7314 {
7315 int logic_cc;
7316
7317 logic_cc = 0;
7318 switch (op) {
7319 case 0: /* and */
7320 tcg_gen_and_i32(t0, t0, t1);
7321 logic_cc = conds;
7322 break;
7323 case 1: /* bic */
7324 tcg_gen_andc_i32(t0, t0, t1);
7325 logic_cc = conds;
7326 break;
7327 case 2: /* orr */
7328 tcg_gen_or_i32(t0, t0, t1);
7329 logic_cc = conds;
7330 break;
7331 case 3: /* orn */
7332 tcg_gen_not_i32(t1, t1);
7333 tcg_gen_or_i32(t0, t0, t1);
7334 logic_cc = conds;
7335 break;
7336 case 4: /* eor */
7337 tcg_gen_xor_i32(t0, t0, t1);
7338 logic_cc = conds;
7339 break;
7340 case 8: /* add */
7341 if (conds)
7342 gen_helper_add_cc(t0, t0, t1);
7343 else
7344 tcg_gen_add_i32(t0, t0, t1);
7345 break;
7346 case 10: /* adc */
7347 if (conds)
7348 gen_helper_adc_cc(t0, t0, t1);
7349 else
7350 gen_adc(t0, t1);
7351 break;
7352 case 11: /* sbc */
7353 if (conds)
7354 gen_helper_sbc_cc(t0, t0, t1);
7355 else
7356 gen_sub_carry(t0, t0, t1);
7357 break;
7358 case 13: /* sub */
7359 if (conds)
7360 gen_helper_sub_cc(t0, t0, t1);
7361 else
7362 tcg_gen_sub_i32(t0, t0, t1);
7363 break;
7364 case 14: /* rsb */
7365 if (conds)
7366 gen_helper_sub_cc(t0, t1, t0);
7367 else
7368 tcg_gen_sub_i32(t0, t1, t0);
7369 break;
7370 default: /* 5, 6, 7, 9, 12, 15. */
7371 return 1;
7372 }
7373 if (logic_cc) {
7374 gen_logic_CC(t0);
7375 if (shifter_out)
7376 gen_set_CF_bit31(t1);
7377 }
7378 return 0;
7379 }
7380
7381 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7382 is not legal. */
7383 static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7384 {
7385 uint32_t insn, imm, shift, offset;
7386 uint32_t rd, rn, rm, rs;
7387 TCGv tmp;
7388 TCGv tmp2;
7389 TCGv tmp3;
7390 TCGv addr;
7391 TCGv_i64 tmp64;
7392 int op;
7393 int shiftop;
7394 int conds;
7395 int logic_cc;
7396
7397 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7398 || arm_feature (env, ARM_FEATURE_M))) {
7399 /* Thumb-1 cores may need to treat bl and blx as a pair of
7400 16-bit instructions to get correct prefetch abort behavior. */
7401 insn = insn_hw1;
7402 if ((insn & (1 << 12)) == 0) {
7403 /* Second half of blx. */
7404 offset = ((insn & 0x7ff) << 1);
7405 tmp = load_reg(s, 14);
7406 tcg_gen_addi_i32(tmp, tmp, offset);
7407 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
7408
7409 tmp2 = new_tmp();
7410 tcg_gen_movi_i32(tmp2, s->pc | 1);
7411 store_reg(s, 14, tmp2);
7412 gen_bx(s, tmp);
7413 return 0;
7414 }
7415 if (insn & (1 << 11)) {
7416 /* Second half of bl. */
7417 offset = ((insn & 0x7ff) << 1) | 1;
7418 tmp = load_reg(s, 14);
7419 tcg_gen_addi_i32(tmp, tmp, offset);
7420
7421 tmp2 = new_tmp();
7422 tcg_gen_movi_i32(tmp2, s->pc | 1);
7423 store_reg(s, 14, tmp2);
7424 gen_bx(s, tmp);
7425 return 0;
7426 }
7427 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7428 /* Instruction spans a page boundary. Implement it as two
7429 16-bit instructions in case the second half causes an
7430 prefetch abort. */
7431 offset = ((int32_t)insn << 21) >> 9;
7432 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
7433 return 0;
7434 }
7435 /* Fall through to 32-bit decode. */
7436 }
7437
7438 insn = lduw_code(s->pc);
7439 s->pc += 2;
7440 insn |= (uint32_t)insn_hw1 << 16;
7441
7442 if ((insn & 0xf800e800) != 0xf000e800) {
7443 ARCH(6T2);
7444 }
7445
7446 rn = (insn >> 16) & 0xf;
7447 rs = (insn >> 12) & 0xf;
7448 rd = (insn >> 8) & 0xf;
7449 rm = insn & 0xf;
7450 switch ((insn >> 25) & 0xf) {
7451 case 0: case 1: case 2: case 3:
7452 /* 16-bit instructions. Should never happen. */
7453 abort();
7454 case 4:
7455 if (insn & (1 << 22)) {
7456 /* Other load/store, table branch. */
7457 if (insn & 0x01200000) {
7458 /* Load/store doubleword. */
7459 if (rn == 15) {
7460 addr = new_tmp();
7461 tcg_gen_movi_i32(addr, s->pc & ~3);
7462 } else {
7463 addr = load_reg(s, rn);
7464 }
7465 offset = (insn & 0xff) * 4;
7466 if ((insn & (1 << 23)) == 0)
7467 offset = -offset;
7468 if (insn & (1 << 24)) {
7469 tcg_gen_addi_i32(addr, addr, offset);
7470 offset = 0;
7471 }
7472 if (insn & (1 << 20)) {
7473 /* ldrd */
7474 tmp = gen_ld32(addr, IS_USER(s));
7475 store_reg(s, rs, tmp);
7476 tcg_gen_addi_i32(addr, addr, 4);
7477 tmp = gen_ld32(addr, IS_USER(s));
7478 store_reg(s, rd, tmp);
7479 } else {
7480 /* strd */
7481 tmp = load_reg(s, rs);
7482 gen_st32(tmp, addr, IS_USER(s));
7483 tcg_gen_addi_i32(addr, addr, 4);
7484 tmp = load_reg(s, rd);
7485 gen_st32(tmp, addr, IS_USER(s));
7486 }
7487 if (insn & (1 << 21)) {
7488 /* Base writeback. */
7489 if (rn == 15)
7490 goto illegal_op;
7491 tcg_gen_addi_i32(addr, addr, offset - 4);
7492 store_reg(s, rn, addr);
7493 } else {
7494 dead_tmp(addr);
7495 }
7496 } else if ((insn & (1 << 23)) == 0) {
7497 /* Load/store exclusive word. */
7498 addr = tcg_temp_local_new();
7499 load_reg_var(s, addr, rn);
7500 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
7501 if (insn & (1 << 20)) {
7502 gen_load_exclusive(s, rs, 15, addr, 2);
7503 } else {
7504 gen_store_exclusive(s, rd, rs, 15, addr, 2);
7505 }
7506 tcg_temp_free(addr);
7507 } else if ((insn & (1 << 6)) == 0) {
7508 /* Table Branch. */
7509 if (rn == 15) {
7510 addr = new_tmp();
7511 tcg_gen_movi_i32(addr, s->pc);
7512 } else {
7513 addr = load_reg(s, rn);
7514 }
7515 tmp = load_reg(s, rm);
7516 tcg_gen_add_i32(addr, addr, tmp);
7517 if (insn & (1 << 4)) {
7518 /* tbh */
7519 tcg_gen_add_i32(addr, addr, tmp);
7520 dead_tmp(tmp);
7521 tmp = gen_ld16u(addr, IS_USER(s));
7522 } else { /* tbb */
7523 dead_tmp(tmp);
7524 tmp = gen_ld8u(addr, IS_USER(s));
7525 }
7526 dead_tmp(addr);
7527 tcg_gen_shli_i32(tmp, tmp, 1);
7528 tcg_gen_addi_i32(tmp, tmp, s->pc);
7529 store_reg(s, 15, tmp);
7530 } else {
7531 /* Load/store exclusive byte/halfword/doubleword. */
7532 ARCH(7);
7533 op = (insn >> 4) & 0x3;
7534 if (op == 2) {
7535 goto illegal_op;
7536 }
7537 addr = tcg_temp_local_new();
7538 load_reg_var(s, addr, rn);
7539 if (insn & (1 << 20)) {
7540 gen_load_exclusive(s, rs, rd, addr, op);
7541 } else {
7542 gen_store_exclusive(s, rm, rs, rd, addr, op);
7543 }
7544 tcg_temp_free(addr);
7545 }
7546 } else {
7547 /* Load/store multiple, RFE, SRS. */
7548 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7549 /* Not available in user mode. */
7550 if (IS_USER(s))
7551 goto illegal_op;
7552 if (insn & (1 << 20)) {
7553 /* rfe */
7554 addr = load_reg(s, rn);
7555 if ((insn & (1 << 24)) == 0)
7556 tcg_gen_addi_i32(addr, addr, -8);
7557 /* Load PC into tmp and CPSR into tmp2. */
7558 tmp = gen_ld32(addr, 0);
7559 tcg_gen_addi_i32(addr, addr, 4);
7560 tmp2 = gen_ld32(addr, 0);
7561 if (insn & (1 << 21)) {
7562 /* Base writeback. */
7563 if (insn & (1 << 24)) {
7564 tcg_gen_addi_i32(addr, addr, 4);
7565 } else {
7566 tcg_gen_addi_i32(addr, addr, -4);
7567 }
7568 store_reg(s, rn, addr);
7569 } else {
7570 dead_tmp(addr);
7571 }
7572 gen_rfe(s, tmp, tmp2);
7573 } else {
7574 /* srs */
7575 op = (insn & 0x1f);
7576 addr = new_tmp();
7577 tmp = tcg_const_i32(op);
7578 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7579 tcg_temp_free_i32(tmp);
7580 if ((insn & (1 << 24)) == 0) {
7581 tcg_gen_addi_i32(addr, addr, -8);
7582 }
7583 tmp = load_reg(s, 14);
7584 gen_st32(tmp, addr, 0);
7585 tcg_gen_addi_i32(addr, addr, 4);
7586 tmp = new_tmp();
7587 gen_helper_cpsr_read(tmp);
7588 gen_st32(tmp, addr, 0);
7589 if (insn & (1 << 21)) {
7590 if ((insn & (1 << 24)) == 0) {
7591 tcg_gen_addi_i32(addr, addr, -4);
7592 } else {
7593 tcg_gen_addi_i32(addr, addr, 4);
7594 }
7595 tmp = tcg_const_i32(op);
7596 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7597 tcg_temp_free_i32(tmp);
7598 } else {
7599 dead_tmp(addr);
7600 }
7601 }
7602 } else {
7603 int i;
7604 /* Load/store multiple. */
7605 addr = load_reg(s, rn);
7606 offset = 0;
7607 for (i = 0; i < 16; i++) {
7608 if (insn & (1 << i))
7609 offset += 4;
7610 }
7611 if (insn & (1 << 24)) {
7612 tcg_gen_addi_i32(addr, addr, -offset);
7613 }
7614
7615 for (i = 0; i < 16; i++) {
7616 if ((insn & (1 << i)) == 0)
7617 continue;
7618 if (insn & (1 << 20)) {
7619 /* Load. */
7620 tmp = gen_ld32(addr, IS_USER(s));
7621 if (i == 15) {
7622 gen_bx(s, tmp);
7623 } else {
7624 store_reg(s, i, tmp);
7625 }
7626 } else {
7627 /* Store. */
7628 tmp = load_reg(s, i);
7629 gen_st32(tmp, addr, IS_USER(s));
7630 }
7631 tcg_gen_addi_i32(addr, addr, 4);
7632 }
7633 if (insn & (1 << 21)) {
7634 /* Base register writeback. */
7635 if (insn & (1 << 24)) {
7636 tcg_gen_addi_i32(addr, addr, -offset);
7637 }
7638 /* Fault if writeback register is in register list. */
7639 if (insn & (1 << rn))
7640 goto illegal_op;
7641 store_reg(s, rn, addr);
7642 } else {
7643 dead_tmp(addr);
7644 }
7645 }
7646 }
7647 break;
7648 case 5:
7649
7650 op = (insn >> 21) & 0xf;
7651 if (op == 6) {
7652 /* Halfword pack. */
7653 tmp = load_reg(s, rn);
7654 tmp2 = load_reg(s, rm);
7655 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7656 if (insn & (1 << 5)) {
7657 /* pkhtb */
7658 if (shift == 0)
7659 shift = 31;
7660 tcg_gen_sari_i32(tmp2, tmp2, shift);
7661 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7662 tcg_gen_ext16u_i32(tmp2, tmp2);
7663 } else {
7664 /* pkhbt */
7665 if (shift)
7666 tcg_gen_shli_i32(tmp2, tmp2, shift);
7667 tcg_gen_ext16u_i32(tmp, tmp);
7668 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7669 }
7670 tcg_gen_or_i32(tmp, tmp, tmp2);
7671 dead_tmp(tmp2);
7672 store_reg(s, rd, tmp);
7673 } else {
7674 /* Data processing register constant shift. */
7675 if (rn == 15) {
7676 tmp = new_tmp();
7677 tcg_gen_movi_i32(tmp, 0);
7678 } else {
7679 tmp = load_reg(s, rn);
7680 }
7681 tmp2 = load_reg(s, rm);
7682
7683 shiftop = (insn >> 4) & 3;
7684 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7685 conds = (insn & (1 << 20)) != 0;
7686 logic_cc = (conds && thumb2_logic_op(op));
7687 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7688 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7689 goto illegal_op;
7690 dead_tmp(tmp2);
7691 if (rd != 15) {
7692 store_reg(s, rd, tmp);
7693 } else {
7694 dead_tmp(tmp);
7695 }
7696 }
7697 break;
7698 case 13: /* Misc data processing. */
7699 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7700 if (op < 4 && (insn & 0xf000) != 0xf000)
7701 goto illegal_op;
7702 switch (op) {
7703 case 0: /* Register controlled shift. */
7704 tmp = load_reg(s, rn);
7705 tmp2 = load_reg(s, rm);
7706 if ((insn & 0x70) != 0)
7707 goto illegal_op;
7708 op = (insn >> 21) & 3;
7709 logic_cc = (insn & (1 << 20)) != 0;
7710 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7711 if (logic_cc)
7712 gen_logic_CC(tmp);
7713 store_reg_bx(env, s, rd, tmp);
7714 break;
7715 case 1: /* Sign/zero extend. */
7716 tmp = load_reg(s, rm);
7717 shift = (insn >> 4) & 3;
7718 /* ??? In many cases it's not neccessary to do a
7719 rotate, a shift is sufficient. */
7720 if (shift != 0)
7721 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
7722 op = (insn >> 20) & 7;
7723 switch (op) {
7724 case 0: gen_sxth(tmp); break;
7725 case 1: gen_uxth(tmp); break;
7726 case 2: gen_sxtb16(tmp); break;
7727 case 3: gen_uxtb16(tmp); break;
7728 case 4: gen_sxtb(tmp); break;
7729 case 5: gen_uxtb(tmp); break;
7730 default: goto illegal_op;
7731 }
7732 if (rn != 15) {
7733 tmp2 = load_reg(s, rn);
7734 if ((op >> 1) == 1) {
7735 gen_add16(tmp, tmp2);
7736 } else {
7737 tcg_gen_add_i32(tmp, tmp, tmp2);
7738 dead_tmp(tmp2);
7739 }
7740 }
7741 store_reg(s, rd, tmp);
7742 break;
7743 case 2: /* SIMD add/subtract. */
7744 op = (insn >> 20) & 7;
7745 shift = (insn >> 4) & 7;
7746 if ((op & 3) == 3 || (shift & 3) == 3)
7747 goto illegal_op;
7748 tmp = load_reg(s, rn);
7749 tmp2 = load_reg(s, rm);
7750 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7751 dead_tmp(tmp2);
7752 store_reg(s, rd, tmp);
7753 break;
7754 case 3: /* Other data processing. */
7755 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7756 if (op < 4) {
7757 /* Saturating add/subtract. */
7758 tmp = load_reg(s, rn);
7759 tmp2 = load_reg(s, rm);
7760 if (op & 1)
7761 gen_helper_double_saturate(tmp, tmp);
7762 if (op & 2)
7763 gen_helper_sub_saturate(tmp, tmp2, tmp);
7764 else
7765 gen_helper_add_saturate(tmp, tmp, tmp2);
7766 dead_tmp(tmp2);
7767 } else {
7768 tmp = load_reg(s, rn);
7769 switch (op) {
7770 case 0x0a: /* rbit */
7771 gen_helper_rbit(tmp, tmp);
7772 break;
7773 case 0x08: /* rev */
7774 tcg_gen_bswap32_i32(tmp, tmp);
7775 break;
7776 case 0x09: /* rev16 */
7777 gen_rev16(tmp);
7778 break;
7779 case 0x0b: /* revsh */
7780 gen_revsh(tmp);
7781 break;
7782 case 0x10: /* sel */
7783 tmp2 = load_reg(s, rm);
7784 tmp3 = new_tmp();
7785 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7786 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7787 dead_tmp(tmp3);
7788 dead_tmp(tmp2);
7789 break;
7790 case 0x18: /* clz */
7791 gen_helper_clz(tmp, tmp);
7792 break;
7793 default:
7794 goto illegal_op;
7795 }
7796 }
7797 store_reg(s, rd, tmp);
7798 break;
7799 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7800 op = (insn >> 4) & 0xf;
7801 tmp = load_reg(s, rn);
7802 tmp2 = load_reg(s, rm);
7803 switch ((insn >> 20) & 7) {
7804 case 0: /* 32 x 32 -> 32 */
7805 tcg_gen_mul_i32(tmp, tmp, tmp2);
7806 dead_tmp(tmp2);
7807 if (rs != 15) {
7808 tmp2 = load_reg(s, rs);
7809 if (op)
7810 tcg_gen_sub_i32(tmp, tmp2, tmp);
7811 else
7812 tcg_gen_add_i32(tmp, tmp, tmp2);
7813 dead_tmp(tmp2);
7814 }
7815 break;
7816 case 1: /* 16 x 16 -> 32 */
7817 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7818 dead_tmp(tmp2);
7819 if (rs != 15) {
7820 tmp2 = load_reg(s, rs);
7821 gen_helper_add_setq(tmp, tmp, tmp2);
7822 dead_tmp(tmp2);
7823 }
7824 break;
7825 case 2: /* Dual multiply add. */
7826 case 4: /* Dual multiply subtract. */
7827 if (op)
7828 gen_swap_half(tmp2);
7829 gen_smul_dual(tmp, tmp2);
7830 /* This addition cannot overflow. */
7831 if (insn & (1 << 22)) {
7832 tcg_gen_sub_i32(tmp, tmp, tmp2);
7833 } else {
7834 tcg_gen_add_i32(tmp, tmp, tmp2);
7835 }
7836 dead_tmp(tmp2);
7837 if (rs != 15)
7838 {
7839 tmp2 = load_reg(s, rs);
7840 gen_helper_add_setq(tmp, tmp, tmp2);
7841 dead_tmp(tmp2);
7842 }
7843 break;
7844 case 3: /* 32 * 16 -> 32msb */
7845 if (op)
7846 tcg_gen_sari_i32(tmp2, tmp2, 16);
7847 else
7848 gen_sxth(tmp2);
7849 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7850 tcg_gen_shri_i64(tmp64, tmp64, 16);
7851 tmp = new_tmp();
7852 tcg_gen_trunc_i64_i32(tmp, tmp64);
7853 tcg_temp_free_i64(tmp64);
7854 if (rs != 15)
7855 {
7856 tmp2 = load_reg(s, rs);
7857 gen_helper_add_setq(tmp, tmp, tmp2);
7858 dead_tmp(tmp2);
7859 }
7860 break;
7861 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7862 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7863 if (rs != 15) {
7864 tmp = load_reg(s, rs);
7865 if (insn & (1 << 20)) {
7866 tmp64 = gen_addq_msw(tmp64, tmp);
7867 } else {
7868 tmp64 = gen_subq_msw(tmp64, tmp);
7869 }
7870 }
7871 if (insn & (1 << 4)) {
7872 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7873 }
7874 tcg_gen_shri_i64(tmp64, tmp64, 32);
7875 tmp = new_tmp();
7876 tcg_gen_trunc_i64_i32(tmp, tmp64);
7877 tcg_temp_free_i64(tmp64);
7878 break;
7879 case 7: /* Unsigned sum of absolute differences. */
7880 gen_helper_usad8(tmp, tmp, tmp2);
7881 dead_tmp(tmp2);
7882 if (rs != 15) {
7883 tmp2 = load_reg(s, rs);
7884 tcg_gen_add_i32(tmp, tmp, tmp2);
7885 dead_tmp(tmp2);
7886 }
7887 break;
7888 }
7889 store_reg(s, rd, tmp);
7890 break;
7891 case 6: case 7: /* 64-bit multiply, Divide. */
7892 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
7893 tmp = load_reg(s, rn);
7894 tmp2 = load_reg(s, rm);
7895 if ((op & 0x50) == 0x10) {
7896 /* sdiv, udiv */
7897 if (!arm_feature(env, ARM_FEATURE_DIV))
7898 goto illegal_op;
7899 if (op & 0x20)
7900 gen_helper_udiv(tmp, tmp, tmp2);
7901 else
7902 gen_helper_sdiv(tmp, tmp, tmp2);
7903 dead_tmp(tmp2);
7904 store_reg(s, rd, tmp);
7905 } else if ((op & 0xe) == 0xc) {
7906 /* Dual multiply accumulate long. */
7907 if (op & 1)
7908 gen_swap_half(tmp2);
7909 gen_smul_dual(tmp, tmp2);
7910 if (op & 0x10) {
7911 tcg_gen_sub_i32(tmp, tmp, tmp2);
7912 } else {
7913 tcg_gen_add_i32(tmp, tmp, tmp2);
7914 }
7915 dead_tmp(tmp2);
7916 /* BUGFIX */
7917 tmp64 = tcg_temp_new_i64();
7918 tcg_gen_ext_i32_i64(tmp64, tmp);
7919 dead_tmp(tmp);
7920 gen_addq(s, tmp64, rs, rd);
7921 gen_storeq_reg(s, rs, rd, tmp64);
7922 tcg_temp_free_i64(tmp64);
7923 } else {
7924 if (op & 0x20) {
7925 /* Unsigned 64-bit multiply */
7926 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
7927 } else {
7928 if (op & 8) {
7929 /* smlalxy */
7930 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7931 dead_tmp(tmp2);
7932 tmp64 = tcg_temp_new_i64();
7933 tcg_gen_ext_i32_i64(tmp64, tmp);
7934 dead_tmp(tmp);
7935 } else {
7936 /* Signed 64-bit multiply */
7937 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7938 }
7939 }
7940 if (op & 4) {
7941 /* umaal */
7942 gen_addq_lo(s, tmp64, rs);
7943 gen_addq_lo(s, tmp64, rd);
7944 } else if (op & 0x40) {
7945 /* 64-bit accumulate. */
7946 gen_addq(s, tmp64, rs, rd);
7947 }
7948 gen_storeq_reg(s, rs, rd, tmp64);
7949 tcg_temp_free_i64(tmp64);
7950 }
7951 break;
7952 }
7953 break;
7954 case 6: case 7: case 14: case 15:
7955 /* Coprocessor. */
7956 if (((insn >> 24) & 3) == 3) {
7957 /* Translate into the equivalent ARM encoding. */
7958 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
7959 if (disas_neon_data_insn(env, s, insn))
7960 goto illegal_op;
7961 } else {
7962 if (insn & (1 << 28))
7963 goto illegal_op;
7964 if (disas_coproc_insn (env, s, insn))
7965 goto illegal_op;
7966 }
7967 break;
7968 case 8: case 9: case 10: case 11:
7969 if (insn & (1 << 15)) {
7970 /* Branches, misc control. */
7971 if (insn & 0x5000) {
7972 /* Unconditional branch. */
7973 /* signextend(hw1[10:0]) -> offset[:12]. */
7974 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7975 /* hw1[10:0] -> offset[11:1]. */
7976 offset |= (insn & 0x7ff) << 1;
7977 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
7978 offset[24:22] already have the same value because of the
7979 sign extension above. */
7980 offset ^= ((~insn) & (1 << 13)) << 10;
7981 offset ^= ((~insn) & (1 << 11)) << 11;
7982
7983 if (insn & (1 << 14)) {
7984 /* Branch and link. */
7985 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
7986 }
7987
7988 offset += s->pc;
7989 if (insn & (1 << 12)) {
7990 /* b/bl */
7991 gen_jmp(s, offset);
7992 } else {
7993 /* blx */
7994 offset &= ~(uint32_t)2;
7995 gen_bx_im(s, offset);
7996 }
7997 } else if (((insn >> 23) & 7) == 7) {
7998 /* Misc control */
7999 if (insn & (1 << 13))
8000 goto illegal_op;
8001
8002 if (insn & (1 << 26)) {
8003 /* Secure monitor call (v6Z) */
8004 goto illegal_op; /* not implemented. */
8005 } else {
8006 op = (insn >> 20) & 7;
8007 switch (op) {
8008 case 0: /* msr cpsr. */
8009 if (IS_M(env)) {
8010 tmp = load_reg(s, rn);
8011 addr = tcg_const_i32(insn & 0xff);
8012 gen_helper_v7m_msr(cpu_env, addr, tmp);
8013 tcg_temp_free_i32(addr);
8014 dead_tmp(tmp);
8015 gen_lookup_tb(s);
8016 break;
8017 }
8018 /* fall through */
8019 case 1: /* msr spsr. */
8020 if (IS_M(env))
8021 goto illegal_op;
8022 tmp = load_reg(s, rn);
8023 if (gen_set_psr(s,
8024 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
8025 op == 1, tmp))
8026 goto illegal_op;
8027 break;
8028 case 2: /* cps, nop-hint. */
8029 if (((insn >> 8) & 7) == 0) {
8030 gen_nop_hint(s, insn & 0xff);
8031 }
8032 /* Implemented as NOP in user mode. */
8033 if (IS_USER(s))
8034 break;
8035 offset = 0;
8036 imm = 0;
8037 if (insn & (1 << 10)) {
8038 if (insn & (1 << 7))
8039 offset |= CPSR_A;
8040 if (insn & (1 << 6))
8041 offset |= CPSR_I;
8042 if (insn & (1 << 5))
8043 offset |= CPSR_F;
8044 if (insn & (1 << 9))
8045 imm = CPSR_A | CPSR_I | CPSR_F;
8046 }
8047 if (insn & (1 << 8)) {
8048 offset |= 0x1f;
8049 imm |= (insn & 0x1f);
8050 }
8051 if (offset) {
8052 gen_set_psr_im(s, offset, 0, imm);
8053 }
8054 break;
8055 case 3: /* Special control operations. */
8056 ARCH(7);
8057 op = (insn >> 4) & 0xf;
8058 switch (op) {
8059 case 2: /* clrex */
8060 gen_clrex(s);
8061 break;
8062 case 4: /* dsb */
8063 case 5: /* dmb */
8064 case 6: /* isb */
8065 /* These execute as NOPs. */
8066 break;
8067 default:
8068 goto illegal_op;
8069 }
8070 break;
8071 case 4: /* bxj */
8072 /* Trivial implementation equivalent to bx. */
8073 tmp = load_reg(s, rn);
8074 gen_bx(s, tmp);
8075 break;
8076 case 5: /* Exception return. */
8077 if (IS_USER(s)) {
8078 goto illegal_op;
8079 }
8080 if (rn != 14 || rd != 15) {
8081 goto illegal_op;
8082 }
8083 tmp = load_reg(s, rn);
8084 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8085 gen_exception_return(s, tmp);
8086 break;
8087 case 6: /* mrs cpsr. */
8088 tmp = new_tmp();
8089 if (IS_M(env)) {
8090 addr = tcg_const_i32(insn & 0xff);
8091 gen_helper_v7m_mrs(tmp, cpu_env, addr);
8092 tcg_temp_free_i32(addr);
8093 } else {
8094 gen_helper_cpsr_read(tmp);
8095 }
8096 store_reg(s, rd, tmp);
8097 break;
8098 case 7: /* mrs spsr. */
8099 /* Not accessible in user mode. */
8100 if (IS_USER(s) || IS_M(env))
8101 goto illegal_op;
8102 tmp = load_cpu_field(spsr);
8103 store_reg(s, rd, tmp);
8104 break;
8105 }
8106 }
8107 } else {
8108 /* Conditional branch. */
8109 op = (insn >> 22) & 0xf;
8110 /* Generate a conditional jump to next instruction. */
8111 s->condlabel = gen_new_label();
8112 gen_test_cc(op ^ 1, s->condlabel);
8113 s->condjmp = 1;
8114
8115 /* offset[11:1] = insn[10:0] */
8116 offset = (insn & 0x7ff) << 1;
8117 /* offset[17:12] = insn[21:16]. */
8118 offset |= (insn & 0x003f0000) >> 4;
8119 /* offset[31:20] = insn[26]. */
8120 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8121 /* offset[18] = insn[13]. */
8122 offset |= (insn & (1 << 13)) << 5;
8123 /* offset[19] = insn[11]. */
8124 offset |= (insn & (1 << 11)) << 8;
8125
8126 /* jump to the offset */
8127 gen_jmp(s, s->pc + offset);
8128 }
8129 } else {
8130 /* Data processing immediate. */
8131 if (insn & (1 << 25)) {
8132 if (insn & (1 << 24)) {
8133 if (insn & (1 << 20))
8134 goto illegal_op;
8135 /* Bitfield/Saturate. */
8136 op = (insn >> 21) & 7;
8137 imm = insn & 0x1f;
8138 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8139 if (rn == 15) {
8140 tmp = new_tmp();
8141 tcg_gen_movi_i32(tmp, 0);
8142 } else {
8143 tmp = load_reg(s, rn);
8144 }
8145 switch (op) {
8146 case 2: /* Signed bitfield extract. */
8147 imm++;
8148 if (shift + imm > 32)
8149 goto illegal_op;
8150 if (imm < 32)
8151 gen_sbfx(tmp, shift, imm);
8152 break;
8153 case 6: /* Unsigned bitfield extract. */
8154 imm++;
8155 if (shift + imm > 32)
8156 goto illegal_op;
8157 if (imm < 32)
8158 gen_ubfx(tmp, shift, (1u << imm) - 1);
8159 break;
8160 case 3: /* Bitfield insert/clear. */
8161 if (imm < shift)
8162 goto illegal_op;
8163 imm = imm + 1 - shift;
8164 if (imm != 32) {
8165 tmp2 = load_reg(s, rd);
8166 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
8167 dead_tmp(tmp2);
8168 }
8169 break;
8170 case 7:
8171 goto illegal_op;
8172 default: /* Saturate. */
8173 if (shift) {
8174 if (op & 1)
8175 tcg_gen_sari_i32(tmp, tmp, shift);
8176 else
8177 tcg_gen_shli_i32(tmp, tmp, shift);
8178 }
8179 tmp2 = tcg_const_i32(imm);
8180 if (op & 4) {
8181 /* Unsigned. */
8182 if ((op & 1) && shift == 0)
8183 gen_helper_usat16(tmp, tmp, tmp2);
8184 else
8185 gen_helper_usat(tmp, tmp, tmp2);
8186 } else {
8187 /* Signed. */
8188 if ((op & 1) && shift == 0)
8189 gen_helper_ssat16(tmp, tmp, tmp2);
8190 else
8191 gen_helper_ssat(tmp, tmp, tmp2);
8192 }
8193 tcg_temp_free_i32(tmp2);
8194 break;
8195 }
8196 store_reg(s, rd, tmp);
8197 } else {
8198 imm = ((insn & 0x04000000) >> 15)
8199 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8200 if (insn & (1 << 22)) {
8201 /* 16-bit immediate. */
8202 imm |= (insn >> 4) & 0xf000;
8203 if (insn & (1 << 23)) {
8204 /* movt */
8205 tmp = load_reg(s, rd);
8206 tcg_gen_ext16u_i32(tmp, tmp);
8207 tcg_gen_ori_i32(tmp, tmp, imm << 16);
8208 } else {
8209 /* movw */
8210 tmp = new_tmp();
8211 tcg_gen_movi_i32(tmp, imm);
8212 }
8213 } else {
8214 /* Add/sub 12-bit immediate. */
8215 if (rn == 15) {
8216 offset = s->pc & ~(uint32_t)3;
8217 if (insn & (1 << 23))
8218 offset -= imm;
8219 else
8220 offset += imm;
8221 tmp = new_tmp();
8222 tcg_gen_movi_i32(tmp, offset);
8223 } else {
8224 tmp = load_reg(s, rn);
8225 if (insn & (1 << 23))
8226 tcg_gen_subi_i32(tmp, tmp, imm);
8227 else
8228 tcg_gen_addi_i32(tmp, tmp, imm);
8229 }
8230 }
8231 store_reg(s, rd, tmp);
8232 }
8233 } else {
8234 int shifter_out = 0;
8235 /* modified 12-bit immediate. */
8236 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8237 imm = (insn & 0xff);
8238 switch (shift) {
8239 case 0: /* XY */
8240 /* Nothing to do. */
8241 break;
8242 case 1: /* 00XY00XY */
8243 imm |= imm << 16;
8244 break;
8245 case 2: /* XY00XY00 */
8246 imm |= imm << 16;
8247 imm <<= 8;
8248 break;
8249 case 3: /* XYXYXYXY */
8250 imm |= imm << 16;
8251 imm |= imm << 8;
8252 break;
8253 default: /* Rotated constant. */
8254 shift = (shift << 1) | (imm >> 7);
8255 imm |= 0x80;
8256 imm = imm << (32 - shift);
8257 shifter_out = 1;
8258 break;
8259 }
8260 tmp2 = new_tmp();
8261 tcg_gen_movi_i32(tmp2, imm);
8262 rn = (insn >> 16) & 0xf;
8263 if (rn == 15) {
8264 tmp = new_tmp();
8265 tcg_gen_movi_i32(tmp, 0);
8266 } else {
8267 tmp = load_reg(s, rn);
8268 }
8269 op = (insn >> 21) & 0xf;
8270 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8271 shifter_out, tmp, tmp2))
8272 goto illegal_op;
8273 dead_tmp(tmp2);
8274 rd = (insn >> 8) & 0xf;
8275 if (rd != 15) {
8276 store_reg(s, rd, tmp);
8277 } else {
8278 dead_tmp(tmp);
8279 }
8280 }
8281 }
8282 break;
8283 case 12: /* Load/store single data item. */
8284 {
8285 int postinc = 0;
8286 int writeback = 0;
8287 int user;
8288 if ((insn & 0x01100000) == 0x01000000) {
8289 if (disas_neon_ls_insn(env, s, insn))
8290 goto illegal_op;
8291 break;
8292 }
8293 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8294 if (rs == 15) {
8295 if (!(insn & (1 << 20))) {
8296 goto illegal_op;
8297 }
8298 if (op != 2) {
8299 /* Byte or halfword load space with dest == r15 : memory hints.
8300 * Catch them early so we don't emit pointless addressing code.
8301 * This space is a mix of:
8302 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8303 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8304 * cores)
8305 * unallocated hints, which must be treated as NOPs
8306 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8307 * which is easiest for the decoding logic
8308 * Some space which must UNDEF
8309 */
8310 int op1 = (insn >> 23) & 3;
8311 int op2 = (insn >> 6) & 0x3f;
8312 if (op & 2) {
8313 goto illegal_op;
8314 }
8315 if (rn == 15) {
8316 /* UNPREDICTABLE or unallocated hint */
8317 return 0;
8318 }
8319 if (op1 & 1) {
8320 return 0; /* PLD* or unallocated hint */
8321 }
8322 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8323 return 0; /* PLD* or unallocated hint */
8324 }
8325 /* UNDEF space, or an UNPREDICTABLE */
8326 return 1;
8327 }
8328 }
8329 user = IS_USER(s);
8330 if (rn == 15) {
8331 addr = new_tmp();
8332 /* PC relative. */
8333 /* s->pc has already been incremented by 4. */
8334 imm = s->pc & 0xfffffffc;
8335 if (insn & (1 << 23))
8336 imm += insn & 0xfff;
8337 else
8338 imm -= insn & 0xfff;
8339 tcg_gen_movi_i32(addr, imm);
8340 } else {
8341 addr = load_reg(s, rn);
8342 if (insn & (1 << 23)) {
8343 /* Positive offset. */
8344 imm = insn & 0xfff;
8345 tcg_gen_addi_i32(addr, addr, imm);
8346 } else {
8347 imm = insn & 0xff;
8348 switch ((insn >> 8) & 7) {
8349 case 0: case 8: /* Shifted Register. */
8350 shift = (insn >> 4) & 0xf;
8351 if (shift > 3)
8352 goto illegal_op;
8353 tmp = load_reg(s, rm);
8354 if (shift)
8355 tcg_gen_shli_i32(tmp, tmp, shift);
8356 tcg_gen_add_i32(addr, addr, tmp);
8357 dead_tmp(tmp);
8358 break;
8359 case 4: /* Negative offset. */
8360 tcg_gen_addi_i32(addr, addr, -imm);
8361 break;
8362 case 6: /* User privilege. */
8363 tcg_gen_addi_i32(addr, addr, imm);
8364 user = 1;
8365 break;
8366 case 1: /* Post-decrement. */
8367 imm = -imm;
8368 /* Fall through. */
8369 case 3: /* Post-increment. */
8370 postinc = 1;
8371 writeback = 1;
8372 break;
8373 case 5: /* Pre-decrement. */
8374 imm = -imm;
8375 /* Fall through. */
8376 case 7: /* Pre-increment. */
8377 tcg_gen_addi_i32(addr, addr, imm);
8378 writeback = 1;
8379 break;
8380 default:
8381 goto illegal_op;
8382 }
8383 }
8384 }
8385 if (insn & (1 << 20)) {
8386 /* Load. */
8387 switch (op) {
8388 case 0: tmp = gen_ld8u(addr, user); break;
8389 case 4: tmp = gen_ld8s(addr, user); break;
8390 case 1: tmp = gen_ld16u(addr, user); break;
8391 case 5: tmp = gen_ld16s(addr, user); break;
8392 case 2: tmp = gen_ld32(addr, user); break;
8393 default: goto illegal_op;
8394 }
8395 if (rs == 15) {
8396 gen_bx(s, tmp);
8397 } else {
8398 store_reg(s, rs, tmp);
8399 }
8400 } else {
8401 /* Store. */
8402 tmp = load_reg(s, rs);
8403 switch (op) {
8404 case 0: gen_st8(tmp, addr, user); break;
8405 case 1: gen_st16(tmp, addr, user); break;
8406 case 2: gen_st32(tmp, addr, user); break;
8407 default: goto illegal_op;
8408 }
8409 }
8410 if (postinc)
8411 tcg_gen_addi_i32(addr, addr, imm);
8412 if (writeback) {
8413 store_reg(s, rn, addr);
8414 } else {
8415 dead_tmp(addr);
8416 }
8417 }
8418 break;
8419 default:
8420 goto illegal_op;
8421 }
8422 return 0;
8423 illegal_op:
8424 return 1;
8425 }
8426
8427 static void disas_thumb_insn(CPUState *env, DisasContext *s)
8428 {
8429 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8430 int32_t offset;
8431 int i;
8432 TCGv tmp;
8433 TCGv tmp2;
8434 TCGv addr;
8435
8436 if (s->condexec_mask) {
8437 cond = s->condexec_cond;
8438 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8439 s->condlabel = gen_new_label();
8440 gen_test_cc(cond ^ 1, s->condlabel);
8441 s->condjmp = 1;
8442 }
8443 }
8444
8445 insn = lduw_code(s->pc);
8446 s->pc += 2;
8447
8448 switch (insn >> 12) {
8449 case 0: case 1:
8450
8451 rd = insn & 7;
8452 op = (insn >> 11) & 3;
8453 if (op == 3) {
8454 /* add/subtract */
8455 rn = (insn >> 3) & 7;
8456 tmp = load_reg(s, rn);
8457 if (insn & (1 << 10)) {
8458 /* immediate */
8459 tmp2 = new_tmp();
8460 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
8461 } else {
8462 /* reg */
8463 rm = (insn >> 6) & 7;
8464 tmp2 = load_reg(s, rm);
8465 }
8466 if (insn & (1 << 9)) {
8467 if (s->condexec_mask)
8468 tcg_gen_sub_i32(tmp, tmp, tmp2);
8469 else
8470 gen_helper_sub_cc(tmp, tmp, tmp2);
8471 } else {
8472 if (s->condexec_mask)
8473 tcg_gen_add_i32(tmp, tmp, tmp2);
8474 else
8475 gen_helper_add_cc(tmp, tmp, tmp2);
8476 }
8477 dead_tmp(tmp2);
8478 store_reg(s, rd, tmp);
8479 } else {
8480 /* shift immediate */
8481 rm = (insn >> 3) & 7;
8482 shift = (insn >> 6) & 0x1f;
8483 tmp = load_reg(s, rm);
8484 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8485 if (!s->condexec_mask)
8486 gen_logic_CC(tmp);
8487 store_reg(s, rd, tmp);
8488 }
8489 break;
8490 case 2: case 3:
8491 /* arithmetic large immediate */
8492 op = (insn >> 11) & 3;
8493 rd = (insn >> 8) & 0x7;
8494 if (op == 0) { /* mov */
8495 tmp = new_tmp();
8496 tcg_gen_movi_i32(tmp, insn & 0xff);
8497 if (!s->condexec_mask)
8498 gen_logic_CC(tmp);
8499 store_reg(s, rd, tmp);
8500 } else {
8501 tmp = load_reg(s, rd);
8502 tmp2 = new_tmp();
8503 tcg_gen_movi_i32(tmp2, insn & 0xff);
8504 switch (op) {
8505 case 1: /* cmp */
8506 gen_helper_sub_cc(tmp, tmp, tmp2);
8507 dead_tmp(tmp);
8508 dead_tmp(tmp2);
8509 break;
8510 case 2: /* add */
8511 if (s->condexec_mask)
8512 tcg_gen_add_i32(tmp, tmp, tmp2);
8513 else
8514 gen_helper_add_cc(tmp, tmp, tmp2);
8515 dead_tmp(tmp2);
8516 store_reg(s, rd, tmp);
8517 break;
8518 case 3: /* sub */
8519 if (s->condexec_mask)
8520 tcg_gen_sub_i32(tmp, tmp, tmp2);
8521 else
8522 gen_helper_sub_cc(tmp, tmp, tmp2);
8523 dead_tmp(tmp2);
8524 store_reg(s, rd, tmp);
8525 break;
8526 }
8527 }
8528 break;
8529 case 4:
8530 if (insn & (1 << 11)) {
8531 rd = (insn >> 8) & 7;
8532 /* load pc-relative. Bit 1 of PC is ignored. */
8533 val = s->pc + 2 + ((insn & 0xff) * 4);
8534 val &= ~(uint32_t)2;
8535 addr = new_tmp();
8536 tcg_gen_movi_i32(addr, val);
8537 tmp = gen_ld32(addr, IS_USER(s));
8538 dead_tmp(addr);
8539 store_reg(s, rd, tmp);
8540 break;
8541 }
8542 if (insn & (1 << 10)) {
8543 /* data processing extended or blx */
8544 rd = (insn & 7) | ((insn >> 4) & 8);
8545 rm = (insn >> 3) & 0xf;
8546 op = (insn >> 8) & 3;
8547 switch (op) {
8548 case 0: /* add */
8549 tmp = load_reg(s, rd);
8550 tmp2 = load_reg(s, rm);
8551 tcg_gen_add_i32(tmp, tmp, tmp2);
8552 dead_tmp(tmp2);
8553 store_reg(s, rd, tmp);
8554 break;
8555 case 1: /* cmp */
8556 tmp = load_reg(s, rd);
8557 tmp2 = load_reg(s, rm);
8558 gen_helper_sub_cc(tmp, tmp, tmp2);
8559 dead_tmp(tmp2);
8560 dead_tmp(tmp);
8561 break;
8562 case 2: /* mov/cpy */
8563 tmp = load_reg(s, rm);
8564 store_reg(s, rd, tmp);
8565 break;
8566 case 3:/* branch [and link] exchange thumb register */
8567 tmp = load_reg(s, rm);
8568 if (insn & (1 << 7)) {
8569 val = (uint32_t)s->pc | 1;
8570 tmp2 = new_tmp();
8571 tcg_gen_movi_i32(tmp2, val);
8572 store_reg(s, 14, tmp2);
8573 }
8574 gen_bx(s, tmp);
8575 break;
8576 }
8577 break;
8578 }
8579
8580 /* data processing register */
8581 rd = insn & 7;
8582 rm = (insn >> 3) & 7;
8583 op = (insn >> 6) & 0xf;
8584 if (op == 2 || op == 3 || op == 4 || op == 7) {
8585 /* the shift/rotate ops want the operands backwards */
8586 val = rm;
8587 rm = rd;
8588 rd = val;
8589 val = 1;
8590 } else {
8591 val = 0;
8592 }
8593
8594 if (op == 9) { /* neg */
8595 tmp = new_tmp();
8596 tcg_gen_movi_i32(tmp, 0);
8597 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8598 tmp = load_reg(s, rd);
8599 } else {
8600 TCGV_UNUSED(tmp);
8601 }
8602
8603 tmp2 = load_reg(s, rm);
8604 switch (op) {
8605 case 0x0: /* and */
8606 tcg_gen_and_i32(tmp, tmp, tmp2);
8607 if (!s->condexec_mask)
8608 gen_logic_CC(tmp);
8609 break;
8610 case 0x1: /* eor */
8611 tcg_gen_xor_i32(tmp, tmp, tmp2);
8612 if (!s->condexec_mask)
8613 gen_logic_CC(tmp);
8614 break;
8615 case 0x2: /* lsl */
8616 if (s->condexec_mask) {
8617 gen_helper_shl(tmp2, tmp2, tmp);
8618 } else {
8619 gen_helper_shl_cc(tmp2, tmp2, tmp);
8620 gen_logic_CC(tmp2);
8621 }
8622 break;
8623 case 0x3: /* lsr */
8624 if (s->condexec_mask) {
8625 gen_helper_shr(tmp2, tmp2, tmp);
8626 } else {
8627 gen_helper_shr_cc(tmp2, tmp2, tmp);
8628 gen_logic_CC(tmp2);
8629 }
8630 break;
8631 case 0x4: /* asr */
8632 if (s->condexec_mask) {
8633 gen_helper_sar(tmp2, tmp2, tmp);
8634 } else {
8635 gen_helper_sar_cc(tmp2, tmp2, tmp);
8636 gen_logic_CC(tmp2);
8637 }
8638 break;
8639 case 0x5: /* adc */
8640 if (s->condexec_mask)
8641 gen_adc(tmp, tmp2);
8642 else
8643 gen_helper_adc_cc(tmp, tmp, tmp2);
8644 break;
8645 case 0x6: /* sbc */
8646 if (s->condexec_mask)
8647 gen_sub_carry(tmp, tmp, tmp2);
8648 else
8649 gen_helper_sbc_cc(tmp, tmp, tmp2);
8650 break;
8651 case 0x7: /* ror */
8652 if (s->condexec_mask) {
8653 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8654 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
8655 } else {
8656 gen_helper_ror_cc(tmp2, tmp2, tmp);
8657 gen_logic_CC(tmp2);
8658 }
8659 break;
8660 case 0x8: /* tst */
8661 tcg_gen_and_i32(tmp, tmp, tmp2);
8662 gen_logic_CC(tmp);
8663 rd = 16;
8664 break;
8665 case 0x9: /* neg */
8666 if (s->condexec_mask)
8667 tcg_gen_neg_i32(tmp, tmp2);
8668 else
8669 gen_helper_sub_cc(tmp, tmp, tmp2);
8670 break;
8671 case 0xa: /* cmp */
8672 gen_helper_sub_cc(tmp, tmp, tmp2);
8673 rd = 16;
8674 break;
8675 case 0xb: /* cmn */
8676 gen_helper_add_cc(tmp, tmp, tmp2);
8677 rd = 16;
8678 break;
8679 case 0xc: /* orr */
8680 tcg_gen_or_i32(tmp, tmp, tmp2);
8681 if (!s->condexec_mask)
8682 gen_logic_CC(tmp);
8683 break;
8684 case 0xd: /* mul */
8685 tcg_gen_mul_i32(tmp, tmp, tmp2);
8686 if (!s->condexec_mask)
8687 gen_logic_CC(tmp);
8688 break;
8689 case 0xe: /* bic */
8690 tcg_gen_andc_i32(tmp, tmp, tmp2);
8691 if (!s->condexec_mask)
8692 gen_logic_CC(tmp);
8693 break;
8694 case 0xf: /* mvn */
8695 tcg_gen_not_i32(tmp2, tmp2);
8696 if (!s->condexec_mask)
8697 gen_logic_CC(tmp2);
8698 val = 1;
8699 rm = rd;
8700 break;
8701 }
8702 if (rd != 16) {
8703 if (val) {
8704 store_reg(s, rm, tmp2);
8705 if (op != 0xf)
8706 dead_tmp(tmp);
8707 } else {
8708 store_reg(s, rd, tmp);
8709 dead_tmp(tmp2);
8710 }
8711 } else {
8712 dead_tmp(tmp);
8713 dead_tmp(tmp2);
8714 }
8715 break;
8716
8717 case 5:
8718 /* load/store register offset. */
8719 rd = insn & 7;
8720 rn = (insn >> 3) & 7;
8721 rm = (insn >> 6) & 7;
8722 op = (insn >> 9) & 7;
8723 addr = load_reg(s, rn);
8724 tmp = load_reg(s, rm);
8725 tcg_gen_add_i32(addr, addr, tmp);
8726 dead_tmp(tmp);
8727
8728 if (op < 3) /* store */
8729 tmp = load_reg(s, rd);
8730
8731 switch (op) {
8732 case 0: /* str */
8733 gen_st32(tmp, addr, IS_USER(s));
8734 break;
8735 case 1: /* strh */
8736 gen_st16(tmp, addr, IS_USER(s));
8737 break;
8738 case 2: /* strb */
8739 gen_st8(tmp, addr, IS_USER(s));
8740 break;
8741 case 3: /* ldrsb */
8742 tmp = gen_ld8s(addr, IS_USER(s));
8743 break;
8744 case 4: /* ldr */
8745 tmp = gen_ld32(addr, IS_USER(s));
8746 break;
8747 case 5: /* ldrh */
8748 tmp = gen_ld16u(addr, IS_USER(s));
8749 break;
8750 case 6: /* ldrb */
8751 tmp = gen_ld8u(addr, IS_USER(s));
8752 break;
8753 case 7: /* ldrsh */
8754 tmp = gen_ld16s(addr, IS_USER(s));
8755 break;
8756 }
8757 if (op >= 3) /* load */
8758 store_reg(s, rd, tmp);
8759 dead_tmp(addr);
8760 break;
8761
8762 case 6:
8763 /* load/store word immediate offset */
8764 rd = insn & 7;
8765 rn = (insn >> 3) & 7;
8766 addr = load_reg(s, rn);
8767 val = (insn >> 4) & 0x7c;
8768 tcg_gen_addi_i32(addr, addr, val);
8769
8770 if (insn & (1 << 11)) {
8771 /* load */
8772 tmp = gen_ld32(addr, IS_USER(s));
8773 store_reg(s, rd, tmp);
8774 } else {
8775 /* store */
8776 tmp = load_reg(s, rd);
8777 gen_st32(tmp, addr, IS_USER(s));
8778 }
8779 dead_tmp(addr);
8780 break;
8781
8782 case 7:
8783 /* load/store byte immediate offset */
8784 rd = insn & 7;
8785 rn = (insn >> 3) & 7;
8786 addr = load_reg(s, rn);
8787 val = (insn >> 6) & 0x1f;
8788 tcg_gen_addi_i32(addr, addr, val);
8789
8790 if (insn & (1 << 11)) {
8791 /* load */
8792 tmp = gen_ld8u(addr, IS_USER(s));
8793 store_reg(s, rd, tmp);
8794 } else {
8795 /* store */
8796 tmp = load_reg(s, rd);
8797 gen_st8(tmp, addr, IS_USER(s));
8798 }
8799 dead_tmp(addr);
8800 break;
8801
8802 case 8:
8803 /* load/store halfword immediate offset */
8804 rd = insn & 7;
8805 rn = (insn >> 3) & 7;
8806 addr = load_reg(s, rn);
8807 val = (insn >> 5) & 0x3e;
8808 tcg_gen_addi_i32(addr, addr, val);
8809
8810 if (insn & (1 << 11)) {
8811 /* load */
8812 tmp = gen_ld16u(addr, IS_USER(s));
8813 store_reg(s, rd, tmp);
8814 } else {
8815 /* store */
8816 tmp = load_reg(s, rd);
8817 gen_st16(tmp, addr, IS_USER(s));
8818 }
8819 dead_tmp(addr);
8820 break;
8821
8822 case 9:
8823 /* load/store from stack */
8824 rd = (insn >> 8) & 7;
8825 addr = load_reg(s, 13);
8826 val = (insn & 0xff) * 4;
8827 tcg_gen_addi_i32(addr, addr, val);
8828
8829 if (insn & (1 << 11)) {
8830 /* load */
8831 tmp = gen_ld32(addr, IS_USER(s));
8832 store_reg(s, rd, tmp);
8833 } else {
8834 /* store */
8835 tmp = load_reg(s, rd);
8836 gen_st32(tmp, addr, IS_USER(s));
8837 }
8838 dead_tmp(addr);
8839 break;
8840
8841 case 10:
8842 /* add to high reg */
8843 rd = (insn >> 8) & 7;
8844 if (insn & (1 << 11)) {
8845 /* SP */
8846 tmp = load_reg(s, 13);
8847 } else {
8848 /* PC. bit 1 is ignored. */
8849 tmp = new_tmp();
8850 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
8851 }
8852 val = (insn & 0xff) * 4;
8853 tcg_gen_addi_i32(tmp, tmp, val);
8854 store_reg(s, rd, tmp);
8855 break;
8856
8857 case 11:
8858 /* misc */
8859 op = (insn >> 8) & 0xf;
8860 switch (op) {
8861 case 0:
8862 /* adjust stack pointer */
8863 tmp = load_reg(s, 13);
8864 val = (insn & 0x7f) * 4;
8865 if (insn & (1 << 7))
8866 val = -(int32_t)val;
8867 tcg_gen_addi_i32(tmp, tmp, val);
8868 store_reg(s, 13, tmp);
8869 break;
8870
8871 case 2: /* sign/zero extend. */
8872 ARCH(6);
8873 rd = insn & 7;
8874 rm = (insn >> 3) & 7;
8875 tmp = load_reg(s, rm);
8876 switch ((insn >> 6) & 3) {
8877 case 0: gen_sxth(tmp); break;
8878 case 1: gen_sxtb(tmp); break;
8879 case 2: gen_uxth(tmp); break;
8880 case 3: gen_uxtb(tmp); break;
8881 }
8882 store_reg(s, rd, tmp);
8883 break;
8884 case 4: case 5: case 0xc: case 0xd:
8885 /* push/pop */
8886 addr = load_reg(s, 13);
8887 if (insn & (1 << 8))
8888 offset = 4;
8889 else
8890 offset = 0;
8891 for (i = 0; i < 8; i++) {
8892 if (insn & (1 << i))
8893 offset += 4;
8894 }
8895 if ((insn & (1 << 11)) == 0) {
8896 tcg_gen_addi_i32(addr, addr, -offset);
8897 }
8898 for (i = 0; i < 8; i++) {
8899 if (insn & (1 << i)) {
8900 if (insn & (1 << 11)) {
8901 /* pop */
8902 tmp = gen_ld32(addr, IS_USER(s));
8903 store_reg(s, i, tmp);
8904 } else {
8905 /* push */
8906 tmp = load_reg(s, i);
8907 gen_st32(tmp, addr, IS_USER(s));
8908 }
8909 /* advance to the next address. */
8910 tcg_gen_addi_i32(addr, addr, 4);
8911 }
8912 }
8913 TCGV_UNUSED(tmp);
8914 if (insn & (1 << 8)) {
8915 if (insn & (1 << 11)) {
8916 /* pop pc */
8917 tmp = gen_ld32(addr, IS_USER(s));
8918 /* don't set the pc until the rest of the instruction
8919 has completed */
8920 } else {
8921 /* push lr */
8922 tmp = load_reg(s, 14);
8923 gen_st32(tmp, addr, IS_USER(s));
8924 }
8925 tcg_gen_addi_i32(addr, addr, 4);
8926 }
8927 if ((insn & (1 << 11)) == 0) {
8928 tcg_gen_addi_i32(addr, addr, -offset);
8929 }
8930 /* write back the new stack pointer */
8931 store_reg(s, 13, addr);
8932 /* set the new PC value */
8933 if ((insn & 0x0900) == 0x0900)
8934 gen_bx(s, tmp);
8935 break;
8936
8937 case 1: case 3: case 9: case 11: /* czb */
8938 rm = insn & 7;
8939 tmp = load_reg(s, rm);
8940 s->condlabel = gen_new_label();
8941 s->condjmp = 1;
8942 if (insn & (1 << 11))
8943 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
8944 else
8945 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
8946 dead_tmp(tmp);
8947 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8948 val = (uint32_t)s->pc + 2;
8949 val += offset;
8950 gen_jmp(s, val);
8951 break;
8952
8953 case 15: /* IT, nop-hint. */
8954 if ((insn & 0xf) == 0) {
8955 gen_nop_hint(s, (insn >> 4) & 0xf);
8956 break;
8957 }
8958 /* If Then. */
8959 s->condexec_cond = (insn >> 4) & 0xe;
8960 s->condexec_mask = insn & 0x1f;
8961 /* No actual code generated for this insn, just setup state. */
8962 break;
8963
8964 case 0xe: /* bkpt */
8965 gen_exception_insn(s, 2, EXCP_BKPT);
8966 break;
8967
8968 case 0xa: /* rev */
8969 ARCH(6);
8970 rn = (insn >> 3) & 0x7;
8971 rd = insn & 0x7;
8972 tmp = load_reg(s, rn);
8973 switch ((insn >> 6) & 3) {
8974 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
8975 case 1: gen_rev16(tmp); break;
8976 case 3: gen_revsh(tmp); break;
8977 default: goto illegal_op;
8978 }
8979 store_reg(s, rd, tmp);
8980 break;
8981
8982 case 6: /* cps */
8983 ARCH(6);
8984 if (IS_USER(s))
8985 break;
8986 if (IS_M(env)) {
8987 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
8988 /* PRIMASK */
8989 if (insn & 1) {
8990 addr = tcg_const_i32(16);
8991 gen_helper_v7m_msr(cpu_env, addr, tmp);
8992 tcg_temp_free_i32(addr);
8993 }
8994 /* FAULTMASK */
8995 if (insn & 2) {
8996 addr = tcg_const_i32(17);
8997 gen_helper_v7m_msr(cpu_env, addr, tmp);
8998 tcg_temp_free_i32(addr);
8999 }
9000 tcg_temp_free_i32(tmp);
9001 gen_lookup_tb(s);
9002 } else {
9003 if (insn & (1 << 4))
9004 shift = CPSR_A | CPSR_I | CPSR_F;
9005 else
9006 shift = 0;
9007 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9008 }
9009 break;
9010
9011 default:
9012 goto undef;
9013 }
9014 break;
9015
9016 case 12:
9017 /* load/store multiple */
9018 rn = (insn >> 8) & 0x7;
9019 addr = load_reg(s, rn);
9020 for (i = 0; i < 8; i++) {
9021 if (insn & (1 << i)) {
9022 if (insn & (1 << 11)) {
9023 /* load */
9024 tmp = gen_ld32(addr, IS_USER(s));
9025 store_reg(s, i, tmp);
9026 } else {
9027 /* store */
9028 tmp = load_reg(s, i);
9029 gen_st32(tmp, addr, IS_USER(s));
9030 }
9031 /* advance to the next address */
9032 tcg_gen_addi_i32(addr, addr, 4);
9033 }
9034 }
9035 /* Base register writeback. */
9036 if ((insn & (1 << rn)) == 0) {
9037 store_reg(s, rn, addr);
9038 } else {
9039 dead_tmp(addr);
9040 }
9041 break;
9042
9043 case 13:
9044 /* conditional branch or swi */
9045 cond = (insn >> 8) & 0xf;
9046 if (cond == 0xe)
9047 goto undef;
9048
9049 if (cond == 0xf) {
9050 /* swi */
9051 gen_set_pc_im(s->pc);
9052 s->is_jmp = DISAS_SWI;
9053 break;
9054 }
9055 /* generate a conditional jump to next instruction */
9056 s->condlabel = gen_new_label();
9057 gen_test_cc(cond ^ 1, s->condlabel);
9058 s->condjmp = 1;
9059
9060 /* jump to the offset */
9061 val = (uint32_t)s->pc + 2;
9062 offset = ((int32_t)insn << 24) >> 24;
9063 val += offset << 1;
9064 gen_jmp(s, val);
9065 break;
9066
9067 case 14:
9068 if (insn & (1 << 11)) {
9069 if (disas_thumb2_insn(env, s, insn))
9070 goto undef32;
9071 break;
9072 }
9073 /* unconditional branch */
9074 val = (uint32_t)s->pc;
9075 offset = ((int32_t)insn << 21) >> 21;
9076 val += (offset << 1) + 2;
9077 gen_jmp(s, val);
9078 break;
9079
9080 case 15:
9081 if (disas_thumb2_insn(env, s, insn))
9082 goto undef32;
9083 break;
9084 }
9085 return;
9086 undef32:
9087 gen_exception_insn(s, 4, EXCP_UDEF);
9088 return;
9089 illegal_op:
9090 undef:
9091 gen_exception_insn(s, 2, EXCP_UDEF);
9092 }
9093
9094 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9095 basic block 'tb'. If search_pc is TRUE, also generate PC
9096 information for each intermediate instruction. */
9097 static inline void gen_intermediate_code_internal(CPUState *env,
9098 TranslationBlock *tb,
9099 int search_pc)
9100 {
9101 DisasContext dc1, *dc = &dc1;
9102 CPUBreakpoint *bp;
9103 uint16_t *gen_opc_end;
9104 int j, lj;
9105 target_ulong pc_start;
9106 uint32_t next_page_start;
9107 int num_insns;
9108 int max_insns;
9109
9110 /* generate intermediate code */
9111 num_temps = 0;
9112
9113 pc_start = tb->pc;
9114
9115 dc->tb = tb;
9116
9117 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9118
9119 dc->is_jmp = DISAS_NEXT;
9120 dc->pc = pc_start;
9121 dc->singlestep_enabled = env->singlestep_enabled;
9122 dc->condjmp = 0;
9123 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
9124 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9125 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
9126 #if !defined(CONFIG_USER_ONLY)
9127 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
9128 #endif
9129 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
9130 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9131 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
9132 cpu_F0s = tcg_temp_new_i32();
9133 cpu_F1s = tcg_temp_new_i32();
9134 cpu_F0d = tcg_temp_new_i64();
9135 cpu_F1d = tcg_temp_new_i64();
9136 cpu_V0 = cpu_F0d;
9137 cpu_V1 = cpu_F1d;
9138 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9139 cpu_M0 = tcg_temp_new_i64();
9140 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
9141 lj = -1;
9142 num_insns = 0;
9143 max_insns = tb->cflags & CF_COUNT_MASK;
9144 if (max_insns == 0)
9145 max_insns = CF_COUNT_MASK;
9146
9147 gen_icount_start();
9148
9149 /* A note on handling of the condexec (IT) bits:
9150 *
9151 * We want to avoid the overhead of having to write the updated condexec
9152 * bits back to the CPUState for every instruction in an IT block. So:
9153 * (1) if the condexec bits are not already zero then we write
9154 * zero back into the CPUState now. This avoids complications trying
9155 * to do it at the end of the block. (For example if we don't do this
9156 * it's hard to identify whether we can safely skip writing condexec
9157 * at the end of the TB, which we definitely want to do for the case
9158 * where a TB doesn't do anything with the IT state at all.)
9159 * (2) if we are going to leave the TB then we call gen_set_condexec()
9160 * which will write the correct value into CPUState if zero is wrong.
9161 * This is done both for leaving the TB at the end, and for leaving
9162 * it because of an exception we know will happen, which is done in
9163 * gen_exception_insn(). The latter is necessary because we need to
9164 * leave the TB with the PC/IT state just prior to execution of the
9165 * instruction which caused the exception.
9166 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9167 * then the CPUState will be wrong and we need to reset it.
9168 * This is handled in the same way as restoration of the
9169 * PC in these situations: we will be called again with search_pc=1
9170 * and generate a mapping of the condexec bits for each PC in
9171 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9172 * the condexec bits.
9173 *
9174 * Note that there are no instructions which can read the condexec
9175 * bits, and none which can write non-static values to them, so
9176 * we don't need to care about whether CPUState is correct in the
9177 * middle of a TB.
9178 */
9179
9180 /* Reset the conditional execution bits immediately. This avoids
9181 complications trying to do it at the end of the block. */
9182 if (dc->condexec_mask || dc->condexec_cond)
9183 {
9184 TCGv tmp = new_tmp();
9185 tcg_gen_movi_i32(tmp, 0);
9186 store_cpu_field(tmp, condexec_bits);
9187 }
9188 do {
9189 #ifdef CONFIG_USER_ONLY
9190 /* Intercept jump to the magic kernel page. */
9191 if (dc->pc >= 0xffff0000) {
9192 /* We always get here via a jump, so know we are not in a
9193 conditional execution block. */
9194 gen_exception(EXCP_KERNEL_TRAP);
9195 dc->is_jmp = DISAS_UPDATE;
9196 break;
9197 }
9198 #else
9199 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9200 /* We always get here via a jump, so know we are not in a
9201 conditional execution block. */
9202 gen_exception(EXCP_EXCEPTION_EXIT);
9203 dc->is_jmp = DISAS_UPDATE;
9204 break;
9205 }
9206 #endif
9207
9208 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9209 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9210 if (bp->pc == dc->pc) {
9211 gen_exception_insn(dc, 0, EXCP_DEBUG);
9212 /* Advance PC so that clearing the breakpoint will
9213 invalidate this TB. */
9214 dc->pc += 2;
9215 goto done_generating;
9216 break;
9217 }
9218 }
9219 }
9220 if (search_pc) {
9221 j = gen_opc_ptr - gen_opc_buf;
9222 if (lj < j) {
9223 lj++;
9224 while (lj < j)
9225 gen_opc_instr_start[lj++] = 0;
9226 }
9227 gen_opc_pc[lj] = dc->pc;
9228 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
9229 gen_opc_instr_start[lj] = 1;
9230 gen_opc_icount[lj] = num_insns;
9231 }
9232
9233 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9234 gen_io_start();
9235
9236 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9237 tcg_gen_debug_insn_start(dc->pc);
9238 }
9239
9240 if (dc->thumb) {
9241 disas_thumb_insn(env, dc);
9242 if (dc->condexec_mask) {
9243 dc->condexec_cond = (dc->condexec_cond & 0xe)
9244 | ((dc->condexec_mask >> 4) & 1);
9245 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9246 if (dc->condexec_mask == 0) {
9247 dc->condexec_cond = 0;
9248 }
9249 }
9250 } else {
9251 disas_arm_insn(env, dc);
9252 }
9253 if (num_temps) {
9254 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9255 num_temps = 0;
9256 }
9257
9258 if (dc->condjmp && !dc->is_jmp) {
9259 gen_set_label(dc->condlabel);
9260 dc->condjmp = 0;
9261 }
9262 /* Translation stops when a conditional branch is encountered.
9263 * Otherwise the subsequent code could get translated several times.
9264 * Also stop translation when a page boundary is reached. This
9265 * ensures prefetch aborts occur at the right place. */
9266 num_insns ++;
9267 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9268 !env->singlestep_enabled &&
9269 !singlestep &&
9270 dc->pc < next_page_start &&
9271 num_insns < max_insns);
9272
9273 if (tb->cflags & CF_LAST_IO) {
9274 if (dc->condjmp) {
9275 /* FIXME: This can theoretically happen with self-modifying
9276 code. */
9277 cpu_abort(env, "IO on conditional branch instruction");
9278 }
9279 gen_io_end();
9280 }
9281
9282 /* At this stage dc->condjmp will only be set when the skipped
9283 instruction was a conditional branch or trap, and the PC has
9284 already been written. */
9285 if (unlikely(env->singlestep_enabled)) {
9286 /* Make sure the pc is updated, and raise a debug exception. */
9287 if (dc->condjmp) {
9288 gen_set_condexec(dc);
9289 if (dc->is_jmp == DISAS_SWI) {
9290 gen_exception(EXCP_SWI);
9291 } else {
9292 gen_exception(EXCP_DEBUG);
9293 }
9294 gen_set_label(dc->condlabel);
9295 }
9296 if (dc->condjmp || !dc->is_jmp) {
9297 gen_set_pc_im(dc->pc);
9298 dc->condjmp = 0;
9299 }
9300 gen_set_condexec(dc);
9301 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
9302 gen_exception(EXCP_SWI);
9303 } else {
9304 /* FIXME: Single stepping a WFI insn will not halt
9305 the CPU. */
9306 gen_exception(EXCP_DEBUG);
9307 }
9308 } else {
9309 /* While branches must always occur at the end of an IT block,
9310 there are a few other things that can cause us to terminate
9311 the TB in the middel of an IT block:
9312 - Exception generating instructions (bkpt, swi, undefined).
9313 - Page boundaries.
9314 - Hardware watchpoints.
9315 Hardware breakpoints have already been handled and skip this code.
9316 */
9317 gen_set_condexec(dc);
9318 switch(dc->is_jmp) {
9319 case DISAS_NEXT:
9320 gen_goto_tb(dc, 1, dc->pc);
9321 break;
9322 default:
9323 case DISAS_JUMP:
9324 case DISAS_UPDATE:
9325 /* indicate that the hash table must be used to find the next TB */
9326 tcg_gen_exit_tb(0);
9327 break;
9328 case DISAS_TB_JUMP:
9329 /* nothing more to generate */
9330 break;
9331 case DISAS_WFI:
9332 gen_helper_wfi();
9333 break;
9334 case DISAS_SWI:
9335 gen_exception(EXCP_SWI);
9336 break;
9337 }
9338 if (dc->condjmp) {
9339 gen_set_label(dc->condlabel);
9340 gen_set_condexec(dc);
9341 gen_goto_tb(dc, 1, dc->pc);
9342 dc->condjmp = 0;
9343 }
9344 }
9345
9346 done_generating:
9347 gen_icount_end(tb, num_insns);
9348 *gen_opc_ptr = INDEX_op_end;
9349
9350 #ifdef DEBUG_DISAS
9351 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9352 qemu_log("----------------\n");
9353 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9354 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
9355 qemu_log("\n");
9356 }
9357 #endif
9358 if (search_pc) {
9359 j = gen_opc_ptr - gen_opc_buf;
9360 lj++;
9361 while (lj <= j)
9362 gen_opc_instr_start[lj++] = 0;
9363 } else {
9364 tb->size = dc->pc - pc_start;
9365 tb->icount = num_insns;
9366 }
9367 }
9368
9369 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
9370 {
9371 gen_intermediate_code_internal(env, tb, 0);
9372 }
9373
9374 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
9375 {
9376 gen_intermediate_code_internal(env, tb, 1);
9377 }
9378
9379 static const char *cpu_mode_names[16] = {
9380 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9381 "???", "???", "???", "und", "???", "???", "???", "sys"
9382 };
9383
9384 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9385 int flags)
9386 {
9387 int i;
9388 #if 0
9389 union {
9390 uint32_t i;
9391 float s;
9392 } s0, s1;
9393 CPU_DoubleU d;
9394 /* ??? This assumes float64 and double have the same layout.
9395 Oh well, it's only debug dumps. */
9396 union {
9397 float64 f64;
9398 double d;
9399 } d0;
9400 #endif
9401 uint32_t psr;
9402
9403 for(i=0;i<16;i++) {
9404 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
9405 if ((i % 4) == 3)
9406 cpu_fprintf(f, "\n");
9407 else
9408 cpu_fprintf(f, " ");
9409 }
9410 psr = cpsr_read(env);
9411 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9412 psr,
9413 psr & (1 << 31) ? 'N' : '-',
9414 psr & (1 << 30) ? 'Z' : '-',
9415 psr & (1 << 29) ? 'C' : '-',
9416 psr & (1 << 28) ? 'V' : '-',
9417 psr & CPSR_T ? 'T' : 'A',
9418 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
9419
9420 #if 0
9421 for (i = 0; i < 16; i++) {
9422 d.d = env->vfp.regs[i];
9423 s0.i = d.l.lower;
9424 s1.i = d.l.upper;
9425 d0.f64 = d.d;
9426 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9427 i * 2, (int)s0.i, s0.s,
9428 i * 2 + 1, (int)s1.i, s1.s,
9429 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
9430 d0.d);
9431 }
9432 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
9433 #endif
9434 }
9435
9436 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9437 unsigned long searched_pc, int pc_pos, void *puc)
9438 {
9439 env->regs[15] = gen_opc_pc[pc_pos];
9440 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
9441 }
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