target-cris/cpu.c

   1 /*
   2  * QEMU CRIS CPU
   3  *
   4  * Copyright (c) 2008 AXIS Communications AB
   5  * Written by Edgar E. Iglesias.
   6  *
   7  * Copyright (c) 2012 SUSE LINUX Products GmbH
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "mmu.h"
  27
  28
  29 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     CRISCPU *cpu = CRIS_CPU(cs);
  32
  33     cpu->env.pc = value;
  34 }
  35
  36 static bool cris_cpu_has_work(CPUState *cs)
  37 {
  38     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  39 }
  40
  41 /* CPUClass::reset() */
  42 static void cris_cpu_reset(CPUState *s)
  43 {
  44     CRISCPU *cpu = CRIS_CPU(s);
  45     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
  46     CPUCRISState *env = &cpu->env;
  47     uint32_t vr;
  48
  49     ccc->parent_reset(s);
  50
  51     vr = env->pregs[PR_VR];
  52     memset(env, 0, offsetof(CPUCRISState, breakpoints));
  53     env->pregs[PR_VR] = vr;
  54     tlb_flush(env, 1);
  55
  56 #if defined(CONFIG_USER_ONLY)
  57     /* start in user mode with interrupts enabled.  */
  58     env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
  59 #else
  60     cris_mmu_init(env);
  61     env->pregs[PR_CCS] = 0;
  62 #endif
  63 }
  64
  65 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
  66 {
  67     ObjectClass *oc;
  68     char *typename;
  69
  70     if (cpu_model == NULL) {
  71         return NULL;
  72     }
  73
  74 #if defined(CONFIG_USER_ONLY)
  75     if (strcasecmp(cpu_model, "any") == 0) {
  76         return object_class_by_name("crisv32-" TYPE_CRIS_CPU);
  77     }
  78 #endif
  79
  80     typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
  81     oc = object_class_by_name(typename);
  82     g_free(typename);
  83     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
  84                        object_class_is_abstract(oc))) {
  85         oc = NULL;
  86     }
  87     return oc;
  88 }
  89
  90 CRISCPU *cpu_cris_init(const char *cpu_model)
  91 {
  92     CRISCPU *cpu;
  93     ObjectClass *oc;
  94
  95     oc = cris_cpu_class_by_name(cpu_model);
  96     if (oc == NULL) {
  97         return NULL;
  98     }
  99     cpu = CRIS_CPU(object_new(object_class_get_name(oc)));
 100
 101     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 102
 103     return cpu;
 104 }
 105
 106 /* Sort alphabetically by VR. */
 107 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
 108 {
 109     CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
 110     CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
 111
 112     /*  */
 113     if (ccc_a->vr > ccc_b->vr) {
 114         return 1;
 115     } else if (ccc_a->vr < ccc_b->vr) {
 116         return -1;
 117     } else {
 118         return 0;
 119     }
 120 }
 121
 122 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
 123 {
 124     ObjectClass *oc = data;
 125     CPUListState *s = user_data;
 126     const char *typename = object_class_get_name(oc);
 127     char *name;
 128
 129     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
 130     (*s->cpu_fprintf)(s->file, "  %s\n", name);
 131     g_free(name);
 132 }
 133
 134 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 135 {
 136     CPUListState s = {
 137         .file = f,
 138         .cpu_fprintf = cpu_fprintf,
 139     };
 140     GSList *list;
 141
 142     list = object_class_get_list(TYPE_CRIS_CPU, false);
 143     list = g_slist_sort(list, cris_cpu_list_compare);
 144     (*cpu_fprintf)(f, "Available CPUs:\n");
 145     g_slist_foreach(list, cris_cpu_list_entry, &s);
 146     g_slist_free(list);
 147 }
 148
 149 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
 150 {
 151     CPUState *cs = CPU(dev);
 152     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
 153
 154     cpu_reset(cs);
 155     qemu_init_vcpu(cs);
 156
 157     ccc->parent_realize(dev, errp);
 158 }
 159
 160 #ifndef CONFIG_USER_ONLY
 161 static void cris_cpu_set_irq(void *opaque, int irq, int level)
 162 {
 163     CRISCPU *cpu = opaque;
 164     CPUState *cs = CPU(cpu);
 165     int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
 166
 167     if (level) {
 168         cpu_interrupt(cs, type);
 169     } else {
 170         cpu_reset_interrupt(cs, type);
 171     }
 172 }
 173 #endif
 174
 175 static void cris_cpu_initfn(Object *obj)
 176 {
 177     CPUState *cs = CPU(obj);
 178     CRISCPU *cpu = CRIS_CPU(obj);
 179     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
 180     CPUCRISState *env = &cpu->env;
 181     static bool tcg_initialized;
 182
 183     cs->env_ptr = env;
 184     cpu_exec_init(env);
 185
 186     env->pregs[PR_VR] = ccc->vr;
 187
 188 #ifndef CONFIG_USER_ONLY
 189     /* IRQ and NMI lines.  */
 190     qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
 191 #endif
 192
 193     if (tcg_enabled() && !tcg_initialized) {
 194         tcg_initialized = true;
 195         if (env->pregs[PR_VR] < 32) {
 196             cris_initialize_crisv10_tcg();
 197         } else {
 198             cris_initialize_tcg();
 199         }
 200     }
 201 }
 202
 203 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
 204 {
 205     CPUClass *cc = CPU_CLASS(oc);
 206     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 207
 208     ccc->vr = 8;
 209     cc->do_interrupt = crisv10_cpu_do_interrupt;
 210     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 211 }
 212
 213 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
 214 {
 215     CPUClass *cc = CPU_CLASS(oc);
 216     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 217
 218     ccc->vr = 9;
 219     cc->do_interrupt = crisv10_cpu_do_interrupt;
 220     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 221 }
 222
 223 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
 224 {
 225     CPUClass *cc = CPU_CLASS(oc);
 226     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 227
 228     ccc->vr = 10;
 229     cc->do_interrupt = crisv10_cpu_do_interrupt;
 230     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 231 }
 232
 233 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
 234 {
 235     CPUClass *cc = CPU_CLASS(oc);
 236     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 237
 238     ccc->vr = 11;
 239     cc->do_interrupt = crisv10_cpu_do_interrupt;
 240     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 241 }
 242
 243 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
 244 {
 245     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 246
 247     ccc->vr = 32;
 248 }
 249
 250 #define TYPE(model) model "-" TYPE_CRIS_CPU
 251
 252 static const TypeInfo cris_cpu_model_type_infos[] = {
 253     {
 254         .name = TYPE("crisv8"),
 255         .parent = TYPE_CRIS_CPU,
 256         .class_init = crisv8_cpu_class_init,
 257     }, {
 258         .name = TYPE("crisv9"),
 259         .parent = TYPE_CRIS_CPU,
 260         .class_init = crisv9_cpu_class_init,
 261     }, {
 262         .name = TYPE("crisv10"),
 263         .parent = TYPE_CRIS_CPU,
 264         .class_init = crisv10_cpu_class_init,
 265     }, {
 266         .name = TYPE("crisv11"),
 267         .parent = TYPE_CRIS_CPU,
 268         .class_init = crisv11_cpu_class_init,
 269     }, {
 270         .name = TYPE("crisv32"),
 271         .parent = TYPE_CRIS_CPU,
 272         .class_init = crisv32_cpu_class_init,
 273     }
 274 };
 275
 276 #undef TYPE
 277
 278 static void cris_cpu_class_init(ObjectClass *oc, void *data)
 279 {
 280     DeviceClass *dc = DEVICE_CLASS(oc);
 281     CPUClass *cc = CPU_CLASS(oc);
 282     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 283
 284     ccc->parent_realize = dc->realize;
 285     dc->realize = cris_cpu_realizefn;
 286
 287     ccc->parent_reset = cc->reset;
 288     cc->reset = cris_cpu_reset;
 289
 290     cc->class_by_name = cris_cpu_class_by_name;
 291     cc->has_work = cris_cpu_has_work;
 292     cc->do_interrupt = cris_cpu_do_interrupt;
 293     cc->dump_state = cris_cpu_dump_state;
 294     cc->set_pc = cris_cpu_set_pc;
 295     cc->gdb_read_register = cris_cpu_gdb_read_register;
 296     cc->gdb_write_register = cris_cpu_gdb_write_register;
 297 #ifndef CONFIG_USER_ONLY
 298     cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
 299 #endif
 300
 301     cc->gdb_num_core_regs = 49;
 302 }
 303
 304 static const TypeInfo cris_cpu_type_info = {
 305     .name = TYPE_CRIS_CPU,
 306     .parent = TYPE_CPU,
 307     .instance_size = sizeof(CRISCPU),
 308     .instance_init = cris_cpu_initfn,
 309     .abstract = true,
 310     .class_size = sizeof(CRISCPUClass),
 311     .class_init = cris_cpu_class_init,
 312 };
 313
 314 static void cris_cpu_register_types(void)
 315 {
 316     int i;
 317
 318     type_register_static(&cris_cpu_type_info);
 319     for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
 320         type_register_static(&cris_cpu_model_type_infos[i]);
 321     }
 322 }
 323
 324 type_init(cris_cpu_register_types)