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1 /*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
20 */
21 #ifndef CPU_CRIS_H
22 #define CPU_CRIS_H
23
24 #define TARGET_LONG_BITS 32
25
26 #define CPUState struct CPUCRISState
27
28 #include "cpu-defs.h"
29
30 #define TARGET_HAS_ICE 1
31
32 #define ELF_MACHINE EM_CRIS
33
34 #define EXCP_NMI 1
35 #define EXCP_GURU 2
36 #define EXCP_BUSFAULT 3
37 #define EXCP_IRQ 4
38 #define EXCP_BREAK 5
39
40 /* Register aliases. R0 - R15 */
41 #define R_FP 8
42 #define R_SP 14
43 #define R_ACR 15
44
45 /* Support regs, P0 - P15 */
46 #define PR_BZ 0
47 #define PR_VR 1
48 #define PR_PID 2
49 #define PR_SRS 3
50 #define PR_WZ 4
51 #define PR_EXS 5
52 #define PR_EDA 6
53 #define PR_MOF 7
54 #define PR_DZ 8
55 #define PR_EBP 9
56 #define PR_ERP 10
57 #define PR_SRP 11
58 #define PR_NRP 12
59 #define PR_CCS 13
60 #define PR_USP 14
61 #define PR_SPC 15
62
63 /* CPU flags. */
64 #define Q_FLAG 0x80000000
65 #define M_FLAG 0x40000000
66 #define S_FLAG 0x200
67 #define R_FLAG 0x100
68 #define P_FLAG 0x80
69 #define U_FLAG 0x40
70 #define P_FLAG 0x80
71 #define U_FLAG 0x40
72 #define I_FLAG 0x20
73 #define X_FLAG 0x10
74 #define N_FLAG 0x08
75 #define Z_FLAG 0x04
76 #define V_FLAG 0x02
77 #define C_FLAG 0x01
78 #define ALU_FLAGS 0x1F
79
80 /* Condition codes. */
81 #define CC_CC 0
82 #define CC_CS 1
83 #define CC_NE 2
84 #define CC_EQ 3
85 #define CC_VC 4
86 #define CC_VS 5
87 #define CC_PL 6
88 #define CC_MI 7
89 #define CC_LS 8
90 #define CC_HI 9
91 #define CC_GE 10
92 #define CC_LT 11
93 #define CC_GT 12
94 #define CC_LE 13
95 #define CC_A 14
96 #define CC_P 15
97
98 /* Internal flags for the implementation. */
99 #define F_DELAYSLOT 1
100
101 #define NB_MMU_MODES 2
102
103 typedef struct CPUCRISState {
104 uint32_t regs[16];
105 /* P0 - P15 are referred to as special registers in the docs. */
106 uint32_t pregs[16];
107
108 /* Pseudo register for the PC. Not directly accessable on CRIS. */
109 uint32_t pc;
110
111 /* Pseudo register for the kernel stack. */
112 uint32_t ksp;
113
114 /* Branch. */
115 int dslot;
116 int btaken;
117 uint32_t btarget;
118
119 /* Condition flag tracking. */
120 uint32_t cc_op;
121 uint32_t cc_mask;
122 uint32_t cc_dest;
123 uint32_t cc_src;
124 uint32_t cc_result;
125 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
126 int cc_size;
127 /* X flag at the time of cc snapshot. */
128 int cc_x;
129
130 int interrupt_vector;
131 int fault_vector;
132 int trap_vector;
133
134 /* FIXME: add a check in the translator to avoid writing to support
135 register sets beyond the 4th. The ISA allows up to 256! but in
136 practice there is no core that implements more than 4.
137
138 Support function registers are used to control units close to the
139 core. Accesses do not pass down the normal hierarchy.
140 */
141 uint32_t sregs[4][16];
142
143 /* Linear feedback shift reg in the mmu. Used to provide pseudo
144 randomness for the 'hint' the mmu gives to sw for chosing valid
145 sets on TLB refills. */
146 uint32_t mmu_rand_lfsr;
147
148 /*
149 * We just store the stores to the tlbset here for later evaluation
150 * when the hw needs access to them.
151 *
152 * One for I and another for D.
153 */
154 struct
155 {
156 uint32_t hi;
157 uint32_t lo;
158 } tlbsets[2][4][16];
159
160 CPU_COMMON
161 } CPUCRISState;
162
163 CPUCRISState *cpu_cris_init(const char *cpu_model);
164 int cpu_cris_exec(CPUCRISState *s);
165 void cpu_cris_close(CPUCRISState *s);
166 void do_interrupt(CPUCRISState *env);
167 /* you can call this signal handler from your SIGBUS and SIGSEGV
168 signal handlers to inform the virtual CPU of exceptions. non zero
169 is returned if the signal was handled by the virtual CPU. */
170 int cpu_cris_signal_handler(int host_signum, void *pinfo,
171 void *puc);
172
173 enum {
174 CC_OP_DYNAMIC, /* Use env->cc_op */
175 CC_OP_FLAGS,
176 CC_OP_CMP,
177 CC_OP_MOVE,
178 CC_OP_ADD,
179 CC_OP_ADDC,
180 CC_OP_MCP,
181 CC_OP_ADDU,
182 CC_OP_SUB,
183 CC_OP_SUBU,
184 CC_OP_NEG,
185 CC_OP_BTST,
186 CC_OP_MULS,
187 CC_OP_MULU,
188 CC_OP_DSTEP,
189 CC_OP_BOUND,
190
191 CC_OP_OR,
192 CC_OP_AND,
193 CC_OP_XOR,
194 CC_OP_LSL,
195 CC_OP_LSR,
196 CC_OP_ASR,
197 CC_OP_LZ
198 };
199
200 /* CRIS uses 8k pages. */
201 #define TARGET_PAGE_BITS 13
202 #define MMAP_SHIFT TARGET_PAGE_BITS
203
204 #define cpu_init cpu_cris_init
205 #define cpu_exec cpu_cris_exec
206 #define cpu_gen_code cpu_cris_gen_code
207 #define cpu_signal_handler cpu_cris_signal_handler
208
209 #define CPU_SAVE_VERSION 1
210
211 /* MMU modes definitions */
212 #define MMU_MODE0_SUFFIX _kernel
213 #define MMU_MODE1_SUFFIX _user
214 #define MMU_USER_IDX 1
215 static inline int cpu_mmu_index (CPUState *env)
216 {
217 return !!(env->pregs[PR_CCS] & U_FLAG);
218 }
219
220 int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
221 int mmu_idx, int is_softmmu);
222
223 #if defined(CONFIG_USER_ONLY)
224 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
225 {
226 if (newsp)
227 env->regs[14] = newsp;
228 env->regs[10] = 0;
229 }
230 #endif
231
232 static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
233 {
234 env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
235 }
236
237 /* Support function regs. */
238 #define SFR_RW_GC_CFG 0][0
239 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
240 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
241 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
242 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
243 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
244 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
245 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
246
247 #include "cpu-all.h"
248 #include "exec-all.h"
249
250 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
251 {
252 env->pc = tb->pc;
253 }
254
255 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
256 target_ulong *cs_base, int *flags)
257 {
258 *pc = env->pc;
259 *cs_base = 0;
260 *flags = env->dslot |
261 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG));
262 }
263
264 #endif