target-cris/cpu.h

   1 /*
   2  *  CRIS virtual CPU header
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #ifndef CPU_CRIS_H
  22 #define CPU_CRIS_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #include "cpu-defs.h"
  27
  28 #define TARGET_HAS_ICE 1
  29
  30 #define ELF_MACHINE     EM_CRIS
  31
  32 #define EXCP_MMU_EXEC    0
  33 #define EXCP_MMU_READ    1
  34 #define EXCP_MMU_WRITE   2
  35 #define EXCP_MMU_FLUSH   3
  36 #define EXCP_MMU_FAULT   4
  37 #define EXCP_BREAK      16 /* trap.  */
  38
  39 /* Register aliases. R0 - R15 */
  40 #define R_FP  8
  41 #define R_SP  14
  42 #define R_ACR 15
  43
  44 /* Support regs, P0 - P15  */
  45 #define PR_BZ  0
  46 #define PR_VR  1
  47 #define PR_PID 2
  48 #define PR_SRS 3
  49 #define PR_WZ  4
  50 #define PR_EXS 5
  51 #define PR_EDA 6
  52 #define PR_MOF 7
  53 #define PR_DZ  8
  54 #define PR_EBP 9
  55 #define PR_ERP 10
  56 #define PR_SRP 11
  57 #define PR_CCS 13
  58 #define PR_USP 14
  59 #define PR_SPC 15
  60
  61 /* CPU flags.  */
  62 #define S_FLAG 0x200
  63 #define R_FLAG 0x100
  64 #define P_FLAG 0x80
  65 #define U_FLAG 0x40
  66 #define P_FLAG 0x80
  67 #define U_FLAG 0x40
  68 #define I_FLAG 0x20
  69 #define X_FLAG 0x10
  70 #define N_FLAG 0x08
  71 #define Z_FLAG 0x04
  72 #define V_FLAG 0x02
  73 #define C_FLAG 0x01
  74 #define ALU_FLAGS 0x1F
  75
  76 /* Condition codes.  */
  77 #define CC_CC   0
  78 #define CC_CS   1
  79 #define CC_NE   2
  80 #define CC_EQ   3
  81 #define CC_VC   4
  82 #define CC_VS   5
  83 #define CC_PL   6
  84 #define CC_MI   7
  85 #define CC_LS   8
  86 #define CC_HI   9
  87 #define CC_GE  10
  88 #define CC_LT  11
  89 #define CC_GT  12
  90 #define CC_LE  13
  91 #define CC_A   14
  92 #define CC_P   15
  93
  94 /* Internal flags for the implementation.  */
  95 #define F_DELAYSLOT 1
  96
  97 #define NB_MMU_MODES 2
  98
  99 typedef struct CPUCRISState {
 100         uint32_t regs[16];
 101         /* P0 - P15 are referred to as special registers in the docs.  */
 102         uint32_t pregs[16];
 103
 104         /* Pseudo register for the PC. Not directly accessable on CRIS.  */
 105         uint32_t pc;
 106
 107         /* Pseudo register for the kernel stack.  */
 108         uint32_t ksp;
 109
 110         /* Branch.  */
 111         int dslot;
 112         int btaken;
 113         uint32_t btarget;
 114
 115         /* Condition flag tracking.  */
 116         uint32_t cc_op;
 117         uint32_t cc_mask;
 118         uint32_t cc_dest;
 119         uint32_t cc_src;
 120         uint32_t cc_result;
 121         /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 122         int cc_size;
 123         /* X flag at the time of cc snapshot.  */
 124         int cc_x;
 125
 126         int interrupt_request;
 127         int interrupt_vector;
 128         int fault_vector;
 129         int trap_vector;
 130
 131         /* FIXME: add a check in the translator to avoid writing to support
 132            register sets beyond the 4th. The ISA allows up to 256! but in
 133            practice there is no core that implements more than 4.
 134
 135            Support function registers are used to control units close to the
 136            core. Accesses do not pass down the normal hierarchy.
 137         */
 138         uint32_t sregs[4][16];
 139
 140         /* Linear feedback shift reg in the mmu. Used to provide pseudo
 141            randomness for the 'hint' the mmu gives to sw for chosing valid
 142            sets on TLB refills.  */
 143         uint32_t mmu_rand_lfsr;
 144
 145         /*
 146          * We just store the stores to the tlbset here for later evaluation
 147          * when the hw needs access to them.
 148          *
 149          * One for I and another for D.
 150          */
 151         struct
 152         {
 153                 uint32_t hi;
 154                 uint32_t lo;
 155         } tlbsets[2][4][16];
 156
 157         int features;
 158         int user_mode_only;
 159
 160         CPU_COMMON
 161 } CPUCRISState;
 162
 163 CPUCRISState *cpu_cris_init(const char *cpu_model);
 164 int cpu_cris_exec(CPUCRISState *s);
 165 void cpu_cris_close(CPUCRISState *s);
 166 void do_interrupt(CPUCRISState *env);
 167 /* you can call this signal handler from your SIGBUS and SIGSEGV
 168    signal handlers to inform the virtual CPU of exceptions. non zero
 169    is returned if the signal was handled by the virtual CPU.  */
 170 int cpu_cris_signal_handler(int host_signum, void *pinfo,
 171                            void *puc);
 172 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 173                           int is_asi);
 174
 175 enum {
 176     CC_OP_DYNAMIC, /* Use env->cc_op  */
 177     CC_OP_FLAGS,
 178     CC_OP_CMP,
 179     CC_OP_MOVE,
 180     CC_OP_ADD,
 181     CC_OP_ADDC,
 182     CC_OP_MCP,
 183     CC_OP_ADDU,
 184     CC_OP_SUB,
 185     CC_OP_SUBU,
 186     CC_OP_NEG,
 187     CC_OP_BTST,
 188     CC_OP_MULS,
 189     CC_OP_MULU,
 190     CC_OP_DSTEP,
 191     CC_OP_BOUND,
 192
 193     CC_OP_OR,
 194     CC_OP_AND,
 195     CC_OP_XOR,
 196     CC_OP_LSL,
 197     CC_OP_LSR,
 198     CC_OP_ASR,
 199     CC_OP_LZ
 200 };
 201
 202 /* CRIS uses 8k pages.  */
 203 #define TARGET_PAGE_BITS 13
 204 #define MMAP_SHIFT TARGET_PAGE_BITS
 205
 206 #define CPUState CPUCRISState
 207 #define cpu_init cpu_cris_init
 208 #define cpu_exec cpu_cris_exec
 209 #define cpu_gen_code cpu_cris_gen_code
 210 #define cpu_signal_handler cpu_cris_signal_handler
 211
 212 /* MMU modes definitions */
 213 #define MMU_MODE0_SUFFIX _kernel
 214 #define MMU_MODE1_SUFFIX _user
 215 #define MMU_USER_IDX 1
 216 static inline int cpu_mmu_index (CPUState *env)
 217 {
 218         return !!(env->pregs[PR_CCS] & U_FLAG);
 219 }
 220
 221 #if defined(CONFIG_USER_ONLY)
 222 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 223 {
 224     if (!newsp)
 225         env->regs[14] = newsp;
 226     env->regs[10] = 0;
 227 }
 228 #endif
 229
 230 /* Support function regs.  */
 231 #define SFR_RW_GC_CFG      0][0
 232 #define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 233 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 234 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 235 #define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 236 #define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 237 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 238 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 239
 240 #include "cpu-all.h"
 241 #endif