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2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * This file implements a CRIS decoder-stage in SW. The decoder translates the
24 * guest (CRIS) machine-code into host machine code via dyngen using the
25 * micro-operations described in op.c
27 * The micro-operations for CRIS translation implement a RISC style ISA.
28 * Note that the micro-operations typically order their operands
29 * starting with the dst. CRIS asm, does the opposite.
31 * For example the following CRIS code:
36 * gen_movl_T0_reg(0); // Fetch $r0 into T0
37 * gen_load_T0_T0(); // Load T0, @T0
38 * gen_movl_reg_T0(1); // Writeback T0 into $r1
40 * The actual names for the micro-code generators vary but the example
41 * illustrates the point.
55 #include "crisv32-decode.h"
71 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
72 #define BUG_ON(x) ({if (x) BUG();})
74 /* Used by the decoder. */
75 #define EXTRACT_FIELD(src, start, end) \
76 (((src) >> start) & ((1 << (end - start + 1)) - 1))
78 #define CC_MASK_NZ 0xc
79 #define CC_MASK_NZV 0xe
80 #define CC_MASK_NZVC 0xf
81 #define CC_MASK_RNZV 0x10e
83 /* This is the state at translation time. */
84 typedef struct DisasContext
{
86 target_ulong pc
, insn_pc
;
93 unsigned int zsize
, zzsize
;
104 uint32_t tb_entry_flags
;
106 int memidx
; /* user or kernel mode. */
115 struct TranslationBlock
*tb
;
116 int singlestep_enabled
;
119 void cris_prepare_jmp (DisasContext
*dc
, uint32_t dst
);
120 static void gen_BUG(DisasContext
*dc
, char *file
, int line
)
122 printf ("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
123 fprintf (logfile
, "BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
124 cpu_dump_state (dc
->env
, stdout
, fprintf
, 0);
126 cris_prepare_jmp (dc
, 0x70000000 + line
);
129 /* Table to generate quick moves from T0 onto any register. */
130 static GenOpFunc
*gen_movl_reg_T0
[16] =
132 gen_op_movl_r0_T0
, gen_op_movl_r1_T0
,
133 gen_op_movl_r2_T0
, gen_op_movl_r3_T0
,
134 gen_op_movl_r4_T0
, gen_op_movl_r5_T0
,
135 gen_op_movl_r6_T0
, gen_op_movl_r7_T0
,
136 gen_op_movl_r8_T0
, gen_op_movl_r9_T0
,
137 gen_op_movl_r10_T0
, gen_op_movl_r11_T0
,
138 gen_op_movl_r12_T0
, gen_op_movl_r13_T0
,
139 gen_op_movl_r14_T0
, gen_op_movl_r15_T0
,
141 static GenOpFunc
*gen_movl_T0_reg
[16] =
143 gen_op_movl_T0_r0
, gen_op_movl_T0_r1
,
144 gen_op_movl_T0_r2
, gen_op_movl_T0_r3
,
145 gen_op_movl_T0_r4
, gen_op_movl_T0_r5
,
146 gen_op_movl_T0_r6
, gen_op_movl_T0_r7
,
147 gen_op_movl_T0_r8
, gen_op_movl_T0_r9
,
148 gen_op_movl_T0_r10
, gen_op_movl_T0_r11
,
149 gen_op_movl_T0_r12
, gen_op_movl_T0_r13
,
150 gen_op_movl_T0_r14
, gen_op_movl_T0_r15
,
153 static void noop_write(void) {
157 static void gen_vr_read(void) {
158 gen_op_movl_T0_im(32);
161 static void gen_movl_T0_p0(void) {
162 gen_op_movl_T0_im(0);
165 static void gen_ccs_read(void) {
166 gen_op_movl_T0_p13();
169 static void gen_ccs_write(void) {
170 gen_op_movl_p13_T0();
173 /* Table to generate quick moves from T0 onto any register. */
174 static GenOpFunc
*gen_movl_preg_T0
[16] =
176 noop_write
, /* bz, not writeable. */
177 noop_write
, /* vr, not writeable. */
178 gen_op_movl_p2_T0
, gen_op_movl_p3_T0
,
179 noop_write
, /* wz, not writeable. */
181 gen_op_movl_p6_T0
, gen_op_movl_p7_T0
,
182 noop_write
, /* dz, not writeable. */
184 gen_op_movl_p10_T0
, gen_op_movl_p11_T0
,
186 gen_ccs_write
, /* ccs needs special treatment. */
187 gen_op_movl_p14_T0
, gen_op_movl_p15_T0
,
189 static GenOpFunc
*gen_movl_T0_preg
[16] =
193 gen_op_movl_T0_p2
, gen_op_movl_T0_p3
,
194 gen_op_movl_T0_p4
, gen_op_movl_T0_p5
,
195 gen_op_movl_T0_p6
, gen_op_movl_T0_p7
,
196 gen_op_movl_T0_p8
, gen_op_movl_T0_p9
,
197 gen_op_movl_T0_p10
, gen_op_movl_T0_p11
,
199 gen_ccs_read
, /* ccs needs special treatment. */
200 gen_op_movl_T0_p14
, gen_op_movl_T0_p15
,
203 /* We need this table to handle moves with implicit width. */
215 #ifdef CONFIG_USER_ONLY
216 #define GEN_OP_LD(width, reg) \
217 void gen_op_ld##width##_T0_##reg (DisasContext *dc) { \
218 gen_op_ld##width##_T0_##reg##_raw(); \
220 #define GEN_OP_ST(width, reg) \
221 void gen_op_st##width##_##reg##_T1 (DisasContext *dc) { \
222 gen_op_st##width##_##reg##_T1_raw(); \
225 #define GEN_OP_LD(width, reg) \
226 void gen_op_ld##width##_T0_##reg (DisasContext *dc) { \
227 if (dc->memidx) gen_op_ld##width##_T0_##reg##_kernel(); \
228 else gen_op_ld##width##_T0_##reg##_user();\
230 #define GEN_OP_ST(width, reg) \
231 void gen_op_st##width##_##reg##_T1 (DisasContext *dc) { \
232 if (dc->memidx) gen_op_st##width##_##reg##_T1_kernel(); \
233 else gen_op_st##width##_##reg##_T1_user();\
246 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
248 TranslationBlock
*tb
;
250 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
252 /* XXX: this code is not finished */
261 /* Sign extend at translation time. */
262 static int sign_extend(unsigned int val
, unsigned int width
)
274 static void cris_evaluate_flags(DisasContext
*dc
)
276 if (!dc
->flags_live
) {
281 gen_op_evaluate_flags_mcp ();
284 gen_op_evaluate_flags_muls ();
287 gen_op_evaluate_flags_mulu ();
293 gen_op_evaluate_flags_move_4();
296 gen_op_evaluate_flags_move_2();
299 gen_op_evaluate_flags ();
309 gen_op_evaluate_flags_alu_4 ();
312 gen_op_evaluate_flags ();
322 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
326 /* Check if we need to evaluate the condition codes due to
328 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
330 /* TODO: optimize this case. It trigs all the time. */
331 cris_evaluate_flags (dc
);
339 gen_op_update_cc_mask(mask
);
344 static void cris_update_cc_op(DisasContext
*dc
, int op
)
347 gen_op_update_cc_op(op
);
350 static void cris_update_cc_size(DisasContext
*dc
, int size
)
353 gen_op_update_cc_size_im(size
);
356 /* op is the operation.
357 T0, T1 are the operands.
358 dst is the destination reg.
360 static void crisv32_alu_op(DisasContext
*dc
, int op
, int rd
, int size
)
364 cris_update_cc_op(dc
, op
);
365 cris_update_cc_size(dc
, size
);
366 gen_op_update_cc_x(dc
->flagx_live
, dc
->flags_x
);
367 gen_op_update_cc_dest_T0();
370 /* Emit the ALU insns. */
375 /* Extended arithmetics. */
378 else if (dc
->flags_x
)
392 /* CRIS flag evaluation needs ~src. */
396 /* Extended arithmetics. */
399 else if (dc
->flags_x
)
425 /* Extended arithmetics. */
442 gen_op_dstep_T0_T1();
445 gen_op_bound_T0_T1();
450 /* CRIS flag evaluation needs ~src. */
454 /* Extended arithmetics. */
459 fprintf (logfile
, "illegal ALU op.\n");
465 gen_op_update_cc_src_T1();
468 gen_op_andl_T0_im(0xff);
470 gen_op_andl_T0_im(0xffff);
474 gen_movl_reg_T0
[rd
]();
477 gen_movl_T0_reg
[rd
]();
479 gen_op_andl_T0_im(~0xff);
481 gen_op_andl_T0_im(~0xffff);
483 gen_movl_reg_T0
[rd
]();
488 gen_op_update_cc_result_T0();
491 /* TODO: Optimize this. */
493 cris_evaluate_flags(dc
);
497 static int arith_cc(DisasContext
*dc
)
501 case CC_OP_ADD
: return 1;
502 case CC_OP_SUB
: return 1;
503 case CC_OP_LSL
: return 1;
504 case CC_OP_LSR
: return 1;
505 case CC_OP_ASR
: return 1;
506 case CC_OP_CMP
: return 1;
514 static void gen_tst_cc (DisasContext
*dc
, int cond
)
518 /* TODO: optimize more condition codes. */
519 arith_opt
= arith_cc(dc
) && !dc
->flags_live
;
523 gen_op_tst_cc_eq_fast ();
525 cris_evaluate_flags(dc
);
531 gen_op_tst_cc_ne_fast ();
533 cris_evaluate_flags(dc
);
538 cris_evaluate_flags(dc
);
542 cris_evaluate_flags(dc
);
546 cris_evaluate_flags(dc
);
550 cris_evaluate_flags(dc
);
555 gen_op_tst_cc_pl_fast ();
557 cris_evaluate_flags(dc
);
563 gen_op_tst_cc_mi_fast ();
565 cris_evaluate_flags(dc
);
570 cris_evaluate_flags(dc
);
574 cris_evaluate_flags(dc
);
578 cris_evaluate_flags(dc
);
582 cris_evaluate_flags(dc
);
586 cris_evaluate_flags(dc
);
590 cris_evaluate_flags(dc
);
594 cris_evaluate_flags(dc
);
598 cris_evaluate_flags(dc
);
599 gen_op_movl_T0_im (1);
607 static void cris_prepare_cc_branch (DisasContext
*dc
, int offset
, int cond
)
609 /* This helps us re-schedule the micro-code to insns in delay-slots
610 before the actual jump. */
611 dc
->delayed_branch
= 2;
612 dc
->delayed_pc
= dc
->pc
+ offset
;
616 gen_tst_cc (dc
, cond
);
617 gen_op_evaluate_bcc ();
619 gen_op_movl_T0_im (dc
->delayed_pc
);
620 gen_op_movl_btarget_T0 ();
623 /* Dynamic jumps, when the dest is in a live reg for example. */
624 void cris_prepare_dyn_jmp (DisasContext
*dc
)
626 /* This helps us re-schedule the micro-code to insns in delay-slots
627 before the actual jump. */
628 dc
->delayed_branch
= 2;
633 void cris_prepare_jmp (DisasContext
*dc
, uint32_t dst
)
635 /* This helps us re-schedule the micro-code to insns in delay-slots
636 before the actual jump. */
637 dc
->delayed_branch
= 2;
638 dc
->delayed_pc
= dst
;
643 void gen_load_T0_T0 (DisasContext
*dc
, unsigned int size
, int sign
)
647 gen_op_ldb_T0_T0(dc
);
649 gen_op_ldub_T0_T0(dc
);
651 else if (size
== 2) {
653 gen_op_ldw_T0_T0(dc
);
655 gen_op_lduw_T0_T0(dc
);
658 gen_op_ldl_T0_T0(dc
);
662 void gen_store_T0_T1 (DisasContext
*dc
, unsigned int size
)
664 /* Remember, operands are flipped. CRIS has reversed order. */
666 gen_op_stb_T0_T1(dc
);
668 else if (size
== 2) {
669 gen_op_stw_T0_T1(dc
);
672 gen_op_stl_T0_T1(dc
);
675 /* sign extend T1 according to size. */
676 static void gen_sext_T1_T0(int size
)
684 static void gen_sext_T1_T1(int size
)
692 static void gen_sext_T0_T0(int size
)
700 static void gen_zext_T0_T0(int size
)
703 gen_op_zextb_T0_T0();
705 gen_op_zextw_T0_T0();
708 static void gen_zext_T1_T0(int size
)
711 gen_op_zextb_T1_T0();
713 gen_op_zextw_T1_T0();
716 static void gen_zext_T1_T1(int size
)
719 gen_op_zextb_T1_T1();
721 gen_op_zextw_T1_T1();
725 static char memsize_char(int size
)
729 case 1: return 'b'; break;
730 case 2: return 'w'; break;
731 case 4: return 'd'; break;
739 static unsigned int memsize_z(DisasContext
*dc
)
741 return dc
->zsize
+ 1;
744 static unsigned int memsize_zz(DisasContext
*dc
)
755 static void do_postinc (DisasContext
*dc
, int size
)
759 gen_movl_T0_reg
[dc
->op1
]();
760 gen_op_addl_T0_im(size
);
761 gen_movl_reg_T0
[dc
->op1
]();
765 static void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
768 gen_movl_T0_reg
[rs
]();
771 gen_sext_T1_T1(size
);
773 gen_zext_T1_T1(size
);
776 /* Prepare T0 and T1 for a register alu operation.
777 s_ext decides if the operand1 should be sign-extended or zero-extended when
779 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
782 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
);
784 gen_movl_T0_reg
[rd
]();
786 gen_sext_T0_T0(size
);
788 gen_zext_T0_T0(size
);
791 /* Prepare T0 and T1 for a memory + alu operation.
792 s_ext decides if the operand1 should be sign-extended or zero-extended when
794 static int dec_prep_alu_m(DisasContext
*dc
, int s_ext
, int memsize
)
803 is_imm
= rs
== 15 && dc
->postinc
;
805 /* Load [$rs] onto T1. */
807 insn_len
= 2 + memsize
;
811 imm
= ldl_code(dc
->pc
+ 2);
814 imm
= sign_extend(imm
, (memsize
* 8) - 1);
822 DIS(fprintf (logfile
, "imm=%x rd=%d sext=%d ms=%d\n",
823 imm
, rd
, s_ext
, memsize
));
824 gen_op_movl_T1_im (imm
);
827 gen_movl_T0_reg
[rs
]();
828 gen_load_T0_T0(dc
, memsize
, 0);
831 gen_sext_T1_T1(memsize
);
833 gen_zext_T1_T1(memsize
);
836 /* put dest in T0. */
837 gen_movl_T0_reg
[rd
]();
842 static const char *cc_name(int cc
)
844 static char *cc_names
[16] = {
845 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
846 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
853 static unsigned int dec_bccq(DisasContext
*dc
)
857 uint32_t cond
= dc
->op2
;
860 offset
= EXTRACT_FIELD (dc
->ir
, 1, 7);
861 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
866 offset
= sign_extend(offset
, 8);
868 /* op2 holds the condition-code. */
870 cris_prepare_cc_branch (dc
, offset
, cond
);
873 static unsigned int dec_addoq(DisasContext
*dc
)
877 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
878 imm
= sign_extend(dc
->op1
, 7);
880 DIS(fprintf (logfile
, "addoq %d, $r%u\n", imm
, dc
->op2
));
882 /* Fetch register operand, */
883 gen_movl_T0_reg
[dc
->op2
]();
884 gen_op_movl_T1_im(imm
);
885 crisv32_alu_op(dc
, CC_OP_ADD
, REG_ACR
, 4);
888 static unsigned int dec_addq(DisasContext
*dc
)
890 DIS(fprintf (logfile
, "addq %u, $r%u\n", dc
->op1
, dc
->op2
));
892 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
894 cris_cc_mask(dc
, CC_MASK_NZVC
);
895 /* Fetch register operand, */
896 gen_movl_T0_reg
[dc
->op2
]();
897 gen_op_movl_T1_im(dc
->op1
);
898 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
901 static unsigned int dec_moveq(DisasContext
*dc
)
905 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
906 imm
= sign_extend(dc
->op1
, 5);
907 DIS(fprintf (logfile
, "moveq %d, $r%u\n", imm
, dc
->op2
));
910 gen_op_movl_T1_im(imm
);
911 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
915 static unsigned int dec_subq(DisasContext
*dc
)
917 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
919 DIS(fprintf (logfile
, "subq %u, $r%u\n", dc
->op1
, dc
->op2
));
921 cris_cc_mask(dc
, CC_MASK_NZVC
);
922 /* Fetch register operand, */
923 gen_movl_T0_reg
[dc
->op2
]();
924 gen_op_movl_T1_im(dc
->op1
);
925 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
928 static unsigned int dec_cmpq(DisasContext
*dc
)
931 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
932 imm
= sign_extend(dc
->op1
, 5);
934 DIS(fprintf (logfile
, "cmpq %d, $r%d\n", imm
, dc
->op2
));
935 cris_cc_mask(dc
, CC_MASK_NZVC
);
936 gen_movl_T0_reg
[dc
->op2
]();
937 gen_op_movl_T1_im(imm
);
938 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, 4);
941 static unsigned int dec_andq(DisasContext
*dc
)
944 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
945 imm
= sign_extend(dc
->op1
, 5);
947 DIS(fprintf (logfile
, "andq %d, $r%d\n", imm
, dc
->op2
));
948 cris_cc_mask(dc
, CC_MASK_NZ
);
949 gen_movl_T0_reg
[dc
->op2
]();
950 gen_op_movl_T1_im(imm
);
951 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, 4);
954 static unsigned int dec_orq(DisasContext
*dc
)
957 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
958 imm
= sign_extend(dc
->op1
, 5);
959 DIS(fprintf (logfile
, "orq %d, $r%d\n", imm
, dc
->op2
));
960 cris_cc_mask(dc
, CC_MASK_NZ
);
961 gen_movl_T0_reg
[dc
->op2
]();
962 gen_op_movl_T1_im(imm
);
963 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, 4);
966 static unsigned int dec_btstq(DisasContext
*dc
)
968 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
969 DIS(fprintf (logfile
, "btstq %u, $r%d\n", dc
->op1
, dc
->op2
));
970 cris_cc_mask(dc
, CC_MASK_NZ
);
971 gen_movl_T0_reg
[dc
->op2
]();
972 gen_op_movl_T1_im(dc
->op1
);
973 crisv32_alu_op(dc
, CC_OP_BTST
, dc
->op2
, 4);
975 cris_update_cc_op(dc
, CC_OP_FLAGS
);
976 gen_op_movl_flags_T0();
980 static unsigned int dec_asrq(DisasContext
*dc
)
982 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
983 DIS(fprintf (logfile
, "asrq %u, $r%d\n", dc
->op1
, dc
->op2
));
984 cris_cc_mask(dc
, CC_MASK_NZ
);
985 gen_movl_T0_reg
[dc
->op2
]();
986 gen_op_movl_T1_im(dc
->op1
);
987 crisv32_alu_op(dc
, CC_OP_ASR
, dc
->op2
, 4);
990 static unsigned int dec_lslq(DisasContext
*dc
)
992 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
993 DIS(fprintf (logfile
, "lslq %u, $r%d\n", dc
->op1
, dc
->op2
));
995 cris_cc_mask(dc
, CC_MASK_NZ
);
996 gen_movl_T0_reg
[dc
->op2
]();
997 gen_op_movl_T1_im(dc
->op1
);
998 crisv32_alu_op(dc
, CC_OP_LSL
, dc
->op2
, 4);
1001 static unsigned int dec_lsrq(DisasContext
*dc
)
1003 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1004 DIS(fprintf (logfile
, "lsrq %u, $r%d\n", dc
->op1
, dc
->op2
));
1006 cris_cc_mask(dc
, CC_MASK_NZ
);
1007 gen_movl_T0_reg
[dc
->op2
]();
1008 gen_op_movl_T1_im(dc
->op1
);
1009 crisv32_alu_op(dc
, CC_OP_LSR
, dc
->op2
, 4);
1013 static unsigned int dec_move_r(DisasContext
*dc
)
1015 int size
= memsize_zz(dc
);
1017 DIS(fprintf (logfile
, "move.%c $r%u, $r%u\n",
1018 memsize_char(size
), dc
->op1
, dc
->op2
));
1020 cris_cc_mask(dc
, CC_MASK_NZ
);
1021 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1022 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, size
);
1026 static unsigned int dec_scc_r(DisasContext
*dc
)
1030 DIS(fprintf (logfile
, "s%s $r%u\n",
1031 cc_name(cond
), dc
->op1
));
1035 gen_tst_cc (dc
, cond
);
1036 gen_op_movl_T1_T0();
1039 gen_op_movl_T1_im(1);
1041 cris_cc_mask(dc
, 0);
1042 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, 4);
1046 static unsigned int dec_and_r(DisasContext
*dc
)
1048 int size
= memsize_zz(dc
);
1050 DIS(fprintf (logfile
, "and.%c $r%u, $r%u\n",
1051 memsize_char(size
), dc
->op1
, dc
->op2
));
1052 cris_cc_mask(dc
, CC_MASK_NZ
);
1053 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1054 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, size
);
1058 static unsigned int dec_lz_r(DisasContext
*dc
)
1060 DIS(fprintf (logfile
, "lz $r%u, $r%u\n",
1062 cris_cc_mask(dc
, CC_MASK_NZ
);
1063 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1064 crisv32_alu_op(dc
, CC_OP_LZ
, dc
->op2
, 4);
1068 static unsigned int dec_lsl_r(DisasContext
*dc
)
1070 int size
= memsize_zz(dc
);
1072 DIS(fprintf (logfile
, "lsl.%c $r%u, $r%u\n",
1073 memsize_char(size
), dc
->op1
, dc
->op2
));
1074 cris_cc_mask(dc
, CC_MASK_NZ
);
1075 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1076 gen_op_andl_T1_im(63);
1077 crisv32_alu_op(dc
, CC_OP_LSL
, dc
->op2
, size
);
1081 static unsigned int dec_lsr_r(DisasContext
*dc
)
1083 int size
= memsize_zz(dc
);
1085 DIS(fprintf (logfile
, "lsr.%c $r%u, $r%u\n",
1086 memsize_char(size
), dc
->op1
, dc
->op2
));
1087 cris_cc_mask(dc
, CC_MASK_NZ
);
1088 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1089 gen_op_andl_T1_im(63);
1090 crisv32_alu_op(dc
, CC_OP_LSR
, dc
->op2
, size
);
1094 static unsigned int dec_asr_r(DisasContext
*dc
)
1096 int size
= memsize_zz(dc
);
1098 DIS(fprintf (logfile
, "asr.%c $r%u, $r%u\n",
1099 memsize_char(size
), dc
->op1
, dc
->op2
));
1100 cris_cc_mask(dc
, CC_MASK_NZ
);
1101 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1);
1102 gen_op_andl_T1_im(63);
1103 crisv32_alu_op(dc
, CC_OP_ASR
, dc
->op2
, size
);
1107 static unsigned int dec_muls_r(DisasContext
*dc
)
1109 int size
= memsize_zz(dc
);
1111 DIS(fprintf (logfile
, "muls.%c $r%u, $r%u\n",
1112 memsize_char(size
), dc
->op1
, dc
->op2
));
1113 cris_cc_mask(dc
, CC_MASK_NZV
);
1114 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1);
1115 gen_sext_T0_T0(size
);
1116 crisv32_alu_op(dc
, CC_OP_MULS
, dc
->op2
, 4);
1120 static unsigned int dec_mulu_r(DisasContext
*dc
)
1122 int size
= memsize_zz(dc
);
1124 DIS(fprintf (logfile
, "mulu.%c $r%u, $r%u\n",
1125 memsize_char(size
), dc
->op1
, dc
->op2
));
1126 cris_cc_mask(dc
, CC_MASK_NZV
);
1127 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1128 gen_zext_T0_T0(size
);
1129 crisv32_alu_op(dc
, CC_OP_MULU
, dc
->op2
, 4);
1134 static unsigned int dec_dstep_r(DisasContext
*dc
)
1136 DIS(fprintf (logfile
, "dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
));
1137 cris_cc_mask(dc
, CC_MASK_NZ
);
1138 gen_movl_T0_reg
[dc
->op1
]();
1139 gen_op_movl_T1_T0();
1140 gen_movl_T0_reg
[dc
->op2
]();
1141 crisv32_alu_op(dc
, CC_OP_DSTEP
, dc
->op2
, 4);
1145 static unsigned int dec_xor_r(DisasContext
*dc
)
1147 int size
= memsize_zz(dc
);
1148 DIS(fprintf (logfile
, "xor.%c $r%u, $r%u\n",
1149 memsize_char(size
), dc
->op1
, dc
->op2
));
1150 BUG_ON(size
!= 4); /* xor is dword. */
1151 cris_cc_mask(dc
, CC_MASK_NZ
);
1152 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1153 crisv32_alu_op(dc
, CC_OP_XOR
, dc
->op2
, 4);
1157 static unsigned int dec_bound_r(DisasContext
*dc
)
1159 int size
= memsize_zz(dc
);
1160 DIS(fprintf (logfile
, "bound.%c $r%u, $r%u\n",
1161 memsize_char(size
), dc
->op1
, dc
->op2
));
1162 cris_cc_mask(dc
, CC_MASK_NZ
);
1163 /* TODO: needs optmimization. */
1164 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1165 /* rd should be 4. */
1166 gen_movl_T0_reg
[dc
->op2
]();
1167 crisv32_alu_op(dc
, CC_OP_BOUND
, dc
->op2
, 4);
1171 static unsigned int dec_cmp_r(DisasContext
*dc
)
1173 int size
= memsize_zz(dc
);
1174 DIS(fprintf (logfile
, "cmp.%c $r%u, $r%u\n",
1175 memsize_char(size
), dc
->op1
, dc
->op2
));
1176 cris_cc_mask(dc
, CC_MASK_NZVC
);
1177 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1178 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, size
);
1182 static unsigned int dec_abs_r(DisasContext
*dc
)
1184 DIS(fprintf (logfile
, "abs $r%u, $r%u\n",
1186 cris_cc_mask(dc
, CC_MASK_NZ
);
1187 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1188 gen_op_absl_T1_T1();
1189 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1193 static unsigned int dec_add_r(DisasContext
*dc
)
1195 int size
= memsize_zz(dc
);
1196 DIS(fprintf (logfile
, "add.%c $r%u, $r%u\n",
1197 memsize_char(size
), dc
->op1
, dc
->op2
));
1198 cris_cc_mask(dc
, CC_MASK_NZVC
);
1199 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1200 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, size
);
1204 static unsigned int dec_addc_r(DisasContext
*dc
)
1206 DIS(fprintf (logfile
, "addc $r%u, $r%u\n",
1208 cris_evaluate_flags(dc
);
1209 cris_cc_mask(dc
, CC_MASK_NZVC
);
1210 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1211 crisv32_alu_op(dc
, CC_OP_ADDC
, dc
->op2
, 4);
1215 static unsigned int dec_mcp_r(DisasContext
*dc
)
1217 DIS(fprintf (logfile
, "mcp $p%u, $r%u\n",
1219 cris_evaluate_flags(dc
);
1220 cris_cc_mask(dc
, CC_MASK_RNZV
);
1221 gen_movl_T0_preg
[dc
->op2
]();
1222 gen_op_movl_T1_T0();
1223 gen_movl_T0_reg
[dc
->op1
]();
1224 crisv32_alu_op(dc
, CC_OP_MCP
, dc
->op1
, 4);
1229 static char * swapmode_name(int mode
, char *modename
) {
1232 modename
[i
++] = 'n';
1234 modename
[i
++] = 'w';
1236 modename
[i
++] = 'b';
1238 modename
[i
++] = 'r';
1244 static unsigned int dec_swap_r(DisasContext
*dc
)
1246 DIS(char modename
[4]);
1247 DIS(fprintf (logfile
, "swap%s $r%u\n",
1248 swapmode_name(dc
->op2
, modename
), dc
->op1
));
1250 cris_cc_mask(dc
, CC_MASK_NZ
);
1251 gen_movl_T0_reg
[dc
->op1
]();
1255 gen_op_swapw_T0_T0();
1257 gen_op_swapb_T0_T0();
1259 gen_op_swapr_T0_T0();
1260 gen_op_movl_T1_T0();
1261 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, 4);
1265 static unsigned int dec_or_r(DisasContext
*dc
)
1267 int size
= memsize_zz(dc
);
1268 DIS(fprintf (logfile
, "or.%c $r%u, $r%u\n",
1269 memsize_char(size
), dc
->op1
, dc
->op2
));
1270 cris_cc_mask(dc
, CC_MASK_NZ
);
1271 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1272 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, size
);
1276 static unsigned int dec_addi_r(DisasContext
*dc
)
1278 DIS(fprintf (logfile
, "addi.%c $r%u, $r%u\n",
1279 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
));
1280 cris_cc_mask(dc
, 0);
1281 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1282 gen_op_lsll_T0_im(dc
->zzsize
);
1283 gen_op_addl_T0_T1();
1284 gen_movl_reg_T0
[dc
->op1
]();
1288 static unsigned int dec_addi_acr(DisasContext
*dc
)
1290 DIS(fprintf (logfile
, "addi.%c $r%u, $r%u, $acr\n",
1291 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
));
1292 cris_cc_mask(dc
, 0);
1293 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1294 gen_op_lsll_T0_im(dc
->zzsize
);
1295 gen_op_addl_T0_T1();
1296 gen_movl_reg_T0
[REG_ACR
]();
1300 static unsigned int dec_neg_r(DisasContext
*dc
)
1302 int size
= memsize_zz(dc
);
1303 DIS(fprintf (logfile
, "neg.%c $r%u, $r%u\n",
1304 memsize_char(size
), dc
->op1
, dc
->op2
));
1305 cris_cc_mask(dc
, CC_MASK_NZVC
);
1306 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1307 crisv32_alu_op(dc
, CC_OP_NEG
, dc
->op2
, size
);
1311 static unsigned int dec_btst_r(DisasContext
*dc
)
1313 DIS(fprintf (logfile
, "btst $r%u, $r%u\n",
1315 cris_cc_mask(dc
, CC_MASK_NZ
);
1316 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1317 crisv32_alu_op(dc
, CC_OP_BTST
, dc
->op2
, 4);
1319 cris_update_cc_op(dc
, CC_OP_FLAGS
);
1320 gen_op_movl_flags_T0();
1325 static unsigned int dec_sub_r(DisasContext
*dc
)
1327 int size
= memsize_zz(dc
);
1328 DIS(fprintf (logfile
, "sub.%c $r%u, $r%u\n",
1329 memsize_char(size
), dc
->op1
, dc
->op2
));
1330 cris_cc_mask(dc
, CC_MASK_NZVC
);
1331 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1332 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, size
);
1336 /* Zero extension. From size to dword. */
1337 static unsigned int dec_movu_r(DisasContext
*dc
)
1339 int size
= memsize_z(dc
);
1340 DIS(fprintf (logfile
, "movu.%c $r%u, $r%u\n",
1344 cris_cc_mask(dc
, CC_MASK_NZ
);
1345 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1346 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1350 /* Sign extension. From size to dword. */
1351 static unsigned int dec_movs_r(DisasContext
*dc
)
1353 int size
= memsize_z(dc
);
1354 DIS(fprintf (logfile
, "movs.%c $r%u, $r%u\n",
1358 cris_cc_mask(dc
, CC_MASK_NZ
);
1359 gen_movl_T0_reg
[dc
->op1
]();
1360 /* Size can only be qi or hi. */
1361 gen_sext_T1_T0(size
);
1362 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1366 /* zero extension. From size to dword. */
1367 static unsigned int dec_addu_r(DisasContext
*dc
)
1369 int size
= memsize_z(dc
);
1370 DIS(fprintf (logfile
, "addu.%c $r%u, $r%u\n",
1374 cris_cc_mask(dc
, CC_MASK_NZVC
);
1375 gen_movl_T0_reg
[dc
->op1
]();
1376 /* Size can only be qi or hi. */
1377 gen_zext_T1_T0(size
);
1378 gen_movl_T0_reg
[dc
->op2
]();
1379 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1382 /* Sign extension. From size to dword. */
1383 static unsigned int dec_adds_r(DisasContext
*dc
)
1385 int size
= memsize_z(dc
);
1386 DIS(fprintf (logfile
, "adds.%c $r%u, $r%u\n",
1390 cris_cc_mask(dc
, CC_MASK_NZVC
);
1391 gen_movl_T0_reg
[dc
->op1
]();
1392 /* Size can only be qi or hi. */
1393 gen_sext_T1_T0(size
);
1394 gen_movl_T0_reg
[dc
->op2
]();
1395 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1399 /* Zero extension. From size to dword. */
1400 static unsigned int dec_subu_r(DisasContext
*dc
)
1402 int size
= memsize_z(dc
);
1403 DIS(fprintf (logfile
, "subu.%c $r%u, $r%u\n",
1407 cris_cc_mask(dc
, CC_MASK_NZVC
);
1408 gen_movl_T0_reg
[dc
->op1
]();
1409 /* Size can only be qi or hi. */
1410 gen_zext_T1_T0(size
);
1411 gen_movl_T0_reg
[dc
->op2
]();
1412 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1416 /* Sign extension. From size to dword. */
1417 static unsigned int dec_subs_r(DisasContext
*dc
)
1419 int size
= memsize_z(dc
);
1420 DIS(fprintf (logfile
, "subs.%c $r%u, $r%u\n",
1424 cris_cc_mask(dc
, CC_MASK_NZVC
);
1425 gen_movl_T0_reg
[dc
->op1
]();
1426 /* Size can only be qi or hi. */
1427 gen_sext_T1_T0(size
);
1428 gen_movl_T0_reg
[dc
->op2
]();
1429 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1433 static unsigned int dec_setclrf(DisasContext
*dc
)
1436 int set
= (~dc
->opcode
>> 2) & 1;
1438 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
1439 | EXTRACT_FIELD(dc
->ir
, 0, 3);
1440 DIS(fprintf (logfile
, "set=%d flags=%x\n", set
, flags
));
1441 if (set
&& flags
== 0)
1442 DIS(fprintf (logfile
, "nop\n"));
1443 else if (!set
&& (flags
& 0x20))
1444 DIS(fprintf (logfile
, "di\n"));
1446 DIS(fprintf (logfile
, "%sf %x\n",
1447 set
? "set" : "clr",
1450 if (set
&& (flags
& X_FLAG
)) {
1455 /* Simply decode the flags. */
1456 cris_evaluate_flags (dc
);
1457 cris_update_cc_op(dc
, CC_OP_FLAGS
);
1459 gen_op_setf (flags
);
1461 gen_op_clrf (flags
);
1466 static unsigned int dec_move_rs(DisasContext
*dc
)
1468 DIS(fprintf (logfile
, "move $r%u, $s%u\n", dc
->op1
, dc
->op2
));
1469 cris_cc_mask(dc
, 0);
1470 gen_movl_T0_reg
[dc
->op1
]();
1471 gen_op_movl_sreg_T0(dc
->op2
);
1473 if (dc
->op2
== 5) /* srs is checked at runtime. */
1474 gen_op_movl_tlb_lo_T0();
1477 static unsigned int dec_move_sr(DisasContext
*dc
)
1479 DIS(fprintf (logfile
, "move $s%u, $r%u\n", dc
->op1
, dc
->op2
));
1480 cris_cc_mask(dc
, 0);
1481 gen_op_movl_T0_sreg(dc
->op1
);
1482 gen_op_movl_T1_T0();
1483 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1486 static unsigned int dec_move_rp(DisasContext
*dc
)
1488 DIS(fprintf (logfile
, "move $r%u, $p%u\n", dc
->op1
, dc
->op2
));
1489 cris_cc_mask(dc
, 0);
1490 gen_movl_T0_reg
[dc
->op1
]();
1491 gen_op_movl_T1_T0();
1492 gen_movl_preg_T0
[dc
->op2
]();
1495 static unsigned int dec_move_pr(DisasContext
*dc
)
1497 DIS(fprintf (logfile
, "move $p%u, $r%u\n", dc
->op1
, dc
->op2
));
1498 cris_cc_mask(dc
, 0);
1499 /* Support register 0 is hardwired to zero.
1500 Treat it specially. */
1502 gen_op_movl_T1_im(0);
1504 gen_movl_T0_preg
[dc
->op2
]();
1505 gen_op_movl_T1_T0();
1507 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, preg_sizes
[dc
->op2
]);
1511 static unsigned int dec_move_mr(DisasContext
*dc
)
1513 int memsize
= memsize_zz(dc
);
1515 DIS(fprintf (logfile
, "move.%c [$r%u%s, $r%u\n",
1516 memsize_char(memsize
),
1517 dc
->op1
, dc
->postinc
? "+]" : "]",
1520 cris_cc_mask(dc
, CC_MASK_NZ
);
1521 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1522 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, memsize
);
1523 do_postinc(dc
, memsize
);
1527 static unsigned int dec_movs_m(DisasContext
*dc
)
1529 int memsize
= memsize_z(dc
);
1531 DIS(fprintf (logfile
, "movs.%c [$r%u%s, $r%u\n",
1532 memsize_char(memsize
),
1533 dc
->op1
, dc
->postinc
? "+]" : "]",
1537 cris_cc_mask(dc
, CC_MASK_NZ
);
1538 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1539 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1540 do_postinc(dc
, memsize
);
1544 static unsigned int dec_addu_m(DisasContext
*dc
)
1546 int memsize
= memsize_z(dc
);
1548 DIS(fprintf (logfile
, "addu.%c [$r%u%s, $r%u\n",
1549 memsize_char(memsize
),
1550 dc
->op1
, dc
->postinc
? "+]" : "]",
1554 cris_cc_mask(dc
, CC_MASK_NZVC
);
1555 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1556 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1557 do_postinc(dc
, memsize
);
1561 static unsigned int dec_adds_m(DisasContext
*dc
)
1563 int memsize
= memsize_z(dc
);
1565 DIS(fprintf (logfile
, "adds.%c [$r%u%s, $r%u\n",
1566 memsize_char(memsize
),
1567 dc
->op1
, dc
->postinc
? "+]" : "]",
1571 cris_cc_mask(dc
, CC_MASK_NZVC
);
1572 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1573 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1574 do_postinc(dc
, memsize
);
1578 static unsigned int dec_subu_m(DisasContext
*dc
)
1580 int memsize
= memsize_z(dc
);
1582 DIS(fprintf (logfile
, "subu.%c [$r%u%s, $r%u\n",
1583 memsize_char(memsize
),
1584 dc
->op1
, dc
->postinc
? "+]" : "]",
1588 cris_cc_mask(dc
, CC_MASK_NZVC
);
1589 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1590 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1591 do_postinc(dc
, memsize
);
1595 static unsigned int dec_subs_m(DisasContext
*dc
)
1597 int memsize
= memsize_z(dc
);
1599 DIS(fprintf (logfile
, "subs.%c [$r%u%s, $r%u\n",
1600 memsize_char(memsize
),
1601 dc
->op1
, dc
->postinc
? "+]" : "]",
1605 cris_cc_mask(dc
, CC_MASK_NZVC
);
1606 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1607 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1608 do_postinc(dc
, memsize
);
1612 static unsigned int dec_movu_m(DisasContext
*dc
)
1614 int memsize
= memsize_z(dc
);
1617 DIS(fprintf (logfile
, "movu.%c [$r%u%s, $r%u\n",
1618 memsize_char(memsize
),
1619 dc
->op1
, dc
->postinc
? "+]" : "]",
1622 cris_cc_mask(dc
, CC_MASK_NZ
);
1623 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1624 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1625 do_postinc(dc
, memsize
);
1629 static unsigned int dec_cmpu_m(DisasContext
*dc
)
1631 int memsize
= memsize_z(dc
);
1633 DIS(fprintf (logfile
, "cmpu.%c [$r%u%s, $r%u\n",
1634 memsize_char(memsize
),
1635 dc
->op1
, dc
->postinc
? "+]" : "]",
1638 cris_cc_mask(dc
, CC_MASK_NZVC
);
1639 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1640 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, 4);
1641 do_postinc(dc
, memsize
);
1645 static unsigned int dec_cmps_m(DisasContext
*dc
)
1647 int memsize
= memsize_z(dc
);
1649 DIS(fprintf (logfile
, "cmps.%c [$r%u%s, $r%u\n",
1650 memsize_char(memsize
),
1651 dc
->op1
, dc
->postinc
? "+]" : "]",
1654 cris_cc_mask(dc
, CC_MASK_NZVC
);
1655 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1656 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
1657 do_postinc(dc
, memsize
);
1661 static unsigned int dec_cmp_m(DisasContext
*dc
)
1663 int memsize
= memsize_zz(dc
);
1665 DIS(fprintf (logfile
, "cmp.%c [$r%u%s, $r%u\n",
1666 memsize_char(memsize
),
1667 dc
->op1
, dc
->postinc
? "+]" : "]",
1670 cris_cc_mask(dc
, CC_MASK_NZVC
);
1671 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1672 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
1673 do_postinc(dc
, memsize
);
1677 static unsigned int dec_test_m(DisasContext
*dc
)
1679 int memsize
= memsize_zz(dc
);
1681 DIS(fprintf (logfile
, "test.%d [$r%u%s] op2=%x\n",
1682 memsize_char(memsize
),
1683 dc
->op1
, dc
->postinc
? "+]" : "]",
1686 cris_cc_mask(dc
, CC_MASK_NZ
);
1688 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1690 gen_op_movl_T1_im(0);
1691 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
1692 do_postinc(dc
, memsize
);
1696 static unsigned int dec_and_m(DisasContext
*dc
)
1698 int memsize
= memsize_zz(dc
);
1700 DIS(fprintf (logfile
, "and.%d [$r%u%s, $r%u\n",
1701 memsize_char(memsize
),
1702 dc
->op1
, dc
->postinc
? "+]" : "]",
1705 cris_cc_mask(dc
, CC_MASK_NZ
);
1706 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1707 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, memsize_zz(dc
));
1708 do_postinc(dc
, memsize
);
1712 static unsigned int dec_add_m(DisasContext
*dc
)
1714 int memsize
= memsize_zz(dc
);
1716 DIS(fprintf (logfile
, "add.%d [$r%u%s, $r%u\n",
1717 memsize_char(memsize
),
1718 dc
->op1
, dc
->postinc
? "+]" : "]",
1721 cris_cc_mask(dc
, CC_MASK_NZVC
);
1722 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1723 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, memsize_zz(dc
));
1724 do_postinc(dc
, memsize
);
1728 static unsigned int dec_addo_m(DisasContext
*dc
)
1730 int memsize
= memsize_zz(dc
);
1732 DIS(fprintf (logfile
, "add.%d [$r%u%s, $r%u\n",
1733 memsize_char(memsize
),
1734 dc
->op1
, dc
->postinc
? "+]" : "]",
1737 cris_cc_mask(dc
, 0);
1738 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1739 crisv32_alu_op(dc
, CC_OP_ADD
, REG_ACR
, 4);
1740 do_postinc(dc
, memsize
);
1744 static unsigned int dec_bound_m(DisasContext
*dc
)
1746 int memsize
= memsize_zz(dc
);
1748 DIS(fprintf (logfile
, "bound.%d [$r%u%s, $r%u\n",
1749 memsize_char(memsize
),
1750 dc
->op1
, dc
->postinc
? "+]" : "]",
1753 cris_cc_mask(dc
, CC_MASK_NZ
);
1754 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1755 crisv32_alu_op(dc
, CC_OP_BOUND
, dc
->op2
, 4);
1756 do_postinc(dc
, memsize
);
1760 static unsigned int dec_addc_mr(DisasContext
*dc
)
1763 DIS(fprintf (logfile
, "addc [$r%u%s, $r%u\n",
1764 dc
->op1
, dc
->postinc
? "+]" : "]",
1767 cris_evaluate_flags(dc
);
1768 cris_cc_mask(dc
, CC_MASK_NZVC
);
1769 insn_len
= dec_prep_alu_m(dc
, 0, 4);
1770 crisv32_alu_op(dc
, CC_OP_ADDC
, dc
->op2
, 4);
1775 static unsigned int dec_sub_m(DisasContext
*dc
)
1777 int memsize
= memsize_zz(dc
);
1779 DIS(fprintf (logfile
, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
1780 memsize_char(memsize
),
1781 dc
->op1
, dc
->postinc
? "+]" : "]",
1782 dc
->op2
, dc
->ir
, dc
->zzsize
));
1784 cris_cc_mask(dc
, CC_MASK_NZVC
);
1785 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1786 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, memsize
);
1787 do_postinc(dc
, memsize
);
1791 static unsigned int dec_or_m(DisasContext
*dc
)
1793 int memsize
= memsize_zz(dc
);
1795 DIS(fprintf (logfile
, "or.%d [$r%u%s, $r%u pc=%x\n",
1796 memsize_char(memsize
),
1797 dc
->op1
, dc
->postinc
? "+]" : "]",
1800 cris_cc_mask(dc
, CC_MASK_NZ
);
1801 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1802 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, memsize_zz(dc
));
1803 do_postinc(dc
, memsize
);
1807 static unsigned int dec_move_mp(DisasContext
*dc
)
1809 int memsize
= memsize_zz(dc
);
1812 DIS(fprintf (logfile
, "move.%c [$r%u%s, $p%u\n",
1813 memsize_char(memsize
),
1815 dc
->postinc
? "+]" : "]",
1818 cris_cc_mask(dc
, 0);
1819 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1820 gen_op_movl_T0_T1();
1821 gen_movl_preg_T0
[dc
->op2
]();
1823 do_postinc(dc
, memsize
);
1827 static unsigned int dec_move_pm(DisasContext
*dc
)
1831 memsize
= preg_sizes
[dc
->op2
];
1833 DIS(fprintf (logfile
, "move.%c $p%u, [$r%u%s\n",
1834 memsize_char(memsize
),
1835 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]"));
1837 cris_cc_mask(dc
, 0);
1838 /* prepare store. Address in T0, value in T1. */
1839 /* Support register 0 is hardwired to zero.
1840 Treat it specially. */
1842 gen_op_movl_T1_im(0);
1845 gen_movl_T0_preg
[dc
->op2
]();
1846 gen_op_movl_T1_T0();
1848 gen_movl_T0_reg
[dc
->op1
]();
1849 gen_store_T0_T1(dc
, memsize
);
1852 gen_op_addl_T0_im(memsize
);
1853 gen_movl_reg_T0
[dc
->op1
]();
1858 static unsigned int dec_movem_mr(DisasContext
*dc
)
1862 DIS(fprintf (logfile
, "movem [$r%u%s, $r%u\n", dc
->op1
,
1863 dc
->postinc
? "+]" : "]", dc
->op2
));
1865 cris_cc_mask(dc
, 0);
1866 /* fetch the address into T1. */
1867 gen_movl_T0_reg
[dc
->op1
]();
1868 gen_op_movl_T1_T0();
1869 for (i
= 0; i
<= dc
->op2
; i
++) {
1870 /* Perform the load onto regnum i. Always dword wide. */
1871 gen_load_T0_T0(dc
, 4, 0);
1872 gen_movl_reg_T0
[i
]();
1873 /* Update the address. */
1874 gen_op_addl_T1_im(4);
1875 gen_op_movl_T0_T1();
1878 /* writeback the updated pointer value. */
1879 gen_movl_reg_T0
[dc
->op1
]();
1884 static unsigned int dec_movem_rm(DisasContext
*dc
)
1888 DIS(fprintf (logfile
, "movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
1889 dc
->postinc
? "+]" : "]"));
1891 cris_cc_mask(dc
, 0);
1892 for (i
= 0; i
<= dc
->op2
; i
++) {
1893 /* Fetch register i into T1. */
1894 gen_movl_T0_reg
[i
]();
1895 gen_op_movl_T1_T0();
1897 /* Fetch the address into T0. */
1898 gen_movl_T0_reg
[dc
->op1
]();
1900 gen_op_addl_T0_im(i
* 4);
1902 /* Perform the store. */
1903 gen_store_T0_T1(dc
, 4);
1906 /* Update the address. */
1907 gen_op_addl_T0_im(4);
1908 /* writeback the updated pointer value. */
1909 gen_movl_reg_T0
[dc
->op1
]();
1914 static unsigned int dec_move_rm(DisasContext
*dc
)
1918 memsize
= memsize_zz(dc
);
1920 DIS(fprintf (logfile
, "move.%d $r%u, [$r%u]\n",
1921 memsize
, dc
->op2
, dc
->op1
));
1923 cris_cc_mask(dc
, 0);
1924 /* prepare store. */
1925 gen_movl_T0_reg
[dc
->op2
]();
1926 gen_op_movl_T1_T0();
1927 gen_movl_T0_reg
[dc
->op1
]();
1928 gen_store_T0_T1(dc
, memsize
);
1931 gen_op_addl_T0_im(memsize
);
1932 gen_movl_reg_T0
[dc
->op1
]();
1938 static unsigned int dec_lapcq(DisasContext
*dc
)
1940 DIS(fprintf (logfile
, "lapcq %x, $r%u\n",
1941 dc
->pc
+ dc
->op1
*2, dc
->op2
));
1942 cris_cc_mask(dc
, 0);
1943 gen_op_movl_T1_im(dc
->pc
+ dc
->op1
*2);
1944 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1948 static unsigned int dec_lapc_im(DisasContext
*dc
)
1956 cris_cc_mask(dc
, 0);
1957 imm
= ldl_code(dc
->pc
+ 2);
1958 DIS(fprintf (logfile
, "lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
));
1959 gen_op_movl_T0_im (dc
->pc
+ imm
);
1960 gen_movl_reg_T0
[rd
] ();
1964 /* Jump to special reg. */
1965 static unsigned int dec_jump_p(DisasContext
*dc
)
1967 DIS(fprintf (logfile
, "jump $p%u\n", dc
->op2
));
1968 cris_cc_mask(dc
, 0);
1969 /* Store the return address in Pd. */
1970 gen_movl_T0_preg
[dc
->op2
]();
1971 gen_op_movl_btarget_T0();
1972 cris_prepare_dyn_jmp(dc
);
1976 /* Jump and save. */
1977 static unsigned int dec_jas_r(DisasContext
*dc
)
1979 DIS(fprintf (logfile
, "jas $r%u, $p%u\n", dc
->op1
, dc
->op2
));
1980 cris_cc_mask(dc
, 0);
1981 /* Stor the return address in Pd. */
1982 gen_movl_T0_reg
[dc
->op1
]();
1983 gen_op_movl_btarget_T0();
1984 gen_op_movl_T0_im(dc
->pc
+ 4);
1985 gen_movl_preg_T0
[dc
->op2
]();
1986 cris_prepare_dyn_jmp(dc
);
1990 static unsigned int dec_jas_im(DisasContext
*dc
)
1994 imm
= ldl_code(dc
->pc
+ 2);
1996 DIS(fprintf (logfile
, "jas 0x%x\n", imm
));
1997 cris_cc_mask(dc
, 0);
1998 /* Stor the return address in Pd. */
1999 gen_op_movl_T0_im(imm
);
2000 gen_op_movl_btarget_T0();
2001 gen_op_movl_T0_im(dc
->pc
+ 8);
2002 gen_movl_preg_T0
[dc
->op2
]();
2003 cris_prepare_dyn_jmp(dc
);
2007 static unsigned int dec_jasc_im(DisasContext
*dc
)
2011 imm
= ldl_code(dc
->pc
+ 2);
2013 DIS(fprintf (logfile
, "jasc 0x%x\n", imm
));
2014 cris_cc_mask(dc
, 0);
2015 /* Stor the return address in Pd. */
2016 gen_op_movl_T0_im(imm
);
2017 gen_op_movl_btarget_T0();
2018 gen_op_movl_T0_im(dc
->pc
+ 8 + 4);
2019 gen_movl_preg_T0
[dc
->op2
]();
2020 cris_prepare_dyn_jmp(dc
);
2024 static unsigned int dec_jasc_r(DisasContext
*dc
)
2026 DIS(fprintf (logfile
, "jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
));
2027 cris_cc_mask(dc
, 0);
2028 /* Stor the return address in Pd. */
2029 gen_movl_T0_reg
[dc
->op1
]();
2030 gen_op_movl_btarget_T0();
2031 gen_op_movl_T0_im(dc
->pc
+ 4 + 4);
2032 gen_movl_preg_T0
[dc
->op2
]();
2033 cris_prepare_dyn_jmp(dc
);
2037 static unsigned int dec_bcc_im(DisasContext
*dc
)
2040 uint32_t cond
= dc
->op2
;
2042 offset
= ldl_code(dc
->pc
+ 2);
2043 offset
= sign_extend(offset
, 15);
2045 DIS(fprintf (logfile
, "b%s %d pc=%x dst=%x\n",
2046 cc_name(cond
), offset
,
2047 dc
->pc
, dc
->pc
+ offset
));
2049 cris_cc_mask(dc
, 0);
2050 /* op2 holds the condition-code. */
2051 cris_prepare_cc_branch (dc
, offset
, cond
);
2055 static unsigned int dec_bas_im(DisasContext
*dc
)
2060 simm
= ldl_code(dc
->pc
+ 2);
2062 DIS(fprintf (logfile
, "bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
));
2063 cris_cc_mask(dc
, 0);
2064 /* Stor the return address in Pd. */
2065 gen_op_movl_T0_im(dc
->pc
+ simm
);
2066 gen_op_movl_btarget_T0();
2067 gen_op_movl_T0_im(dc
->pc
+ 8);
2068 gen_movl_preg_T0
[dc
->op2
]();
2069 cris_prepare_dyn_jmp(dc
);
2073 static unsigned int dec_basc_im(DisasContext
*dc
)
2076 simm
= ldl_code(dc
->pc
+ 2);
2078 DIS(fprintf (logfile
, "basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
));
2079 cris_cc_mask(dc
, 0);
2080 /* Stor the return address in Pd. */
2081 gen_op_movl_T0_im(dc
->pc
+ simm
);
2082 gen_op_movl_btarget_T0();
2083 gen_op_movl_T0_im(dc
->pc
+ 12);
2084 gen_movl_preg_T0
[dc
->op2
]();
2085 cris_prepare_dyn_jmp(dc
);
2089 static unsigned int dec_rfe_etc(DisasContext
*dc
)
2091 DIS(fprintf (logfile
, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2092 dc
->opcode
, dc
->pc
, dc
->op1
, dc
->op2
));
2094 cris_cc_mask(dc
, 0);
2096 if (dc
->op2
== 15) /* ignore halt. */
2099 switch (dc
->op2
& 7) {
2102 cris_evaluate_flags(dc
);
2103 gen_op_ccs_rshift();
2111 gen_op_movl_T0_im(dc
->pc
);
2112 gen_op_movl_pc_T0();
2113 /* Breaks start at 16 in the exception vector. */
2114 gen_op_break_im(dc
->op1
+ 16);
2117 printf ("op2=%x\n", dc
->op2
);
2126 static unsigned int dec_null(DisasContext
*dc
)
2128 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2129 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
2135 struct decoder_info
{
2140 unsigned int (*dec
)(DisasContext
*dc
);
2142 /* Order matters here. */
2143 {DEC_MOVEQ
, dec_moveq
},
2144 {DEC_BTSTQ
, dec_btstq
},
2145 {DEC_CMPQ
, dec_cmpq
},
2146 {DEC_ADDOQ
, dec_addoq
},
2147 {DEC_ADDQ
, dec_addq
},
2148 {DEC_SUBQ
, dec_subq
},
2149 {DEC_ANDQ
, dec_andq
},
2151 {DEC_ASRQ
, dec_asrq
},
2152 {DEC_LSLQ
, dec_lslq
},
2153 {DEC_LSRQ
, dec_lsrq
},
2154 {DEC_BCCQ
, dec_bccq
},
2156 {DEC_BCC_IM
, dec_bcc_im
},
2157 {DEC_JAS_IM
, dec_jas_im
},
2158 {DEC_JAS_R
, dec_jas_r
},
2159 {DEC_JASC_IM
, dec_jasc_im
},
2160 {DEC_JASC_R
, dec_jasc_r
},
2161 {DEC_BAS_IM
, dec_bas_im
},
2162 {DEC_BASC_IM
, dec_basc_im
},
2163 {DEC_JUMP_P
, dec_jump_p
},
2164 {DEC_LAPC_IM
, dec_lapc_im
},
2165 {DEC_LAPCQ
, dec_lapcq
},
2167 {DEC_RFE_ETC
, dec_rfe_etc
},
2168 {DEC_ADDC_MR
, dec_addc_mr
},
2170 {DEC_MOVE_MP
, dec_move_mp
},
2171 {DEC_MOVE_PM
, dec_move_pm
},
2172 {DEC_MOVEM_MR
, dec_movem_mr
},
2173 {DEC_MOVEM_RM
, dec_movem_rm
},
2174 {DEC_MOVE_PR
, dec_move_pr
},
2175 {DEC_SCC_R
, dec_scc_r
},
2176 {DEC_SETF
, dec_setclrf
},
2177 {DEC_CLEARF
, dec_setclrf
},
2179 {DEC_MOVE_SR
, dec_move_sr
},
2180 {DEC_MOVE_RP
, dec_move_rp
},
2181 {DEC_SWAP_R
, dec_swap_r
},
2182 {DEC_ABS_R
, dec_abs_r
},
2183 {DEC_LZ_R
, dec_lz_r
},
2184 {DEC_MOVE_RS
, dec_move_rs
},
2185 {DEC_BTST_R
, dec_btst_r
},
2186 {DEC_ADDC_R
, dec_addc_r
},
2188 {DEC_DSTEP_R
, dec_dstep_r
},
2189 {DEC_XOR_R
, dec_xor_r
},
2190 {DEC_MCP_R
, dec_mcp_r
},
2191 {DEC_CMP_R
, dec_cmp_r
},
2193 {DEC_ADDI_R
, dec_addi_r
},
2194 {DEC_ADDI_ACR
, dec_addi_acr
},
2196 {DEC_ADD_R
, dec_add_r
},
2197 {DEC_SUB_R
, dec_sub_r
},
2199 {DEC_ADDU_R
, dec_addu_r
},
2200 {DEC_ADDS_R
, dec_adds_r
},
2201 {DEC_SUBU_R
, dec_subu_r
},
2202 {DEC_SUBS_R
, dec_subs_r
},
2203 {DEC_LSL_R
, dec_lsl_r
},
2205 {DEC_AND_R
, dec_and_r
},
2206 {DEC_OR_R
, dec_or_r
},
2207 {DEC_BOUND_R
, dec_bound_r
},
2208 {DEC_ASR_R
, dec_asr_r
},
2209 {DEC_LSR_R
, dec_lsr_r
},
2211 {DEC_MOVU_R
, dec_movu_r
},
2212 {DEC_MOVS_R
, dec_movs_r
},
2213 {DEC_NEG_R
, dec_neg_r
},
2214 {DEC_MOVE_R
, dec_move_r
},
2216 /* ftag_fidx_i_m. */
2217 /* ftag_fidx_d_m. */
2219 {DEC_MULS_R
, dec_muls_r
},
2220 {DEC_MULU_R
, dec_mulu_r
},
2222 {DEC_ADDU_M
, dec_addu_m
},
2223 {DEC_ADDS_M
, dec_adds_m
},
2224 {DEC_SUBU_M
, dec_subu_m
},
2225 {DEC_SUBS_M
, dec_subs_m
},
2227 {DEC_CMPU_M
, dec_cmpu_m
},
2228 {DEC_CMPS_M
, dec_cmps_m
},
2229 {DEC_MOVU_M
, dec_movu_m
},
2230 {DEC_MOVS_M
, dec_movs_m
},
2232 {DEC_CMP_M
, dec_cmp_m
},
2233 {DEC_ADDO_M
, dec_addo_m
},
2234 {DEC_BOUND_M
, dec_bound_m
},
2235 {DEC_ADD_M
, dec_add_m
},
2236 {DEC_SUB_M
, dec_sub_m
},
2237 {DEC_AND_M
, dec_and_m
},
2238 {DEC_OR_M
, dec_or_m
},
2239 {DEC_MOVE_RM
, dec_move_rm
},
2240 {DEC_TEST_M
, dec_test_m
},
2241 {DEC_MOVE_MR
, dec_move_mr
},
2246 static inline unsigned int
2247 cris_decoder(DisasContext
*dc
)
2249 unsigned int insn_len
= 2;
2253 /* Load a halfword onto the instruction register. */
2254 tmp
= ldl_code(dc
->pc
);
2255 dc
->ir
= tmp
& 0xffff;
2257 /* Now decode it. */
2258 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
2259 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
2260 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
2261 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
2262 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
2263 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
2265 /* Large switch for all insns. */
2266 for (i
= 0; i
< sizeof decinfo
/ sizeof decinfo
[0]; i
++) {
2267 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
)
2269 insn_len
= decinfo
[i
].dec(dc
);
2277 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
2280 if (env
->nb_breakpoints
> 0) {
2281 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
2282 if (env
->breakpoints
[j
] == dc
->pc
) {
2283 cris_evaluate_flags (dc
);
2284 gen_op_movl_T0_im((long)dc
->pc
);
2285 gen_op_movl_pc_T0();
2287 dc
->is_jmp
= DISAS_UPDATE
;
2294 /* generate intermediate code for basic block 'tb'. */
2295 struct DisasContext ctx
;
2297 gen_intermediate_code_internal(CPUState
*env
, TranslationBlock
*tb
,
2300 uint16_t *gen_opc_end
;
2302 unsigned int insn_len
;
2304 struct DisasContext
*dc
= &ctx
;
2305 uint32_t next_page_start
;
2311 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2313 dc
->is_jmp
= DISAS_NEXT
;
2315 dc
->singlestep_enabled
= env
->singlestep_enabled
;
2318 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2322 check_breakpoint(env
, dc
);
2323 if (dc
->is_jmp
== DISAS_JUMP
)
2327 j
= gen_opc_ptr
- gen_opc_buf
;
2331 gen_opc_instr_start
[lj
++] = 0;
2333 gen_opc_pc
[lj
] = dc
->pc
;
2334 gen_opc_instr_start
[lj
] = 1;
2337 insn_len
= cris_decoder(dc
);
2338 STATS(gen_op_exec_insn());
2341 || (dc
->flagx_live
&&
2342 !(dc
->cc_op
== CC_OP_FLAGS
&& dc
->flags_x
))) {
2343 gen_movl_T0_preg
[SR_CCS
]();
2344 gen_op_andl_T0_im(~X_FLAG
);
2345 gen_movl_preg_T0
[SR_CCS
]();
2350 /* Check for delayed branches here. If we do it before
2351 actually genereating any host code, the simulator will just
2352 loop doing nothing for on this program location. */
2353 if (dc
->delayed_branch
) {
2354 dc
->delayed_branch
--;
2355 if (dc
->delayed_branch
== 0)
2357 if (dc
->bcc
== CC_A
) {
2359 dc
->is_jmp
= DISAS_UPDATE
;
2362 /* Conditional jmp. */
2363 gen_op_cc_jmp (dc
->delayed_pc
, dc
->pc
);
2364 dc
->is_jmp
= DISAS_UPDATE
;
2369 if (env
->singlestep_enabled
)
2371 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
2372 && dc
->pc
< next_page_start
);
2375 gen_op_movl_T0_im((long)dc
->pc
);
2376 gen_op_movl_pc_T0();
2379 cris_evaluate_flags (dc
);
2381 if (__builtin_expect(env
->singlestep_enabled
, 0)) {
2384 switch(dc
->is_jmp
) {
2386 gen_goto_tb(dc
, 1, dc
->pc
);
2391 /* indicate that the hash table must be used
2392 to find the next TB */
2396 /* nothing more to generate */
2400 *gen_opc_ptr
= INDEX_op_end
;
2402 j
= gen_opc_ptr
- gen_opc_buf
;
2405 gen_opc_instr_start
[lj
++] = 0;
2407 tb
->size
= dc
->pc
- pc_start
;
2411 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2412 fprintf(logfile
, "--------------\n");
2413 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2414 target_disas(logfile
, pc_start
, dc
->pc
+ 4 - pc_start
, 0);
2415 fprintf(logfile
, "\n");
2421 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2423 return gen_intermediate_code_internal(env
, tb
, 0);
2426 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2428 return gen_intermediate_code_internal(env
, tb
, 1);
2431 void cpu_dump_state (CPUState
*env
, FILE *f
,
2432 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
2441 cpu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2442 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2444 env
->pc
, env
->pregs
[SR_CCS
], env
->btaken
, env
->btarget
,
2446 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
,
2447 env
->debug1
, env
->debug2
, env
->debug3
);
2449 for (i
= 0; i
< 16; i
++) {
2450 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
2451 if ((i
+ 1) % 4 == 0)
2452 cpu_fprintf(f
, "\n");
2454 cpu_fprintf(f
, "\nspecial regs:\n");
2455 for (i
= 0; i
< 16; i
++) {
2456 cpu_fprintf(f
, "p%2.2d=%8.8x ", i
, env
->pregs
[i
]);
2457 if ((i
+ 1) % 4 == 0)
2458 cpu_fprintf(f
, "\n");
2460 srs
= env
->pregs
[SR_SRS
];
2461 cpu_fprintf(f
, "\nsupport function regs bank %d:\n", srs
);
2463 for (i
= 0; i
< 16; i
++) {
2464 cpu_fprintf(f
, "s%2.2d=%8.8x ",
2465 i
, env
->sregs
[srs
][i
]);
2466 if ((i
+ 1) % 4 == 0)
2467 cpu_fprintf(f
, "\n");
2470 cpu_fprintf(f
, "\n\n");
2474 CPUCRISState
*cpu_cris_init (const char *cpu_model
)
2478 env
= qemu_mallocz(sizeof(CPUCRISState
));
2486 void cpu_reset (CPUCRISState
*env
)
2488 memset(env
, 0, offsetof(CPUCRISState
, breakpoints
));