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1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "cpu.h"
27 #include "disas/disas.h"
28 #include "tcg-op.h"
29 #include "exec/helper-proto.h"
30 #include "mmu.h"
31 #include "crisv32-decode.h"
32
33 #include "exec/helper-gen.h"
34
35 #define DISAS_CRIS 0
36 #if DISAS_CRIS
37 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
38 #else
39 # define LOG_DIS(...) do { } while (0)
40 #endif
41
42 #define D(x)
43 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
44 #define BUG_ON(x) ({if (x) BUG();})
45
46 #define DISAS_SWI 5
47
48 /* Used by the decoder. */
49 #define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52 #define CC_MASK_NZ 0xc
53 #define CC_MASK_NZV 0xe
54 #define CC_MASK_NZVC 0xf
55 #define CC_MASK_RNZV 0x10e
56
57 static TCGv_ptr cpu_env;
58 static TCGv cpu_R[16];
59 static TCGv cpu_PR[16];
60 static TCGv cc_x;
61 static TCGv cc_src;
62 static TCGv cc_dest;
63 static TCGv cc_result;
64 static TCGv cc_op;
65 static TCGv cc_size;
66 static TCGv cc_mask;
67
68 static TCGv env_btaken;
69 static TCGv env_btarget;
70 static TCGv env_pc;
71
72 #include "exec/gen-icount.h"
73
74 /* This is the state at translation time. */
75 typedef struct DisasContext {
76 CRISCPU *cpu;
77 target_ulong pc, ppc;
78
79 /* Decoder. */
80 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
81 uint32_t ir;
82 uint32_t opcode;
83 unsigned int op1;
84 unsigned int op2;
85 unsigned int zsize, zzsize;
86 unsigned int mode;
87 unsigned int postinc;
88
89 unsigned int size;
90 unsigned int src;
91 unsigned int dst;
92 unsigned int cond;
93
94 int update_cc;
95 int cc_op;
96 int cc_size;
97 uint32_t cc_mask;
98
99 int cc_size_uptodate; /* -1 invalid or last written value. */
100
101 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
102 int flags_uptodate; /* Wether or not $ccs is uptodate. */
103 int flagx_known; /* Wether or not flags_x has the x flag known at
104 translation time. */
105 int flags_x;
106
107 int clear_x; /* Clear x after this insn? */
108 int clear_prefix; /* Clear prefix after this insn? */
109 int clear_locked_irq; /* Clear the irq lockout. */
110 int cpustate_changed;
111 unsigned int tb_flags; /* tb dependent flags. */
112 int is_jmp;
113
114 #define JMP_NOJMP 0
115 #define JMP_DIRECT 1
116 #define JMP_DIRECT_CC 2
117 #define JMP_INDIRECT 3
118 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
119 uint32_t jmp_pc;
120
121 int delayed_branch;
122
123 struct TranslationBlock *tb;
124 int singlestep_enabled;
125 } DisasContext;
126
127 static void gen_BUG(DisasContext *dc, const char *file, int line)
128 {
129 printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
130 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
131 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
132 }
133
134 static const char *regnames[] =
135 {
136 "$r0", "$r1", "$r2", "$r3",
137 "$r4", "$r5", "$r6", "$r7",
138 "$r8", "$r9", "$r10", "$r11",
139 "$r12", "$r13", "$sp", "$acr",
140 };
141 static const char *pregnames[] =
142 {
143 "$bz", "$vr", "$pid", "$srs",
144 "$wz", "$exs", "$eda", "$mof",
145 "$dz", "$ebp", "$erp", "$srp",
146 "$nrp", "$ccs", "$usp", "$spc",
147 };
148
149 /* We need this table to handle preg-moves with implicit width. */
150 static int preg_sizes[] = {
151 1, /* bz. */
152 1, /* vr. */
153 4, /* pid. */
154 1, /* srs. */
155 2, /* wz. */
156 4, 4, 4,
157 4, 4, 4, 4,
158 4, 4, 4, 4,
159 };
160
161 #define t_gen_mov_TN_env(tn, member) \
162 _t_gen_mov_TN_env((tn), offsetof(CPUCRISState, member))
163 #define t_gen_mov_env_TN(member, tn) \
164 _t_gen_mov_env_TN(offsetof(CPUCRISState, member), (tn))
165
166 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
167 {
168 if (r < 0 || r > 15) {
169 fprintf(stderr, "wrong register read $r%d\n", r);
170 }
171 tcg_gen_mov_tl(tn, cpu_R[r]);
172 }
173 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
174 {
175 if (r < 0 || r > 15) {
176 fprintf(stderr, "wrong register write $r%d\n", r);
177 }
178 tcg_gen_mov_tl(cpu_R[r], tn);
179 }
180
181 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
182 {
183 if (offset > sizeof(CPUCRISState)) {
184 fprintf(stderr, "wrong load from env from off=%d\n", offset);
185 }
186 tcg_gen_ld_tl(tn, cpu_env, offset);
187 }
188 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
189 {
190 if (offset > sizeof(CPUCRISState)) {
191 fprintf(stderr, "wrong store to env at off=%d\n", offset);
192 }
193 tcg_gen_st_tl(tn, cpu_env, offset);
194 }
195
196 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
197 {
198 if (r < 0 || r > 15) {
199 fprintf(stderr, "wrong register read $p%d\n", r);
200 }
201 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
202 tcg_gen_mov_tl(tn, tcg_const_tl(0));
203 } else if (r == PR_VR) {
204 tcg_gen_mov_tl(tn, tcg_const_tl(32));
205 } else {
206 tcg_gen_mov_tl(tn, cpu_PR[r]);
207 }
208 }
209 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
210 {
211 if (r < 0 || r > 15) {
212 fprintf(stderr, "wrong register write $p%d\n", r);
213 }
214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
215 return;
216 } else if (r == PR_SRS) {
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
218 } else {
219 if (r == PR_PID) {
220 gen_helper_tlb_flush_pid(cpu_env, tn);
221 }
222 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
223 gen_helper_spc_write(cpu_env, tn);
224 } else if (r == PR_CCS) {
225 dc->cpustate_changed = 1;
226 }
227 tcg_gen_mov_tl(cpu_PR[r], tn);
228 }
229 }
230
231 /* Sign extend at translation time. */
232 static int sign_extend(unsigned int val, unsigned int width)
233 {
234 int sval;
235
236 /* LSL. */
237 val <<= 31 - width;
238 sval = val;
239 /* ASR. */
240 sval >>= 31 - width;
241 return sval;
242 }
243
244 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
245 unsigned int size, unsigned int sign)
246 {
247 int r;
248
249 switch (size) {
250 case 4:
251 {
252 r = cpu_ldl_code(env, addr);
253 break;
254 }
255 case 2:
256 {
257 if (sign) {
258 r = cpu_ldsw_code(env, addr);
259 } else {
260 r = cpu_lduw_code(env, addr);
261 }
262 break;
263 }
264 case 1:
265 {
266 if (sign) {
267 r = cpu_ldsb_code(env, addr);
268 } else {
269 r = cpu_ldub_code(env, addr);
270 }
271 break;
272 }
273 default:
274 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
275 break;
276 }
277 return r;
278 }
279
280 static void cris_lock_irq(DisasContext *dc)
281 {
282 dc->clear_locked_irq = 0;
283 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
284 }
285
286 static inline void t_gen_raise_exception(uint32_t index)
287 {
288 TCGv_i32 tmp = tcg_const_i32(index);
289 gen_helper_raise_exception(cpu_env, tmp);
290 tcg_temp_free_i32(tmp);
291 }
292
293 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
294 {
295 TCGv t0, t_31;
296
297 t0 = tcg_temp_new();
298 t_31 = tcg_const_tl(31);
299 tcg_gen_shl_tl(d, a, b);
300
301 tcg_gen_sub_tl(t0, t_31, b);
302 tcg_gen_sar_tl(t0, t0, t_31);
303 tcg_gen_and_tl(t0, t0, d);
304 tcg_gen_xor_tl(d, d, t0);
305 tcg_temp_free(t0);
306 tcg_temp_free(t_31);
307 }
308
309 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
310 {
311 TCGv t0, t_31;
312
313 t0 = tcg_temp_new();
314 t_31 = tcg_temp_new();
315 tcg_gen_shr_tl(d, a, b);
316
317 tcg_gen_movi_tl(t_31, 31);
318 tcg_gen_sub_tl(t0, t_31, b);
319 tcg_gen_sar_tl(t0, t0, t_31);
320 tcg_gen_and_tl(t0, t0, d);
321 tcg_gen_xor_tl(d, d, t0);
322 tcg_temp_free(t0);
323 tcg_temp_free(t_31);
324 }
325
326 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
327 {
328 TCGv t0, t_31;
329
330 t0 = tcg_temp_new();
331 t_31 = tcg_temp_new();
332 tcg_gen_sar_tl(d, a, b);
333
334 tcg_gen_movi_tl(t_31, 31);
335 tcg_gen_sub_tl(t0, t_31, b);
336 tcg_gen_sar_tl(t0, t0, t_31);
337 tcg_gen_or_tl(d, d, t0);
338 tcg_temp_free(t0);
339 tcg_temp_free(t_31);
340 }
341
342 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
343 {
344 int l1;
345
346 l1 = gen_new_label();
347
348 /*
349 * d <<= 1
350 * if (d >= s)
351 * d -= s;
352 */
353 tcg_gen_shli_tl(d, a, 1);
354 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
355 tcg_gen_sub_tl(d, d, b);
356 gen_set_label(l1);
357 }
358
359 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
360 {
361 TCGv t;
362
363 /*
364 * d <<= 1
365 * if (n)
366 * d += s;
367 */
368 t = tcg_temp_new();
369 tcg_gen_shli_tl(d, a, 1);
370 tcg_gen_shli_tl(t, ccs, 31 - 3);
371 tcg_gen_sari_tl(t, t, 31);
372 tcg_gen_and_tl(t, t, b);
373 tcg_gen_add_tl(d, d, t);
374 tcg_temp_free(t);
375 }
376
377 /* Extended arithmetics on CRIS. */
378 static inline void t_gen_add_flag(TCGv d, int flag)
379 {
380 TCGv c;
381
382 c = tcg_temp_new();
383 t_gen_mov_TN_preg(c, PR_CCS);
384 /* Propagate carry into d. */
385 tcg_gen_andi_tl(c, c, 1 << flag);
386 if (flag) {
387 tcg_gen_shri_tl(c, c, flag);
388 }
389 tcg_gen_add_tl(d, d, c);
390 tcg_temp_free(c);
391 }
392
393 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
394 {
395 if (dc->flagx_known) {
396 if (dc->flags_x) {
397 TCGv c;
398
399 c = tcg_temp_new();
400 t_gen_mov_TN_preg(c, PR_CCS);
401 /* C flag is already at bit 0. */
402 tcg_gen_andi_tl(c, c, C_FLAG);
403 tcg_gen_add_tl(d, d, c);
404 tcg_temp_free(c);
405 }
406 } else {
407 TCGv x, c;
408
409 x = tcg_temp_new();
410 c = tcg_temp_new();
411 t_gen_mov_TN_preg(x, PR_CCS);
412 tcg_gen_mov_tl(c, x);
413
414 /* Propagate carry into d if X is set. Branch free. */
415 tcg_gen_andi_tl(c, c, C_FLAG);
416 tcg_gen_andi_tl(x, x, X_FLAG);
417 tcg_gen_shri_tl(x, x, 4);
418
419 tcg_gen_and_tl(x, x, c);
420 tcg_gen_add_tl(d, d, x);
421 tcg_temp_free(x);
422 tcg_temp_free(c);
423 }
424 }
425
426 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
427 {
428 if (dc->flagx_known) {
429 if (dc->flags_x) {
430 TCGv c;
431
432 c = tcg_temp_new();
433 t_gen_mov_TN_preg(c, PR_CCS);
434 /* C flag is already at bit 0. */
435 tcg_gen_andi_tl(c, c, C_FLAG);
436 tcg_gen_sub_tl(d, d, c);
437 tcg_temp_free(c);
438 }
439 } else {
440 TCGv x, c;
441
442 x = tcg_temp_new();
443 c = tcg_temp_new();
444 t_gen_mov_TN_preg(x, PR_CCS);
445 tcg_gen_mov_tl(c, x);
446
447 /* Propagate carry into d if X is set. Branch free. */
448 tcg_gen_andi_tl(c, c, C_FLAG);
449 tcg_gen_andi_tl(x, x, X_FLAG);
450 tcg_gen_shri_tl(x, x, 4);
451
452 tcg_gen_and_tl(x, x, c);
453 tcg_gen_sub_tl(d, d, x);
454 tcg_temp_free(x);
455 tcg_temp_free(c);
456 }
457 }
458
459 /* Swap the two bytes within each half word of the s operand.
460 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
461 static inline void t_gen_swapb(TCGv d, TCGv s)
462 {
463 TCGv t, org_s;
464
465 t = tcg_temp_new();
466 org_s = tcg_temp_new();
467
468 /* d and s may refer to the same object. */
469 tcg_gen_mov_tl(org_s, s);
470 tcg_gen_shli_tl(t, org_s, 8);
471 tcg_gen_andi_tl(d, t, 0xff00ff00);
472 tcg_gen_shri_tl(t, org_s, 8);
473 tcg_gen_andi_tl(t, t, 0x00ff00ff);
474 tcg_gen_or_tl(d, d, t);
475 tcg_temp_free(t);
476 tcg_temp_free(org_s);
477 }
478
479 /* Swap the halfwords of the s operand. */
480 static inline void t_gen_swapw(TCGv d, TCGv s)
481 {
482 TCGv t;
483 /* d and s refer the same object. */
484 t = tcg_temp_new();
485 tcg_gen_mov_tl(t, s);
486 tcg_gen_shli_tl(d, t, 16);
487 tcg_gen_shri_tl(t, t, 16);
488 tcg_gen_or_tl(d, d, t);
489 tcg_temp_free(t);
490 }
491
492 /* Reverse the within each byte.
493 T0 = (((T0 << 7) & 0x80808080) |
494 ((T0 << 5) & 0x40404040) |
495 ((T0 << 3) & 0x20202020) |
496 ((T0 << 1) & 0x10101010) |
497 ((T0 >> 1) & 0x08080808) |
498 ((T0 >> 3) & 0x04040404) |
499 ((T0 >> 5) & 0x02020202) |
500 ((T0 >> 7) & 0x01010101));
501 */
502 static inline void t_gen_swapr(TCGv d, TCGv s)
503 {
504 struct {
505 int shift; /* LSL when positive, LSR when negative. */
506 uint32_t mask;
507 } bitrev[] = {
508 {7, 0x80808080},
509 {5, 0x40404040},
510 {3, 0x20202020},
511 {1, 0x10101010},
512 {-1, 0x08080808},
513 {-3, 0x04040404},
514 {-5, 0x02020202},
515 {-7, 0x01010101}
516 };
517 int i;
518 TCGv t, org_s;
519
520 /* d and s refer the same object. */
521 t = tcg_temp_new();
522 org_s = tcg_temp_new();
523 tcg_gen_mov_tl(org_s, s);
524
525 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
526 tcg_gen_andi_tl(d, t, bitrev[0].mask);
527 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
528 if (bitrev[i].shift >= 0) {
529 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
530 } else {
531 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
532 }
533 tcg_gen_andi_tl(t, t, bitrev[i].mask);
534 tcg_gen_or_tl(d, d, t);
535 }
536 tcg_temp_free(t);
537 tcg_temp_free(org_s);
538 }
539
540 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
541 {
542 int l1;
543
544 l1 = gen_new_label();
545
546 /* Conditional jmp. */
547 tcg_gen_mov_tl(env_pc, pc_false);
548 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
549 tcg_gen_mov_tl(env_pc, pc_true);
550 gen_set_label(l1);
551 }
552
553 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
554 {
555 TranslationBlock *tb;
556 tb = dc->tb;
557 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
558 tcg_gen_goto_tb(n);
559 tcg_gen_movi_tl(env_pc, dest);
560 tcg_gen_exit_tb((uintptr_t)tb + n);
561 } else {
562 tcg_gen_movi_tl(env_pc, dest);
563 tcg_gen_exit_tb(0);
564 }
565 }
566
567 static inline void cris_clear_x_flag(DisasContext *dc)
568 {
569 if (dc->flagx_known && dc->flags_x) {
570 dc->flags_uptodate = 0;
571 }
572
573 dc->flagx_known = 1;
574 dc->flags_x = 0;
575 }
576
577 static void cris_flush_cc_state(DisasContext *dc)
578 {
579 if (dc->cc_size_uptodate != dc->cc_size) {
580 tcg_gen_movi_tl(cc_size, dc->cc_size);
581 dc->cc_size_uptodate = dc->cc_size;
582 }
583 tcg_gen_movi_tl(cc_op, dc->cc_op);
584 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
585 }
586
587 static void cris_evaluate_flags(DisasContext *dc)
588 {
589 if (dc->flags_uptodate) {
590 return;
591 }
592
593 cris_flush_cc_state(dc);
594
595 switch (dc->cc_op) {
596 case CC_OP_MCP:
597 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
598 cpu_PR[PR_CCS], cc_src,
599 cc_dest, cc_result);
600 break;
601 case CC_OP_MULS:
602 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
603 cpu_PR[PR_CCS], cc_result,
604 cpu_PR[PR_MOF]);
605 break;
606 case CC_OP_MULU:
607 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
608 cpu_PR[PR_CCS], cc_result,
609 cpu_PR[PR_MOF]);
610 break;
611 case CC_OP_MOVE:
612 case CC_OP_AND:
613 case CC_OP_OR:
614 case CC_OP_XOR:
615 case CC_OP_ASR:
616 case CC_OP_LSR:
617 case CC_OP_LSL:
618 switch (dc->cc_size) {
619 case 4:
620 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
621 cpu_env, cpu_PR[PR_CCS], cc_result);
622 break;
623 case 2:
624 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
625 cpu_env, cpu_PR[PR_CCS], cc_result);
626 break;
627 default:
628 gen_helper_evaluate_flags(cpu_env);
629 break;
630 }
631 break;
632 case CC_OP_FLAGS:
633 /* live. */
634 break;
635 case CC_OP_SUB:
636 case CC_OP_CMP:
637 if (dc->cc_size == 4) {
638 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
639 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
640 } else {
641 gen_helper_evaluate_flags(cpu_env);
642 }
643
644 break;
645 default:
646 switch (dc->cc_size) {
647 case 4:
648 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
649 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
650 break;
651 default:
652 gen_helper_evaluate_flags(cpu_env);
653 break;
654 }
655 break;
656 }
657
658 if (dc->flagx_known) {
659 if (dc->flags_x) {
660 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
661 } else if (dc->cc_op == CC_OP_FLAGS) {
662 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
663 }
664 }
665 dc->flags_uptodate = 1;
666 }
667
668 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
669 {
670 uint32_t ovl;
671
672 if (!mask) {
673 dc->update_cc = 0;
674 return;
675 }
676
677 /* Check if we need to evaluate the condition codes due to
678 CC overlaying. */
679 ovl = (dc->cc_mask ^ mask) & ~mask;
680 if (ovl) {
681 /* TODO: optimize this case. It trigs all the time. */
682 cris_evaluate_flags(dc);
683 }
684 dc->cc_mask = mask;
685 dc->update_cc = 1;
686 }
687
688 static void cris_update_cc_op(DisasContext *dc, int op, int size)
689 {
690 dc->cc_op = op;
691 dc->cc_size = size;
692 dc->flags_uptodate = 0;
693 }
694
695 static inline void cris_update_cc_x(DisasContext *dc)
696 {
697 /* Save the x flag state at the time of the cc snapshot. */
698 if (dc->flagx_known) {
699 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
700 return;
701 }
702 tcg_gen_movi_tl(cc_x, dc->flags_x);
703 dc->cc_x_uptodate = 2 | dc->flags_x;
704 } else {
705 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
706 dc->cc_x_uptodate = 1;
707 }
708 }
709
710 /* Update cc prior to executing ALU op. Needs source operands untouched. */
711 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
712 TCGv dst, TCGv src, int size)
713 {
714 if (dc->update_cc) {
715 cris_update_cc_op(dc, op, size);
716 tcg_gen_mov_tl(cc_src, src);
717
718 if (op != CC_OP_MOVE
719 && op != CC_OP_AND
720 && op != CC_OP_OR
721 && op != CC_OP_XOR
722 && op != CC_OP_ASR
723 && op != CC_OP_LSR
724 && op != CC_OP_LSL) {
725 tcg_gen_mov_tl(cc_dest, dst);
726 }
727
728 cris_update_cc_x(dc);
729 }
730 }
731
732 /* Update cc after executing ALU op. needs the result. */
733 static inline void cris_update_result(DisasContext *dc, TCGv res)
734 {
735 if (dc->update_cc) {
736 tcg_gen_mov_tl(cc_result, res);
737 }
738 }
739
740 /* Returns one if the write back stage should execute. */
741 static void cris_alu_op_exec(DisasContext *dc, int op,
742 TCGv dst, TCGv a, TCGv b, int size)
743 {
744 /* Emit the ALU insns. */
745 switch (op) {
746 case CC_OP_ADD:
747 tcg_gen_add_tl(dst, a, b);
748 /* Extended arithmetics. */
749 t_gen_addx_carry(dc, dst);
750 break;
751 case CC_OP_ADDC:
752 tcg_gen_add_tl(dst, a, b);
753 t_gen_add_flag(dst, 0); /* C_FLAG. */
754 break;
755 case CC_OP_MCP:
756 tcg_gen_add_tl(dst, a, b);
757 t_gen_add_flag(dst, 8); /* R_FLAG. */
758 break;
759 case CC_OP_SUB:
760 tcg_gen_sub_tl(dst, a, b);
761 /* Extended arithmetics. */
762 t_gen_subx_carry(dc, dst);
763 break;
764 case CC_OP_MOVE:
765 tcg_gen_mov_tl(dst, b);
766 break;
767 case CC_OP_OR:
768 tcg_gen_or_tl(dst, a, b);
769 break;
770 case CC_OP_AND:
771 tcg_gen_and_tl(dst, a, b);
772 break;
773 case CC_OP_XOR:
774 tcg_gen_xor_tl(dst, a, b);
775 break;
776 case CC_OP_LSL:
777 t_gen_lsl(dst, a, b);
778 break;
779 case CC_OP_LSR:
780 t_gen_lsr(dst, a, b);
781 break;
782 case CC_OP_ASR:
783 t_gen_asr(dst, a, b);
784 break;
785 case CC_OP_NEG:
786 tcg_gen_neg_tl(dst, b);
787 /* Extended arithmetics. */
788 t_gen_subx_carry(dc, dst);
789 break;
790 case CC_OP_LZ:
791 gen_helper_lz(dst, b);
792 break;
793 case CC_OP_MULS:
794 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
795 break;
796 case CC_OP_MULU:
797 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
798 break;
799 case CC_OP_DSTEP:
800 t_gen_cris_dstep(dst, a, b);
801 break;
802 case CC_OP_MSTEP:
803 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
804 break;
805 case CC_OP_BOUND:
806 {
807 int l1;
808 l1 = gen_new_label();
809 tcg_gen_mov_tl(dst, a);
810 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
811 tcg_gen_mov_tl(dst, b);
812 gen_set_label(l1);
813 }
814 break;
815 case CC_OP_CMP:
816 tcg_gen_sub_tl(dst, a, b);
817 /* Extended arithmetics. */
818 t_gen_subx_carry(dc, dst);
819 break;
820 default:
821 qemu_log("illegal ALU op.\n");
822 BUG();
823 break;
824 }
825
826 if (size == 1) {
827 tcg_gen_andi_tl(dst, dst, 0xff);
828 } else if (size == 2) {
829 tcg_gen_andi_tl(dst, dst, 0xffff);
830 }
831 }
832
833 static void cris_alu(DisasContext *dc, int op,
834 TCGv d, TCGv op_a, TCGv op_b, int size)
835 {
836 TCGv tmp;
837 int writeback;
838
839 writeback = 1;
840
841 if (op == CC_OP_CMP) {
842 tmp = tcg_temp_new();
843 writeback = 0;
844 } else if (size == 4) {
845 tmp = d;
846 writeback = 0;
847 } else {
848 tmp = tcg_temp_new();
849 }
850
851
852 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
853 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
854 cris_update_result(dc, tmp);
855
856 /* Writeback. */
857 if (writeback) {
858 if (size == 1) {
859 tcg_gen_andi_tl(d, d, ~0xff);
860 } else {
861 tcg_gen_andi_tl(d, d, ~0xffff);
862 }
863 tcg_gen_or_tl(d, d, tmp);
864 }
865 if (!TCGV_EQUAL(tmp, d)) {
866 tcg_temp_free(tmp);
867 }
868 }
869
870 static int arith_cc(DisasContext *dc)
871 {
872 if (dc->update_cc) {
873 switch (dc->cc_op) {
874 case CC_OP_ADDC: return 1;
875 case CC_OP_ADD: return 1;
876 case CC_OP_SUB: return 1;
877 case CC_OP_DSTEP: return 1;
878 case CC_OP_LSL: return 1;
879 case CC_OP_LSR: return 1;
880 case CC_OP_ASR: return 1;
881 case CC_OP_CMP: return 1;
882 case CC_OP_NEG: return 1;
883 case CC_OP_OR: return 1;
884 case CC_OP_AND: return 1;
885 case CC_OP_XOR: return 1;
886 case CC_OP_MULU: return 1;
887 case CC_OP_MULS: return 1;
888 default:
889 return 0;
890 }
891 }
892 return 0;
893 }
894
895 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
896 {
897 int arith_opt, move_opt;
898
899 /* TODO: optimize more condition codes. */
900
901 /*
902 * If the flags are live, we've gotta look into the bits of CCS.
903 * Otherwise, if we just did an arithmetic operation we try to
904 * evaluate the condition code faster.
905 *
906 * When this function is done, T0 should be non-zero if the condition
907 * code is true.
908 */
909 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
910 move_opt = (dc->cc_op == CC_OP_MOVE);
911 switch (cond) {
912 case CC_EQ:
913 if ((arith_opt || move_opt)
914 && dc->cc_x_uptodate != (2 | X_FLAG)) {
915 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
916 cc_result, tcg_const_tl(0));
917 } else {
918 cris_evaluate_flags(dc);
919 tcg_gen_andi_tl(cc,
920 cpu_PR[PR_CCS], Z_FLAG);
921 }
922 break;
923 case CC_NE:
924 if ((arith_opt || move_opt)
925 && dc->cc_x_uptodate != (2 | X_FLAG)) {
926 tcg_gen_mov_tl(cc, cc_result);
927 } else {
928 cris_evaluate_flags(dc);
929 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
930 Z_FLAG);
931 tcg_gen_andi_tl(cc, cc, Z_FLAG);
932 }
933 break;
934 case CC_CS:
935 cris_evaluate_flags(dc);
936 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
937 break;
938 case CC_CC:
939 cris_evaluate_flags(dc);
940 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
941 tcg_gen_andi_tl(cc, cc, C_FLAG);
942 break;
943 case CC_VS:
944 cris_evaluate_flags(dc);
945 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
946 break;
947 case CC_VC:
948 cris_evaluate_flags(dc);
949 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
950 V_FLAG);
951 tcg_gen_andi_tl(cc, cc, V_FLAG);
952 break;
953 case CC_PL:
954 if (arith_opt || move_opt) {
955 int bits = 31;
956
957 if (dc->cc_size == 1) {
958 bits = 7;
959 } else if (dc->cc_size == 2) {
960 bits = 15;
961 }
962
963 tcg_gen_shri_tl(cc, cc_result, bits);
964 tcg_gen_xori_tl(cc, cc, 1);
965 } else {
966 cris_evaluate_flags(dc);
967 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
968 N_FLAG);
969 tcg_gen_andi_tl(cc, cc, N_FLAG);
970 }
971 break;
972 case CC_MI:
973 if (arith_opt || move_opt) {
974 int bits = 31;
975
976 if (dc->cc_size == 1) {
977 bits = 7;
978 } else if (dc->cc_size == 2) {
979 bits = 15;
980 }
981
982 tcg_gen_shri_tl(cc, cc_result, bits);
983 tcg_gen_andi_tl(cc, cc, 1);
984 } else {
985 cris_evaluate_flags(dc);
986 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
987 N_FLAG);
988 }
989 break;
990 case CC_LS:
991 cris_evaluate_flags(dc);
992 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
993 C_FLAG | Z_FLAG);
994 break;
995 case CC_HI:
996 cris_evaluate_flags(dc);
997 {
998 TCGv tmp;
999
1000 tmp = tcg_temp_new();
1001 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1002 C_FLAG | Z_FLAG);
1003 /* Overlay the C flag on top of the Z. */
1004 tcg_gen_shli_tl(cc, tmp, 2);
1005 tcg_gen_and_tl(cc, tmp, cc);
1006 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1007
1008 tcg_temp_free(tmp);
1009 }
1010 break;
1011 case CC_GE:
1012 cris_evaluate_flags(dc);
1013 /* Overlay the V flag on top of the N. */
1014 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1015 tcg_gen_xor_tl(cc,
1016 cpu_PR[PR_CCS], cc);
1017 tcg_gen_andi_tl(cc, cc, N_FLAG);
1018 tcg_gen_xori_tl(cc, cc, N_FLAG);
1019 break;
1020 case CC_LT:
1021 cris_evaluate_flags(dc);
1022 /* Overlay the V flag on top of the N. */
1023 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1024 tcg_gen_xor_tl(cc,
1025 cpu_PR[PR_CCS], cc);
1026 tcg_gen_andi_tl(cc, cc, N_FLAG);
1027 break;
1028 case CC_GT:
1029 cris_evaluate_flags(dc);
1030 {
1031 TCGv n, z;
1032
1033 n = tcg_temp_new();
1034 z = tcg_temp_new();
1035
1036 /* To avoid a shift we overlay everything on
1037 the V flag. */
1038 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1039 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1040 /* invert Z. */
1041 tcg_gen_xori_tl(z, z, 2);
1042
1043 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1044 tcg_gen_xori_tl(n, n, 2);
1045 tcg_gen_and_tl(cc, z, n);
1046 tcg_gen_andi_tl(cc, cc, 2);
1047
1048 tcg_temp_free(n);
1049 tcg_temp_free(z);
1050 }
1051 break;
1052 case CC_LE:
1053 cris_evaluate_flags(dc);
1054 {
1055 TCGv n, z;
1056
1057 n = tcg_temp_new();
1058 z = tcg_temp_new();
1059
1060 /* To avoid a shift we overlay everything on
1061 the V flag. */
1062 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1063 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1064
1065 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1066 tcg_gen_or_tl(cc, z, n);
1067 tcg_gen_andi_tl(cc, cc, 2);
1068
1069 tcg_temp_free(n);
1070 tcg_temp_free(z);
1071 }
1072 break;
1073 case CC_P:
1074 cris_evaluate_flags(dc);
1075 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1076 break;
1077 case CC_A:
1078 tcg_gen_movi_tl(cc, 1);
1079 break;
1080 default:
1081 BUG();
1082 break;
1083 };
1084 }
1085
1086 static void cris_store_direct_jmp(DisasContext *dc)
1087 {
1088 /* Store the direct jmp state into the cpu-state. */
1089 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1090 if (dc->jmp == JMP_DIRECT) {
1091 tcg_gen_movi_tl(env_btaken, 1);
1092 }
1093 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1094 dc->jmp = JMP_INDIRECT;
1095 }
1096 }
1097
1098 static void cris_prepare_cc_branch (DisasContext *dc,
1099 int offset, int cond)
1100 {
1101 /* This helps us re-schedule the micro-code to insns in delay-slots
1102 before the actual jump. */
1103 dc->delayed_branch = 2;
1104 dc->jmp = JMP_DIRECT_CC;
1105 dc->jmp_pc = dc->pc + offset;
1106
1107 gen_tst_cc(dc, env_btaken, cond);
1108 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1109 }
1110
1111
1112 /* jumps, when the dest is in a live reg for example. Direct should be set
1113 when the dest addr is constant to allow tb chaining. */
1114 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1115 {
1116 /* This helps us re-schedule the micro-code to insns in delay-slots
1117 before the actual jump. */
1118 dc->delayed_branch = 2;
1119 dc->jmp = type;
1120 if (type == JMP_INDIRECT) {
1121 tcg_gen_movi_tl(env_btaken, 1);
1122 }
1123 }
1124
1125 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1126 {
1127 int mem_index = cpu_mmu_index(&dc->cpu->env);
1128
1129 /* If we get a fault on a delayslot we must keep the jmp state in
1130 the cpu-state to be able to re-execute the jmp. */
1131 if (dc->delayed_branch == 1) {
1132 cris_store_direct_jmp(dc);
1133 }
1134
1135 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
1136 }
1137
1138 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1139 unsigned int size, int sign)
1140 {
1141 int mem_index = cpu_mmu_index(&dc->cpu->env);
1142
1143 /* If we get a fault on a delayslot we must keep the jmp state in
1144 the cpu-state to be able to re-execute the jmp. */
1145 if (dc->delayed_branch == 1) {
1146 cris_store_direct_jmp(dc);
1147 }
1148
1149 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1150 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1151 }
1152
1153 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1154 unsigned int size)
1155 {
1156 int mem_index = cpu_mmu_index(&dc->cpu->env);
1157
1158 /* If we get a fault on a delayslot we must keep the jmp state in
1159 the cpu-state to be able to re-execute the jmp. */
1160 if (dc->delayed_branch == 1) {
1161 cris_store_direct_jmp(dc);
1162 }
1163
1164
1165 /* Conditional writes. We only support the kind were X and P are known
1166 at translation time. */
1167 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1168 dc->postinc = 0;
1169 cris_evaluate_flags(dc);
1170 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1171 return;
1172 }
1173
1174 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
1175
1176 if (dc->flagx_known && dc->flags_x) {
1177 cris_evaluate_flags(dc);
1178 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1179 }
1180 }
1181
1182 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1183 {
1184 if (size == 1) {
1185 tcg_gen_ext8s_i32(d, s);
1186 } else if (size == 2) {
1187 tcg_gen_ext16s_i32(d, s);
1188 } else if (!TCGV_EQUAL(d, s)) {
1189 tcg_gen_mov_tl(d, s);
1190 }
1191 }
1192
1193 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1194 {
1195 if (size == 1) {
1196 tcg_gen_ext8u_i32(d, s);
1197 } else if (size == 2) {
1198 tcg_gen_ext16u_i32(d, s);
1199 } else if (!TCGV_EQUAL(d, s)) {
1200 tcg_gen_mov_tl(d, s);
1201 }
1202 }
1203
1204 #if DISAS_CRIS
1205 static char memsize_char(int size)
1206 {
1207 switch (size) {
1208 case 1: return 'b'; break;
1209 case 2: return 'w'; break;
1210 case 4: return 'd'; break;
1211 default:
1212 return 'x';
1213 break;
1214 }
1215 }
1216 #endif
1217
1218 static inline unsigned int memsize_z(DisasContext *dc)
1219 {
1220 return dc->zsize + 1;
1221 }
1222
1223 static inline unsigned int memsize_zz(DisasContext *dc)
1224 {
1225 switch (dc->zzsize) {
1226 case 0: return 1;
1227 case 1: return 2;
1228 default:
1229 return 4;
1230 }
1231 }
1232
1233 static inline void do_postinc (DisasContext *dc, int size)
1234 {
1235 if (dc->postinc) {
1236 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1237 }
1238 }
1239
1240 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1241 int size, int s_ext, TCGv dst)
1242 {
1243 if (s_ext) {
1244 t_gen_sext(dst, cpu_R[rs], size);
1245 } else {
1246 t_gen_zext(dst, cpu_R[rs], size);
1247 }
1248 }
1249
1250 /* Prepare T0 and T1 for a register alu operation.
1251 s_ext decides if the operand1 should be sign-extended or zero-extended when
1252 needed. */
1253 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1254 int size, int s_ext, TCGv dst, TCGv src)
1255 {
1256 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1257
1258 if (s_ext) {
1259 t_gen_sext(dst, cpu_R[rd], size);
1260 } else {
1261 t_gen_zext(dst, cpu_R[rd], size);
1262 }
1263 }
1264
1265 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1266 int s_ext, int memsize, TCGv dst)
1267 {
1268 unsigned int rs;
1269 uint32_t imm;
1270 int is_imm;
1271 int insn_len = 2;
1272
1273 rs = dc->op1;
1274 is_imm = rs == 15 && dc->postinc;
1275
1276 /* Load [$rs] onto T1. */
1277 if (is_imm) {
1278 insn_len = 2 + memsize;
1279 if (memsize == 1) {
1280 insn_len++;
1281 }
1282
1283 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1284 tcg_gen_movi_tl(dst, imm);
1285 dc->postinc = 0;
1286 } else {
1287 cris_flush_cc_state(dc);
1288 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1289 if (s_ext) {
1290 t_gen_sext(dst, dst, memsize);
1291 } else {
1292 t_gen_zext(dst, dst, memsize);
1293 }
1294 }
1295 return insn_len;
1296 }
1297
1298 /* Prepare T0 and T1 for a memory + alu operation.
1299 s_ext decides if the operand1 should be sign-extended or zero-extended when
1300 needed. */
1301 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1302 int s_ext, int memsize, TCGv dst, TCGv src)
1303 {
1304 int insn_len;
1305
1306 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1307 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1308 return insn_len;
1309 }
1310
1311 #if DISAS_CRIS
1312 static const char *cc_name(int cc)
1313 {
1314 static const char *cc_names[16] = {
1315 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1316 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1317 };
1318 assert(cc < 16);
1319 return cc_names[cc];
1320 }
1321 #endif
1322
1323 /* Start of insn decoders. */
1324
1325 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1326 {
1327 int32_t offset;
1328 int sign;
1329 uint32_t cond = dc->op2;
1330
1331 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1332 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1333
1334 offset *= 2;
1335 offset |= sign << 8;
1336 offset = sign_extend(offset, 8);
1337
1338 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1339
1340 /* op2 holds the condition-code. */
1341 cris_cc_mask(dc, 0);
1342 cris_prepare_cc_branch(dc, offset, cond);
1343 return 2;
1344 }
1345 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1346 {
1347 int32_t imm;
1348
1349 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1350 imm = sign_extend(dc->op1, 7);
1351
1352 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1353 cris_cc_mask(dc, 0);
1354 /* Fetch register operand, */
1355 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1356
1357 return 2;
1358 }
1359 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1360 {
1361 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1362
1363 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1364
1365 cris_cc_mask(dc, CC_MASK_NZVC);
1366
1367 cris_alu(dc, CC_OP_ADD,
1368 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1369 return 2;
1370 }
1371 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1372 {
1373 uint32_t imm;
1374
1375 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1376 imm = sign_extend(dc->op1, 5);
1377 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1378
1379 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1380 return 2;
1381 }
1382 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1383 {
1384 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1385
1386 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1387
1388 cris_cc_mask(dc, CC_MASK_NZVC);
1389 cris_alu(dc, CC_OP_SUB,
1390 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1391 return 2;
1392 }
1393 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1394 {
1395 uint32_t imm;
1396 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1397 imm = sign_extend(dc->op1, 5);
1398
1399 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1400 cris_cc_mask(dc, CC_MASK_NZVC);
1401
1402 cris_alu(dc, CC_OP_CMP,
1403 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1404 return 2;
1405 }
1406 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1407 {
1408 uint32_t imm;
1409 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1410 imm = sign_extend(dc->op1, 5);
1411
1412 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1413 cris_cc_mask(dc, CC_MASK_NZ);
1414
1415 cris_alu(dc, CC_OP_AND,
1416 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1417 return 2;
1418 }
1419 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1420 {
1421 uint32_t imm;
1422 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1423 imm = sign_extend(dc->op1, 5);
1424 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1425 cris_cc_mask(dc, CC_MASK_NZ);
1426
1427 cris_alu(dc, CC_OP_OR,
1428 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1429 return 2;
1430 }
1431 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1432 {
1433 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1434 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1435
1436 cris_cc_mask(dc, CC_MASK_NZ);
1437 cris_evaluate_flags(dc);
1438 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1439 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1440 cris_alu(dc, CC_OP_MOVE,
1441 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1442 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1443 dc->flags_uptodate = 1;
1444 return 2;
1445 }
1446 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1447 {
1448 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1449 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1450 cris_cc_mask(dc, CC_MASK_NZ);
1451
1452 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1453 cris_alu(dc, CC_OP_MOVE,
1454 cpu_R[dc->op2],
1455 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1456 return 2;
1457 }
1458 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1459 {
1460 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1461 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1462
1463 cris_cc_mask(dc, CC_MASK_NZ);
1464
1465 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1466
1467 cris_alu(dc, CC_OP_MOVE,
1468 cpu_R[dc->op2],
1469 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1470 return 2;
1471 }
1472 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1473 {
1474 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1475 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1476
1477 cris_cc_mask(dc, CC_MASK_NZ);
1478
1479 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1480 cris_alu(dc, CC_OP_MOVE,
1481 cpu_R[dc->op2],
1482 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1483 return 2;
1484 }
1485
1486 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1487 {
1488 int size = memsize_zz(dc);
1489
1490 LOG_DIS("move.%c $r%u, $r%u\n",
1491 memsize_char(size), dc->op1, dc->op2);
1492
1493 cris_cc_mask(dc, CC_MASK_NZ);
1494 if (size == 4) {
1495 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1496 cris_cc_mask(dc, CC_MASK_NZ);
1497 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1498 cris_update_cc_x(dc);
1499 cris_update_result(dc, cpu_R[dc->op2]);
1500 } else {
1501 TCGv t0;
1502
1503 t0 = tcg_temp_new();
1504 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1505 cris_alu(dc, CC_OP_MOVE,
1506 cpu_R[dc->op2],
1507 cpu_R[dc->op2], t0, size);
1508 tcg_temp_free(t0);
1509 }
1510 return 2;
1511 }
1512
1513 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1514 {
1515 int cond = dc->op2;
1516
1517 LOG_DIS("s%s $r%u\n",
1518 cc_name(cond), dc->op1);
1519
1520 if (cond != CC_A) {
1521 int l1;
1522
1523 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1524 l1 = gen_new_label();
1525 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1526 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1527 gen_set_label(l1);
1528 } else {
1529 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1530 }
1531
1532 cris_cc_mask(dc, 0);
1533 return 2;
1534 }
1535
1536 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1537 {
1538 if (size == 4) {
1539 t[0] = cpu_R[dc->op2];
1540 t[1] = cpu_R[dc->op1];
1541 } else {
1542 t[0] = tcg_temp_new();
1543 t[1] = tcg_temp_new();
1544 }
1545 }
1546
1547 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1548 {
1549 if (size != 4) {
1550 tcg_temp_free(t[0]);
1551 tcg_temp_free(t[1]);
1552 }
1553 }
1554
1555 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1556 {
1557 TCGv t[2];
1558 int size = memsize_zz(dc);
1559
1560 LOG_DIS("and.%c $r%u, $r%u\n",
1561 memsize_char(size), dc->op1, dc->op2);
1562
1563 cris_cc_mask(dc, CC_MASK_NZ);
1564
1565 cris_alu_alloc_temps(dc, size, t);
1566 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1567 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1568 cris_alu_free_temps(dc, size, t);
1569 return 2;
1570 }
1571
1572 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1573 {
1574 TCGv t0;
1575 LOG_DIS("lz $r%u, $r%u\n",
1576 dc->op1, dc->op2);
1577 cris_cc_mask(dc, CC_MASK_NZ);
1578 t0 = tcg_temp_new();
1579 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1580 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1581 tcg_temp_free(t0);
1582 return 2;
1583 }
1584
1585 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1586 {
1587 TCGv t[2];
1588 int size = memsize_zz(dc);
1589
1590 LOG_DIS("lsl.%c $r%u, $r%u\n",
1591 memsize_char(size), dc->op1, dc->op2);
1592
1593 cris_cc_mask(dc, CC_MASK_NZ);
1594 cris_alu_alloc_temps(dc, size, t);
1595 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1596 tcg_gen_andi_tl(t[1], t[1], 63);
1597 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1598 cris_alu_alloc_temps(dc, size, t);
1599 return 2;
1600 }
1601
1602 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1603 {
1604 TCGv t[2];
1605 int size = memsize_zz(dc);
1606
1607 LOG_DIS("lsr.%c $r%u, $r%u\n",
1608 memsize_char(size), dc->op1, dc->op2);
1609
1610 cris_cc_mask(dc, CC_MASK_NZ);
1611 cris_alu_alloc_temps(dc, size, t);
1612 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1613 tcg_gen_andi_tl(t[1], t[1], 63);
1614 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1615 cris_alu_free_temps(dc, size, t);
1616 return 2;
1617 }
1618
1619 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1620 {
1621 TCGv t[2];
1622 int size = memsize_zz(dc);
1623
1624 LOG_DIS("asr.%c $r%u, $r%u\n",
1625 memsize_char(size), dc->op1, dc->op2);
1626
1627 cris_cc_mask(dc, CC_MASK_NZ);
1628 cris_alu_alloc_temps(dc, size, t);
1629 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1630 tcg_gen_andi_tl(t[1], t[1], 63);
1631 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1632 cris_alu_free_temps(dc, size, t);
1633 return 2;
1634 }
1635
1636 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1637 {
1638 TCGv t[2];
1639 int size = memsize_zz(dc);
1640
1641 LOG_DIS("muls.%c $r%u, $r%u\n",
1642 memsize_char(size), dc->op1, dc->op2);
1643 cris_cc_mask(dc, CC_MASK_NZV);
1644 cris_alu_alloc_temps(dc, size, t);
1645 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1646
1647 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1648 cris_alu_free_temps(dc, size, t);
1649 return 2;
1650 }
1651
1652 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1653 {
1654 TCGv t[2];
1655 int size = memsize_zz(dc);
1656
1657 LOG_DIS("mulu.%c $r%u, $r%u\n",
1658 memsize_char(size), dc->op1, dc->op2);
1659 cris_cc_mask(dc, CC_MASK_NZV);
1660 cris_alu_alloc_temps(dc, size, t);
1661 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1662
1663 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1664 cris_alu_alloc_temps(dc, size, t);
1665 return 2;
1666 }
1667
1668
1669 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1670 {
1671 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1672 cris_cc_mask(dc, CC_MASK_NZ);
1673 cris_alu(dc, CC_OP_DSTEP,
1674 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1675 return 2;
1676 }
1677
1678 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1679 {
1680 TCGv t[2];
1681 int size = memsize_zz(dc);
1682 LOG_DIS("xor.%c $r%u, $r%u\n",
1683 memsize_char(size), dc->op1, dc->op2);
1684 BUG_ON(size != 4); /* xor is dword. */
1685 cris_cc_mask(dc, CC_MASK_NZ);
1686 cris_alu_alloc_temps(dc, size, t);
1687 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1688
1689 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1690 cris_alu_free_temps(dc, size, t);
1691 return 2;
1692 }
1693
1694 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1695 {
1696 TCGv l0;
1697 int size = memsize_zz(dc);
1698 LOG_DIS("bound.%c $r%u, $r%u\n",
1699 memsize_char(size), dc->op1, dc->op2);
1700 cris_cc_mask(dc, CC_MASK_NZ);
1701 l0 = tcg_temp_local_new();
1702 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1703 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1704 tcg_temp_free(l0);
1705 return 2;
1706 }
1707
1708 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1709 {
1710 TCGv t[2];
1711 int size = memsize_zz(dc);
1712 LOG_DIS("cmp.%c $r%u, $r%u\n",
1713 memsize_char(size), dc->op1, dc->op2);
1714 cris_cc_mask(dc, CC_MASK_NZVC);
1715 cris_alu_alloc_temps(dc, size, t);
1716 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1717
1718 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1719 cris_alu_free_temps(dc, size, t);
1720 return 2;
1721 }
1722
1723 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1724 {
1725 TCGv t0;
1726
1727 LOG_DIS("abs $r%u, $r%u\n",
1728 dc->op1, dc->op2);
1729 cris_cc_mask(dc, CC_MASK_NZ);
1730
1731 t0 = tcg_temp_new();
1732 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1733 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1734 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1735 tcg_temp_free(t0);
1736
1737 cris_alu(dc, CC_OP_MOVE,
1738 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1739 return 2;
1740 }
1741
1742 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1743 {
1744 TCGv t[2];
1745 int size = memsize_zz(dc);
1746 LOG_DIS("add.%c $r%u, $r%u\n",
1747 memsize_char(size), dc->op1, dc->op2);
1748 cris_cc_mask(dc, CC_MASK_NZVC);
1749 cris_alu_alloc_temps(dc, size, t);
1750 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1751
1752 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1753 cris_alu_free_temps(dc, size, t);
1754 return 2;
1755 }
1756
1757 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1758 {
1759 LOG_DIS("addc $r%u, $r%u\n",
1760 dc->op1, dc->op2);
1761 cris_evaluate_flags(dc);
1762 /* Set for this insn. */
1763 dc->flagx_known = 1;
1764 dc->flags_x = X_FLAG;
1765
1766 cris_cc_mask(dc, CC_MASK_NZVC);
1767 cris_alu(dc, CC_OP_ADDC,
1768 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1769 return 2;
1770 }
1771
1772 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1773 {
1774 LOG_DIS("mcp $p%u, $r%u\n",
1775 dc->op2, dc->op1);
1776 cris_evaluate_flags(dc);
1777 cris_cc_mask(dc, CC_MASK_RNZV);
1778 cris_alu(dc, CC_OP_MCP,
1779 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1780 return 2;
1781 }
1782
1783 #if DISAS_CRIS
1784 static char * swapmode_name(int mode, char *modename) {
1785 int i = 0;
1786 if (mode & 8) {
1787 modename[i++] = 'n';
1788 }
1789 if (mode & 4) {
1790 modename[i++] = 'w';
1791 }
1792 if (mode & 2) {
1793 modename[i++] = 'b';
1794 }
1795 if (mode & 1) {
1796 modename[i++] = 'r';
1797 }
1798 modename[i++] = 0;
1799 return modename;
1800 }
1801 #endif
1802
1803 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1804 {
1805 TCGv t0;
1806 #if DISAS_CRIS
1807 char modename[4];
1808 #endif
1809 LOG_DIS("swap%s $r%u\n",
1810 swapmode_name(dc->op2, modename), dc->op1);
1811
1812 cris_cc_mask(dc, CC_MASK_NZ);
1813 t0 = tcg_temp_new();
1814 t_gen_mov_TN_reg(t0, dc->op1);
1815 if (dc->op2 & 8) {
1816 tcg_gen_not_tl(t0, t0);
1817 }
1818 if (dc->op2 & 4) {
1819 t_gen_swapw(t0, t0);
1820 }
1821 if (dc->op2 & 2) {
1822 t_gen_swapb(t0, t0);
1823 }
1824 if (dc->op2 & 1) {
1825 t_gen_swapr(t0, t0);
1826 }
1827 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1828 tcg_temp_free(t0);
1829 return 2;
1830 }
1831
1832 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1833 {
1834 TCGv t[2];
1835 int size = memsize_zz(dc);
1836 LOG_DIS("or.%c $r%u, $r%u\n",
1837 memsize_char(size), dc->op1, dc->op2);
1838 cris_cc_mask(dc, CC_MASK_NZ);
1839 cris_alu_alloc_temps(dc, size, t);
1840 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1841 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1842 cris_alu_free_temps(dc, size, t);
1843 return 2;
1844 }
1845
1846 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1847 {
1848 TCGv t0;
1849 LOG_DIS("addi.%c $r%u, $r%u\n",
1850 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1851 cris_cc_mask(dc, 0);
1852 t0 = tcg_temp_new();
1853 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1854 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1855 tcg_temp_free(t0);
1856 return 2;
1857 }
1858
1859 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1860 {
1861 TCGv t0;
1862 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1863 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1864 cris_cc_mask(dc, 0);
1865 t0 = tcg_temp_new();
1866 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1867 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1868 tcg_temp_free(t0);
1869 return 2;
1870 }
1871
1872 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1873 {
1874 TCGv t[2];
1875 int size = memsize_zz(dc);
1876 LOG_DIS("neg.%c $r%u, $r%u\n",
1877 memsize_char(size), dc->op1, dc->op2);
1878 cris_cc_mask(dc, CC_MASK_NZVC);
1879 cris_alu_alloc_temps(dc, size, t);
1880 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1881
1882 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1883 cris_alu_free_temps(dc, size, t);
1884 return 2;
1885 }
1886
1887 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1888 {
1889 LOG_DIS("btst $r%u, $r%u\n",
1890 dc->op1, dc->op2);
1891 cris_cc_mask(dc, CC_MASK_NZ);
1892 cris_evaluate_flags(dc);
1893 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1894 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1895 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1896 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1897 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1898 dc->flags_uptodate = 1;
1899 return 2;
1900 }
1901
1902 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1903 {
1904 TCGv t[2];
1905 int size = memsize_zz(dc);
1906 LOG_DIS("sub.%c $r%u, $r%u\n",
1907 memsize_char(size), dc->op1, dc->op2);
1908 cris_cc_mask(dc, CC_MASK_NZVC);
1909 cris_alu_alloc_temps(dc, size, t);
1910 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1911 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1912 cris_alu_free_temps(dc, size, t);
1913 return 2;
1914 }
1915
1916 /* Zero extension. From size to dword. */
1917 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1918 {
1919 TCGv t0;
1920 int size = memsize_z(dc);
1921 LOG_DIS("movu.%c $r%u, $r%u\n",
1922 memsize_char(size),
1923 dc->op1, dc->op2);
1924
1925 cris_cc_mask(dc, CC_MASK_NZ);
1926 t0 = tcg_temp_new();
1927 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1928 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1929 tcg_temp_free(t0);
1930 return 2;
1931 }
1932
1933 /* Sign extension. From size to dword. */
1934 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1935 {
1936 TCGv t0;
1937 int size = memsize_z(dc);
1938 LOG_DIS("movs.%c $r%u, $r%u\n",
1939 memsize_char(size),
1940 dc->op1, dc->op2);
1941
1942 cris_cc_mask(dc, CC_MASK_NZ);
1943 t0 = tcg_temp_new();
1944 /* Size can only be qi or hi. */
1945 t_gen_sext(t0, cpu_R[dc->op1], size);
1946 cris_alu(dc, CC_OP_MOVE,
1947 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1948 tcg_temp_free(t0);
1949 return 2;
1950 }
1951
1952 /* zero extension. From size to dword. */
1953 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1954 {
1955 TCGv t0;
1956 int size = memsize_z(dc);
1957 LOG_DIS("addu.%c $r%u, $r%u\n",
1958 memsize_char(size),
1959 dc->op1, dc->op2);
1960
1961 cris_cc_mask(dc, CC_MASK_NZVC);
1962 t0 = tcg_temp_new();
1963 /* Size can only be qi or hi. */
1964 t_gen_zext(t0, cpu_R[dc->op1], size);
1965 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1966 tcg_temp_free(t0);
1967 return 2;
1968 }
1969
1970 /* Sign extension. From size to dword. */
1971 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1972 {
1973 TCGv t0;
1974 int size = memsize_z(dc);
1975 LOG_DIS("adds.%c $r%u, $r%u\n",
1976 memsize_char(size),
1977 dc->op1, dc->op2);
1978
1979 cris_cc_mask(dc, CC_MASK_NZVC);
1980 t0 = tcg_temp_new();
1981 /* Size can only be qi or hi. */
1982 t_gen_sext(t0, cpu_R[dc->op1], size);
1983 cris_alu(dc, CC_OP_ADD,
1984 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1985 tcg_temp_free(t0);
1986 return 2;
1987 }
1988
1989 /* Zero extension. From size to dword. */
1990 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1991 {
1992 TCGv t0;
1993 int size = memsize_z(dc);
1994 LOG_DIS("subu.%c $r%u, $r%u\n",
1995 memsize_char(size),
1996 dc->op1, dc->op2);
1997
1998 cris_cc_mask(dc, CC_MASK_NZVC);
1999 t0 = tcg_temp_new();
2000 /* Size can only be qi or hi. */
2001 t_gen_zext(t0, cpu_R[dc->op1], size);
2002 cris_alu(dc, CC_OP_SUB,
2003 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2004 tcg_temp_free(t0);
2005 return 2;
2006 }
2007
2008 /* Sign extension. From size to dword. */
2009 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
2010 {
2011 TCGv t0;
2012 int size = memsize_z(dc);
2013 LOG_DIS("subs.%c $r%u, $r%u\n",
2014 memsize_char(size),
2015 dc->op1, dc->op2);
2016
2017 cris_cc_mask(dc, CC_MASK_NZVC);
2018 t0 = tcg_temp_new();
2019 /* Size can only be qi or hi. */
2020 t_gen_sext(t0, cpu_R[dc->op1], size);
2021 cris_alu(dc, CC_OP_SUB,
2022 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2023 tcg_temp_free(t0);
2024 return 2;
2025 }
2026
2027 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
2028 {
2029 uint32_t flags;
2030 int set = (~dc->opcode >> 2) & 1;
2031
2032
2033 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2034 | EXTRACT_FIELD(dc->ir, 0, 3);
2035 if (set && flags == 0) {
2036 LOG_DIS("nop\n");
2037 return 2;
2038 } else if (!set && (flags & 0x20)) {
2039 LOG_DIS("di\n");
2040 } else {
2041 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
2042 }
2043
2044 /* User space is not allowed to touch these. Silently ignore. */
2045 if (dc->tb_flags & U_FLAG) {
2046 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2047 }
2048
2049 if (flags & X_FLAG) {
2050 dc->flagx_known = 1;
2051 if (set) {
2052 dc->flags_x = X_FLAG;
2053 } else {
2054 dc->flags_x = 0;
2055 }
2056 }
2057
2058 /* Break the TB if any of the SPI flag changes. */
2059 if (flags & (P_FLAG | S_FLAG)) {
2060 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2061 dc->is_jmp = DISAS_UPDATE;
2062 dc->cpustate_changed = 1;
2063 }
2064
2065 /* For the I flag, only act on posedge. */
2066 if ((flags & I_FLAG)) {
2067 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2068 dc->is_jmp = DISAS_UPDATE;
2069 dc->cpustate_changed = 1;
2070 }
2071
2072
2073 /* Simply decode the flags. */
2074 cris_evaluate_flags(dc);
2075 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2076 cris_update_cc_x(dc);
2077 tcg_gen_movi_tl(cc_op, dc->cc_op);
2078
2079 if (set) {
2080 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2081 /* Enter user mode. */
2082 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2083 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2084 dc->cpustate_changed = 1;
2085 }
2086 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2087 } else {
2088 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2089 }
2090
2091 dc->flags_uptodate = 1;
2092 dc->clear_x = 0;
2093 return 2;
2094 }
2095
2096 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2097 {
2098 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2099 cris_cc_mask(dc, 0);
2100 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2101 tcg_const_tl(dc->op1));
2102 return 2;
2103 }
2104 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2105 {
2106 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2107 cris_cc_mask(dc, 0);
2108 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2109 tcg_const_tl(dc->op2));
2110 return 2;
2111 }
2112
2113 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2114 {
2115 TCGv t[2];
2116 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2117 cris_cc_mask(dc, 0);
2118
2119 t[0] = tcg_temp_new();
2120 if (dc->op2 == PR_CCS) {
2121 cris_evaluate_flags(dc);
2122 t_gen_mov_TN_reg(t[0], dc->op1);
2123 if (dc->tb_flags & U_FLAG) {
2124 t[1] = tcg_temp_new();
2125 /* User space is not allowed to touch all flags. */
2126 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2127 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2128 tcg_gen_or_tl(t[0], t[1], t[0]);
2129 tcg_temp_free(t[1]);
2130 }
2131 } else {
2132 t_gen_mov_TN_reg(t[0], dc->op1);
2133 }
2134
2135 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2136 if (dc->op2 == PR_CCS) {
2137 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2138 dc->flags_uptodate = 1;
2139 }
2140 tcg_temp_free(t[0]);
2141 return 2;
2142 }
2143 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2144 {
2145 TCGv t0;
2146 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2147 cris_cc_mask(dc, 0);
2148
2149 if (dc->op2 == PR_CCS) {
2150 cris_evaluate_flags(dc);
2151 }
2152
2153 if (dc->op2 == PR_DZ) {
2154 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2155 } else {
2156 t0 = tcg_temp_new();
2157 t_gen_mov_TN_preg(t0, dc->op2);
2158 cris_alu(dc, CC_OP_MOVE,
2159 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2160 preg_sizes[dc->op2]);
2161 tcg_temp_free(t0);
2162 }
2163 return 2;
2164 }
2165
2166 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2167 {
2168 int memsize = memsize_zz(dc);
2169 int insn_len;
2170 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2171 memsize_char(memsize),
2172 dc->op1, dc->postinc ? "+]" : "]",
2173 dc->op2);
2174
2175 if (memsize == 4) {
2176 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2177 cris_cc_mask(dc, CC_MASK_NZ);
2178 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2179 cris_update_cc_x(dc);
2180 cris_update_result(dc, cpu_R[dc->op2]);
2181 } else {
2182 TCGv t0;
2183
2184 t0 = tcg_temp_new();
2185 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2186 cris_cc_mask(dc, CC_MASK_NZ);
2187 cris_alu(dc, CC_OP_MOVE,
2188 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2189 tcg_temp_free(t0);
2190 }
2191 do_postinc(dc, memsize);
2192 return insn_len;
2193 }
2194
2195 static inline void cris_alu_m_alloc_temps(TCGv *t)
2196 {
2197 t[0] = tcg_temp_new();
2198 t[1] = tcg_temp_new();
2199 }
2200
2201 static inline void cris_alu_m_free_temps(TCGv *t)
2202 {
2203 tcg_temp_free(t[0]);
2204 tcg_temp_free(t[1]);
2205 }
2206
2207 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2208 {
2209 TCGv t[2];
2210 int memsize = memsize_z(dc);
2211 int insn_len;
2212 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2213 memsize_char(memsize),
2214 dc->op1, dc->postinc ? "+]" : "]",
2215 dc->op2);
2216
2217 cris_alu_m_alloc_temps(t);
2218 /* sign extend. */
2219 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2220 cris_cc_mask(dc, CC_MASK_NZ);
2221 cris_alu(dc, CC_OP_MOVE,
2222 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2223 do_postinc(dc, memsize);
2224 cris_alu_m_free_temps(t);
2225 return insn_len;
2226 }
2227
2228 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2229 {
2230 TCGv t[2];
2231 int memsize = memsize_z(dc);
2232 int insn_len;
2233 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2234 memsize_char(memsize),
2235 dc->op1, dc->postinc ? "+]" : "]",
2236 dc->op2);
2237
2238 cris_alu_m_alloc_temps(t);
2239 /* sign extend. */
2240 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2241 cris_cc_mask(dc, CC_MASK_NZVC);
2242 cris_alu(dc, CC_OP_ADD,
2243 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2244 do_postinc(dc, memsize);
2245 cris_alu_m_free_temps(t);
2246 return insn_len;
2247 }
2248
2249 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2250 {
2251 TCGv t[2];
2252 int memsize = memsize_z(dc);
2253 int insn_len;
2254 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2255 memsize_char(memsize),
2256 dc->op1, dc->postinc ? "+]" : "]",
2257 dc->op2);
2258
2259 cris_alu_m_alloc_temps(t);
2260 /* sign extend. */
2261 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2262 cris_cc_mask(dc, CC_MASK_NZVC);
2263 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2264 do_postinc(dc, memsize);
2265 cris_alu_m_free_temps(t);
2266 return insn_len;
2267 }
2268
2269 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2270 {
2271 TCGv t[2];
2272 int memsize = memsize_z(dc);
2273 int insn_len;
2274 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2275 memsize_char(memsize),
2276 dc->op1, dc->postinc ? "+]" : "]",
2277 dc->op2);
2278
2279 cris_alu_m_alloc_temps(t);
2280 /* sign extend. */
2281 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2282 cris_cc_mask(dc, CC_MASK_NZVC);
2283 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2284 do_postinc(dc, memsize);
2285 cris_alu_m_free_temps(t);
2286 return insn_len;
2287 }
2288
2289 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2290 {
2291 TCGv t[2];
2292 int memsize = memsize_z(dc);
2293 int insn_len;
2294 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2295 memsize_char(memsize),
2296 dc->op1, dc->postinc ? "+]" : "]",
2297 dc->op2);
2298
2299 cris_alu_m_alloc_temps(t);
2300 /* sign extend. */
2301 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2302 cris_cc_mask(dc, CC_MASK_NZVC);
2303 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2304 do_postinc(dc, memsize);
2305 cris_alu_m_free_temps(t);
2306 return insn_len;
2307 }
2308
2309 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2310 {
2311 TCGv t[2];
2312 int memsize = memsize_z(dc);
2313 int insn_len;
2314
2315 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2316 memsize_char(memsize),
2317 dc->op1, dc->postinc ? "+]" : "]",
2318 dc->op2);
2319
2320 cris_alu_m_alloc_temps(t);
2321 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2322 cris_cc_mask(dc, CC_MASK_NZ);
2323 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2324 do_postinc(dc, memsize);
2325 cris_alu_m_free_temps(t);
2326 return insn_len;
2327 }
2328
2329 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2330 {
2331 TCGv t[2];
2332 int memsize = memsize_z(dc);
2333 int insn_len;
2334 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2335 memsize_char(memsize),
2336 dc->op1, dc->postinc ? "+]" : "]",
2337 dc->op2);
2338
2339 cris_alu_m_alloc_temps(t);
2340 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2341 cris_cc_mask(dc, CC_MASK_NZVC);
2342 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2343 do_postinc(dc, memsize);
2344 cris_alu_m_free_temps(t);
2345 return insn_len;
2346 }
2347
2348 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2349 {
2350 TCGv t[2];
2351 int memsize = memsize_z(dc);
2352 int insn_len;
2353 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2354 memsize_char(memsize),
2355 dc->op1, dc->postinc ? "+]" : "]",
2356 dc->op2);
2357
2358 cris_alu_m_alloc_temps(t);
2359 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2360 cris_cc_mask(dc, CC_MASK_NZVC);
2361 cris_alu(dc, CC_OP_CMP,
2362 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2363 memsize_zz(dc));
2364 do_postinc(dc, memsize);
2365 cris_alu_m_free_temps(t);
2366 return insn_len;
2367 }
2368
2369 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2370 {
2371 TCGv t[2];
2372 int memsize = memsize_zz(dc);
2373 int insn_len;
2374 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2375 memsize_char(memsize),
2376 dc->op1, dc->postinc ? "+]" : "]",
2377 dc->op2);
2378
2379 cris_alu_m_alloc_temps(t);
2380 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2381 cris_cc_mask(dc, CC_MASK_NZVC);
2382 cris_alu(dc, CC_OP_CMP,
2383 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2384 memsize_zz(dc));
2385 do_postinc(dc, memsize);
2386 cris_alu_m_free_temps(t);
2387 return insn_len;
2388 }
2389
2390 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2391 {
2392 TCGv t[2];
2393 int memsize = memsize_zz(dc);
2394 int insn_len;
2395 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2396 memsize_char(memsize),
2397 dc->op1, dc->postinc ? "+]" : "]",
2398 dc->op2);
2399
2400 cris_evaluate_flags(dc);
2401
2402 cris_alu_m_alloc_temps(t);
2403 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2404 cris_cc_mask(dc, CC_MASK_NZ);
2405 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2406
2407 cris_alu(dc, CC_OP_CMP,
2408 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2409 do_postinc(dc, memsize);
2410 cris_alu_m_free_temps(t);
2411 return insn_len;
2412 }
2413
2414 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2415 {
2416 TCGv t[2];
2417 int memsize = memsize_zz(dc);
2418 int insn_len;
2419 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2420 memsize_char(memsize),
2421 dc->op1, dc->postinc ? "+]" : "]",
2422 dc->op2);
2423
2424 cris_alu_m_alloc_temps(t);
2425 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2426 cris_cc_mask(dc, CC_MASK_NZ);
2427 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2428 do_postinc(dc, memsize);
2429 cris_alu_m_free_temps(t);
2430 return insn_len;
2431 }
2432
2433 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2434 {
2435 TCGv t[2];
2436 int memsize = memsize_zz(dc);
2437 int insn_len;
2438 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2439 memsize_char(memsize),
2440 dc->op1, dc->postinc ? "+]" : "]",
2441 dc->op2);
2442
2443 cris_alu_m_alloc_temps(t);
2444 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2445 cris_cc_mask(dc, CC_MASK_NZVC);
2446 cris_alu(dc, CC_OP_ADD,
2447 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2448 do_postinc(dc, memsize);
2449 cris_alu_m_free_temps(t);
2450 return insn_len;
2451 }
2452
2453 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2454 {
2455 TCGv t[2];
2456 int memsize = memsize_zz(dc);
2457 int insn_len;
2458 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2459 memsize_char(memsize),
2460 dc->op1, dc->postinc ? "+]" : "]",
2461 dc->op2);
2462
2463 cris_alu_m_alloc_temps(t);
2464 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2465 cris_cc_mask(dc, 0);
2466 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2467 do_postinc(dc, memsize);
2468 cris_alu_m_free_temps(t);
2469 return insn_len;
2470 }
2471
2472 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2473 {
2474 TCGv l[2];
2475 int memsize = memsize_zz(dc);
2476 int insn_len;
2477 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2478 memsize_char(memsize),
2479 dc->op1, dc->postinc ? "+]" : "]",
2480 dc->op2);
2481
2482 l[0] = tcg_temp_local_new();
2483 l[1] = tcg_temp_local_new();
2484 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2485 cris_cc_mask(dc, CC_MASK_NZ);
2486 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2487 do_postinc(dc, memsize);
2488 tcg_temp_free(l[0]);
2489 tcg_temp_free(l[1]);
2490 return insn_len;
2491 }
2492
2493 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2494 {
2495 TCGv t[2];
2496 int insn_len = 2;
2497 LOG_DIS("addc [$r%u%s, $r%u\n",
2498 dc->op1, dc->postinc ? "+]" : "]",
2499 dc->op2);
2500
2501 cris_evaluate_flags(dc);
2502
2503 /* Set for this insn. */
2504 dc->flagx_known = 1;
2505 dc->flags_x = X_FLAG;
2506
2507 cris_alu_m_alloc_temps(t);
2508 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2509 cris_cc_mask(dc, CC_MASK_NZVC);
2510 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2511 do_postinc(dc, 4);
2512 cris_alu_m_free_temps(t);
2513 return insn_len;
2514 }
2515
2516 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2517 {
2518 TCGv t[2];
2519 int memsize = memsize_zz(dc);
2520 int insn_len;
2521 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2522 memsize_char(memsize),
2523 dc->op1, dc->postinc ? "+]" : "]",
2524 dc->op2, dc->ir, dc->zzsize);
2525
2526 cris_alu_m_alloc_temps(t);
2527 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2528 cris_cc_mask(dc, CC_MASK_NZVC);
2529 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2530 do_postinc(dc, memsize);
2531 cris_alu_m_free_temps(t);
2532 return insn_len;
2533 }
2534
2535 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2536 {
2537 TCGv t[2];
2538 int memsize = memsize_zz(dc);
2539 int insn_len;
2540 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2541 memsize_char(memsize),
2542 dc->op1, dc->postinc ? "+]" : "]",
2543 dc->op2, dc->pc);
2544
2545 cris_alu_m_alloc_temps(t);
2546 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2547 cris_cc_mask(dc, CC_MASK_NZ);
2548 cris_alu(dc, CC_OP_OR,
2549 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2550 do_postinc(dc, memsize);
2551 cris_alu_m_free_temps(t);
2552 return insn_len;
2553 }
2554
2555 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2556 {
2557 TCGv t[2];
2558 int memsize = memsize_zz(dc);
2559 int insn_len = 2;
2560
2561 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2562 memsize_char(memsize),
2563 dc->op1,
2564 dc->postinc ? "+]" : "]",
2565 dc->op2);
2566
2567 cris_alu_m_alloc_temps(t);
2568 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2569 cris_cc_mask(dc, 0);
2570 if (dc->op2 == PR_CCS) {
2571 cris_evaluate_flags(dc);
2572 if (dc->tb_flags & U_FLAG) {
2573 /* User space is not allowed to touch all flags. */
2574 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2575 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2576 tcg_gen_or_tl(t[1], t[0], t[1]);
2577 }
2578 }
2579
2580 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2581
2582 do_postinc(dc, memsize);
2583 cris_alu_m_free_temps(t);
2584 return insn_len;
2585 }
2586
2587 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2588 {
2589 TCGv t0;
2590 int memsize;
2591
2592 memsize = preg_sizes[dc->op2];
2593
2594 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2595 memsize_char(memsize),
2596 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2597
2598 /* prepare store. Address in T0, value in T1. */
2599 if (dc->op2 == PR_CCS) {
2600 cris_evaluate_flags(dc);
2601 }
2602 t0 = tcg_temp_new();
2603 t_gen_mov_TN_preg(t0, dc->op2);
2604 cris_flush_cc_state(dc);
2605 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2606 tcg_temp_free(t0);
2607
2608 cris_cc_mask(dc, 0);
2609 if (dc->postinc) {
2610 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2611 }
2612 return 2;
2613 }
2614
2615 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2616 {
2617 TCGv_i64 tmp[16];
2618 TCGv tmp32;
2619 TCGv addr;
2620 int i;
2621 int nr = dc->op2 + 1;
2622
2623 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2624 dc->postinc ? "+]" : "]", dc->op2);
2625
2626 addr = tcg_temp_new();
2627 /* There are probably better ways of doing this. */
2628 cris_flush_cc_state(dc);
2629 for (i = 0; i < (nr >> 1); i++) {
2630 tmp[i] = tcg_temp_new_i64();
2631 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2632 gen_load64(dc, tmp[i], addr);
2633 }
2634 if (nr & 1) {
2635 tmp32 = tcg_temp_new_i32();
2636 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2637 gen_load(dc, tmp32, addr, 4, 0);
2638 } else {
2639 TCGV_UNUSED(tmp32);
2640 }
2641 tcg_temp_free(addr);
2642
2643 for (i = 0; i < (nr >> 1); i++) {
2644 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2645 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2646 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2647 tcg_temp_free_i64(tmp[i]);
2648 }
2649 if (nr & 1) {
2650 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2651 tcg_temp_free(tmp32);
2652 }
2653
2654 /* writeback the updated pointer value. */
2655 if (dc->postinc) {
2656 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2657 }
2658
2659 /* gen_load might want to evaluate the previous insns flags. */
2660 cris_cc_mask(dc, 0);
2661 return 2;
2662 }
2663
2664 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2665 {
2666 TCGv tmp;
2667 TCGv addr;
2668 int i;
2669
2670 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2671 dc->postinc ? "+]" : "]");
2672
2673 cris_flush_cc_state(dc);
2674
2675 tmp = tcg_temp_new();
2676 addr = tcg_temp_new();
2677 tcg_gen_movi_tl(tmp, 4);
2678 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2679 for (i = 0; i <= dc->op2; i++) {
2680 /* Displace addr. */
2681 /* Perform the store. */
2682 gen_store(dc, addr, cpu_R[i], 4);
2683 tcg_gen_add_tl(addr, addr, tmp);
2684 }
2685 if (dc->postinc) {
2686 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2687 }
2688 cris_cc_mask(dc, 0);
2689 tcg_temp_free(tmp);
2690 tcg_temp_free(addr);
2691 return 2;
2692 }
2693
2694 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2695 {
2696 int memsize;
2697
2698 memsize = memsize_zz(dc);
2699
2700 LOG_DIS("move.%c $r%u, [$r%u]\n",
2701 memsize_char(memsize), dc->op2, dc->op1);
2702
2703 /* prepare store. */
2704 cris_flush_cc_state(dc);
2705 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2706
2707 if (dc->postinc) {
2708 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2709 }
2710 cris_cc_mask(dc, 0);
2711 return 2;
2712 }
2713
2714 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2715 {
2716 LOG_DIS("lapcq %x, $r%u\n",
2717 dc->pc + dc->op1*2, dc->op2);
2718 cris_cc_mask(dc, 0);
2719 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2720 return 2;
2721 }
2722
2723 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2724 {
2725 unsigned int rd;
2726 int32_t imm;
2727 int32_t pc;
2728
2729 rd = dc->op2;
2730
2731 cris_cc_mask(dc, 0);
2732 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2733 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2734
2735 pc = dc->pc;
2736 pc += imm;
2737 tcg_gen_movi_tl(cpu_R[rd], pc);
2738 return 6;
2739 }
2740
2741 /* Jump to special reg. */
2742 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2743 {
2744 LOG_DIS("jump $p%u\n", dc->op2);
2745
2746 if (dc->op2 == PR_CCS) {
2747 cris_evaluate_flags(dc);
2748 }
2749 t_gen_mov_TN_preg(env_btarget, dc->op2);
2750 /* rete will often have low bit set to indicate delayslot. */
2751 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2752 cris_cc_mask(dc, 0);
2753 cris_prepare_jmp(dc, JMP_INDIRECT);
2754 return 2;
2755 }
2756
2757 /* Jump and save. */
2758 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2759 {
2760 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2761 cris_cc_mask(dc, 0);
2762 /* Store the return address in Pd. */
2763 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2764 if (dc->op2 > 15) {
2765 abort();
2766 }
2767 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2768
2769 cris_prepare_jmp(dc, JMP_INDIRECT);
2770 return 2;
2771 }
2772
2773 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2774 {
2775 uint32_t imm;
2776
2777 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2778
2779 LOG_DIS("jas 0x%x\n", imm);
2780 cris_cc_mask(dc, 0);
2781 /* Store the return address in Pd. */
2782 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2783
2784 dc->jmp_pc = imm;
2785 cris_prepare_jmp(dc, JMP_DIRECT);
2786 return 6;
2787 }
2788
2789 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2790 {
2791 uint32_t imm;
2792
2793 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2794
2795 LOG_DIS("jasc 0x%x\n", imm);
2796 cris_cc_mask(dc, 0);
2797 /* Store the return address in Pd. */
2798 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2799
2800 dc->jmp_pc = imm;
2801 cris_prepare_jmp(dc, JMP_DIRECT);
2802 return 6;
2803 }
2804
2805 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2806 {
2807 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2808 cris_cc_mask(dc, 0);
2809 /* Store the return address in Pd. */
2810 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2811 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2812 cris_prepare_jmp(dc, JMP_INDIRECT);
2813 return 2;
2814 }
2815
2816 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2817 {
2818 int32_t offset;
2819 uint32_t cond = dc->op2;
2820
2821 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2822
2823 LOG_DIS("b%s %d pc=%x dst=%x\n",
2824 cc_name(cond), offset,
2825 dc->pc, dc->pc + offset);
2826
2827 cris_cc_mask(dc, 0);
2828 /* op2 holds the condition-code. */
2829 cris_prepare_cc_branch(dc, offset, cond);
2830 return 4;
2831 }
2832
2833 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2834 {
2835 int32_t simm;
2836
2837 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2838
2839 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2840 cris_cc_mask(dc, 0);
2841 /* Store the return address in Pd. */
2842 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2843
2844 dc->jmp_pc = dc->pc + simm;
2845 cris_prepare_jmp(dc, JMP_DIRECT);
2846 return 6;
2847 }
2848
2849 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2850 {
2851 int32_t simm;
2852 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2853
2854 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2855 cris_cc_mask(dc, 0);
2856 /* Store the return address in Pd. */
2857 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2858
2859 dc->jmp_pc = dc->pc + simm;
2860 cris_prepare_jmp(dc, JMP_DIRECT);
2861 return 6;
2862 }
2863
2864 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2865 {
2866 cris_cc_mask(dc, 0);
2867
2868 if (dc->op2 == 15) {
2869 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2870 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2871 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2872 t_gen_raise_exception(EXCP_HLT);
2873 return 2;
2874 }
2875
2876 switch (dc->op2 & 7) {
2877 case 2:
2878 /* rfe. */
2879 LOG_DIS("rfe\n");
2880 cris_evaluate_flags(dc);
2881 gen_helper_rfe(cpu_env);
2882 dc->is_jmp = DISAS_UPDATE;
2883 break;
2884 case 5:
2885 /* rfn. */
2886 LOG_DIS("rfn\n");
2887 cris_evaluate_flags(dc);
2888 gen_helper_rfn(cpu_env);
2889 dc->is_jmp = DISAS_UPDATE;
2890 break;
2891 case 6:
2892 LOG_DIS("break %d\n", dc->op1);
2893 cris_evaluate_flags(dc);
2894 /* break. */
2895 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2896
2897 /* Breaks start at 16 in the exception vector. */
2898 t_gen_mov_env_TN(trap_vector,
2899 tcg_const_tl(dc->op1 + 16));
2900 t_gen_raise_exception(EXCP_BREAK);
2901 dc->is_jmp = DISAS_UPDATE;
2902 break;
2903 default:
2904 printf("op2=%x\n", dc->op2);
2905 BUG();
2906 break;
2907
2908 }
2909 return 2;
2910 }
2911
2912 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2913 {
2914 return 2;
2915 }
2916
2917 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2918 {
2919 return 2;
2920 }
2921
2922 static int dec_null(CPUCRISState *env, DisasContext *dc)
2923 {
2924 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2925 dc->pc, dc->opcode, dc->op1, dc->op2);
2926 fflush(NULL);
2927 BUG();
2928 return 2;
2929 }
2930
2931 static struct decoder_info {
2932 struct {
2933 uint32_t bits;
2934 uint32_t mask;
2935 };
2936 int (*dec)(CPUCRISState *env, DisasContext *dc);
2937 } decinfo[] = {
2938 /* Order matters here. */
2939 {DEC_MOVEQ, dec_moveq},
2940 {DEC_BTSTQ, dec_btstq},
2941 {DEC_CMPQ, dec_cmpq},
2942 {DEC_ADDOQ, dec_addoq},
2943 {DEC_ADDQ, dec_addq},
2944 {DEC_SUBQ, dec_subq},
2945 {DEC_ANDQ, dec_andq},
2946 {DEC_ORQ, dec_orq},
2947 {DEC_ASRQ, dec_asrq},
2948 {DEC_LSLQ, dec_lslq},
2949 {DEC_LSRQ, dec_lsrq},
2950 {DEC_BCCQ, dec_bccq},
2951
2952 {DEC_BCC_IM, dec_bcc_im},
2953 {DEC_JAS_IM, dec_jas_im},
2954 {DEC_JAS_R, dec_jas_r},
2955 {DEC_JASC_IM, dec_jasc_im},
2956 {DEC_JASC_R, dec_jasc_r},
2957 {DEC_BAS_IM, dec_bas_im},
2958 {DEC_BASC_IM, dec_basc_im},
2959 {DEC_JUMP_P, dec_jump_p},
2960 {DEC_LAPC_IM, dec_lapc_im},
2961 {DEC_LAPCQ, dec_lapcq},
2962
2963 {DEC_RFE_ETC, dec_rfe_etc},
2964 {DEC_ADDC_MR, dec_addc_mr},
2965
2966 {DEC_MOVE_MP, dec_move_mp},
2967 {DEC_MOVE_PM, dec_move_pm},
2968 {DEC_MOVEM_MR, dec_movem_mr},
2969 {DEC_MOVEM_RM, dec_movem_rm},
2970 {DEC_MOVE_PR, dec_move_pr},
2971 {DEC_SCC_R, dec_scc_r},
2972 {DEC_SETF, dec_setclrf},
2973 {DEC_CLEARF, dec_setclrf},
2974
2975 {DEC_MOVE_SR, dec_move_sr},
2976 {DEC_MOVE_RP, dec_move_rp},
2977 {DEC_SWAP_R, dec_swap_r},
2978 {DEC_ABS_R, dec_abs_r},
2979 {DEC_LZ_R, dec_lz_r},
2980 {DEC_MOVE_RS, dec_move_rs},
2981 {DEC_BTST_R, dec_btst_r},
2982 {DEC_ADDC_R, dec_addc_r},
2983
2984 {DEC_DSTEP_R, dec_dstep_r},
2985 {DEC_XOR_R, dec_xor_r},
2986 {DEC_MCP_R, dec_mcp_r},
2987 {DEC_CMP_R, dec_cmp_r},
2988
2989 {DEC_ADDI_R, dec_addi_r},
2990 {DEC_ADDI_ACR, dec_addi_acr},
2991
2992 {DEC_ADD_R, dec_add_r},
2993 {DEC_SUB_R, dec_sub_r},
2994
2995 {DEC_ADDU_R, dec_addu_r},
2996 {DEC_ADDS_R, dec_adds_r},
2997 {DEC_SUBU_R, dec_subu_r},
2998 {DEC_SUBS_R, dec_subs_r},
2999 {DEC_LSL_R, dec_lsl_r},
3000
3001 {DEC_AND_R, dec_and_r},
3002 {DEC_OR_R, dec_or_r},
3003 {DEC_BOUND_R, dec_bound_r},
3004 {DEC_ASR_R, dec_asr_r},
3005 {DEC_LSR_R, dec_lsr_r},
3006
3007 {DEC_MOVU_R, dec_movu_r},
3008 {DEC_MOVS_R, dec_movs_r},
3009 {DEC_NEG_R, dec_neg_r},
3010 {DEC_MOVE_R, dec_move_r},
3011
3012 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3013 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3014
3015 {DEC_MULS_R, dec_muls_r},
3016 {DEC_MULU_R, dec_mulu_r},
3017
3018 {DEC_ADDU_M, dec_addu_m},
3019 {DEC_ADDS_M, dec_adds_m},
3020 {DEC_SUBU_M, dec_subu_m},
3021 {DEC_SUBS_M, dec_subs_m},
3022
3023 {DEC_CMPU_M, dec_cmpu_m},
3024 {DEC_CMPS_M, dec_cmps_m},
3025 {DEC_MOVU_M, dec_movu_m},
3026 {DEC_MOVS_M, dec_movs_m},
3027
3028 {DEC_CMP_M, dec_cmp_m},
3029 {DEC_ADDO_M, dec_addo_m},
3030 {DEC_BOUND_M, dec_bound_m},
3031 {DEC_ADD_M, dec_add_m},
3032 {DEC_SUB_M, dec_sub_m},
3033 {DEC_AND_M, dec_and_m},
3034 {DEC_OR_M, dec_or_m},
3035 {DEC_MOVE_RM, dec_move_rm},
3036 {DEC_TEST_M, dec_test_m},
3037 {DEC_MOVE_MR, dec_move_mr},
3038
3039 {{0, 0}, dec_null}
3040 };
3041
3042 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
3043 {
3044 int insn_len = 2;
3045 int i;
3046
3047 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
3048 tcg_gen_debug_insn_start(dc->pc);
3049 }
3050
3051 /* Load a halfword onto the instruction register. */
3052 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3053
3054 /* Now decode it. */
3055 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3056 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3057 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3058 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3059 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3060 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3061
3062 /* Large switch for all insns. */
3063 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3064 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3065 insn_len = decinfo[i].dec(env, dc);
3066 break;
3067 }
3068 }
3069
3070 #if !defined(CONFIG_USER_ONLY)
3071 /* Single-stepping ? */
3072 if (dc->tb_flags & S_FLAG) {
3073 int l1;
3074
3075 l1 = gen_new_label();
3076 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3077 /* We treat SPC as a break with an odd trap vector. */
3078 cris_evaluate_flags(dc);
3079 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3080 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3081 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3082 t_gen_raise_exception(EXCP_BREAK);
3083 gen_set_label(l1);
3084 }
3085 #endif
3086 return insn_len;
3087 }
3088
3089 static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
3090 {
3091 CPUState *cs = CPU(cris_env_get_cpu(env));
3092 CPUBreakpoint *bp;
3093
3094 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
3095 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
3096 if (bp->pc == dc->pc) {
3097 cris_evaluate_flags(dc);
3098 tcg_gen_movi_tl(env_pc, dc->pc);
3099 t_gen_raise_exception(EXCP_DEBUG);
3100 dc->is_jmp = DISAS_UPDATE;
3101 }
3102 }
3103 }
3104 }
3105
3106 #include "translate_v10.c"
3107
3108 /*
3109 * Delay slots on QEMU/CRIS.
3110 *
3111 * If an exception hits on a delayslot, the core will let ERP (the Exception
3112 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3113 * to give SW a hint that the exception actually hit on the dslot.
3114 *
3115 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3116 * the core and any jmp to an odd addresses will mask off that lsb. It is
3117 * simply there to let sw know there was an exception on a dslot.
3118 *
3119 * When the software returns from an exception, the branch will re-execute.
3120 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3121 * and the branch and delayslot dont share pages.
3122 *
3123 * The TB contaning the branch insn will set up env->btarget and evaluate
3124 * env->btaken. When the translation loop exits we will note that the branch
3125 * sequence is broken and let env->dslot be the size of the branch insn (those
3126 * vary in length).
3127 *
3128 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3129 * set). It will also expect to have env->dslot setup with the size of the
3130 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3131 * will execute the dslot and take the branch, either to btarget or just one
3132 * insn ahead.
3133 *
3134 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3135 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3136 * branch and set lsb). Then env->dslot gets cleared so that the exception
3137 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3138 * masked off and we will reexecute the branch insn.
3139 *
3140 */
3141
3142 /* generate intermediate code for basic block 'tb'. */
3143 static inline void
3144 gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
3145 bool search_pc)
3146 {
3147 CPUState *cs = CPU(cpu);
3148 CPUCRISState *env = &cpu->env;
3149 uint16_t *gen_opc_end;
3150 uint32_t pc_start;
3151 unsigned int insn_len;
3152 int j, lj;
3153 struct DisasContext ctx;
3154 struct DisasContext *dc = &ctx;
3155 uint32_t next_page_start;
3156 target_ulong npc;
3157 int num_insns;
3158 int max_insns;
3159
3160 if (env->pregs[PR_VR] == 32) {
3161 dc->decoder = crisv32_decoder;
3162 dc->clear_locked_irq = 0;
3163 } else {
3164 dc->decoder = crisv10_decoder;
3165 dc->clear_locked_irq = 1;
3166 }
3167
3168 /* Odd PC indicates that branch is rexecuting due to exception in the
3169 * delayslot, like in real hw.
3170 */
3171 pc_start = tb->pc & ~1;
3172 dc->cpu = cpu;
3173 dc->tb = tb;
3174
3175 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
3176
3177 dc->is_jmp = DISAS_NEXT;
3178 dc->ppc = pc_start;
3179 dc->pc = pc_start;
3180 dc->singlestep_enabled = cs->singlestep_enabled;
3181 dc->flags_uptodate = 1;
3182 dc->flagx_known = 1;
3183 dc->flags_x = tb->flags & X_FLAG;
3184 dc->cc_x_uptodate = 0;
3185 dc->cc_mask = 0;
3186 dc->update_cc = 0;
3187 dc->clear_prefix = 0;
3188
3189 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3190 dc->cc_size_uptodate = -1;
3191
3192 /* Decode TB flags. */
3193 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3194 | X_FLAG | PFIX_FLAG);
3195 dc->delayed_branch = !!(tb->flags & 7);
3196 if (dc->delayed_branch) {
3197 dc->jmp = JMP_INDIRECT;
3198 } else {
3199 dc->jmp = JMP_NOJMP;
3200 }
3201
3202 dc->cpustate_changed = 0;
3203
3204 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3205 qemu_log(
3206 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3207 "pid=%x usp=%x\n"
3208 "%x.%x.%x.%x\n"
3209 "%x.%x.%x.%x\n"
3210 "%x.%x.%x.%x\n"
3211 "%x.%x.%x.%x\n",
3212 search_pc, dc->pc, dc->ppc,
3213 (uint64_t)tb->flags,
3214 env->btarget, (unsigned)tb->flags & 7,
3215 env->pregs[PR_CCS],
3216 env->pregs[PR_PID], env->pregs[PR_USP],
3217 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3218 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3219 env->regs[8], env->regs[9],
3220 env->regs[10], env->regs[11],
3221 env->regs[12], env->regs[13],
3222 env->regs[14], env->regs[15]);
3223 qemu_log("--------------\n");
3224 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3225 }
3226
3227 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3228 lj = -1;
3229 num_insns = 0;
3230 max_insns = tb->cflags & CF_COUNT_MASK;
3231 if (max_insns == 0) {
3232 max_insns = CF_COUNT_MASK;
3233 }
3234
3235 gen_tb_start();
3236 do {
3237 check_breakpoint(env, dc);
3238
3239 if (search_pc) {
3240 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3241 if (lj < j) {
3242 lj++;
3243 while (lj < j) {
3244 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3245 }
3246 }
3247 if (dc->delayed_branch == 1) {
3248 tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1;
3249 } else {
3250 tcg_ctx.gen_opc_pc[lj] = dc->pc;
3251 }
3252 tcg_ctx.gen_opc_instr_start[lj] = 1;
3253 tcg_ctx.gen_opc_icount[lj] = num_insns;
3254 }
3255
3256 /* Pretty disas. */
3257 LOG_DIS("%8.8x:\t", dc->pc);
3258
3259 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3260 gen_io_start();
3261 }
3262 dc->clear_x = 1;
3263
3264 insn_len = dc->decoder(env, dc);
3265 dc->ppc = dc->pc;
3266 dc->pc += insn_len;
3267 if (dc->clear_x) {
3268 cris_clear_x_flag(dc);
3269 }
3270
3271 num_insns++;
3272 /* Check for delayed branches here. If we do it before
3273 actually generating any host code, the simulator will just
3274 loop doing nothing for on this program location. */
3275 if (dc->delayed_branch) {
3276 dc->delayed_branch--;
3277 if (dc->delayed_branch == 0) {
3278 if (tb->flags & 7) {
3279 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3280 }
3281 if (dc->cpustate_changed || !dc->flagx_known
3282 || (dc->flags_x != (tb->flags & X_FLAG))) {
3283 cris_store_direct_jmp(dc);
3284 }
3285
3286 if (dc->clear_locked_irq) {
3287 dc->clear_locked_irq = 0;
3288 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3289 }
3290
3291 if (dc->jmp == JMP_DIRECT_CC) {
3292 int l1;
3293
3294 l1 = gen_new_label();
3295 cris_evaluate_flags(dc);
3296
3297 /* Conditional jmp. */
3298 tcg_gen_brcondi_tl(TCG_COND_EQ,
3299 env_btaken, 0, l1);
3300 gen_goto_tb(dc, 1, dc->jmp_pc);
3301 gen_set_label(l1);
3302 gen_goto_tb(dc, 0, dc->pc);
3303 dc->is_jmp = DISAS_TB_JUMP;
3304 dc->jmp = JMP_NOJMP;
3305 } else if (dc->jmp == JMP_DIRECT) {
3306 cris_evaluate_flags(dc);
3307 gen_goto_tb(dc, 0, dc->jmp_pc);
3308 dc->is_jmp = DISAS_TB_JUMP;
3309 dc->jmp = JMP_NOJMP;
3310 } else {
3311 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3312 dc->is_jmp = DISAS_JUMP;
3313 }
3314 break;
3315 }
3316 }
3317
3318 /* If we are rexecuting a branch due to exceptions on
3319 delay slots dont break. */
3320 if (!(tb->pc & 1) && cs->singlestep_enabled) {
3321 break;
3322 }
3323 } while (!dc->is_jmp && !dc->cpustate_changed
3324 && tcg_ctx.gen_opc_ptr < gen_opc_end
3325 && !singlestep
3326 && (dc->pc < next_page_start)
3327 && num_insns < max_insns);
3328
3329 if (dc->clear_locked_irq) {
3330 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3331 }
3332
3333 npc = dc->pc;
3334
3335 if (tb->cflags & CF_LAST_IO)
3336 gen_io_end();
3337 /* Force an update if the per-tb cpu state has changed. */
3338 if (dc->is_jmp == DISAS_NEXT
3339 && (dc->cpustate_changed || !dc->flagx_known
3340 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3341 dc->is_jmp = DISAS_UPDATE;
3342 tcg_gen_movi_tl(env_pc, npc);
3343 }
3344 /* Broken branch+delayslot sequence. */
3345 if (dc->delayed_branch == 1) {
3346 /* Set env->dslot to the size of the branch insn. */
3347 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3348 cris_store_direct_jmp(dc);
3349 }
3350
3351 cris_evaluate_flags(dc);
3352
3353 if (unlikely(cs->singlestep_enabled)) {
3354 if (dc->is_jmp == DISAS_NEXT) {
3355 tcg_gen_movi_tl(env_pc, npc);
3356 }
3357 t_gen_raise_exception(EXCP_DEBUG);
3358 } else {
3359 switch (dc->is_jmp) {
3360 case DISAS_NEXT:
3361 gen_goto_tb(dc, 1, npc);
3362 break;
3363 default:
3364 case DISAS_JUMP:
3365 case DISAS_UPDATE:
3366 /* indicate that the hash table must be used
3367 to find the next TB */
3368 tcg_gen_exit_tb(0);
3369 break;
3370 case DISAS_SWI:
3371 case DISAS_TB_JUMP:
3372 /* nothing more to generate */
3373 break;
3374 }
3375 }
3376 gen_tb_end(tb, num_insns);
3377 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3378 if (search_pc) {
3379 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3380 lj++;
3381 while (lj <= j) {
3382 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3383 }
3384 } else {
3385 tb->size = dc->pc - pc_start;
3386 tb->icount = num_insns;
3387 }
3388
3389 #ifdef DEBUG_DISAS
3390 #if !DISAS_CRIS
3391 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3392 log_target_disas(env, pc_start, dc->pc - pc_start,
3393 env->pregs[PR_VR]);
3394 qemu_log("\nisize=%d osize=%td\n",
3395 dc->pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf);
3396 }
3397 #endif
3398 #endif
3399 }
3400
3401 void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb)
3402 {
3403 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, false);
3404 }
3405
3406 void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb)
3407 {
3408 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, true);
3409 }
3410
3411 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3412 int flags)
3413 {
3414 CRISCPU *cpu = CRIS_CPU(cs);
3415 CPUCRISState *env = &cpu->env;
3416 int i;
3417 uint32_t srs;
3418
3419 if (!env || !f) {
3420 return;
3421 }
3422
3423 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3424 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3425 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3426 env->cc_op,
3427 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3428
3429
3430 for (i = 0; i < 16; i++) {
3431 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3432 if ((i + 1) % 4 == 0) {
3433 cpu_fprintf(f, "\n");
3434 }
3435 }
3436 cpu_fprintf(f, "\nspecial regs:\n");
3437 for (i = 0; i < 16; i++) {
3438 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3439 if ((i + 1) % 4 == 0) {
3440 cpu_fprintf(f, "\n");
3441 }
3442 }
3443 srs = env->pregs[PR_SRS];
3444 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3445 if (srs < ARRAY_SIZE(env->sregs)) {
3446 for (i = 0; i < 16; i++) {
3447 cpu_fprintf(f, "s%2.2d=%8.8x ",
3448 i, env->sregs[srs][i]);
3449 if ((i + 1) % 4 == 0) {
3450 cpu_fprintf(f, "\n");
3451 }
3452 }
3453 }
3454 cpu_fprintf(f, "\n\n");
3455
3456 }
3457
3458 void cris_initialize_tcg(void)
3459 {
3460 int i;
3461
3462 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3463 cc_x = tcg_global_mem_new(TCG_AREG0,
3464 offsetof(CPUCRISState, cc_x), "cc_x");
3465 cc_src = tcg_global_mem_new(TCG_AREG0,
3466 offsetof(CPUCRISState, cc_src), "cc_src");
3467 cc_dest = tcg_global_mem_new(TCG_AREG0,
3468 offsetof(CPUCRISState, cc_dest),
3469 "cc_dest");
3470 cc_result = tcg_global_mem_new(TCG_AREG0,
3471 offsetof(CPUCRISState, cc_result),
3472 "cc_result");
3473 cc_op = tcg_global_mem_new(TCG_AREG0,
3474 offsetof(CPUCRISState, cc_op), "cc_op");
3475 cc_size = tcg_global_mem_new(TCG_AREG0,
3476 offsetof(CPUCRISState, cc_size),
3477 "cc_size");
3478 cc_mask = tcg_global_mem_new(TCG_AREG0,
3479 offsetof(CPUCRISState, cc_mask),
3480 "cc_mask");
3481
3482 env_pc = tcg_global_mem_new(TCG_AREG0,
3483 offsetof(CPUCRISState, pc),
3484 "pc");
3485 env_btarget = tcg_global_mem_new(TCG_AREG0,
3486 offsetof(CPUCRISState, btarget),
3487 "btarget");
3488 env_btaken = tcg_global_mem_new(TCG_AREG0,
3489 offsetof(CPUCRISState, btaken),
3490 "btaken");
3491 for (i = 0; i < 16; i++) {
3492 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3493 offsetof(CPUCRISState, regs[i]),
3494 regnames[i]);
3495 }
3496 for (i = 0; i < 16; i++) {
3497 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3498 offsetof(CPUCRISState, pregs[i]),
3499 pregnames[i]);
3500 }
3501 }
3502
3503 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
3504 {
3505 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3506 }
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