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[qemu.git] / target-cris / translate.c
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
20 */
21
22 /*
23 * FIXME:
24 * The condition code translation is in need of attention.
25 */
26
27 #include <stdarg.h>
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <string.h>
31 #include <inttypes.h>
32 #include <assert.h>
33
34 #include "cpu.h"
35 #include "exec-all.h"
36 #include "disas.h"
37 #include "tcg-op.h"
38 #include "helper.h"
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
41
42 #define GEN_HELPER 1
43 #include "helper.h"
44
45 #define DISAS_CRIS 0
46 #if DISAS_CRIS
47 #define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
48 #else
49 #define DIS(x)
50 #endif
51
52 #define D(x)
53 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
54 #define BUG_ON(x) ({if (x) BUG();})
55
56 #define DISAS_SWI 5
57
58 /* Used by the decoder. */
59 #define EXTRACT_FIELD(src, start, end) \
60 (((src) >> start) & ((1 << (end - start + 1)) - 1))
61
62 #define CC_MASK_NZ 0xc
63 #define CC_MASK_NZV 0xe
64 #define CC_MASK_NZVC 0xf
65 #define CC_MASK_RNZV 0x10e
66
67 static TCGv_ptr cpu_env;
68 static TCGv cpu_R[16];
69 static TCGv cpu_PR[16];
70 static TCGv cc_x;
71 static TCGv cc_src;
72 static TCGv cc_dest;
73 static TCGv cc_result;
74 static TCGv cc_op;
75 static TCGv cc_size;
76 static TCGv cc_mask;
77
78 static TCGv env_btaken;
79 static TCGv env_btarget;
80 static TCGv env_pc;
81
82 #include "gen-icount.h"
83
84 /* This is the state at translation time. */
85 typedef struct DisasContext {
86 CPUState *env;
87 target_ulong pc, ppc;
88
89 /* Decoder. */
90 uint32_t ir;
91 uint32_t opcode;
92 unsigned int op1;
93 unsigned int op2;
94 unsigned int zsize, zzsize;
95 unsigned int mode;
96 unsigned int postinc;
97
98 int update_cc;
99 int cc_op;
100 int cc_size;
101 uint32_t cc_mask;
102
103 int cc_size_uptodate; /* -1 invalid or last written value. */
104
105 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
106 int flags_uptodate; /* Wether or not $ccs is uptodate. */
107 int flagx_known; /* Wether or not flags_x has the x flag known at
108 translation time. */
109 int flags_x;
110
111 int clear_x; /* Clear x after this insn? */
112 int cpustate_changed;
113 unsigned int tb_flags; /* tb dependent flags. */
114 int is_jmp;
115
116 #define JMP_NOJMP 0
117 #define JMP_DIRECT 1
118 #define JMP_INDIRECT 2
119 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
120 uint32_t jmp_pc;
121
122 int delayed_branch;
123
124 struct TranslationBlock *tb;
125 int singlestep_enabled;
126 } DisasContext;
127
128 static void gen_BUG(DisasContext *dc, const char *file, int line)
129 {
130 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
131 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
132 cpu_abort(dc->env, "%s:%d\n", file, line);
133 }
134
135 static const char *regnames[] =
136 {
137 "$r0", "$r1", "$r2", "$r3",
138 "$r4", "$r5", "$r6", "$r7",
139 "$r8", "$r9", "$r10", "$r11",
140 "$r12", "$r13", "$sp", "$acr",
141 };
142 static const char *pregnames[] =
143 {
144 "$bz", "$vr", "$pid", "$srs",
145 "$wz", "$exs", "$eda", "$mof",
146 "$dz", "$ebp", "$erp", "$srp",
147 "$nrp", "$ccs", "$usp", "$spc",
148 };
149
150 /* We need this table to handle preg-moves with implicit width. */
151 static int preg_sizes[] = {
152 1, /* bz. */
153 1, /* vr. */
154 4, /* pid. */
155 1, /* srs. */
156 2, /* wz. */
157 4, 4, 4,
158 4, 4, 4, 4,
159 4, 4, 4, 4,
160 };
161
162 #define t_gen_mov_TN_env(tn, member) \
163 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
164 #define t_gen_mov_env_TN(member, tn) \
165 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
166
167 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
168 {
169 if (r < 0 || r > 15)
170 fprintf(stderr, "wrong register read $r%d\n", r);
171 tcg_gen_mov_tl(tn, cpu_R[r]);
172 }
173 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
174 {
175 if (r < 0 || r > 15)
176 fprintf(stderr, "wrong register write $r%d\n", r);
177 tcg_gen_mov_tl(cpu_R[r], tn);
178 }
179
180 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
181 {
182 if (offset > sizeof (CPUState))
183 fprintf(stderr, "wrong load from env from off=%d\n", offset);
184 tcg_gen_ld_tl(tn, cpu_env, offset);
185 }
186 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
187 {
188 if (offset > sizeof (CPUState))
189 fprintf(stderr, "wrong store to env at off=%d\n", offset);
190 tcg_gen_st_tl(tn, cpu_env, offset);
191 }
192
193 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
194 {
195 if (r < 0 || r > 15)
196 fprintf(stderr, "wrong register read $p%d\n", r);
197 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
198 tcg_gen_mov_tl(tn, tcg_const_tl(0));
199 else if (r == PR_VR)
200 tcg_gen_mov_tl(tn, tcg_const_tl(32));
201 else if (r == PR_EDA) {
202 printf("read from EDA!\n");
203 tcg_gen_mov_tl(tn, cpu_PR[r]);
204 }
205 else
206 tcg_gen_mov_tl(tn, cpu_PR[r]);
207 }
208 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
209 {
210 if (r < 0 || r > 15)
211 fprintf(stderr, "wrong register write $p%d\n", r);
212 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
213 return;
214 else if (r == PR_SRS)
215 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
216 else {
217 if (r == PR_PID)
218 gen_helper_tlb_flush_pid(tn);
219 if (dc->tb_flags & S_FLAG && r == PR_SPC)
220 gen_helper_spc_write(tn);
221 else if (r == PR_CCS)
222 dc->cpustate_changed = 1;
223 tcg_gen_mov_tl(cpu_PR[r], tn);
224 }
225 }
226
227 static inline void t_gen_raise_exception(uint32_t index)
228 {
229 TCGv_i32 tmp = tcg_const_i32(index);
230 gen_helper_raise_exception(tmp);
231 tcg_temp_free_i32(tmp);
232 }
233
234 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
235 {
236 TCGv t0, t_31;
237
238 t0 = tcg_temp_new();
239 t_31 = tcg_const_tl(31);
240 tcg_gen_shl_tl(d, a, b);
241
242 tcg_gen_sub_tl(t0, t_31, b);
243 tcg_gen_sar_tl(t0, t0, t_31);
244 tcg_gen_and_tl(t0, t0, d);
245 tcg_gen_xor_tl(d, d, t0);
246 tcg_temp_free(t0);
247 tcg_temp_free(t_31);
248 }
249
250 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
251 {
252 TCGv t0, t_31;
253
254 t0 = tcg_temp_new();
255 t_31 = tcg_temp_new();
256 tcg_gen_shr_tl(d, a, b);
257
258 tcg_gen_movi_tl(t_31, 31);
259 tcg_gen_sub_tl(t0, t_31, b);
260 tcg_gen_sar_tl(t0, t0, t_31);
261 tcg_gen_and_tl(t0, t0, d);
262 tcg_gen_xor_tl(d, d, t0);
263 tcg_temp_free(t0);
264 tcg_temp_free(t_31);
265 }
266
267 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
268 {
269 TCGv t0, t_31;
270
271 t0 = tcg_temp_new();
272 t_31 = tcg_temp_new();
273 tcg_gen_sar_tl(d, a, b);
274
275 tcg_gen_movi_tl(t_31, 31);
276 tcg_gen_sub_tl(t0, t_31, b);
277 tcg_gen_sar_tl(t0, t0, t_31);
278 tcg_gen_or_tl(d, d, t0);
279 tcg_temp_free(t0);
280 tcg_temp_free(t_31);
281 }
282
283 /* 64-bit signed mul, lower result in d and upper in d2. */
284 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
285 {
286 TCGv_i64 t0, t1;
287
288 t0 = tcg_temp_new_i64();
289 t1 = tcg_temp_new_i64();
290
291 tcg_gen_ext_i32_i64(t0, a);
292 tcg_gen_ext_i32_i64(t1, b);
293 tcg_gen_mul_i64(t0, t0, t1);
294
295 tcg_gen_trunc_i64_i32(d, t0);
296 tcg_gen_shri_i64(t0, t0, 32);
297 tcg_gen_trunc_i64_i32(d2, t0);
298
299 tcg_temp_free_i64(t0);
300 tcg_temp_free_i64(t1);
301 }
302
303 /* 64-bit unsigned muls, lower result in d and upper in d2. */
304 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
305 {
306 TCGv_i64 t0, t1;
307
308 t0 = tcg_temp_new_i64();
309 t1 = tcg_temp_new_i64();
310
311 tcg_gen_extu_i32_i64(t0, a);
312 tcg_gen_extu_i32_i64(t1, b);
313 tcg_gen_mul_i64(t0, t0, t1);
314
315 tcg_gen_trunc_i64_i32(d, t0);
316 tcg_gen_shri_i64(t0, t0, 32);
317 tcg_gen_trunc_i64_i32(d2, t0);
318
319 tcg_temp_free_i64(t0);
320 tcg_temp_free_i64(t1);
321 }
322
323 /* 32bit branch-free binary search for counting leading zeros. */
324 static void t_gen_lz_i32(TCGv d, TCGv x)
325 {
326 TCGv_i32 y, m, n;
327
328 y = tcg_temp_new_i32();
329 m = tcg_temp_new_i32();
330 n = tcg_temp_new_i32();
331
332 /* y = -(x >> 16) */
333 tcg_gen_shri_i32(y, x, 16);
334 tcg_gen_neg_i32(y, y);
335
336 /* m = (y >> 16) & 16 */
337 tcg_gen_sari_i32(m, y, 16);
338 tcg_gen_andi_i32(m, m, 16);
339
340 /* n = 16 - m */
341 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
342 /* x = x >> m */
343 tcg_gen_shr_i32(x, x, m);
344
345 /* y = x - 0x100 */
346 tcg_gen_subi_i32(y, x, 0x100);
347 /* m = (y >> 16) & 8 */
348 tcg_gen_sari_i32(m, y, 16);
349 tcg_gen_andi_i32(m, m, 8);
350 /* n = n + m */
351 tcg_gen_add_i32(n, n, m);
352 /* x = x << m */
353 tcg_gen_shl_i32(x, x, m);
354
355 /* y = x - 0x1000 */
356 tcg_gen_subi_i32(y, x, 0x1000);
357 /* m = (y >> 16) & 4 */
358 tcg_gen_sari_i32(m, y, 16);
359 tcg_gen_andi_i32(m, m, 4);
360 /* n = n + m */
361 tcg_gen_add_i32(n, n, m);
362 /* x = x << m */
363 tcg_gen_shl_i32(x, x, m);
364
365 /* y = x - 0x4000 */
366 tcg_gen_subi_i32(y, x, 0x4000);
367 /* m = (y >> 16) & 2 */
368 tcg_gen_sari_i32(m, y, 16);
369 tcg_gen_andi_i32(m, m, 2);
370 /* n = n + m */
371 tcg_gen_add_i32(n, n, m);
372 /* x = x << m */
373 tcg_gen_shl_i32(x, x, m);
374
375 /* y = x >> 14 */
376 tcg_gen_shri_i32(y, x, 14);
377 /* m = y & ~(y >> 1) */
378 tcg_gen_sari_i32(m, y, 1);
379 tcg_gen_not_i32(m, m);
380 tcg_gen_and_i32(m, m, y);
381
382 /* d = n + 2 - m */
383 tcg_gen_addi_i32(d, n, 2);
384 tcg_gen_sub_i32(d, d, m);
385
386 tcg_temp_free(y);
387 tcg_temp_free(m);
388 tcg_temp_free(n);
389 }
390
391 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
392 {
393 int l1;
394
395 l1 = gen_new_label();
396
397 /*
398 * d <<= 1
399 * if (d >= s)
400 * d -= s;
401 */
402 tcg_gen_shli_tl(d, a, 1);
403 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
404 tcg_gen_sub_tl(d, d, b);
405 gen_set_label(l1);
406 }
407
408 /* Extended arithmetics on CRIS. */
409 static inline void t_gen_add_flag(TCGv d, int flag)
410 {
411 TCGv c;
412
413 c = tcg_temp_new();
414 t_gen_mov_TN_preg(c, PR_CCS);
415 /* Propagate carry into d. */
416 tcg_gen_andi_tl(c, c, 1 << flag);
417 if (flag)
418 tcg_gen_shri_tl(c, c, flag);
419 tcg_gen_add_tl(d, d, c);
420 tcg_temp_free(c);
421 }
422
423 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
424 {
425 if (dc->flagx_known) {
426 if (dc->flags_x) {
427 TCGv c;
428
429 c = tcg_temp_new();
430 t_gen_mov_TN_preg(c, PR_CCS);
431 /* C flag is already at bit 0. */
432 tcg_gen_andi_tl(c, c, C_FLAG);
433 tcg_gen_add_tl(d, d, c);
434 tcg_temp_free(c);
435 }
436 } else {
437 TCGv x, c;
438
439 x = tcg_temp_new();
440 c = tcg_temp_new();
441 t_gen_mov_TN_preg(x, PR_CCS);
442 tcg_gen_mov_tl(c, x);
443
444 /* Propagate carry into d if X is set. Branch free. */
445 tcg_gen_andi_tl(c, c, C_FLAG);
446 tcg_gen_andi_tl(x, x, X_FLAG);
447 tcg_gen_shri_tl(x, x, 4);
448
449 tcg_gen_and_tl(x, x, c);
450 tcg_gen_add_tl(d, d, x);
451 tcg_temp_free(x);
452 tcg_temp_free(c);
453 }
454 }
455
456 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
457 {
458 if (dc->flagx_known) {
459 if (dc->flags_x) {
460 TCGv c;
461
462 c = tcg_temp_new();
463 t_gen_mov_TN_preg(c, PR_CCS);
464 /* C flag is already at bit 0. */
465 tcg_gen_andi_tl(c, c, C_FLAG);
466 tcg_gen_sub_tl(d, d, c);
467 tcg_temp_free(c);
468 }
469 } else {
470 TCGv x, c;
471
472 x = tcg_temp_new();
473 c = tcg_temp_new();
474 t_gen_mov_TN_preg(x, PR_CCS);
475 tcg_gen_mov_tl(c, x);
476
477 /* Propagate carry into d if X is set. Branch free. */
478 tcg_gen_andi_tl(c, c, C_FLAG);
479 tcg_gen_andi_tl(x, x, X_FLAG);
480 tcg_gen_shri_tl(x, x, 4);
481
482 tcg_gen_and_tl(x, x, c);
483 tcg_gen_sub_tl(d, d, x);
484 tcg_temp_free(x);
485 tcg_temp_free(c);
486 }
487 }
488
489 /* Swap the two bytes within each half word of the s operand.
490 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
491 static inline void t_gen_swapb(TCGv d, TCGv s)
492 {
493 TCGv t, org_s;
494
495 t = tcg_temp_new();
496 org_s = tcg_temp_new();
497
498 /* d and s may refer to the same object. */
499 tcg_gen_mov_tl(org_s, s);
500 tcg_gen_shli_tl(t, org_s, 8);
501 tcg_gen_andi_tl(d, t, 0xff00ff00);
502 tcg_gen_shri_tl(t, org_s, 8);
503 tcg_gen_andi_tl(t, t, 0x00ff00ff);
504 tcg_gen_or_tl(d, d, t);
505 tcg_temp_free(t);
506 tcg_temp_free(org_s);
507 }
508
509 /* Swap the halfwords of the s operand. */
510 static inline void t_gen_swapw(TCGv d, TCGv s)
511 {
512 TCGv t;
513 /* d and s refer the same object. */
514 t = tcg_temp_new();
515 tcg_gen_mov_tl(t, s);
516 tcg_gen_shli_tl(d, t, 16);
517 tcg_gen_shri_tl(t, t, 16);
518 tcg_gen_or_tl(d, d, t);
519 tcg_temp_free(t);
520 }
521
522 /* Reverse the within each byte.
523 T0 = (((T0 << 7) & 0x80808080) |
524 ((T0 << 5) & 0x40404040) |
525 ((T0 << 3) & 0x20202020) |
526 ((T0 << 1) & 0x10101010) |
527 ((T0 >> 1) & 0x08080808) |
528 ((T0 >> 3) & 0x04040404) |
529 ((T0 >> 5) & 0x02020202) |
530 ((T0 >> 7) & 0x01010101));
531 */
532 static inline void t_gen_swapr(TCGv d, TCGv s)
533 {
534 struct {
535 int shift; /* LSL when positive, LSR when negative. */
536 uint32_t mask;
537 } bitrev [] = {
538 {7, 0x80808080},
539 {5, 0x40404040},
540 {3, 0x20202020},
541 {1, 0x10101010},
542 {-1, 0x08080808},
543 {-3, 0x04040404},
544 {-5, 0x02020202},
545 {-7, 0x01010101}
546 };
547 int i;
548 TCGv t, org_s;
549
550 /* d and s refer the same object. */
551 t = tcg_temp_new();
552 org_s = tcg_temp_new();
553 tcg_gen_mov_tl(org_s, s);
554
555 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
556 tcg_gen_andi_tl(d, t, bitrev[0].mask);
557 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
558 if (bitrev[i].shift >= 0) {
559 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
560 } else {
561 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
562 }
563 tcg_gen_andi_tl(t, t, bitrev[i].mask);
564 tcg_gen_or_tl(d, d, t);
565 }
566 tcg_temp_free(t);
567 tcg_temp_free(org_s);
568 }
569
570 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
571 {
572 TCGv btaken;
573 int l1;
574
575 l1 = gen_new_label();
576 btaken = tcg_temp_new();
577
578 /* Conditional jmp. */
579 tcg_gen_mov_tl(btaken, env_btaken);
580 tcg_gen_mov_tl(env_pc, pc_false);
581 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
582 tcg_gen_mov_tl(env_pc, pc_true);
583 gen_set_label(l1);
584
585 tcg_temp_free(btaken);
586 }
587
588 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
589 {
590 TranslationBlock *tb;
591 tb = dc->tb;
592 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
593 tcg_gen_goto_tb(n);
594 tcg_gen_movi_tl(env_pc, dest);
595 tcg_gen_exit_tb((long)tb + n);
596 } else {
597 tcg_gen_movi_tl(env_pc, dest);
598 tcg_gen_exit_tb(0);
599 }
600 }
601
602 /* Sign extend at translation time. */
603 static int sign_extend(unsigned int val, unsigned int width)
604 {
605 int sval;
606
607 /* LSL. */
608 val <<= 31 - width;
609 sval = val;
610 /* ASR. */
611 sval >>= 31 - width;
612 return sval;
613 }
614
615 static inline void cris_clear_x_flag(DisasContext *dc)
616 {
617 if (dc->flagx_known && dc->flags_x)
618 dc->flags_uptodate = 0;
619
620 dc->flagx_known = 1;
621 dc->flags_x = 0;
622 }
623
624 static void cris_flush_cc_state(DisasContext *dc)
625 {
626 if (dc->cc_size_uptodate != dc->cc_size) {
627 tcg_gen_movi_tl(cc_size, dc->cc_size);
628 dc->cc_size_uptodate = dc->cc_size;
629 }
630 tcg_gen_movi_tl(cc_op, dc->cc_op);
631 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
632 }
633
634 static void cris_evaluate_flags(DisasContext *dc)
635 {
636 if (!dc->flags_uptodate) {
637 cris_flush_cc_state(dc);
638
639 switch (dc->cc_op)
640 {
641 case CC_OP_MCP:
642 gen_helper_evaluate_flags_mcp();
643 break;
644 case CC_OP_MULS:
645 gen_helper_evaluate_flags_muls();
646 break;
647 case CC_OP_MULU:
648 gen_helper_evaluate_flags_mulu();
649 break;
650 case CC_OP_MOVE:
651 case CC_OP_AND:
652 case CC_OP_OR:
653 case CC_OP_XOR:
654 case CC_OP_ASR:
655 case CC_OP_LSR:
656 case CC_OP_LSL:
657 switch (dc->cc_size)
658 {
659 case 4:
660 gen_helper_evaluate_flags_move_4();
661 break;
662 case 2:
663 gen_helper_evaluate_flags_move_2();
664 break;
665 default:
666 gen_helper_evaluate_flags();
667 break;
668 }
669 break;
670 case CC_OP_FLAGS:
671 /* live. */
672 break;
673 case CC_OP_SUB:
674 case CC_OP_CMP:
675 if (dc->cc_size == 4)
676 gen_helper_evaluate_flags_sub_4();
677 else
678 gen_helper_evaluate_flags();
679
680 break;
681 default:
682 switch (dc->cc_size)
683 {
684 case 4:
685 gen_helper_evaluate_flags_alu_4();
686 break;
687 default:
688 gen_helper_evaluate_flags();
689 break;
690 }
691 break;
692 }
693 if (dc->flagx_known) {
694 if (dc->flags_x)
695 tcg_gen_ori_tl(cpu_PR[PR_CCS],
696 cpu_PR[PR_CCS], X_FLAG);
697 else
698 tcg_gen_andi_tl(cpu_PR[PR_CCS],
699 cpu_PR[PR_CCS], ~X_FLAG);
700 }
701
702 dc->flags_uptodate = 1;
703 }
704 }
705
706 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
707 {
708 uint32_t ovl;
709
710 if (!mask) {
711 dc->update_cc = 0;
712 return;
713 }
714
715 /* Check if we need to evaluate the condition codes due to
716 CC overlaying. */
717 ovl = (dc->cc_mask ^ mask) & ~mask;
718 if (ovl) {
719 /* TODO: optimize this case. It trigs all the time. */
720 cris_evaluate_flags (dc);
721 }
722 dc->cc_mask = mask;
723 dc->update_cc = 1;
724 }
725
726 static void cris_update_cc_op(DisasContext *dc, int op, int size)
727 {
728 dc->cc_op = op;
729 dc->cc_size = size;
730 dc->flags_uptodate = 0;
731 }
732
733 static inline void cris_update_cc_x(DisasContext *dc)
734 {
735 /* Save the x flag state at the time of the cc snapshot. */
736 if (dc->flagx_known) {
737 if (dc->cc_x_uptodate == (2 | dc->flags_x))
738 return;
739 tcg_gen_movi_tl(cc_x, dc->flags_x);
740 dc->cc_x_uptodate = 2 | dc->flags_x;
741 }
742 else {
743 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
744 dc->cc_x_uptodate = 1;
745 }
746 }
747
748 /* Update cc prior to executing ALU op. Needs source operands untouched. */
749 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
750 TCGv dst, TCGv src, int size)
751 {
752 if (dc->update_cc) {
753 cris_update_cc_op(dc, op, size);
754 tcg_gen_mov_tl(cc_src, src);
755
756 if (op != CC_OP_MOVE
757 && op != CC_OP_AND
758 && op != CC_OP_OR
759 && op != CC_OP_XOR
760 && op != CC_OP_ASR
761 && op != CC_OP_LSR
762 && op != CC_OP_LSL)
763 tcg_gen_mov_tl(cc_dest, dst);
764
765 cris_update_cc_x(dc);
766 }
767 }
768
769 /* Update cc after executing ALU op. needs the result. */
770 static inline void cris_update_result(DisasContext *dc, TCGv res)
771 {
772 if (dc->update_cc)
773 tcg_gen_mov_tl(cc_result, res);
774 }
775
776 /* Returns one if the write back stage should execute. */
777 static void cris_alu_op_exec(DisasContext *dc, int op,
778 TCGv dst, TCGv a, TCGv b, int size)
779 {
780 /* Emit the ALU insns. */
781 switch (op)
782 {
783 case CC_OP_ADD:
784 tcg_gen_add_tl(dst, a, b);
785 /* Extended arithmetics. */
786 t_gen_addx_carry(dc, dst);
787 break;
788 case CC_OP_ADDC:
789 tcg_gen_add_tl(dst, a, b);
790 t_gen_add_flag(dst, 0); /* C_FLAG. */
791 break;
792 case CC_OP_MCP:
793 tcg_gen_add_tl(dst, a, b);
794 t_gen_add_flag(dst, 8); /* R_FLAG. */
795 break;
796 case CC_OP_SUB:
797 tcg_gen_sub_tl(dst, a, b);
798 /* Extended arithmetics. */
799 t_gen_subx_carry(dc, dst);
800 break;
801 case CC_OP_MOVE:
802 tcg_gen_mov_tl(dst, b);
803 break;
804 case CC_OP_OR:
805 tcg_gen_or_tl(dst, a, b);
806 break;
807 case CC_OP_AND:
808 tcg_gen_and_tl(dst, a, b);
809 break;
810 case CC_OP_XOR:
811 tcg_gen_xor_tl(dst, a, b);
812 break;
813 case CC_OP_LSL:
814 t_gen_lsl(dst, a, b);
815 break;
816 case CC_OP_LSR:
817 t_gen_lsr(dst, a, b);
818 break;
819 case CC_OP_ASR:
820 t_gen_asr(dst, a, b);
821 break;
822 case CC_OP_NEG:
823 tcg_gen_neg_tl(dst, b);
824 /* Extended arithmetics. */
825 t_gen_subx_carry(dc, dst);
826 break;
827 case CC_OP_LZ:
828 t_gen_lz_i32(dst, b);
829 break;
830 case CC_OP_MULS:
831 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
832 break;
833 case CC_OP_MULU:
834 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
835 break;
836 case CC_OP_DSTEP:
837 t_gen_cris_dstep(dst, a, b);
838 break;
839 case CC_OP_BOUND:
840 {
841 int l1;
842 l1 = gen_new_label();
843 tcg_gen_mov_tl(dst, a);
844 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
845 tcg_gen_mov_tl(dst, b);
846 gen_set_label(l1);
847 }
848 break;
849 case CC_OP_CMP:
850 tcg_gen_sub_tl(dst, a, b);
851 /* Extended arithmetics. */
852 t_gen_subx_carry(dc, dst);
853 break;
854 default:
855 fprintf (logfile, "illegal ALU op.\n");
856 BUG();
857 break;
858 }
859
860 if (size == 1)
861 tcg_gen_andi_tl(dst, dst, 0xff);
862 else if (size == 2)
863 tcg_gen_andi_tl(dst, dst, 0xffff);
864 }
865
866 static void cris_alu(DisasContext *dc, int op,
867 TCGv d, TCGv op_a, TCGv op_b, int size)
868 {
869 TCGv tmp;
870 int writeback;
871
872 writeback = 1;
873
874 if (op == CC_OP_CMP) {
875 tmp = tcg_temp_new();
876 writeback = 0;
877 } else if (size == 4) {
878 tmp = d;
879 writeback = 0;
880 } else
881 tmp = tcg_temp_new();
882
883
884 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
885 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
886 cris_update_result(dc, tmp);
887
888 /* Writeback. */
889 if (writeback) {
890 if (size == 1)
891 tcg_gen_andi_tl(d, d, ~0xff);
892 else
893 tcg_gen_andi_tl(d, d, ~0xffff);
894 tcg_gen_or_tl(d, d, tmp);
895 }
896 if (!TCGV_EQUAL(tmp, d))
897 tcg_temp_free(tmp);
898 }
899
900 static int arith_cc(DisasContext *dc)
901 {
902 if (dc->update_cc) {
903 switch (dc->cc_op) {
904 case CC_OP_ADDC: return 1;
905 case CC_OP_ADD: return 1;
906 case CC_OP_SUB: return 1;
907 case CC_OP_DSTEP: return 1;
908 case CC_OP_LSL: return 1;
909 case CC_OP_LSR: return 1;
910 case CC_OP_ASR: return 1;
911 case CC_OP_CMP: return 1;
912 case CC_OP_NEG: return 1;
913 case CC_OP_OR: return 1;
914 case CC_OP_AND: return 1;
915 case CC_OP_XOR: return 1;
916 case CC_OP_MULU: return 1;
917 case CC_OP_MULS: return 1;
918 default:
919 return 0;
920 }
921 }
922 return 0;
923 }
924
925 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
926 {
927 int arith_opt, move_opt;
928
929 /* TODO: optimize more condition codes. */
930
931 /*
932 * If the flags are live, we've gotta look into the bits of CCS.
933 * Otherwise, if we just did an arithmetic operation we try to
934 * evaluate the condition code faster.
935 *
936 * When this function is done, T0 should be non-zero if the condition
937 * code is true.
938 */
939 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
940 move_opt = (dc->cc_op == CC_OP_MOVE);
941 switch (cond) {
942 case CC_EQ:
943 if (arith_opt || move_opt) {
944 /* If cc_result is zero, T0 should be
945 non-zero otherwise T0 should be zero. */
946 int l1;
947 l1 = gen_new_label();
948 tcg_gen_movi_tl(cc, 0);
949 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
950 0, l1);
951 tcg_gen_movi_tl(cc, 1);
952 gen_set_label(l1);
953 }
954 else {
955 cris_evaluate_flags(dc);
956 tcg_gen_andi_tl(cc,
957 cpu_PR[PR_CCS], Z_FLAG);
958 }
959 break;
960 case CC_NE:
961 if (arith_opt || move_opt)
962 tcg_gen_mov_tl(cc, cc_result);
963 else {
964 cris_evaluate_flags(dc);
965 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
966 Z_FLAG);
967 tcg_gen_andi_tl(cc, cc, Z_FLAG);
968 }
969 break;
970 case CC_CS:
971 cris_evaluate_flags(dc);
972 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
973 break;
974 case CC_CC:
975 cris_evaluate_flags(dc);
976 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
977 tcg_gen_andi_tl(cc, cc, C_FLAG);
978 break;
979 case CC_VS:
980 cris_evaluate_flags(dc);
981 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
982 break;
983 case CC_VC:
984 cris_evaluate_flags(dc);
985 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
986 V_FLAG);
987 tcg_gen_andi_tl(cc, cc, V_FLAG);
988 break;
989 case CC_PL:
990 if (arith_opt || move_opt) {
991 int bits = 31;
992
993 if (dc->cc_size == 1)
994 bits = 7;
995 else if (dc->cc_size == 2)
996 bits = 15;
997
998 tcg_gen_shri_tl(cc, cc_result, bits);
999 tcg_gen_xori_tl(cc, cc, 1);
1000 } else {
1001 cris_evaluate_flags(dc);
1002 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1003 N_FLAG);
1004 tcg_gen_andi_tl(cc, cc, N_FLAG);
1005 }
1006 break;
1007 case CC_MI:
1008 if (arith_opt || move_opt) {
1009 int bits = 31;
1010
1011 if (dc->cc_size == 1)
1012 bits = 7;
1013 else if (dc->cc_size == 2)
1014 bits = 15;
1015
1016 tcg_gen_shri_tl(cc, cc_result, 31);
1017 }
1018 else {
1019 cris_evaluate_flags(dc);
1020 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1021 N_FLAG);
1022 }
1023 break;
1024 case CC_LS:
1025 cris_evaluate_flags(dc);
1026 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1027 C_FLAG | Z_FLAG);
1028 break;
1029 case CC_HI:
1030 cris_evaluate_flags(dc);
1031 {
1032 TCGv tmp;
1033
1034 tmp = tcg_temp_new();
1035 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1036 C_FLAG | Z_FLAG);
1037 /* Overlay the C flag on top of the Z. */
1038 tcg_gen_shli_tl(cc, tmp, 2);
1039 tcg_gen_and_tl(cc, tmp, cc);
1040 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1041
1042 tcg_temp_free(tmp);
1043 }
1044 break;
1045 case CC_GE:
1046 cris_evaluate_flags(dc);
1047 /* Overlay the V flag on top of the N. */
1048 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1049 tcg_gen_xor_tl(cc,
1050 cpu_PR[PR_CCS], cc);
1051 tcg_gen_andi_tl(cc, cc, N_FLAG);
1052 tcg_gen_xori_tl(cc, cc, N_FLAG);
1053 break;
1054 case CC_LT:
1055 cris_evaluate_flags(dc);
1056 /* Overlay the V flag on top of the N. */
1057 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1058 tcg_gen_xor_tl(cc,
1059 cpu_PR[PR_CCS], cc);
1060 tcg_gen_andi_tl(cc, cc, N_FLAG);
1061 break;
1062 case CC_GT:
1063 cris_evaluate_flags(dc);
1064 {
1065 TCGv n, z;
1066
1067 n = tcg_temp_new();
1068 z = tcg_temp_new();
1069
1070 /* To avoid a shift we overlay everything on
1071 the V flag. */
1072 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1073 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1074 /* invert Z. */
1075 tcg_gen_xori_tl(z, z, 2);
1076
1077 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1078 tcg_gen_xori_tl(n, n, 2);
1079 tcg_gen_and_tl(cc, z, n);
1080 tcg_gen_andi_tl(cc, cc, 2);
1081
1082 tcg_temp_free(n);
1083 tcg_temp_free(z);
1084 }
1085 break;
1086 case CC_LE:
1087 cris_evaluate_flags(dc);
1088 {
1089 TCGv n, z;
1090
1091 n = tcg_temp_new();
1092 z = tcg_temp_new();
1093
1094 /* To avoid a shift we overlay everything on
1095 the V flag. */
1096 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1097 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1098
1099 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1100 tcg_gen_or_tl(cc, z, n);
1101 tcg_gen_andi_tl(cc, cc, 2);
1102
1103 tcg_temp_free(n);
1104 tcg_temp_free(z);
1105 }
1106 break;
1107 case CC_P:
1108 cris_evaluate_flags(dc);
1109 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1110 break;
1111 case CC_A:
1112 tcg_gen_movi_tl(cc, 1);
1113 break;
1114 default:
1115 BUG();
1116 break;
1117 };
1118 }
1119
1120 static void cris_store_direct_jmp(DisasContext *dc)
1121 {
1122 /* Store the direct jmp state into the cpu-state. */
1123 if (dc->jmp == JMP_DIRECT) {
1124 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1125 tcg_gen_movi_tl(env_btaken, 1);
1126 }
1127 }
1128
1129 static void cris_prepare_cc_branch (DisasContext *dc,
1130 int offset, int cond)
1131 {
1132 /* This helps us re-schedule the micro-code to insns in delay-slots
1133 before the actual jump. */
1134 dc->delayed_branch = 2;
1135 dc->jmp_pc = dc->pc + offset;
1136
1137 if (cond != CC_A)
1138 {
1139 dc->jmp = JMP_INDIRECT;
1140 gen_tst_cc (dc, env_btaken, cond);
1141 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1142 } else {
1143 /* Allow chaining. */
1144 dc->jmp = JMP_DIRECT;
1145 }
1146 }
1147
1148
1149 /* jumps, when the dest is in a live reg for example. Direct should be set
1150 when the dest addr is constant to allow tb chaining. */
1151 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1152 {
1153 /* This helps us re-schedule the micro-code to insns in delay-slots
1154 before the actual jump. */
1155 dc->delayed_branch = 2;
1156 dc->jmp = type;
1157 if (type == JMP_INDIRECT)
1158 tcg_gen_movi_tl(env_btaken, 1);
1159 }
1160
1161 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1162 {
1163 int mem_index = cpu_mmu_index(dc->env);
1164
1165 /* If we get a fault on a delayslot we must keep the jmp state in
1166 the cpu-state to be able to re-execute the jmp. */
1167 if (dc->delayed_branch == 1)
1168 cris_store_direct_jmp(dc);
1169
1170 tcg_gen_qemu_ld64(dst, addr, mem_index);
1171 }
1172
1173 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1174 unsigned int size, int sign)
1175 {
1176 int mem_index = cpu_mmu_index(dc->env);
1177
1178 /* If we get a fault on a delayslot we must keep the jmp state in
1179 the cpu-state to be able to re-execute the jmp. */
1180 if (dc->delayed_branch == 1)
1181 cris_store_direct_jmp(dc);
1182
1183 if (size == 1) {
1184 if (sign)
1185 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1186 else
1187 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1188 }
1189 else if (size == 2) {
1190 if (sign)
1191 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1192 else
1193 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1194 }
1195 else if (size == 4) {
1196 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1197 }
1198 else {
1199 abort();
1200 }
1201 }
1202
1203 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1204 unsigned int size)
1205 {
1206 int mem_index = cpu_mmu_index(dc->env);
1207
1208 /* If we get a fault on a delayslot we must keep the jmp state in
1209 the cpu-state to be able to re-execute the jmp. */
1210 if (dc->delayed_branch == 1)
1211 cris_store_direct_jmp(dc);
1212
1213
1214 /* Conditional writes. We only support the kind were X and P are known
1215 at translation time. */
1216 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1217 dc->postinc = 0;
1218 cris_evaluate_flags(dc);
1219 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1220 return;
1221 }
1222
1223 if (size == 1)
1224 tcg_gen_qemu_st8(val, addr, mem_index);
1225 else if (size == 2)
1226 tcg_gen_qemu_st16(val, addr, mem_index);
1227 else
1228 tcg_gen_qemu_st32(val, addr, mem_index);
1229
1230 if (dc->flagx_known && dc->flags_x) {
1231 cris_evaluate_flags(dc);
1232 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1233 }
1234 }
1235
1236 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1237 {
1238 if (size == 1)
1239 tcg_gen_ext8s_i32(d, s);
1240 else if (size == 2)
1241 tcg_gen_ext16s_i32(d, s);
1242 else if(!TCGV_EQUAL(d, s))
1243 tcg_gen_mov_tl(d, s);
1244 }
1245
1246 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1247 {
1248 if (size == 1)
1249 tcg_gen_ext8u_i32(d, s);
1250 else if (size == 2)
1251 tcg_gen_ext16u_i32(d, s);
1252 else if (!TCGV_EQUAL(d, s))
1253 tcg_gen_mov_tl(d, s);
1254 }
1255
1256 #if DISAS_CRIS
1257 static char memsize_char(int size)
1258 {
1259 switch (size)
1260 {
1261 case 1: return 'b'; break;
1262 case 2: return 'w'; break;
1263 case 4: return 'd'; break;
1264 default:
1265 return 'x';
1266 break;
1267 }
1268 }
1269 #endif
1270
1271 static inline unsigned int memsize_z(DisasContext *dc)
1272 {
1273 return dc->zsize + 1;
1274 }
1275
1276 static inline unsigned int memsize_zz(DisasContext *dc)
1277 {
1278 switch (dc->zzsize)
1279 {
1280 case 0: return 1;
1281 case 1: return 2;
1282 default:
1283 return 4;
1284 }
1285 }
1286
1287 static inline void do_postinc (DisasContext *dc, int size)
1288 {
1289 if (dc->postinc)
1290 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1291 }
1292
1293 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1294 int size, int s_ext, TCGv dst)
1295 {
1296 if (s_ext)
1297 t_gen_sext(dst, cpu_R[rs], size);
1298 else
1299 t_gen_zext(dst, cpu_R[rs], size);
1300 }
1301
1302 /* Prepare T0 and T1 for a register alu operation.
1303 s_ext decides if the operand1 should be sign-extended or zero-extended when
1304 needed. */
1305 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1306 int size, int s_ext, TCGv dst, TCGv src)
1307 {
1308 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1309
1310 if (s_ext)
1311 t_gen_sext(dst, cpu_R[rd], size);
1312 else
1313 t_gen_zext(dst, cpu_R[rd], size);
1314 }
1315
1316 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1317 TCGv dst)
1318 {
1319 unsigned int rs, rd;
1320 uint32_t imm;
1321 int is_imm;
1322 int insn_len = 2;
1323
1324 rs = dc->op1;
1325 rd = dc->op2;
1326 is_imm = rs == 15 && dc->postinc;
1327
1328 /* Load [$rs] onto T1. */
1329 if (is_imm) {
1330 insn_len = 2 + memsize;
1331 if (memsize == 1)
1332 insn_len++;
1333
1334 if (memsize != 4) {
1335 if (s_ext) {
1336 if (memsize == 1)
1337 imm = ldsb_code(dc->pc + 2);
1338 else
1339 imm = ldsw_code(dc->pc + 2);
1340 } else {
1341 if (memsize == 1)
1342 imm = ldub_code(dc->pc + 2);
1343 else
1344 imm = lduw_code(dc->pc + 2);
1345 }
1346 } else
1347 imm = ldl_code(dc->pc + 2);
1348
1349 tcg_gen_movi_tl(dst, imm);
1350 dc->postinc = 0;
1351 } else {
1352 cris_flush_cc_state(dc);
1353 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1354 if (s_ext)
1355 t_gen_sext(dst, dst, memsize);
1356 else
1357 t_gen_zext(dst, dst, memsize);
1358 }
1359 return insn_len;
1360 }
1361
1362 /* Prepare T0 and T1 for a memory + alu operation.
1363 s_ext decides if the operand1 should be sign-extended or zero-extended when
1364 needed. */
1365 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
1366 TCGv dst, TCGv src)
1367 {
1368 int insn_len;
1369
1370 insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
1371 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1372 return insn_len;
1373 }
1374
1375 #if DISAS_CRIS
1376 static const char *cc_name(int cc)
1377 {
1378 static const char *cc_names[16] = {
1379 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1380 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1381 };
1382 assert(cc < 16);
1383 return cc_names[cc];
1384 }
1385 #endif
1386
1387 /* Start of insn decoders. */
1388
1389 static unsigned int dec_bccq(DisasContext *dc)
1390 {
1391 int32_t offset;
1392 int sign;
1393 uint32_t cond = dc->op2;
1394 int tmp;
1395
1396 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1397 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1398
1399 offset *= 2;
1400 offset |= sign << 8;
1401 tmp = offset;
1402 offset = sign_extend(offset, 8);
1403
1404 DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
1405
1406 /* op2 holds the condition-code. */
1407 cris_cc_mask(dc, 0);
1408 cris_prepare_cc_branch (dc, offset, cond);
1409 return 2;
1410 }
1411 static unsigned int dec_addoq(DisasContext *dc)
1412 {
1413 int32_t imm;
1414
1415 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1416 imm = sign_extend(dc->op1, 7);
1417
1418 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1419 cris_cc_mask(dc, 0);
1420 /* Fetch register operand, */
1421 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1422
1423 return 2;
1424 }
1425 static unsigned int dec_addq(DisasContext *dc)
1426 {
1427 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1428
1429 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1430
1431 cris_cc_mask(dc, CC_MASK_NZVC);
1432
1433 cris_alu(dc, CC_OP_ADD,
1434 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1435 return 2;
1436 }
1437 static unsigned int dec_moveq(DisasContext *dc)
1438 {
1439 uint32_t imm;
1440
1441 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1442 imm = sign_extend(dc->op1, 5);
1443 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1444
1445 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
1446 return 2;
1447 }
1448 static unsigned int dec_subq(DisasContext *dc)
1449 {
1450 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1451
1452 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1453
1454 cris_cc_mask(dc, CC_MASK_NZVC);
1455 cris_alu(dc, CC_OP_SUB,
1456 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1457 return 2;
1458 }
1459 static unsigned int dec_cmpq(DisasContext *dc)
1460 {
1461 uint32_t imm;
1462 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1463 imm = sign_extend(dc->op1, 5);
1464
1465 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1466 cris_cc_mask(dc, CC_MASK_NZVC);
1467
1468 cris_alu(dc, CC_OP_CMP,
1469 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1470 return 2;
1471 }
1472 static unsigned int dec_andq(DisasContext *dc)
1473 {
1474 uint32_t imm;
1475 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1476 imm = sign_extend(dc->op1, 5);
1477
1478 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1479 cris_cc_mask(dc, CC_MASK_NZ);
1480
1481 cris_alu(dc, CC_OP_AND,
1482 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1483 return 2;
1484 }
1485 static unsigned int dec_orq(DisasContext *dc)
1486 {
1487 uint32_t imm;
1488 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1489 imm = sign_extend(dc->op1, 5);
1490 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1491 cris_cc_mask(dc, CC_MASK_NZ);
1492
1493 cris_alu(dc, CC_OP_OR,
1494 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1495 return 2;
1496 }
1497 static unsigned int dec_btstq(DisasContext *dc)
1498 {
1499 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1500 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1501
1502 cris_cc_mask(dc, CC_MASK_NZ);
1503 cris_evaluate_flags(dc);
1504 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1505 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1506 cris_alu(dc, CC_OP_MOVE,
1507 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1508 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1509 dc->flags_uptodate = 1;
1510 return 2;
1511 }
1512 static unsigned int dec_asrq(DisasContext *dc)
1513 {
1514 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1515 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1516 cris_cc_mask(dc, CC_MASK_NZ);
1517
1518 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1519 cris_alu(dc, CC_OP_MOVE,
1520 cpu_R[dc->op2],
1521 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1522 return 2;
1523 }
1524 static unsigned int dec_lslq(DisasContext *dc)
1525 {
1526 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1527 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1528
1529 cris_cc_mask(dc, CC_MASK_NZ);
1530
1531 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1532
1533 cris_alu(dc, CC_OP_MOVE,
1534 cpu_R[dc->op2],
1535 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1536 return 2;
1537 }
1538 static unsigned int dec_lsrq(DisasContext *dc)
1539 {
1540 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1541 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1542
1543 cris_cc_mask(dc, CC_MASK_NZ);
1544
1545 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1546 cris_alu(dc, CC_OP_MOVE,
1547 cpu_R[dc->op2],
1548 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1549 return 2;
1550 }
1551
1552 static unsigned int dec_move_r(DisasContext *dc)
1553 {
1554 int size = memsize_zz(dc);
1555
1556 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1557 memsize_char(size), dc->op1, dc->op2));
1558
1559 cris_cc_mask(dc, CC_MASK_NZ);
1560 if (size == 4) {
1561 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1562 cris_cc_mask(dc, CC_MASK_NZ);
1563 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1564 cris_update_cc_x(dc);
1565 cris_update_result(dc, cpu_R[dc->op2]);
1566 }
1567 else {
1568 TCGv t0;
1569
1570 t0 = tcg_temp_new();
1571 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1572 cris_alu(dc, CC_OP_MOVE,
1573 cpu_R[dc->op2],
1574 cpu_R[dc->op2], t0, size);
1575 tcg_temp_free(t0);
1576 }
1577 return 2;
1578 }
1579
1580 static unsigned int dec_scc_r(DisasContext *dc)
1581 {
1582 int cond = dc->op2;
1583
1584 DIS(fprintf (logfile, "s%s $r%u\n",
1585 cc_name(cond), dc->op1));
1586
1587 if (cond != CC_A)
1588 {
1589 int l1;
1590
1591 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1592 l1 = gen_new_label();
1593 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1594 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1595 gen_set_label(l1);
1596 }
1597 else
1598 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1599
1600 cris_cc_mask(dc, 0);
1601 return 2;
1602 }
1603
1604 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1605 {
1606 if (size == 4) {
1607 t[0] = cpu_R[dc->op2];
1608 t[1] = cpu_R[dc->op1];
1609 } else {
1610 t[0] = tcg_temp_new();
1611 t[1] = tcg_temp_new();
1612 }
1613 }
1614
1615 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1616 {
1617 if (size != 4) {
1618 tcg_temp_free(t[0]);
1619 tcg_temp_free(t[1]);
1620 }
1621 }
1622
1623 static unsigned int dec_and_r(DisasContext *dc)
1624 {
1625 TCGv t[2];
1626 int size = memsize_zz(dc);
1627
1628 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1629 memsize_char(size), dc->op1, dc->op2));
1630
1631 cris_cc_mask(dc, CC_MASK_NZ);
1632
1633 cris_alu_alloc_temps(dc, size, t);
1634 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1635 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1636 cris_alu_free_temps(dc, size, t);
1637 return 2;
1638 }
1639
1640 static unsigned int dec_lz_r(DisasContext *dc)
1641 {
1642 TCGv t0;
1643 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1644 dc->op1, dc->op2));
1645 cris_cc_mask(dc, CC_MASK_NZ);
1646 t0 = tcg_temp_new();
1647 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1648 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1649 tcg_temp_free(t0);
1650 return 2;
1651 }
1652
1653 static unsigned int dec_lsl_r(DisasContext *dc)
1654 {
1655 TCGv t[2];
1656 int size = memsize_zz(dc);
1657
1658 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1659 memsize_char(size), dc->op1, dc->op2));
1660
1661 cris_cc_mask(dc, CC_MASK_NZ);
1662 cris_alu_alloc_temps(dc, size, t);
1663 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1664 tcg_gen_andi_tl(t[1], t[1], 63);
1665 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1666 cris_alu_alloc_temps(dc, size, t);
1667 return 2;
1668 }
1669
1670 static unsigned int dec_lsr_r(DisasContext *dc)
1671 {
1672 TCGv t[2];
1673 int size = memsize_zz(dc);
1674
1675 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1676 memsize_char(size), dc->op1, dc->op2));
1677
1678 cris_cc_mask(dc, CC_MASK_NZ);
1679 cris_alu_alloc_temps(dc, size, t);
1680 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1681 tcg_gen_andi_tl(t[1], t[1], 63);
1682 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1683 cris_alu_free_temps(dc, size, t);
1684 return 2;
1685 }
1686
1687 static unsigned int dec_asr_r(DisasContext *dc)
1688 {
1689 TCGv t[2];
1690 int size = memsize_zz(dc);
1691
1692 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1693 memsize_char(size), dc->op1, dc->op2));
1694
1695 cris_cc_mask(dc, CC_MASK_NZ);
1696 cris_alu_alloc_temps(dc, size, t);
1697 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1698 tcg_gen_andi_tl(t[1], t[1], 63);
1699 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1700 cris_alu_free_temps(dc, size, t);
1701 return 2;
1702 }
1703
1704 static unsigned int dec_muls_r(DisasContext *dc)
1705 {
1706 TCGv t[2];
1707 int size = memsize_zz(dc);
1708
1709 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1710 memsize_char(size), dc->op1, dc->op2));
1711 cris_cc_mask(dc, CC_MASK_NZV);
1712 cris_alu_alloc_temps(dc, size, t);
1713 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1714
1715 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1716 cris_alu_free_temps(dc, size, t);
1717 return 2;
1718 }
1719
1720 static unsigned int dec_mulu_r(DisasContext *dc)
1721 {
1722 TCGv t[2];
1723 int size = memsize_zz(dc);
1724
1725 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1726 memsize_char(size), dc->op1, dc->op2));
1727 cris_cc_mask(dc, CC_MASK_NZV);
1728 cris_alu_alloc_temps(dc, size, t);
1729 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1730
1731 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1732 cris_alu_alloc_temps(dc, size, t);
1733 return 2;
1734 }
1735
1736
1737 static unsigned int dec_dstep_r(DisasContext *dc)
1738 {
1739 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1740 cris_cc_mask(dc, CC_MASK_NZ);
1741 cris_alu(dc, CC_OP_DSTEP,
1742 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1743 return 2;
1744 }
1745
1746 static unsigned int dec_xor_r(DisasContext *dc)
1747 {
1748 TCGv t[2];
1749 int size = memsize_zz(dc);
1750 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1751 memsize_char(size), dc->op1, dc->op2));
1752 BUG_ON(size != 4); /* xor is dword. */
1753 cris_cc_mask(dc, CC_MASK_NZ);
1754 cris_alu_alloc_temps(dc, size, t);
1755 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1756
1757 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1758 cris_alu_free_temps(dc, size, t);
1759 return 2;
1760 }
1761
1762 static unsigned int dec_bound_r(DisasContext *dc)
1763 {
1764 TCGv l0;
1765 int size = memsize_zz(dc);
1766 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1767 memsize_char(size), dc->op1, dc->op2));
1768 cris_cc_mask(dc, CC_MASK_NZ);
1769 l0 = tcg_temp_local_new();
1770 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1771 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1772 tcg_temp_free(l0);
1773 return 2;
1774 }
1775
1776 static unsigned int dec_cmp_r(DisasContext *dc)
1777 {
1778 TCGv t[2];
1779 int size = memsize_zz(dc);
1780 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1781 memsize_char(size), dc->op1, dc->op2));
1782 cris_cc_mask(dc, CC_MASK_NZVC);
1783 cris_alu_alloc_temps(dc, size, t);
1784 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1785
1786 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1787 cris_alu_free_temps(dc, size, t);
1788 return 2;
1789 }
1790
1791 static unsigned int dec_abs_r(DisasContext *dc)
1792 {
1793 TCGv t0;
1794
1795 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1796 dc->op1, dc->op2));
1797 cris_cc_mask(dc, CC_MASK_NZ);
1798
1799 t0 = tcg_temp_new();
1800 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1801 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1802 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1803 tcg_temp_free(t0);
1804
1805 cris_alu(dc, CC_OP_MOVE,
1806 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1807 return 2;
1808 }
1809
1810 static unsigned int dec_add_r(DisasContext *dc)
1811 {
1812 TCGv t[2];
1813 int size = memsize_zz(dc);
1814 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1815 memsize_char(size), dc->op1, dc->op2));
1816 cris_cc_mask(dc, CC_MASK_NZVC);
1817 cris_alu_alloc_temps(dc, size, t);
1818 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1819
1820 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1821 cris_alu_free_temps(dc, size, t);
1822 return 2;
1823 }
1824
1825 static unsigned int dec_addc_r(DisasContext *dc)
1826 {
1827 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1828 dc->op1, dc->op2));
1829 cris_evaluate_flags(dc);
1830 /* Set for this insn. */
1831 dc->flagx_known = 1;
1832 dc->flags_x = X_FLAG;
1833
1834 cris_cc_mask(dc, CC_MASK_NZVC);
1835 cris_alu(dc, CC_OP_ADDC,
1836 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1837 return 2;
1838 }
1839
1840 static unsigned int dec_mcp_r(DisasContext *dc)
1841 {
1842 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1843 dc->op2, dc->op1));
1844 cris_evaluate_flags(dc);
1845 cris_cc_mask(dc, CC_MASK_RNZV);
1846 cris_alu(dc, CC_OP_MCP,
1847 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1848 return 2;
1849 }
1850
1851 #if DISAS_CRIS
1852 static char * swapmode_name(int mode, char *modename) {
1853 int i = 0;
1854 if (mode & 8)
1855 modename[i++] = 'n';
1856 if (mode & 4)
1857 modename[i++] = 'w';
1858 if (mode & 2)
1859 modename[i++] = 'b';
1860 if (mode & 1)
1861 modename[i++] = 'r';
1862 modename[i++] = 0;
1863 return modename;
1864 }
1865 #endif
1866
1867 static unsigned int dec_swap_r(DisasContext *dc)
1868 {
1869 TCGv t0;
1870 #if DISAS_CRIS
1871 char modename[4];
1872 #endif
1873 DIS(fprintf (logfile, "swap%s $r%u\n",
1874 swapmode_name(dc->op2, modename), dc->op1));
1875
1876 cris_cc_mask(dc, CC_MASK_NZ);
1877 t0 = tcg_temp_new();
1878 t_gen_mov_TN_reg(t0, dc->op1);
1879 if (dc->op2 & 8)
1880 tcg_gen_not_tl(t0, t0);
1881 if (dc->op2 & 4)
1882 t_gen_swapw(t0, t0);
1883 if (dc->op2 & 2)
1884 t_gen_swapb(t0, t0);
1885 if (dc->op2 & 1)
1886 t_gen_swapr(t0, t0);
1887 cris_alu(dc, CC_OP_MOVE,
1888 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1889 tcg_temp_free(t0);
1890 return 2;
1891 }
1892
1893 static unsigned int dec_or_r(DisasContext *dc)
1894 {
1895 TCGv t[2];
1896 int size = memsize_zz(dc);
1897 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1898 memsize_char(size), dc->op1, dc->op2));
1899 cris_cc_mask(dc, CC_MASK_NZ);
1900 cris_alu_alloc_temps(dc, size, t);
1901 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1902 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1903 cris_alu_free_temps(dc, size, t);
1904 return 2;
1905 }
1906
1907 static unsigned int dec_addi_r(DisasContext *dc)
1908 {
1909 TCGv t0;
1910 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1911 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1912 cris_cc_mask(dc, 0);
1913 t0 = tcg_temp_new();
1914 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1915 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1916 tcg_temp_free(t0);
1917 return 2;
1918 }
1919
1920 static unsigned int dec_addi_acr(DisasContext *dc)
1921 {
1922 TCGv t0;
1923 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1924 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1925 cris_cc_mask(dc, 0);
1926 t0 = tcg_temp_new();
1927 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1928 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1929 tcg_temp_free(t0);
1930 return 2;
1931 }
1932
1933 static unsigned int dec_neg_r(DisasContext *dc)
1934 {
1935 TCGv t[2];
1936 int size = memsize_zz(dc);
1937 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1938 memsize_char(size), dc->op1, dc->op2));
1939 cris_cc_mask(dc, CC_MASK_NZVC);
1940 cris_alu_alloc_temps(dc, size, t);
1941 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1942
1943 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1944 cris_alu_free_temps(dc, size, t);
1945 return 2;
1946 }
1947
1948 static unsigned int dec_btst_r(DisasContext *dc)
1949 {
1950 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1951 dc->op1, dc->op2));
1952 cris_cc_mask(dc, CC_MASK_NZ);
1953 cris_evaluate_flags(dc);
1954 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1955 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1956 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1957 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1958 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1959 dc->flags_uptodate = 1;
1960 return 2;
1961 }
1962
1963 static unsigned int dec_sub_r(DisasContext *dc)
1964 {
1965 TCGv t[2];
1966 int size = memsize_zz(dc);
1967 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1968 memsize_char(size), dc->op1, dc->op2));
1969 cris_cc_mask(dc, CC_MASK_NZVC);
1970 cris_alu_alloc_temps(dc, size, t);
1971 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1972 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1973 cris_alu_free_temps(dc, size, t);
1974 return 2;
1975 }
1976
1977 /* Zero extension. From size to dword. */
1978 static unsigned int dec_movu_r(DisasContext *dc)
1979 {
1980 TCGv t0;
1981 int size = memsize_z(dc);
1982 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1983 memsize_char(size),
1984 dc->op1, dc->op2));
1985
1986 cris_cc_mask(dc, CC_MASK_NZ);
1987 t0 = tcg_temp_new();
1988 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1989 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1990 tcg_temp_free(t0);
1991 return 2;
1992 }
1993
1994 /* Sign extension. From size to dword. */
1995 static unsigned int dec_movs_r(DisasContext *dc)
1996 {
1997 TCGv t0;
1998 int size = memsize_z(dc);
1999 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
2000 memsize_char(size),
2001 dc->op1, dc->op2));
2002
2003 cris_cc_mask(dc, CC_MASK_NZ);
2004 t0 = tcg_temp_new();
2005 /* Size can only be qi or hi. */
2006 t_gen_sext(t0, cpu_R[dc->op1], size);
2007 cris_alu(dc, CC_OP_MOVE,
2008 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
2009 tcg_temp_free(t0);
2010 return 2;
2011 }
2012
2013 /* zero extension. From size to dword. */
2014 static unsigned int dec_addu_r(DisasContext *dc)
2015 {
2016 TCGv t0;
2017 int size = memsize_z(dc);
2018 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
2019 memsize_char(size),
2020 dc->op1, dc->op2));
2021
2022 cris_cc_mask(dc, CC_MASK_NZVC);
2023 t0 = tcg_temp_new();
2024 /* Size can only be qi or hi. */
2025 t_gen_zext(t0, cpu_R[dc->op1], size);
2026 cris_alu(dc, CC_OP_ADD,
2027 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2028 tcg_temp_free(t0);
2029 return 2;
2030 }
2031
2032 /* Sign extension. From size to dword. */
2033 static unsigned int dec_adds_r(DisasContext *dc)
2034 {
2035 TCGv t0;
2036 int size = memsize_z(dc);
2037 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
2038 memsize_char(size),
2039 dc->op1, dc->op2));
2040
2041 cris_cc_mask(dc, CC_MASK_NZVC);
2042 t0 = tcg_temp_new();
2043 /* Size can only be qi or hi. */
2044 t_gen_sext(t0, cpu_R[dc->op1], size);
2045 cris_alu(dc, CC_OP_ADD,
2046 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2047 tcg_temp_free(t0);
2048 return 2;
2049 }
2050
2051 /* Zero extension. From size to dword. */
2052 static unsigned int dec_subu_r(DisasContext *dc)
2053 {
2054 TCGv t0;
2055 int size = memsize_z(dc);
2056 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
2057 memsize_char(size),
2058 dc->op1, dc->op2));
2059
2060 cris_cc_mask(dc, CC_MASK_NZVC);
2061 t0 = tcg_temp_new();
2062 /* Size can only be qi or hi. */
2063 t_gen_zext(t0, cpu_R[dc->op1], size);
2064 cris_alu(dc, CC_OP_SUB,
2065 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2066 tcg_temp_free(t0);
2067 return 2;
2068 }
2069
2070 /* Sign extension. From size to dword. */
2071 static unsigned int dec_subs_r(DisasContext *dc)
2072 {
2073 TCGv t0;
2074 int size = memsize_z(dc);
2075 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
2076 memsize_char(size),
2077 dc->op1, dc->op2));
2078
2079 cris_cc_mask(dc, CC_MASK_NZVC);
2080 t0 = tcg_temp_new();
2081 /* Size can only be qi or hi. */
2082 t_gen_sext(t0, cpu_R[dc->op1], size);
2083 cris_alu(dc, CC_OP_SUB,
2084 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2085 tcg_temp_free(t0);
2086 return 2;
2087 }
2088
2089 static unsigned int dec_setclrf(DisasContext *dc)
2090 {
2091 uint32_t flags;
2092 int set = (~dc->opcode >> 2) & 1;
2093
2094
2095 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2096 | EXTRACT_FIELD(dc->ir, 0, 3);
2097 if (set && flags == 0) {
2098 DIS(fprintf (logfile, "nop\n"));
2099 return 2;
2100 } else if (!set && (flags & 0x20)) {
2101 DIS(fprintf (logfile, "di\n"));
2102 }
2103 else {
2104 DIS(fprintf (logfile, "%sf %x\n",
2105 set ? "set" : "clr",
2106 flags));
2107 }
2108
2109 /* User space is not allowed to touch these. Silently ignore. */
2110 if (dc->tb_flags & U_FLAG) {
2111 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2112 }
2113
2114 if (flags & X_FLAG) {
2115 dc->flagx_known = 1;
2116 if (set)
2117 dc->flags_x = X_FLAG;
2118 else
2119 dc->flags_x = 0;
2120 }
2121
2122 /* Break the TB if the P flag changes. */
2123 if (flags & P_FLAG) {
2124 if ((set && !(dc->tb_flags & P_FLAG))
2125 || (!set && (dc->tb_flags & P_FLAG))) {
2126 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2127 dc->is_jmp = DISAS_UPDATE;
2128 dc->cpustate_changed = 1;
2129 }
2130 }
2131 if (flags & S_FLAG) {
2132 dc->cpustate_changed = 1;
2133 }
2134
2135
2136 /* Simply decode the flags. */
2137 cris_evaluate_flags (dc);
2138 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2139 cris_update_cc_x(dc);
2140 tcg_gen_movi_tl(cc_op, dc->cc_op);
2141
2142 if (set) {
2143 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2144 /* Enter user mode. */
2145 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2146 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2147 dc->cpustate_changed = 1;
2148 }
2149 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2150 }
2151 else
2152 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2153
2154 dc->flags_uptodate = 1;
2155 dc->clear_x = 0;
2156 return 2;
2157 }
2158
2159 static unsigned int dec_move_rs(DisasContext *dc)
2160 {
2161 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
2162 cris_cc_mask(dc, 0);
2163 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2164 return 2;
2165 }
2166 static unsigned int dec_move_sr(DisasContext *dc)
2167 {
2168 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
2169 cris_cc_mask(dc, 0);
2170 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2171 return 2;
2172 }
2173
2174 static unsigned int dec_move_rp(DisasContext *dc)
2175 {
2176 TCGv t[2];
2177 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
2178 cris_cc_mask(dc, 0);
2179
2180 t[0] = tcg_temp_new();
2181 if (dc->op2 == PR_CCS) {
2182 cris_evaluate_flags(dc);
2183 t_gen_mov_TN_reg(t[0], dc->op1);
2184 if (dc->tb_flags & U_FLAG) {
2185 t[1] = tcg_temp_new();
2186 /* User space is not allowed to touch all flags. */
2187 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2188 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2189 tcg_gen_or_tl(t[0], t[1], t[0]);
2190 tcg_temp_free(t[1]);
2191 }
2192 }
2193 else
2194 t_gen_mov_TN_reg(t[0], dc->op1);
2195
2196 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2197 if (dc->op2 == PR_CCS) {
2198 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2199 dc->flags_uptodate = 1;
2200 }
2201 tcg_temp_free(t[0]);
2202 return 2;
2203 }
2204 static unsigned int dec_move_pr(DisasContext *dc)
2205 {
2206 TCGv t0;
2207 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
2208 cris_cc_mask(dc, 0);
2209
2210 if (dc->op2 == PR_CCS)
2211 cris_evaluate_flags(dc);
2212
2213 t0 = tcg_temp_new();
2214 t_gen_mov_TN_preg(t0, dc->op2);
2215 cris_alu(dc, CC_OP_MOVE,
2216 cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]);
2217 tcg_temp_free(t0);
2218 return 2;
2219 }
2220
2221 static unsigned int dec_move_mr(DisasContext *dc)
2222 {
2223 int memsize = memsize_zz(dc);
2224 int insn_len;
2225 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2226 memsize_char(memsize),
2227 dc->op1, dc->postinc ? "+]" : "]",
2228 dc->op2));
2229
2230 if (memsize == 4) {
2231 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2232 cris_cc_mask(dc, CC_MASK_NZ);
2233 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2234 cris_update_cc_x(dc);
2235 cris_update_result(dc, cpu_R[dc->op2]);
2236 }
2237 else {
2238 TCGv t0;
2239
2240 t0 = tcg_temp_new();
2241 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2242 cris_cc_mask(dc, CC_MASK_NZ);
2243 cris_alu(dc, CC_OP_MOVE,
2244 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2245 tcg_temp_free(t0);
2246 }
2247 do_postinc(dc, memsize);
2248 return insn_len;
2249 }
2250
2251 static inline void cris_alu_m_alloc_temps(TCGv *t)
2252 {
2253 t[0] = tcg_temp_new();
2254 t[1] = tcg_temp_new();
2255 }
2256
2257 static inline void cris_alu_m_free_temps(TCGv *t)
2258 {
2259 tcg_temp_free(t[0]);
2260 tcg_temp_free(t[1]);
2261 }
2262
2263 static unsigned int dec_movs_m(DisasContext *dc)
2264 {
2265 TCGv t[2];
2266 int memsize = memsize_z(dc);
2267 int insn_len;
2268 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2269 memsize_char(memsize),
2270 dc->op1, dc->postinc ? "+]" : "]",
2271 dc->op2));
2272
2273 cris_alu_m_alloc_temps(t);
2274 /* sign extend. */
2275 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2276 cris_cc_mask(dc, CC_MASK_NZ);
2277 cris_alu(dc, CC_OP_MOVE,
2278 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2279 do_postinc(dc, memsize);
2280 cris_alu_m_free_temps(t);
2281 return insn_len;
2282 }
2283
2284 static unsigned int dec_addu_m(DisasContext *dc)
2285 {
2286 TCGv t[2];
2287 int memsize = memsize_z(dc);
2288 int insn_len;
2289 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2290 memsize_char(memsize),
2291 dc->op1, dc->postinc ? "+]" : "]",
2292 dc->op2));
2293
2294 cris_alu_m_alloc_temps(t);
2295 /* sign extend. */
2296 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2297 cris_cc_mask(dc, CC_MASK_NZVC);
2298 cris_alu(dc, CC_OP_ADD,
2299 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2300 do_postinc(dc, memsize);
2301 cris_alu_m_free_temps(t);
2302 return insn_len;
2303 }
2304
2305 static unsigned int dec_adds_m(DisasContext *dc)
2306 {
2307 TCGv t[2];
2308 int memsize = memsize_z(dc);
2309 int insn_len;
2310 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2311 memsize_char(memsize),
2312 dc->op1, dc->postinc ? "+]" : "]",
2313 dc->op2));
2314
2315 cris_alu_m_alloc_temps(t);
2316 /* sign extend. */
2317 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2318 cris_cc_mask(dc, CC_MASK_NZVC);
2319 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2320 do_postinc(dc, memsize);
2321 cris_alu_m_free_temps(t);
2322 return insn_len;
2323 }
2324
2325 static unsigned int dec_subu_m(DisasContext *dc)
2326 {
2327 TCGv t[2];
2328 int memsize = memsize_z(dc);
2329 int insn_len;
2330 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2331 memsize_char(memsize),
2332 dc->op1, dc->postinc ? "+]" : "]",
2333 dc->op2));
2334
2335 cris_alu_m_alloc_temps(t);
2336 /* sign extend. */
2337 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2338 cris_cc_mask(dc, CC_MASK_NZVC);
2339 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2340 do_postinc(dc, memsize);
2341 cris_alu_m_free_temps(t);
2342 return insn_len;
2343 }
2344
2345 static unsigned int dec_subs_m(DisasContext *dc)
2346 {
2347 TCGv t[2];
2348 int memsize = memsize_z(dc);
2349 int insn_len;
2350 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2351 memsize_char(memsize),
2352 dc->op1, dc->postinc ? "+]" : "]",
2353 dc->op2));
2354
2355 cris_alu_m_alloc_temps(t);
2356 /* sign extend. */
2357 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2358 cris_cc_mask(dc, CC_MASK_NZVC);
2359 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2360 do_postinc(dc, memsize);
2361 cris_alu_m_free_temps(t);
2362 return insn_len;
2363 }
2364
2365 static unsigned int dec_movu_m(DisasContext *dc)
2366 {
2367 TCGv t[2];
2368 int memsize = memsize_z(dc);
2369 int insn_len;
2370
2371 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2372 memsize_char(memsize),
2373 dc->op1, dc->postinc ? "+]" : "]",
2374 dc->op2));
2375
2376 cris_alu_m_alloc_temps(t);
2377 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2378 cris_cc_mask(dc, CC_MASK_NZ);
2379 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2380 do_postinc(dc, memsize);
2381 cris_alu_m_free_temps(t);
2382 return insn_len;
2383 }
2384
2385 static unsigned int dec_cmpu_m(DisasContext *dc)
2386 {
2387 TCGv t[2];
2388 int memsize = memsize_z(dc);
2389 int insn_len;
2390 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2391 memsize_char(memsize),
2392 dc->op1, dc->postinc ? "+]" : "]",
2393 dc->op2));
2394
2395 cris_alu_m_alloc_temps(t);
2396 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2397 cris_cc_mask(dc, CC_MASK_NZVC);
2398 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2399 do_postinc(dc, memsize);
2400 cris_alu_m_free_temps(t);
2401 return insn_len;
2402 }
2403
2404 static unsigned int dec_cmps_m(DisasContext *dc)
2405 {
2406 TCGv t[2];
2407 int memsize = memsize_z(dc);
2408 int insn_len;
2409 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2410 memsize_char(memsize),
2411 dc->op1, dc->postinc ? "+]" : "]",
2412 dc->op2));
2413
2414 cris_alu_m_alloc_temps(t);
2415 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2416 cris_cc_mask(dc, CC_MASK_NZVC);
2417 cris_alu(dc, CC_OP_CMP,
2418 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2419 memsize_zz(dc));
2420 do_postinc(dc, memsize);
2421 cris_alu_m_free_temps(t);
2422 return insn_len;
2423 }
2424
2425 static unsigned int dec_cmp_m(DisasContext *dc)
2426 {
2427 TCGv t[2];
2428 int memsize = memsize_zz(dc);
2429 int insn_len;
2430 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2431 memsize_char(memsize),
2432 dc->op1, dc->postinc ? "+]" : "]",
2433 dc->op2));
2434
2435 cris_alu_m_alloc_temps(t);
2436 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2437 cris_cc_mask(dc, CC_MASK_NZVC);
2438 cris_alu(dc, CC_OP_CMP,
2439 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2440 memsize_zz(dc));
2441 do_postinc(dc, memsize);
2442 cris_alu_m_free_temps(t);
2443 return insn_len;
2444 }
2445
2446 static unsigned int dec_test_m(DisasContext *dc)
2447 {
2448 TCGv t[2];
2449 int memsize = memsize_zz(dc);
2450 int insn_len;
2451 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2452 memsize_char(memsize),
2453 dc->op1, dc->postinc ? "+]" : "]",
2454 dc->op2));
2455
2456 cris_evaluate_flags(dc);
2457
2458 cris_alu_m_alloc_temps(t);
2459 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2460 cris_cc_mask(dc, CC_MASK_NZ);
2461 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2462
2463 cris_alu(dc, CC_OP_CMP,
2464 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2465 do_postinc(dc, memsize);
2466 cris_alu_m_free_temps(t);
2467 return insn_len;
2468 }
2469
2470 static unsigned int dec_and_m(DisasContext *dc)
2471 {
2472 TCGv t[2];
2473 int memsize = memsize_zz(dc);
2474 int insn_len;
2475 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2476 memsize_char(memsize),
2477 dc->op1, dc->postinc ? "+]" : "]",
2478 dc->op2));
2479
2480 cris_alu_m_alloc_temps(t);
2481 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2482 cris_cc_mask(dc, CC_MASK_NZ);
2483 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2484 do_postinc(dc, memsize);
2485 cris_alu_m_free_temps(t);
2486 return insn_len;
2487 }
2488
2489 static unsigned int dec_add_m(DisasContext *dc)
2490 {
2491 TCGv t[2];
2492 int memsize = memsize_zz(dc);
2493 int insn_len;
2494 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2495 memsize_char(memsize),
2496 dc->op1, dc->postinc ? "+]" : "]",
2497 dc->op2));
2498
2499 cris_alu_m_alloc_temps(t);
2500 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2501 cris_cc_mask(dc, CC_MASK_NZVC);
2502 cris_alu(dc, CC_OP_ADD,
2503 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2504 do_postinc(dc, memsize);
2505 cris_alu_m_free_temps(t);
2506 return insn_len;
2507 }
2508
2509 static unsigned int dec_addo_m(DisasContext *dc)
2510 {
2511 TCGv t[2];
2512 int memsize = memsize_zz(dc);
2513 int insn_len;
2514 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2515 memsize_char(memsize),
2516 dc->op1, dc->postinc ? "+]" : "]",
2517 dc->op2));
2518
2519 cris_alu_m_alloc_temps(t);
2520 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2521 cris_cc_mask(dc, 0);
2522 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2523 do_postinc(dc, memsize);
2524 cris_alu_m_free_temps(t);
2525 return insn_len;
2526 }
2527
2528 static unsigned int dec_bound_m(DisasContext *dc)
2529 {
2530 TCGv l[2];
2531 int memsize = memsize_zz(dc);
2532 int insn_len;
2533 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2534 memsize_char(memsize),
2535 dc->op1, dc->postinc ? "+]" : "]",
2536 dc->op2));
2537
2538 l[0] = tcg_temp_local_new();
2539 l[1] = tcg_temp_local_new();
2540 insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
2541 cris_cc_mask(dc, CC_MASK_NZ);
2542 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2543 do_postinc(dc, memsize);
2544 tcg_temp_free(l[0]);
2545 tcg_temp_free(l[1]);
2546 return insn_len;
2547 }
2548
2549 static unsigned int dec_addc_mr(DisasContext *dc)
2550 {
2551 TCGv t[2];
2552 int insn_len = 2;
2553 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2554 dc->op1, dc->postinc ? "+]" : "]",
2555 dc->op2));
2556
2557 cris_evaluate_flags(dc);
2558
2559 /* Set for this insn. */
2560 dc->flagx_known = 1;
2561 dc->flags_x = X_FLAG;
2562
2563 cris_alu_m_alloc_temps(t);
2564 insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
2565 cris_cc_mask(dc, CC_MASK_NZVC);
2566 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2567 do_postinc(dc, 4);
2568 cris_alu_m_free_temps(t);
2569 return insn_len;
2570 }
2571
2572 static unsigned int dec_sub_m(DisasContext *dc)
2573 {
2574 TCGv t[2];
2575 int memsize = memsize_zz(dc);
2576 int insn_len;
2577 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2578 memsize_char(memsize),
2579 dc->op1, dc->postinc ? "+]" : "]",
2580 dc->op2, dc->ir, dc->zzsize));
2581
2582 cris_alu_m_alloc_temps(t);
2583 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2584 cris_cc_mask(dc, CC_MASK_NZVC);
2585 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2586 do_postinc(dc, memsize);
2587 cris_alu_m_free_temps(t);
2588 return insn_len;
2589 }
2590
2591 static unsigned int dec_or_m(DisasContext *dc)
2592 {
2593 TCGv t[2];
2594 int memsize = memsize_zz(dc);
2595 int insn_len;
2596 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2597 memsize_char(memsize),
2598 dc->op1, dc->postinc ? "+]" : "]",
2599 dc->op2, dc->pc));
2600
2601 cris_alu_m_alloc_temps(t);
2602 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2603 cris_cc_mask(dc, CC_MASK_NZ);
2604 cris_alu(dc, CC_OP_OR,
2605 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2606 do_postinc(dc, memsize);
2607 cris_alu_m_free_temps(t);
2608 return insn_len;
2609 }
2610
2611 static unsigned int dec_move_mp(DisasContext *dc)
2612 {
2613 TCGv t[2];
2614 int memsize = memsize_zz(dc);
2615 int insn_len = 2;
2616
2617 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2618 memsize_char(memsize),
2619 dc->op1,
2620 dc->postinc ? "+]" : "]",
2621 dc->op2));
2622
2623 cris_alu_m_alloc_temps(t);
2624 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2625 cris_cc_mask(dc, 0);
2626 if (dc->op2 == PR_CCS) {
2627 cris_evaluate_flags(dc);
2628 if (dc->tb_flags & U_FLAG) {
2629 /* User space is not allowed to touch all flags. */
2630 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2631 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2632 tcg_gen_or_tl(t[1], t[0], t[1]);
2633 }
2634 }
2635
2636 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2637
2638 do_postinc(dc, memsize);
2639 cris_alu_m_free_temps(t);
2640 return insn_len;
2641 }
2642
2643 static unsigned int dec_move_pm(DisasContext *dc)
2644 {
2645 TCGv t0;
2646 int memsize;
2647
2648 memsize = preg_sizes[dc->op2];
2649
2650 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2651 memsize_char(memsize),
2652 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2653
2654 /* prepare store. Address in T0, value in T1. */
2655 if (dc->op2 == PR_CCS)
2656 cris_evaluate_flags(dc);
2657 t0 = tcg_temp_new();
2658 t_gen_mov_TN_preg(t0, dc->op2);
2659 cris_flush_cc_state(dc);
2660 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2661 tcg_temp_free(t0);
2662
2663 cris_cc_mask(dc, 0);
2664 if (dc->postinc)
2665 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2666 return 2;
2667 }
2668
2669 static unsigned int dec_movem_mr(DisasContext *dc)
2670 {
2671 TCGv_i64 tmp[16];
2672 TCGv tmp32;
2673 TCGv addr;
2674 int i;
2675 int nr = dc->op2 + 1;
2676
2677 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2678 dc->postinc ? "+]" : "]", dc->op2));
2679
2680 addr = tcg_temp_new();
2681 /* There are probably better ways of doing this. */
2682 cris_flush_cc_state(dc);
2683 for (i = 0; i < (nr >> 1); i++) {
2684 tmp[i] = tcg_temp_new_i64();
2685 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2686 gen_load64(dc, tmp[i], addr);
2687 }
2688 if (nr & 1) {
2689 tmp32 = tcg_temp_new_i32();
2690 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2691 gen_load(dc, tmp32, addr, 4, 0);
2692 }
2693 tcg_temp_free(addr);
2694
2695 for (i = 0; i < (nr >> 1); i++) {
2696 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2697 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2698 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2699 tcg_temp_free_i64(tmp[i]);
2700 }
2701 if (nr & 1) {
2702 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2703 tcg_temp_free(tmp32);
2704 }
2705
2706 /* writeback the updated pointer value. */
2707 if (dc->postinc)
2708 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2709
2710 /* gen_load might want to evaluate the previous insns flags. */
2711 cris_cc_mask(dc, 0);
2712 return 2;
2713 }
2714
2715 static unsigned int dec_movem_rm(DisasContext *dc)
2716 {
2717 TCGv tmp;
2718 TCGv addr;
2719 int i;
2720
2721 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2722 dc->postinc ? "+]" : "]"));
2723
2724 cris_flush_cc_state(dc);
2725
2726 tmp = tcg_temp_new();
2727 addr = tcg_temp_new();
2728 tcg_gen_movi_tl(tmp, 4);
2729 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2730 for (i = 0; i <= dc->op2; i++) {
2731 /* Displace addr. */
2732 /* Perform the store. */
2733 gen_store(dc, addr, cpu_R[i], 4);
2734 tcg_gen_add_tl(addr, addr, tmp);
2735 }
2736 if (dc->postinc)
2737 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2738 cris_cc_mask(dc, 0);
2739 tcg_temp_free(tmp);
2740 tcg_temp_free(addr);
2741 return 2;
2742 }
2743
2744 static unsigned int dec_move_rm(DisasContext *dc)
2745 {
2746 int memsize;
2747
2748 memsize = memsize_zz(dc);
2749
2750 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2751 memsize, dc->op2, dc->op1));
2752
2753 /* prepare store. */
2754 cris_flush_cc_state(dc);
2755 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2756
2757 if (dc->postinc)
2758 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2759 cris_cc_mask(dc, 0);
2760 return 2;
2761 }
2762
2763 static unsigned int dec_lapcq(DisasContext *dc)
2764 {
2765 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2766 dc->pc + dc->op1*2, dc->op2));
2767 cris_cc_mask(dc, 0);
2768 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2769 return 2;
2770 }
2771
2772 static unsigned int dec_lapc_im(DisasContext *dc)
2773 {
2774 unsigned int rd;
2775 int32_t imm;
2776 int32_t pc;
2777
2778 rd = dc->op2;
2779
2780 cris_cc_mask(dc, 0);
2781 imm = ldl_code(dc->pc + 2);
2782 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2783
2784 pc = dc->pc;
2785 pc += imm;
2786 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2787 return 6;
2788 }
2789
2790 /* Jump to special reg. */
2791 static unsigned int dec_jump_p(DisasContext *dc)
2792 {
2793 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2794
2795 if (dc->op2 == PR_CCS)
2796 cris_evaluate_flags(dc);
2797 t_gen_mov_TN_preg(env_btarget, dc->op2);
2798 /* rete will often have low bit set to indicate delayslot. */
2799 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2800 cris_cc_mask(dc, 0);
2801 cris_prepare_jmp(dc, JMP_INDIRECT);
2802 return 2;
2803 }
2804
2805 /* Jump and save. */
2806 static unsigned int dec_jas_r(DisasContext *dc)
2807 {
2808 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2809 cris_cc_mask(dc, 0);
2810 /* Store the return address in Pd. */
2811 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2812 if (dc->op2 > 15)
2813 abort();
2814 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2815
2816 cris_prepare_jmp(dc, JMP_INDIRECT);
2817 return 2;
2818 }
2819
2820 static unsigned int dec_jas_im(DisasContext *dc)
2821 {
2822 uint32_t imm;
2823
2824 imm = ldl_code(dc->pc + 2);
2825
2826 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2827 cris_cc_mask(dc, 0);
2828 /* Store the return address in Pd. */
2829 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2830
2831 dc->jmp_pc = imm;
2832 cris_prepare_jmp(dc, JMP_DIRECT);
2833 return 6;
2834 }
2835
2836 static unsigned int dec_jasc_im(DisasContext *dc)
2837 {
2838 uint32_t imm;
2839
2840 imm = ldl_code(dc->pc + 2);
2841
2842 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2843 cris_cc_mask(dc, 0);
2844 /* Store the return address in Pd. */
2845 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2846
2847 dc->jmp_pc = imm;
2848 cris_prepare_jmp(dc, JMP_DIRECT);
2849 return 6;
2850 }
2851
2852 static unsigned int dec_jasc_r(DisasContext *dc)
2853 {
2854 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2855 cris_cc_mask(dc, 0);
2856 /* Store the return address in Pd. */
2857 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2858 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2859 cris_prepare_jmp(dc, JMP_INDIRECT);
2860 return 2;
2861 }
2862
2863 static unsigned int dec_bcc_im(DisasContext *dc)
2864 {
2865 int32_t offset;
2866 uint32_t cond = dc->op2;
2867
2868 offset = ldsw_code(dc->pc + 2);
2869
2870 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2871 cc_name(cond), offset,
2872 dc->pc, dc->pc + offset));
2873
2874 cris_cc_mask(dc, 0);
2875 /* op2 holds the condition-code. */
2876 cris_prepare_cc_branch (dc, offset, cond);
2877 return 4;
2878 }
2879
2880 static unsigned int dec_bas_im(DisasContext *dc)
2881 {
2882 int32_t simm;
2883
2884
2885 simm = ldl_code(dc->pc + 2);
2886
2887 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2888 cris_cc_mask(dc, 0);
2889 /* Store the return address in Pd. */
2890 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2891
2892 dc->jmp_pc = dc->pc + simm;
2893 cris_prepare_jmp(dc, JMP_DIRECT);
2894 return 6;
2895 }
2896
2897 static unsigned int dec_basc_im(DisasContext *dc)
2898 {
2899 int32_t simm;
2900 simm = ldl_code(dc->pc + 2);
2901
2902 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2903 cris_cc_mask(dc, 0);
2904 /* Store the return address in Pd. */
2905 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2906
2907 dc->jmp_pc = dc->pc + simm;
2908 cris_prepare_jmp(dc, JMP_DIRECT);
2909 return 6;
2910 }
2911
2912 static unsigned int dec_rfe_etc(DisasContext *dc)
2913 {
2914 cris_cc_mask(dc, 0);
2915
2916 if (dc->op2 == 15) {
2917 t_gen_mov_env_TN(halted, tcg_const_tl(1));
2918 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2919 t_gen_raise_exception(EXCP_HLT);
2920 return 2;
2921 }
2922
2923 switch (dc->op2 & 7) {
2924 case 2:
2925 /* rfe. */
2926 DIS(fprintf(logfile, "rfe\n"));
2927 cris_evaluate_flags(dc);
2928 gen_helper_rfe();
2929 dc->is_jmp = DISAS_UPDATE;
2930 break;
2931 case 5:
2932 /* rfn. */
2933 DIS(fprintf(logfile, "rfn\n"));
2934 cris_evaluate_flags(dc);
2935 gen_helper_rfn();
2936 dc->is_jmp = DISAS_UPDATE;
2937 break;
2938 case 6:
2939 DIS(fprintf(logfile, "break %d\n", dc->op1));
2940 cris_evaluate_flags (dc);
2941 /* break. */
2942 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2943
2944 /* Breaks start at 16 in the exception vector. */
2945 t_gen_mov_env_TN(trap_vector,
2946 tcg_const_tl(dc->op1 + 16));
2947 t_gen_raise_exception(EXCP_BREAK);
2948 dc->is_jmp = DISAS_UPDATE;
2949 break;
2950 default:
2951 printf ("op2=%x\n", dc->op2);
2952 BUG();
2953 break;
2954
2955 }
2956 return 2;
2957 }
2958
2959 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2960 {
2961 return 2;
2962 }
2963
2964 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2965 {
2966 return 2;
2967 }
2968
2969 static unsigned int dec_null(DisasContext *dc)
2970 {
2971 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2972 dc->pc, dc->opcode, dc->op1, dc->op2);
2973 fflush(NULL);
2974 BUG();
2975 return 2;
2976 }
2977
2978 static struct decoder_info {
2979 struct {
2980 uint32_t bits;
2981 uint32_t mask;
2982 };
2983 unsigned int (*dec)(DisasContext *dc);
2984 } decinfo[] = {
2985 /* Order matters here. */
2986 {DEC_MOVEQ, dec_moveq},
2987 {DEC_BTSTQ, dec_btstq},
2988 {DEC_CMPQ, dec_cmpq},
2989 {DEC_ADDOQ, dec_addoq},
2990 {DEC_ADDQ, dec_addq},
2991 {DEC_SUBQ, dec_subq},
2992 {DEC_ANDQ, dec_andq},
2993 {DEC_ORQ, dec_orq},
2994 {DEC_ASRQ, dec_asrq},
2995 {DEC_LSLQ, dec_lslq},
2996 {DEC_LSRQ, dec_lsrq},
2997 {DEC_BCCQ, dec_bccq},
2998
2999 {DEC_BCC_IM, dec_bcc_im},
3000 {DEC_JAS_IM, dec_jas_im},
3001 {DEC_JAS_R, dec_jas_r},
3002 {DEC_JASC_IM, dec_jasc_im},
3003 {DEC_JASC_R, dec_jasc_r},
3004 {DEC_BAS_IM, dec_bas_im},
3005 {DEC_BASC_IM, dec_basc_im},
3006 {DEC_JUMP_P, dec_jump_p},
3007 {DEC_LAPC_IM, dec_lapc_im},
3008 {DEC_LAPCQ, dec_lapcq},
3009
3010 {DEC_RFE_ETC, dec_rfe_etc},
3011 {DEC_ADDC_MR, dec_addc_mr},
3012
3013 {DEC_MOVE_MP, dec_move_mp},
3014 {DEC_MOVE_PM, dec_move_pm},
3015 {DEC_MOVEM_MR, dec_movem_mr},
3016 {DEC_MOVEM_RM, dec_movem_rm},
3017 {DEC_MOVE_PR, dec_move_pr},
3018 {DEC_SCC_R, dec_scc_r},
3019 {DEC_SETF, dec_setclrf},
3020 {DEC_CLEARF, dec_setclrf},
3021
3022 {DEC_MOVE_SR, dec_move_sr},
3023 {DEC_MOVE_RP, dec_move_rp},
3024 {DEC_SWAP_R, dec_swap_r},
3025 {DEC_ABS_R, dec_abs_r},
3026 {DEC_LZ_R, dec_lz_r},
3027 {DEC_MOVE_RS, dec_move_rs},
3028 {DEC_BTST_R, dec_btst_r},
3029 {DEC_ADDC_R, dec_addc_r},
3030
3031 {DEC_DSTEP_R, dec_dstep_r},
3032 {DEC_XOR_R, dec_xor_r},
3033 {DEC_MCP_R, dec_mcp_r},
3034 {DEC_CMP_R, dec_cmp_r},
3035
3036 {DEC_ADDI_R, dec_addi_r},
3037 {DEC_ADDI_ACR, dec_addi_acr},
3038
3039 {DEC_ADD_R, dec_add_r},
3040 {DEC_SUB_R, dec_sub_r},
3041
3042 {DEC_ADDU_R, dec_addu_r},
3043 {DEC_ADDS_R, dec_adds_r},
3044 {DEC_SUBU_R, dec_subu_r},
3045 {DEC_SUBS_R, dec_subs_r},
3046 {DEC_LSL_R, dec_lsl_r},
3047
3048 {DEC_AND_R, dec_and_r},
3049 {DEC_OR_R, dec_or_r},
3050 {DEC_BOUND_R, dec_bound_r},
3051 {DEC_ASR_R, dec_asr_r},
3052 {DEC_LSR_R, dec_lsr_r},
3053
3054 {DEC_MOVU_R, dec_movu_r},
3055 {DEC_MOVS_R, dec_movs_r},
3056 {DEC_NEG_R, dec_neg_r},
3057 {DEC_MOVE_R, dec_move_r},
3058
3059 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3060 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3061
3062 {DEC_MULS_R, dec_muls_r},
3063 {DEC_MULU_R, dec_mulu_r},
3064
3065 {DEC_ADDU_M, dec_addu_m},
3066 {DEC_ADDS_M, dec_adds_m},
3067 {DEC_SUBU_M, dec_subu_m},
3068 {DEC_SUBS_M, dec_subs_m},
3069
3070 {DEC_CMPU_M, dec_cmpu_m},
3071 {DEC_CMPS_M, dec_cmps_m},
3072 {DEC_MOVU_M, dec_movu_m},
3073 {DEC_MOVS_M, dec_movs_m},
3074
3075 {DEC_CMP_M, dec_cmp_m},
3076 {DEC_ADDO_M, dec_addo_m},
3077 {DEC_BOUND_M, dec_bound_m},
3078 {DEC_ADD_M, dec_add_m},
3079 {DEC_SUB_M, dec_sub_m},
3080 {DEC_AND_M, dec_and_m},
3081 {DEC_OR_M, dec_or_m},
3082 {DEC_MOVE_RM, dec_move_rm},
3083 {DEC_TEST_M, dec_test_m},
3084 {DEC_MOVE_MR, dec_move_mr},
3085
3086 {{0, 0}, dec_null}
3087 };
3088
3089 static inline unsigned int
3090 cris_decoder(DisasContext *dc)
3091 {
3092 unsigned int insn_len = 2;
3093 int i;
3094
3095 if (unlikely(loglevel & CPU_LOG_TB_OP))
3096 tcg_gen_debug_insn_start(dc->pc);
3097
3098 /* Load a halfword onto the instruction register. */
3099 dc->ir = lduw_code(dc->pc);
3100
3101 /* Now decode it. */
3102 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3103 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3104 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3105 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3106 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3107 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3108
3109 /* Large switch for all insns. */
3110 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3111 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3112 {
3113 insn_len = decinfo[i].dec(dc);
3114 break;
3115 }
3116 }
3117
3118 #if !defined(CONFIG_USER_ONLY)
3119 /* Single-stepping ? */
3120 if (dc->tb_flags & S_FLAG) {
3121 int l1;
3122
3123 l1 = gen_new_label();
3124 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3125 /* We treat SPC as a break with an odd trap vector. */
3126 cris_evaluate_flags (dc);
3127 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3128 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3129 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3130 t_gen_raise_exception(EXCP_BREAK);
3131 gen_set_label(l1);
3132 }
3133 #endif
3134 return insn_len;
3135 }
3136
3137 static void check_breakpoint(CPUState *env, DisasContext *dc)
3138 {
3139 CPUBreakpoint *bp;
3140
3141 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
3142 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
3143 if (bp->pc == dc->pc) {
3144 cris_evaluate_flags (dc);
3145 tcg_gen_movi_tl(env_pc, dc->pc);
3146 t_gen_raise_exception(EXCP_DEBUG);
3147 dc->is_jmp = DISAS_UPDATE;
3148 }
3149 }
3150 }
3151 }
3152
3153
3154 /*
3155 * Delay slots on QEMU/CRIS.
3156 *
3157 * If an exception hits on a delayslot, the core will let ERP (the Exception
3158 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3159 * to give SW a hint that the exception actually hit on the dslot.
3160 *
3161 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3162 * the core and any jmp to an odd addresses will mask off that lsb. It is
3163 * simply there to let sw know there was an exception on a dslot.
3164 *
3165 * When the software returns from an exception, the branch will re-execute.
3166 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3167 * and the branch and delayslot dont share pages.
3168 *
3169 * The TB contaning the branch insn will set up env->btarget and evaluate
3170 * env->btaken. When the translation loop exits we will note that the branch
3171 * sequence is broken and let env->dslot be the size of the branch insn (those
3172 * vary in length).
3173 *
3174 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3175 * set). It will also expect to have env->dslot setup with the size of the
3176 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3177 * will execute the dslot and take the branch, either to btarget or just one
3178 * insn ahead.
3179 *
3180 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3181 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3182 * branch and set lsb). Then env->dslot gets cleared so that the exception
3183 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3184 * masked off and we will reexecute the branch insn.
3185 *
3186 */
3187
3188 /* generate intermediate code for basic block 'tb'. */
3189 static void
3190 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3191 int search_pc)
3192 {
3193 uint16_t *gen_opc_end;
3194 uint32_t pc_start;
3195 unsigned int insn_len;
3196 int j, lj;
3197 struct DisasContext ctx;
3198 struct DisasContext *dc = &ctx;
3199 uint32_t next_page_start;
3200 target_ulong npc;
3201 int num_insns;
3202 int max_insns;
3203
3204 if (!logfile)
3205 logfile = stderr;
3206
3207 /* Odd PC indicates that branch is rexecuting due to exception in the
3208 * delayslot, like in real hw.
3209 */
3210 pc_start = tb->pc & ~1;
3211 dc->env = env;
3212 dc->tb = tb;
3213
3214 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3215
3216 dc->is_jmp = DISAS_NEXT;
3217 dc->ppc = pc_start;
3218 dc->pc = pc_start;
3219 dc->singlestep_enabled = env->singlestep_enabled;
3220 dc->flags_uptodate = 1;
3221 dc->flagx_known = 1;
3222 dc->flags_x = tb->flags & X_FLAG;
3223 dc->cc_x_uptodate = 0;
3224 dc->cc_mask = 0;
3225 dc->update_cc = 0;
3226
3227 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3228 dc->cc_size_uptodate = -1;
3229
3230 /* Decode TB flags. */
3231 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
3232 dc->delayed_branch = !!(tb->flags & 7);
3233 if (dc->delayed_branch)
3234 dc->jmp = JMP_INDIRECT;
3235 else
3236 dc->jmp = JMP_NOJMP;
3237
3238 dc->cpustate_changed = 0;
3239
3240 if (loglevel & CPU_LOG_TB_IN_ASM) {
3241 fprintf(logfile,
3242 "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
3243 "pid=%x usp=%x\n"
3244 "%x.%x.%x.%x\n"
3245 "%x.%x.%x.%x\n"
3246 "%x.%x.%x.%x\n"
3247 "%x.%x.%x.%x\n",
3248 search_pc, dc->pc, dc->ppc,
3249 (unsigned long long)tb->flags,
3250 env->btarget, (unsigned)tb->flags & 7,
3251 env->pregs[PR_CCS],
3252 env->pregs[PR_PID], env->pregs[PR_USP],
3253 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3254 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3255 env->regs[8], env->regs[9],
3256 env->regs[10], env->regs[11],
3257 env->regs[12], env->regs[13],
3258 env->regs[14], env->regs[15]);
3259 fprintf(logfile, "--------------\n");
3260 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3261 }
3262
3263 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3264 lj = -1;
3265 num_insns = 0;
3266 max_insns = tb->cflags & CF_COUNT_MASK;
3267 if (max_insns == 0)
3268 max_insns = CF_COUNT_MASK;
3269
3270 gen_icount_start();
3271 do
3272 {
3273 check_breakpoint(env, dc);
3274
3275 if (search_pc) {
3276 j = gen_opc_ptr - gen_opc_buf;
3277 if (lj < j) {
3278 lj++;
3279 while (lj < j)
3280 gen_opc_instr_start[lj++] = 0;
3281 }
3282 if (dc->delayed_branch == 1)
3283 gen_opc_pc[lj] = dc->ppc | 1;
3284 else
3285 gen_opc_pc[lj] = dc->pc;
3286 gen_opc_instr_start[lj] = 1;
3287 gen_opc_icount[lj] = num_insns;
3288 }
3289
3290 /* Pretty disas. */
3291 DIS(fprintf(logfile, "%8.8x:\t", dc->pc));
3292
3293 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3294 gen_io_start();
3295 dc->clear_x = 1;
3296
3297 insn_len = cris_decoder(dc);
3298 dc->ppc = dc->pc;
3299 dc->pc += insn_len;
3300 if (dc->clear_x)
3301 cris_clear_x_flag(dc);
3302
3303 num_insns++;
3304 /* Check for delayed branches here. If we do it before
3305 actually generating any host code, the simulator will just
3306 loop doing nothing for on this program location. */
3307 if (dc->delayed_branch) {
3308 dc->delayed_branch--;
3309 if (dc->delayed_branch == 0)
3310 {
3311 if (tb->flags & 7)
3312 t_gen_mov_env_TN(dslot,
3313 tcg_const_tl(0));
3314 if (dc->jmp == JMP_DIRECT) {
3315 dc->is_jmp = DISAS_NEXT;
3316 } else {
3317 t_gen_cc_jmp(env_btarget,
3318 tcg_const_tl(dc->pc));
3319 dc->is_jmp = DISAS_JUMP;
3320 }
3321 break;
3322 }
3323 }
3324
3325 /* If we are rexecuting a branch due to exceptions on
3326 delay slots dont break. */
3327 if (!(tb->pc & 1) && env->singlestep_enabled)
3328 break;
3329 } while (!dc->is_jmp && !dc->cpustate_changed
3330 && gen_opc_ptr < gen_opc_end
3331 && (dc->pc < next_page_start)
3332 && num_insns < max_insns);
3333
3334 npc = dc->pc;
3335 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3336 npc = dc->jmp_pc;
3337
3338 if (tb->cflags & CF_LAST_IO)
3339 gen_io_end();
3340 /* Force an update if the per-tb cpu state has changed. */
3341 if (dc->is_jmp == DISAS_NEXT
3342 && (dc->cpustate_changed || !dc->flagx_known
3343 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3344 dc->is_jmp = DISAS_UPDATE;
3345 tcg_gen_movi_tl(env_pc, npc);
3346 }
3347 /* Broken branch+delayslot sequence. */
3348 if (dc->delayed_branch == 1) {
3349 /* Set env->dslot to the size of the branch insn. */
3350 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3351 cris_store_direct_jmp(dc);
3352 }
3353
3354 cris_evaluate_flags (dc);
3355
3356 if (unlikely(env->singlestep_enabled)) {
3357 if (dc->is_jmp == DISAS_NEXT)
3358 tcg_gen_movi_tl(env_pc, npc);
3359 t_gen_raise_exception(EXCP_DEBUG);
3360 } else {
3361 switch(dc->is_jmp) {
3362 case DISAS_NEXT:
3363 gen_goto_tb(dc, 1, npc);
3364 break;
3365 default:
3366 case DISAS_JUMP:
3367 case DISAS_UPDATE:
3368 /* indicate that the hash table must be used
3369 to find the next TB */
3370 tcg_gen_exit_tb(0);
3371 break;
3372 case DISAS_SWI:
3373 case DISAS_TB_JUMP:
3374 /* nothing more to generate */
3375 break;
3376 }
3377 }
3378 gen_icount_end(tb, num_insns);
3379 *gen_opc_ptr = INDEX_op_end;
3380 if (search_pc) {
3381 j = gen_opc_ptr - gen_opc_buf;
3382 lj++;
3383 while (lj <= j)
3384 gen_opc_instr_start[lj++] = 0;
3385 } else {
3386 tb->size = dc->pc - pc_start;
3387 tb->icount = num_insns;
3388 }
3389
3390 #ifdef DEBUG_DISAS
3391 #if !DISAS_CRIS
3392 if (loglevel & CPU_LOG_TB_IN_ASM) {
3393 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
3394 fprintf(logfile, "\nisize=%d osize=%zd\n",
3395 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3396 }
3397 #endif
3398 #endif
3399 }
3400
3401 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3402 {
3403 gen_intermediate_code_internal(env, tb, 0);
3404 }
3405
3406 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3407 {
3408 gen_intermediate_code_internal(env, tb, 1);
3409 }
3410
3411 void cpu_dump_state (CPUState *env, FILE *f,
3412 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3413 int flags)
3414 {
3415 int i;
3416 uint32_t srs;
3417
3418 if (!env || !f)
3419 return;
3420
3421 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3422 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3423 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3424 env->cc_op,
3425 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3426
3427
3428 for (i = 0; i < 16; i++) {
3429 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3430 if ((i + 1) % 4 == 0)
3431 cpu_fprintf(f, "\n");
3432 }
3433 cpu_fprintf(f, "\nspecial regs:\n");
3434 for (i = 0; i < 16; i++) {
3435 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3436 if ((i + 1) % 4 == 0)
3437 cpu_fprintf(f, "\n");
3438 }
3439 srs = env->pregs[PR_SRS];
3440 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3441 if (srs < 256) {
3442 for (i = 0; i < 16; i++) {
3443 cpu_fprintf(f, "s%2.2d=%8.8x ",
3444 i, env->sregs[srs][i]);
3445 if ((i + 1) % 4 == 0)
3446 cpu_fprintf(f, "\n");
3447 }
3448 }
3449 cpu_fprintf(f, "\n\n");
3450
3451 }
3452
3453 CPUCRISState *cpu_cris_init (const char *cpu_model)
3454 {
3455 CPUCRISState *env;
3456 static int tcg_initialized = 0;
3457 int i;
3458
3459 env = qemu_mallocz(sizeof(CPUCRISState));
3460 if (!env)
3461 return NULL;
3462
3463 cpu_exec_init(env);
3464 cpu_reset(env);
3465
3466 if (tcg_initialized)
3467 return env;
3468
3469 tcg_initialized = 1;
3470
3471 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3472 cc_x = tcg_global_mem_new(TCG_AREG0,
3473 offsetof(CPUState, cc_x), "cc_x");
3474 cc_src = tcg_global_mem_new(TCG_AREG0,
3475 offsetof(CPUState, cc_src), "cc_src");
3476 cc_dest = tcg_global_mem_new(TCG_AREG0,
3477 offsetof(CPUState, cc_dest),
3478 "cc_dest");
3479 cc_result = tcg_global_mem_new(TCG_AREG0,
3480 offsetof(CPUState, cc_result),
3481 "cc_result");
3482 cc_op = tcg_global_mem_new(TCG_AREG0,
3483 offsetof(CPUState, cc_op), "cc_op");
3484 cc_size = tcg_global_mem_new(TCG_AREG0,
3485 offsetof(CPUState, cc_size),
3486 "cc_size");
3487 cc_mask = tcg_global_mem_new(TCG_AREG0,
3488 offsetof(CPUState, cc_mask),
3489 "cc_mask");
3490
3491 env_pc = tcg_global_mem_new(TCG_AREG0,
3492 offsetof(CPUState, pc),
3493 "pc");
3494 env_btarget = tcg_global_mem_new(TCG_AREG0,
3495 offsetof(CPUState, btarget),
3496 "btarget");
3497 env_btaken = tcg_global_mem_new(TCG_AREG0,
3498 offsetof(CPUState, btaken),
3499 "btaken");
3500 for (i = 0; i < 16; i++) {
3501 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3502 offsetof(CPUState, regs[i]),
3503 regnames[i]);
3504 }
3505 for (i = 0; i < 16; i++) {
3506 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3507 offsetof(CPUState, pregs[i]),
3508 pregnames[i]);
3509 }
3510
3511 #define GEN_HELPER 2
3512 #include "helper.h"
3513
3514 return env;
3515 }
3516
3517 void cpu_reset (CPUCRISState *env)
3518 {
3519 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3520 tlb_flush(env, 1);
3521
3522 env->pregs[PR_VR] = 32;
3523 #if defined(CONFIG_USER_ONLY)
3524 /* start in user mode with interrupts enabled. */
3525 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3526 #else
3527 env->pregs[PR_CCS] = 0;
3528 #endif
3529 }
3530
3531 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3532 unsigned long searched_pc, int pc_pos, void *puc)
3533 {
3534 env->pc = gen_opc_pc[pc_pos];
3535 }
Qemu copy for testing