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[mirror_qemu.git] / target-cris / translate.c
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 * FIXME:
24 * The condition code translation is in desperate need of attention. It's slow
25 * and for system simulation it seems buggy. It sucks.
26 */
27
28 #include <stdarg.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <assert.h>
34
35 #include "cpu.h"
36 #include "exec-all.h"
37 #include "disas.h"
38 #include "tcg-op.h"
39 #include "helper.h"
40 #include "crisv32-decode.h"
41 #include "qemu-common.h"
42
43 #define CRIS_STATS 0
44 #if CRIS_STATS
45 #define STATS(x) x
46 #else
47 #define STATS(x)
48 #endif
49
50 #define DISAS_CRIS 0
51 #if DISAS_CRIS
52 #define DIS(x) x
53 #else
54 #define DIS(x)
55 #endif
56
57 #define D(x)
58 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
59 #define BUG_ON(x) ({if (x) BUG();})
60
61 #define DISAS_SWI 5
62
63 /* Used by the decoder. */
64 #define EXTRACT_FIELD(src, start, end) \
65 (((src) >> start) & ((1 << (end - start + 1)) - 1))
66
67 #define CC_MASK_NZ 0xc
68 #define CC_MASK_NZV 0xe
69 #define CC_MASK_NZVC 0xf
70 #define CC_MASK_RNZV 0x10e
71
72 TCGv cpu_env;
73 TCGv cpu_T[2];
74 TCGv cpu_R[16];
75 TCGv cpu_PR[16];
76 TCGv cc_src;
77 TCGv cc_dest;
78 TCGv cc_result;
79 TCGv cc_op;
80 TCGv cc_size;
81 TCGv cc_mask;
82
83 TCGv env_btarget;
84 TCGv env_pc;
85
86 /* This is the state at translation time. */
87 typedef struct DisasContext {
88 CPUState *env;
89 target_ulong pc, ppc;
90
91 /* Decoder. */
92 uint32_t ir;
93 uint32_t opcode;
94 unsigned int op1;
95 unsigned int op2;
96 unsigned int zsize, zzsize;
97 unsigned int mode;
98 unsigned int postinc;
99
100 int update_cc;
101 int cc_op;
102 int cc_size;
103 uint32_t cc_mask;
104 int flags_live; /* Wether or not $ccs is uptodate. */
105 int flagx_live; /* Wether or not flags_x has the x flag known at
106 translation time. */
107 int flags_x;
108 int clear_x; /* Clear x after this insn? */
109
110 int user; /* user or kernel mode. */
111 int is_jmp;
112 int dyn_jmp;
113
114 uint32_t delayed_pc;
115 int delayed_branch;
116 int bcc;
117 uint32_t condlabel;
118
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
121 } DisasContext;
122
123 void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
124 static void gen_BUG(DisasContext *dc, char *file, int line)
125 {
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_dump_state (dc->env, stdout, fprintf, 0);
129 fflush(NULL);
130 cris_prepare_jmp (dc, 0x70000000 + line);
131 }
132
133 const char *regnames[] =
134 {
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
139 };
140 const char *pregnames[] =
141 {
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
146 };
147
148 /* We need this table to handle preg-moves with implicit width. */
149 int preg_sizes[] = {
150 1, /* bz. */
151 1, /* vr. */
152 4, /* pid. */
153 1, /* srs. */
154 2, /* wz. */
155 4, 4, 4,
156 4, 4, 4, 4,
157 4, 4, 4, 4,
158 };
159
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
164
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
166 {
167 if (r < 0 || r > 15)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
170 }
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
172 {
173 if (r < 0 || r > 15)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
176 }
177
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
179 {
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
183 }
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
185 {
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
189 }
190
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
192 {
193 if (r < 0 || r > 15)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
197 else if (r == PR_VR)
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EXS) {
200 printf("read from EXS!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
202 }
203 else if (r == PR_EDA) {
204 printf("read from EDA!\n");
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 }
207 else
208 tcg_gen_mov_tl(tn, cpu_PR[r]);
209 }
210 static inline void t_gen_mov_preg_TN(int r, TCGv tn)
211 {
212 if (r < 0 || r > 15)
213 fprintf(stderr, "wrong register write $p%d\n", r);
214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
215 return;
216 else if (r == PR_SRS)
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
218 else {
219 if (r == PR_PID) {
220 tcg_gen_helper_0_0(helper_tlb_flush);
221 }
222 tcg_gen_mov_tl(cpu_PR[r], tn);
223 }
224 }
225
226 static inline void t_gen_mov_TN_im(TCGv tn, int32_t val)
227 {
228 tcg_gen_movi_tl(tn, val);
229 }
230
231 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
232 {
233 int l1;
234
235 l1 = gen_new_label();
236 /* Speculative shift. */
237 tcg_gen_shl_tl(d, a, b);
238 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
239 /* Clear dst if shift operands were to large. */
240 tcg_gen_movi_tl(d, 0);
241 gen_set_label(l1);
242 }
243
244 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
245 {
246 int l1;
247
248 l1 = gen_new_label();
249 /* Speculative shift. */
250 tcg_gen_shr_tl(d, a, b);
251 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
252 /* Clear dst if shift operands were to large. */
253 tcg_gen_movi_tl(d, 0);
254 gen_set_label(l1);
255 }
256
257 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
258 {
259 int l1;
260
261 l1 = gen_new_label();
262 /* Speculative shift. */
263 tcg_gen_sar_tl(d, a, b);
264 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
265 /* Clear dst if shift operands were to large. */
266 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
267 gen_set_label(l1);
268 }
269
270 /* 64-bit signed mul, lower result in d and upper in d2. */
271 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
272 {
273 TCGv t0, t1;
274
275 t0 = tcg_temp_new(TCG_TYPE_I64);
276 t1 = tcg_temp_new(TCG_TYPE_I64);
277
278 tcg_gen_ext32s_i64(t0, a);
279 tcg_gen_ext32s_i64(t1, b);
280 tcg_gen_mul_i64(t0, t0, t1);
281
282 tcg_gen_trunc_i64_i32(d, t0);
283 tcg_gen_shri_i64(t0, t0, 32);
284 tcg_gen_trunc_i64_i32(d2, t0);
285
286 tcg_gen_discard_i64(t0);
287 tcg_gen_discard_i64(t1);
288 }
289
290 /* 64-bit unsigned muls, lower result in d and upper in d2. */
291 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
292 {
293 TCGv t0, t1;
294
295 t0 = tcg_temp_new(TCG_TYPE_I64);
296 t1 = tcg_temp_new(TCG_TYPE_I64);
297
298 tcg_gen_extu_i32_i64(t0, a);
299 tcg_gen_extu_i32_i64(t1, b);
300 tcg_gen_mul_i64(t0, t0, t1);
301
302 tcg_gen_trunc_i64_i32(d, t0);
303 tcg_gen_shri_i64(t0, t0, 32);
304 tcg_gen_trunc_i64_i32(d2, t0);
305
306 tcg_gen_discard_i64(t0);
307 tcg_gen_discard_i64(t1);
308 }
309
310 /* 32bit branch-free binary search for counting leading zeros. */
311 static void t_gen_lz_i32(TCGv d, TCGv x)
312 {
313 TCGv y, m, n;
314
315 y = tcg_temp_new(TCG_TYPE_I32);
316 m = tcg_temp_new(TCG_TYPE_I32);
317 n = tcg_temp_new(TCG_TYPE_I32);
318
319 /* y = -(x >> 16) */
320 tcg_gen_shri_i32(y, x, 16);
321 tcg_gen_sub_i32(y, tcg_const_i32(0), y);
322
323 /* m = (y >> 16) & 16 */
324 tcg_gen_sari_i32(m, y, 16);
325 tcg_gen_andi_i32(m, m, 16);
326
327 /* n = 16 - m */
328 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
329 /* x = x >> m */
330 tcg_gen_shr_i32(x, x, m);
331
332 /* y = x - 0x100 */
333 tcg_gen_subi_i32(y, x, 0x100);
334 /* m = (y >> 16) & 8 */
335 tcg_gen_sari_i32(m, y, 16);
336 tcg_gen_andi_i32(m, m, 8);
337 /* n = n + m */
338 tcg_gen_add_i32(n, n, m);
339 /* x = x << m */
340 tcg_gen_shl_i32(x, x, m);
341
342 /* y = x - 0x1000 */
343 tcg_gen_subi_i32(y, x, 0x1000);
344 /* m = (y >> 16) & 4 */
345 tcg_gen_sari_i32(m, y, 16);
346 tcg_gen_andi_i32(m, m, 4);
347 /* n = n + m */
348 tcg_gen_add_i32(n, n, m);
349 /* x = x << m */
350 tcg_gen_shl_i32(x, x, m);
351
352 /* y = x - 0x4000 */
353 tcg_gen_subi_i32(y, x, 0x4000);
354 /* m = (y >> 16) & 2 */
355 tcg_gen_sari_i32(m, y, 16);
356 tcg_gen_andi_i32(m, m, 2);
357 /* n = n + m */
358 tcg_gen_add_i32(n, n, m);
359 /* x = x << m */
360 tcg_gen_shl_i32(x, x, m);
361
362 /* y = x >> 14 */
363 tcg_gen_shri_i32(y, x, 14);
364 /* m = y & ~(y >> 1) */
365 tcg_gen_sari_i32(m, y, 1);
366 tcg_gen_xori_i32(m, m, 0xffffffff);
367 tcg_gen_and_i32(m, m, y);
368
369 /* d = n + 2 - m */
370 tcg_gen_addi_i32(d, n, 2);
371 tcg_gen_sub_i32(d, d, m);
372
373 tcg_gen_discard_i32(y);
374 tcg_gen_discard_i32(m);
375 tcg_gen_discard_i32(n);
376 }
377
378 static void t_gen_cris_dstep(TCGv d, TCGv s)
379 {
380 int l1;
381
382 l1 = gen_new_label();
383
384 /*
385 * d <<= 1
386 * if (d >= s)
387 * d -= s;
388 */
389 tcg_gen_shli_tl(d, d, 1);
390 tcg_gen_brcond_tl(TCG_COND_LTU, d, s, l1);
391 tcg_gen_sub_tl(d, d, s);
392 gen_set_label(l1);
393 }
394
395 /* Extended arithmetics on CRIS. */
396 static inline void t_gen_add_flag(TCGv d, int flag)
397 {
398 TCGv c;
399
400 c = tcg_temp_new(TCG_TYPE_TL);
401 t_gen_mov_TN_preg(c, PR_CCS);
402 /* Propagate carry into d. */
403 tcg_gen_andi_tl(c, c, 1 << flag);
404 if (flag)
405 tcg_gen_shri_tl(c, c, flag);
406 tcg_gen_add_tl(d, d, c);
407 tcg_gen_discard_tl(c);
408 }
409
410 static inline void t_gen_addx_carry(TCGv d)
411 {
412 TCGv x, c;
413
414 x = tcg_temp_new(TCG_TYPE_TL);
415 c = tcg_temp_new(TCG_TYPE_TL);
416 t_gen_mov_TN_preg(x, PR_CCS);
417 tcg_gen_mov_tl(c, x);
418
419 /* Propagate carry into d if X is set. Branch free. */
420 tcg_gen_andi_tl(c, c, C_FLAG);
421 tcg_gen_andi_tl(x, x, X_FLAG);
422 tcg_gen_shri_tl(x, x, 4);
423
424 tcg_gen_and_tl(x, x, c);
425 tcg_gen_add_tl(d, d, x);
426 tcg_gen_discard_tl(x);
427 tcg_gen_discard_tl(c);
428 }
429
430 static inline void t_gen_subx_carry(TCGv d)
431 {
432 TCGv x, c;
433
434 x = tcg_temp_new(TCG_TYPE_TL);
435 c = tcg_temp_new(TCG_TYPE_TL);
436 t_gen_mov_TN_preg(x, PR_CCS);
437 tcg_gen_mov_tl(c, x);
438
439 /* Propagate carry into d if X is set. Branch free. */
440 tcg_gen_andi_tl(c, c, C_FLAG);
441 tcg_gen_andi_tl(x, x, X_FLAG);
442 tcg_gen_shri_tl(x, x, 4);
443
444 tcg_gen_and_tl(x, x, c);
445 tcg_gen_sub_tl(d, d, x);
446 tcg_gen_discard_tl(x);
447 tcg_gen_discard_tl(c);
448 }
449
450 /* Swap the two bytes within each half word of the s operand.
451 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
452 static inline void t_gen_swapb(TCGv d, TCGv s)
453 {
454 TCGv t, org_s;
455
456 t = tcg_temp_new(TCG_TYPE_TL);
457 org_s = tcg_temp_new(TCG_TYPE_TL);
458
459 /* d and s may refer to the same object. */
460 tcg_gen_mov_tl(org_s, s);
461 tcg_gen_shli_tl(t, org_s, 8);
462 tcg_gen_andi_tl(d, t, 0xff00ff00);
463 tcg_gen_shri_tl(t, org_s, 8);
464 tcg_gen_andi_tl(t, t, 0x00ff00ff);
465 tcg_gen_or_tl(d, d, t);
466 tcg_gen_discard_tl(t);
467 tcg_gen_discard_tl(org_s);
468 }
469
470 /* Swap the halfwords of the s operand. */
471 static inline void t_gen_swapw(TCGv d, TCGv s)
472 {
473 TCGv t;
474 /* d and s refer the same object. */
475 t = tcg_temp_new(TCG_TYPE_TL);
476 tcg_gen_mov_tl(t, s);
477 tcg_gen_shli_tl(d, t, 16);
478 tcg_gen_shri_tl(t, t, 16);
479 tcg_gen_or_tl(d, d, t);
480 tcg_gen_discard_tl(t);
481 }
482
483 /* Reverse the within each byte.
484 T0 = (((T0 << 7) & 0x80808080) |
485 ((T0 << 5) & 0x40404040) |
486 ((T0 << 3) & 0x20202020) |
487 ((T0 << 1) & 0x10101010) |
488 ((T0 >> 1) & 0x08080808) |
489 ((T0 >> 3) & 0x04040404) |
490 ((T0 >> 5) & 0x02020202) |
491 ((T0 >> 7) & 0x01010101));
492 */
493 static inline void t_gen_swapr(TCGv d, TCGv s)
494 {
495 struct {
496 int shift; /* LSL when positive, LSR when negative. */
497 uint32_t mask;
498 } bitrev [] = {
499 {7, 0x80808080},
500 {5, 0x40404040},
501 {3, 0x20202020},
502 {1, 0x10101010},
503 {-1, 0x08080808},
504 {-3, 0x04040404},
505 {-5, 0x02020202},
506 {-7, 0x01010101}
507 };
508 int i;
509 TCGv t, org_s;
510
511 /* d and s refer the same object. */
512 t = tcg_temp_new(TCG_TYPE_TL);
513 org_s = tcg_temp_new(TCG_TYPE_TL);
514 tcg_gen_mov_tl(org_s, s);
515
516 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
517 tcg_gen_andi_tl(d, t, bitrev[0].mask);
518 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
519 if (bitrev[i].shift >= 0) {
520 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
521 } else {
522 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
523 }
524 tcg_gen_andi_tl(t, t, bitrev[i].mask);
525 tcg_gen_or_tl(d, d, t);
526 }
527 tcg_gen_discard_tl(t);
528 tcg_gen_discard_tl(org_s);
529 }
530
531 static void t_gen_cc_jmp(target_ulong pc_true, target_ulong pc_false)
532 {
533 TCGv btaken;
534 int l1;
535
536 l1 = gen_new_label();
537 btaken = tcg_temp_new(TCG_TYPE_TL);
538
539 /* Conditional jmp. */
540 t_gen_mov_TN_env(btaken, btaken);
541 tcg_gen_movi_tl(env_pc, pc_false);
542 tcg_gen_brcond_tl(TCG_COND_EQ, btaken, tcg_const_tl(0), l1);
543 tcg_gen_movi_tl(env_pc, pc_true);
544 gen_set_label(l1);
545
546 tcg_gen_discard_tl(btaken);
547 }
548
549 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
550 {
551 TranslationBlock *tb;
552 tb = dc->tb;
553 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
554 tcg_gen_goto_tb(n);
555 tcg_gen_movi_tl(env_pc, dest);
556 tcg_gen_exit_tb((long)tb + n);
557 } else {
558 tcg_gen_mov_tl(env_pc, cpu_T[0]);
559 tcg_gen_exit_tb(0);
560 }
561 }
562
563 /* Sign extend at translation time. */
564 static int sign_extend(unsigned int val, unsigned int width)
565 {
566 int sval;
567
568 /* LSL. */
569 val <<= 31 - width;
570 sval = val;
571 /* ASR. */
572 sval >>= 31 - width;
573 return sval;
574 }
575
576 static inline void cris_clear_x_flag(DisasContext *dc)
577 {
578 if (!dc->flagx_live
579 || (dc->flagx_live && dc->flags_x)
580 || dc->cc_op != CC_OP_FLAGS)
581 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
582 dc->flagx_live = 1;
583 dc->flags_x = 0;
584 }
585
586 static void cris_evaluate_flags(DisasContext *dc)
587 {
588 if (!dc->flags_live) {
589 tcg_gen_movi_tl(cc_op, dc->cc_op);
590 tcg_gen_movi_tl(cc_size, dc->cc_size);
591 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
592
593 switch (dc->cc_op)
594 {
595 case CC_OP_MCP:
596 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
597 break;
598 case CC_OP_MULS:
599 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
600 break;
601 case CC_OP_MULU:
602 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
603 break;
604 case CC_OP_MOVE:
605 switch (dc->cc_size)
606 {
607 case 4:
608 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
609 break;
610 case 2:
611 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
612 break;
613 default:
614 tcg_gen_helper_0_0(helper_evaluate_flags);
615 break;
616 }
617 break;
618 case CC_OP_FLAGS:
619 /* live. */
620 break;
621 default:
622 {
623 switch (dc->cc_size)
624 {
625 case 4:
626 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
627 break;
628 default:
629 tcg_gen_helper_0_0(helper_evaluate_flags);
630 break;
631 }
632 }
633 break;
634 }
635 dc->flags_live = 1;
636 }
637 }
638
639 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
640 {
641 uint32_t ovl;
642
643 /* Check if we need to evaluate the condition codes due to
644 CC overlaying. */
645 ovl = (dc->cc_mask ^ mask) & ~mask;
646 if (ovl) {
647 /* TODO: optimize this case. It trigs all the time. */
648 cris_evaluate_flags (dc);
649 }
650 dc->cc_mask = mask;
651 dc->update_cc = 1;
652
653 if (mask == 0)
654 dc->update_cc = 0;
655 else
656 dc->flags_live = 0;
657 }
658
659 static void cris_update_cc_op(DisasContext *dc, int op, int size)
660 {
661 dc->cc_op = op;
662 dc->cc_size = size;
663 dc->flags_live = 0;
664 }
665
666 /* op is the operation.
667 T0, T1 are the operands.
668 dst is the destination reg.
669 */
670 static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
671 {
672 int writeback = 1;
673 if (dc->update_cc) {
674 cris_update_cc_op(dc, op, size);
675 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
676
677 /* FIXME: This shouldn't be needed. But we don't pass the
678 tests without it. Investigate. */
679 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
680 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
681 }
682
683 /* Emit the ALU insns. */
684 switch (op)
685 {
686 case CC_OP_ADD:
687 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
688 /* Extended arithmetics. */
689 t_gen_addx_carry(cpu_T[0]);
690 break;
691 case CC_OP_ADDC:
692 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
693 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
694 break;
695 case CC_OP_MCP:
696 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
697 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
698 break;
699 case CC_OP_SUB:
700 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
701 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
702 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
703 /* CRIS flag evaluation needs ~src. */
704 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
705
706 /* Extended arithmetics. */
707 t_gen_subx_carry(cpu_T[0]);
708 break;
709 case CC_OP_MOVE:
710 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
711 break;
712 case CC_OP_OR:
713 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
714 break;
715 case CC_OP_AND:
716 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
717 break;
718 case CC_OP_XOR:
719 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
720 break;
721 case CC_OP_LSL:
722 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
723 break;
724 case CC_OP_LSR:
725 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
726 break;
727 case CC_OP_ASR:
728 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
729 break;
730 case CC_OP_NEG:
731 /* Hopefully the TCG backend recognizes this pattern
732 and makes a real neg out of it. */
733 tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
734 /* Extended arithmetics. */
735 t_gen_subx_carry(cpu_T[0]);
736 break;
737 case CC_OP_LZ:
738 t_gen_lz_i32(cpu_T[0], cpu_T[1]);
739 break;
740 case CC_OP_BTST:
741 gen_op_btst_T0_T1();
742 writeback = 0;
743 break;
744 case CC_OP_MULS:
745 {
746 TCGv mof;
747 mof = tcg_temp_new(TCG_TYPE_TL);
748 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
749 t_gen_mov_preg_TN(PR_MOF, mof);
750 tcg_gen_discard_tl(mof);
751 }
752 break;
753 case CC_OP_MULU:
754 {
755 TCGv mof;
756 mof = tcg_temp_new(TCG_TYPE_TL);
757 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
758 t_gen_mov_preg_TN(PR_MOF, mof);
759 tcg_gen_discard_tl(mof);
760 }
761 break;
762 case CC_OP_DSTEP:
763 t_gen_cris_dstep(cpu_T[0], cpu_T[1]);
764 break;
765 case CC_OP_BOUND:
766 {
767 int l1;
768 l1 = gen_new_label();
769 tcg_gen_brcond_tl(TCG_COND_LEU,
770 cpu_T[0], cpu_T[1], l1);
771 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
772 gen_set_label(l1);
773 }
774 break;
775 case CC_OP_CMP:
776 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
777 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
778 /* CRIS flag evaluation needs ~src. */
779 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
780 /* CRIS flag evaluation needs ~src. */
781 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
782
783 /* Extended arithmetics. */
784 t_gen_subx_carry(cpu_T[0]);
785 writeback = 0;
786 break;
787 default:
788 fprintf (logfile, "illegal ALU op.\n");
789 BUG();
790 break;
791 }
792
793 if (dc->update_cc)
794 tcg_gen_mov_tl(cc_src, cpu_T[1]);
795
796 if (size == 1)
797 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
798 else if (size == 2)
799 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
800
801 /* Writeback. */
802 if (writeback) {
803 if (size == 4)
804 t_gen_mov_reg_TN(rd, cpu_T[0]);
805 else {
806 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
807 t_gen_mov_TN_reg(cpu_T[0], rd);
808 if (size == 1)
809 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
810 else
811 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
812 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
813 t_gen_mov_reg_TN(rd, cpu_T[0]);
814 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
815 }
816 }
817 if (dc->update_cc)
818 tcg_gen_mov_tl(cc_result, cpu_T[0]);
819
820 {
821 /* TODO: Optimize this. */
822 if (!dc->flagx_live)
823 cris_evaluate_flags(dc);
824 }
825 }
826
827 static int arith_cc(DisasContext *dc)
828 {
829 if (dc->update_cc) {
830 switch (dc->cc_op) {
831 case CC_OP_ADD: return 1;
832 case CC_OP_SUB: return 1;
833 case CC_OP_LSL: return 1;
834 case CC_OP_LSR: return 1;
835 case CC_OP_ASR: return 1;
836 case CC_OP_CMP: return 1;
837 default:
838 return 0;
839 }
840 }
841 return 0;
842 }
843
844 static void gen_tst_cc (DisasContext *dc, int cond)
845 {
846 int arith_opt;
847
848 /* TODO: optimize more condition codes. */
849 arith_opt = arith_cc(dc) && !dc->flags_live;
850 switch (cond) {
851 case CC_EQ:
852 if (arith_opt)
853 gen_op_tst_cc_eq_fast ();
854 else {
855 cris_evaluate_flags(dc);
856 gen_op_tst_cc_eq ();
857 }
858 break;
859 case CC_NE:
860 if (arith_opt)
861 gen_op_tst_cc_ne_fast ();
862 else {
863 cris_evaluate_flags(dc);
864 gen_op_tst_cc_ne ();
865 }
866 break;
867 case CC_CS:
868 cris_evaluate_flags(dc);
869 gen_op_tst_cc_cs ();
870 break;
871 case CC_CC:
872 cris_evaluate_flags(dc);
873 gen_op_tst_cc_cc ();
874 break;
875 case CC_VS:
876 cris_evaluate_flags(dc);
877 gen_op_tst_cc_vs ();
878 break;
879 case CC_VC:
880 cris_evaluate_flags(dc);
881 gen_op_tst_cc_vc ();
882 break;
883 case CC_PL:
884 if (arith_opt)
885 gen_op_tst_cc_pl_fast ();
886 else {
887 cris_evaluate_flags(dc);
888 gen_op_tst_cc_pl ();
889 }
890 break;
891 case CC_MI:
892 if (arith_opt)
893 gen_op_tst_cc_mi_fast ();
894 else {
895 cris_evaluate_flags(dc);
896 gen_op_tst_cc_mi ();
897 }
898 break;
899 case CC_LS:
900 cris_evaluate_flags(dc);
901 gen_op_tst_cc_ls ();
902 break;
903 case CC_HI:
904 cris_evaluate_flags(dc);
905 gen_op_tst_cc_hi ();
906 break;
907 case CC_GE:
908 cris_evaluate_flags(dc);
909 gen_op_tst_cc_ge ();
910 break;
911 case CC_LT:
912 cris_evaluate_flags(dc);
913 gen_op_tst_cc_lt ();
914 break;
915 case CC_GT:
916 cris_evaluate_flags(dc);
917 gen_op_tst_cc_gt ();
918 break;
919 case CC_LE:
920 cris_evaluate_flags(dc);
921 gen_op_tst_cc_le ();
922 break;
923 case CC_P:
924 cris_evaluate_flags(dc);
925 gen_op_tst_cc_p ();
926 break;
927 case CC_A:
928 cris_evaluate_flags(dc);
929 tcg_gen_movi_tl(cpu_T[0], 1);
930 break;
931 default:
932 BUG();
933 break;
934 };
935 }
936
937 static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
938 {
939 /* This helps us re-schedule the micro-code to insns in delay-slots
940 before the actual jump. */
941 dc->delayed_branch = 2;
942 dc->delayed_pc = dc->pc + offset;
943 dc->bcc = cond;
944 if (cond != CC_A)
945 {
946 gen_tst_cc (dc, cond);
947 gen_op_evaluate_bcc ();
948 }
949 tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
950 }
951
952
953 /* Dynamic jumps, when the dest is in a live reg for example. */
954 void cris_prepare_dyn_jmp (DisasContext *dc)
955 {
956 /* This helps us re-schedule the micro-code to insns in delay-slots
957 before the actual jump. */
958 dc->delayed_branch = 2;
959 dc->dyn_jmp = 1;
960 dc->bcc = CC_A;
961 }
962
963 void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
964 {
965 /* This helps us re-schedule the micro-code to insns in delay-slots
966 before the actual jump. */
967 dc->delayed_branch = 2;
968 dc->delayed_pc = dst;
969 dc->dyn_jmp = 0;
970 dc->bcc = CC_A;
971 }
972
973 void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
974 unsigned int size, int sign)
975 {
976 int mem_index = cpu_mmu_index(dc->env);
977
978 cris_evaluate_flags(dc);
979 if (size == 1) {
980 if (sign)
981 tcg_gen_qemu_ld8s(dst, addr, mem_index);
982 else
983 tcg_gen_qemu_ld8u(dst, addr, mem_index);
984 }
985 else if (size == 2) {
986 if (sign)
987 tcg_gen_qemu_ld16s(dst, addr, mem_index);
988 else
989 tcg_gen_qemu_ld16u(dst, addr, mem_index);
990 }
991 else {
992 tcg_gen_qemu_ld32s(dst, addr, mem_index);
993 }
994 }
995
996 void gen_store (DisasContext *dc, TCGv addr, TCGv val,
997 unsigned int size)
998 {
999 int mem_index = cpu_mmu_index(dc->env);
1000
1001 cris_evaluate_flags(dc);
1002
1003 /* Remember, operands are flipped. CRIS has reversed order. */
1004 if (size == 1)
1005 tcg_gen_qemu_st8(val, addr, mem_index);
1006 else if (size == 2)
1007 tcg_gen_qemu_st16(val, addr, mem_index);
1008 else
1009 tcg_gen_qemu_st32(val, addr, mem_index);
1010 }
1011
1012 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1013 {
1014 if (size == 1)
1015 tcg_gen_ext8s_i32(d, s);
1016 else if (size == 2)
1017 tcg_gen_ext16s_i32(d, s);
1018 else
1019 tcg_gen_mov_tl(d, s);
1020 }
1021
1022 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1023 {
1024 /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
1025 if (size == 1)
1026 tcg_gen_andi_i32(d, s, 0xff);
1027 else if (size == 2)
1028 tcg_gen_andi_i32(d, s, 0xffff);
1029 else
1030 tcg_gen_mov_tl(d, s);
1031 }
1032
1033 #if DISAS_CRIS
1034 static char memsize_char(int size)
1035 {
1036 switch (size)
1037 {
1038 case 1: return 'b'; break;
1039 case 2: return 'w'; break;
1040 case 4: return 'd'; break;
1041 default:
1042 return 'x';
1043 break;
1044 }
1045 }
1046 #endif
1047
1048 static unsigned int memsize_z(DisasContext *dc)
1049 {
1050 return dc->zsize + 1;
1051 }
1052
1053 static unsigned int memsize_zz(DisasContext *dc)
1054 {
1055 switch (dc->zzsize)
1056 {
1057 case 0: return 1;
1058 case 1: return 2;
1059 default:
1060 return 4;
1061 }
1062 }
1063
1064 static inline void do_postinc (DisasContext *dc, int size)
1065 {
1066 if (dc->postinc)
1067 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1068 }
1069
1070
1071 static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1072 int size, int s_ext)
1073 {
1074 if (s_ext)
1075 t_gen_sext(cpu_T[1], cpu_R[rs], size);
1076 else
1077 t_gen_zext(cpu_T[1], cpu_R[rs], size);
1078 }
1079
1080 /* Prepare T0 and T1 for a register alu operation.
1081 s_ext decides if the operand1 should be sign-extended or zero-extended when
1082 needed. */
1083 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1084 int size, int s_ext)
1085 {
1086 dec_prep_move_r(dc, rs, rd, size, s_ext);
1087
1088 if (s_ext)
1089 t_gen_sext(cpu_T[0], cpu_R[rd], size);
1090 else
1091 t_gen_zext(cpu_T[0], cpu_R[rd], size);
1092 }
1093
1094 /* Prepare T0 and T1 for a memory + alu operation.
1095 s_ext decides if the operand1 should be sign-extended or zero-extended when
1096 needed. */
1097 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1098 {
1099 unsigned int rs, rd;
1100 uint32_t imm;
1101 int is_imm;
1102 int insn_len = 2;
1103
1104 rs = dc->op1;
1105 rd = dc->op2;
1106 is_imm = rs == 15 && dc->postinc;
1107
1108 /* Load [$rs] onto T1. */
1109 if (is_imm) {
1110 insn_len = 2 + memsize;
1111 if (memsize == 1)
1112 insn_len++;
1113
1114 if (memsize != 4) {
1115 if (s_ext) {
1116 if (memsize == 1)
1117 imm = ldsb_code(dc->pc + 2);
1118 else
1119 imm = ldsw_code(dc->pc + 2);
1120 } else {
1121 if (memsize == 1)
1122 imm = ldub_code(dc->pc + 2);
1123 else
1124 imm = lduw_code(dc->pc + 2);
1125 }
1126 } else
1127 imm = ldl_code(dc->pc + 2);
1128
1129 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1130 imm, rd, s_ext, memsize));
1131 tcg_gen_movi_tl(cpu_T[1], imm);
1132 dc->postinc = 0;
1133 } else {
1134 /* FIXME: qemu_ld does not act as a barrier? */
1135 tcg_gen_helper_0_0(helper_dummy);
1136 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
1137 if (s_ext)
1138 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
1139 else
1140 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
1141 }
1142
1143 /* put dest in T0. */
1144 t_gen_mov_TN_reg(cpu_T[0], rd);
1145 return insn_len;
1146 }
1147
1148 #if DISAS_CRIS
1149 static const char *cc_name(int cc)
1150 {
1151 static char *cc_names[16] = {
1152 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1153 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1154 };
1155 assert(cc < 16);
1156 return cc_names[cc];
1157 }
1158 #endif
1159
1160 /* Start of insn decoders. */
1161
1162 static unsigned int dec_bccq(DisasContext *dc)
1163 {
1164 int32_t offset;
1165 int sign;
1166 uint32_t cond = dc->op2;
1167 int tmp;
1168
1169 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1170 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1171
1172 offset *= 2;
1173 offset |= sign << 8;
1174 tmp = offset;
1175 offset = sign_extend(offset, 8);
1176
1177 /* op2 holds the condition-code. */
1178 cris_cc_mask(dc, 0);
1179 cris_prepare_cc_branch (dc, offset, cond);
1180 return 2;
1181 }
1182 static unsigned int dec_addoq(DisasContext *dc)
1183 {
1184 int32_t imm;
1185
1186 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1187 imm = sign_extend(dc->op1, 7);
1188
1189 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1190 cris_cc_mask(dc, 0);
1191 /* Fetch register operand, */
1192 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1193 return 2;
1194 }
1195 static unsigned int dec_addq(DisasContext *dc)
1196 {
1197 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1198
1199 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1200
1201 cris_cc_mask(dc, CC_MASK_NZVC);
1202 /* Fetch register operand, */
1203 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1204 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1205 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1206 return 2;
1207 }
1208 static unsigned int dec_moveq(DisasContext *dc)
1209 {
1210 uint32_t imm;
1211
1212 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1213 imm = sign_extend(dc->op1, 5);
1214 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1215
1216 t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
1217 return 2;
1218 }
1219 static unsigned int dec_subq(DisasContext *dc)
1220 {
1221 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1222
1223 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1224
1225 cris_cc_mask(dc, CC_MASK_NZVC);
1226 /* Fetch register operand, */
1227 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1228 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1229 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1230 return 2;
1231 }
1232 static unsigned int dec_cmpq(DisasContext *dc)
1233 {
1234 uint32_t imm;
1235 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1236 imm = sign_extend(dc->op1, 5);
1237
1238 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1239 cris_cc_mask(dc, CC_MASK_NZVC);
1240 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1241 t_gen_mov_TN_im(cpu_T[1], imm);
1242 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1243 return 2;
1244 }
1245 static unsigned int dec_andq(DisasContext *dc)
1246 {
1247 uint32_t imm;
1248 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1249 imm = sign_extend(dc->op1, 5);
1250
1251 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1252 cris_cc_mask(dc, CC_MASK_NZ);
1253 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1254 t_gen_mov_TN_im(cpu_T[1], imm);
1255 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1256 return 2;
1257 }
1258 static unsigned int dec_orq(DisasContext *dc)
1259 {
1260 uint32_t imm;
1261 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1262 imm = sign_extend(dc->op1, 5);
1263 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1264 cris_cc_mask(dc, CC_MASK_NZ);
1265 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1266 t_gen_mov_TN_im(cpu_T[1], imm);
1267 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1268 return 2;
1269 }
1270 static unsigned int dec_btstq(DisasContext *dc)
1271 {
1272 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1273 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1274
1275 cris_evaluate_flags(dc);
1276 cris_cc_mask(dc, CC_MASK_NZ);
1277 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1278 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1279 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1280
1281 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1282 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1283 dc->flags_live = 1;
1284 return 2;
1285 }
1286 static unsigned int dec_asrq(DisasContext *dc)
1287 {
1288 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1289 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1290 cris_cc_mask(dc, CC_MASK_NZ);
1291 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1292 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1293 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1294 return 2;
1295 }
1296 static unsigned int dec_lslq(DisasContext *dc)
1297 {
1298 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1299 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1300
1301 cris_cc_mask(dc, CC_MASK_NZ);
1302 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1303 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1304 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1305 return 2;
1306 }
1307 static unsigned int dec_lsrq(DisasContext *dc)
1308 {
1309 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1310 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1311
1312 cris_cc_mask(dc, CC_MASK_NZ);
1313 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1314 t_gen_mov_TN_im(cpu_T[1], dc->op1);
1315 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1316 return 2;
1317 }
1318
1319 static unsigned int dec_move_r(DisasContext *dc)
1320 {
1321 int size = memsize_zz(dc);
1322
1323 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1324 memsize_char(size), dc->op1, dc->op2));
1325
1326 cris_cc_mask(dc, CC_MASK_NZ);
1327 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1328 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1329 return 2;
1330 }
1331
1332 static unsigned int dec_scc_r(DisasContext *dc)
1333 {
1334 int cond = dc->op2;
1335
1336 DIS(fprintf (logfile, "s%s $r%u\n",
1337 cc_name(cond), dc->op1));
1338
1339 if (cond != CC_A)
1340 {
1341 gen_tst_cc (dc, cond);
1342 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1343 }
1344 else
1345 tcg_gen_movi_tl(cpu_T[1], 1);
1346
1347 cris_cc_mask(dc, 0);
1348 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1349 return 2;
1350 }
1351
1352 static unsigned int dec_and_r(DisasContext *dc)
1353 {
1354 int size = memsize_zz(dc);
1355
1356 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1357 memsize_char(size), dc->op1, dc->op2));
1358 cris_cc_mask(dc, CC_MASK_NZ);
1359 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1360 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1361 return 2;
1362 }
1363
1364 static unsigned int dec_lz_r(DisasContext *dc)
1365 {
1366 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1367 dc->op1, dc->op2));
1368 cris_cc_mask(dc, CC_MASK_NZ);
1369 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1370 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1371 return 2;
1372 }
1373
1374 static unsigned int dec_lsl_r(DisasContext *dc)
1375 {
1376 int size = memsize_zz(dc);
1377
1378 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1379 memsize_char(size), dc->op1, dc->op2));
1380 cris_cc_mask(dc, CC_MASK_NZ);
1381 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1382 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1383 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1384 return 2;
1385 }
1386
1387 static unsigned int dec_lsr_r(DisasContext *dc)
1388 {
1389 int size = memsize_zz(dc);
1390
1391 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1392 memsize_char(size), dc->op1, dc->op2));
1393 cris_cc_mask(dc, CC_MASK_NZ);
1394 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1395 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1396 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1397 return 2;
1398 }
1399
1400 static unsigned int dec_asr_r(DisasContext *dc)
1401 {
1402 int size = memsize_zz(dc);
1403
1404 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1405 memsize_char(size), dc->op1, dc->op2));
1406 cris_cc_mask(dc, CC_MASK_NZ);
1407 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1408 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1409 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1410 return 2;
1411 }
1412
1413 static unsigned int dec_muls_r(DisasContext *dc)
1414 {
1415 int size = memsize_zz(dc);
1416
1417 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1418 memsize_char(size), dc->op1, dc->op2));
1419 cris_cc_mask(dc, CC_MASK_NZV);
1420 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1421 t_gen_sext(cpu_T[0], cpu_T[0], size);
1422 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1423 return 2;
1424 }
1425
1426 static unsigned int dec_mulu_r(DisasContext *dc)
1427 {
1428 int size = memsize_zz(dc);
1429
1430 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1431 memsize_char(size), dc->op1, dc->op2));
1432 cris_cc_mask(dc, CC_MASK_NZV);
1433 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1434 t_gen_zext(cpu_T[0], cpu_T[0], size);
1435 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1436 return 2;
1437 }
1438
1439
1440 static unsigned int dec_dstep_r(DisasContext *dc)
1441 {
1442 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1443 cris_cc_mask(dc, CC_MASK_NZ);
1444 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1445 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1446 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1447 return 2;
1448 }
1449
1450 static unsigned int dec_xor_r(DisasContext *dc)
1451 {
1452 int size = memsize_zz(dc);
1453 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1454 memsize_char(size), dc->op1, dc->op2));
1455 BUG_ON(size != 4); /* xor is dword. */
1456 cris_cc_mask(dc, CC_MASK_NZ);
1457 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1458 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1459 return 2;
1460 }
1461
1462 static unsigned int dec_bound_r(DisasContext *dc)
1463 {
1464 int size = memsize_zz(dc);
1465 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1466 memsize_char(size), dc->op1, dc->op2));
1467 cris_cc_mask(dc, CC_MASK_NZ);
1468 /* TODO: needs optmimization. */
1469 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1470 /* rd should be 4. */
1471 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1472 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1473 return 2;
1474 }
1475
1476 static unsigned int dec_cmp_r(DisasContext *dc)
1477 {
1478 int size = memsize_zz(dc);
1479 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1480 memsize_char(size), dc->op1, dc->op2));
1481 cris_cc_mask(dc, CC_MASK_NZVC);
1482 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1483 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1484 return 2;
1485 }
1486
1487 static unsigned int dec_abs_r(DisasContext *dc)
1488 {
1489 int l1;
1490
1491 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1492 dc->op1, dc->op2));
1493 cris_cc_mask(dc, CC_MASK_NZ);
1494 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
1495
1496 /* TODO: consider a branch free approach. */
1497 l1 = gen_new_label();
1498 tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
1499 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
1500 gen_set_label(l1);
1501 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1502 return 2;
1503 }
1504
1505 static unsigned int dec_add_r(DisasContext *dc)
1506 {
1507 int size = memsize_zz(dc);
1508 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1509 memsize_char(size), dc->op1, dc->op2));
1510 cris_cc_mask(dc, CC_MASK_NZVC);
1511 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1512 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1513 return 2;
1514 }
1515
1516 static unsigned int dec_addc_r(DisasContext *dc)
1517 {
1518 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1519 dc->op1, dc->op2));
1520 cris_evaluate_flags(dc);
1521 cris_cc_mask(dc, CC_MASK_NZVC);
1522 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1523 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1524 return 2;
1525 }
1526
1527 static unsigned int dec_mcp_r(DisasContext *dc)
1528 {
1529 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1530 dc->op2, dc->op1));
1531 cris_evaluate_flags(dc);
1532 cris_cc_mask(dc, CC_MASK_RNZV);
1533 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1534 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1535 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1536 return 2;
1537 }
1538
1539 #if DISAS_CRIS
1540 static char * swapmode_name(int mode, char *modename) {
1541 int i = 0;
1542 if (mode & 8)
1543 modename[i++] = 'n';
1544 if (mode & 4)
1545 modename[i++] = 'w';
1546 if (mode & 2)
1547 modename[i++] = 'b';
1548 if (mode & 1)
1549 modename[i++] = 'r';
1550 modename[i++] = 0;
1551 return modename;
1552 }
1553 #endif
1554
1555 static unsigned int dec_swap_r(DisasContext *dc)
1556 {
1557 DIS(char modename[4]);
1558 DIS(fprintf (logfile, "swap%s $r%u\n",
1559 swapmode_name(dc->op2, modename), dc->op1));
1560
1561 cris_cc_mask(dc, CC_MASK_NZ);
1562 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1563 if (dc->op2 & 8)
1564 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
1565 if (dc->op2 & 4)
1566 t_gen_swapw(cpu_T[0], cpu_T[0]);
1567 if (dc->op2 & 2)
1568 t_gen_swapb(cpu_T[0], cpu_T[0]);
1569 if (dc->op2 & 1)
1570 t_gen_swapr(cpu_T[0], cpu_T[0]);
1571 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1572 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1573 return 2;
1574 }
1575
1576 static unsigned int dec_or_r(DisasContext *dc)
1577 {
1578 int size = memsize_zz(dc);
1579 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1580 memsize_char(size), dc->op1, dc->op2));
1581 cris_cc_mask(dc, CC_MASK_NZ);
1582 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1583 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1584 return 2;
1585 }
1586
1587 static unsigned int dec_addi_r(DisasContext *dc)
1588 {
1589 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1590 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1591 cris_cc_mask(dc, 0);
1592 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1593 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1594 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1595 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1596 return 2;
1597 }
1598
1599 static unsigned int dec_addi_acr(DisasContext *dc)
1600 {
1601 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1602 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1603 cris_cc_mask(dc, 0);
1604 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1605 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1606
1607 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1608 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
1609 return 2;
1610 }
1611
1612 static unsigned int dec_neg_r(DisasContext *dc)
1613 {
1614 int size = memsize_zz(dc);
1615 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1616 memsize_char(size), dc->op1, dc->op2));
1617 cris_cc_mask(dc, CC_MASK_NZVC);
1618 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1619 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1620 return 2;
1621 }
1622
1623 static unsigned int dec_btst_r(DisasContext *dc)
1624 {
1625 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1626 dc->op1, dc->op2));
1627 cris_evaluate_flags(dc);
1628 cris_cc_mask(dc, CC_MASK_NZ);
1629 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1630 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1631
1632 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1633 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1634 dc->flags_live = 1;
1635 return 2;
1636 }
1637
1638 static unsigned int dec_sub_r(DisasContext *dc)
1639 {
1640 int size = memsize_zz(dc);
1641 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1642 memsize_char(size), dc->op1, dc->op2));
1643 cris_cc_mask(dc, CC_MASK_NZVC);
1644 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1645 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1646 return 2;
1647 }
1648
1649 /* Zero extension. From size to dword. */
1650 static unsigned int dec_movu_r(DisasContext *dc)
1651 {
1652 int size = memsize_z(dc);
1653 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1654 memsize_char(size),
1655 dc->op1, dc->op2));
1656
1657 cris_cc_mask(dc, CC_MASK_NZ);
1658 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1659 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1660 return 2;
1661 }
1662
1663 /* Sign extension. From size to dword. */
1664 static unsigned int dec_movs_r(DisasContext *dc)
1665 {
1666 int size = memsize_z(dc);
1667 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1668 memsize_char(size),
1669 dc->op1, dc->op2));
1670
1671 cris_cc_mask(dc, CC_MASK_NZ);
1672 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1673 /* Size can only be qi or hi. */
1674 t_gen_sext(cpu_T[1], cpu_T[0], size);
1675 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1676 return 2;
1677 }
1678
1679 /* zero extension. From size to dword. */
1680 static unsigned int dec_addu_r(DisasContext *dc)
1681 {
1682 int size = memsize_z(dc);
1683 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1684 memsize_char(size),
1685 dc->op1, dc->op2));
1686
1687 cris_cc_mask(dc, CC_MASK_NZVC);
1688 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1689 /* Size can only be qi or hi. */
1690 t_gen_zext(cpu_T[1], cpu_T[1], size);
1691 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1692 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1693 return 2;
1694 }
1695
1696 /* Sign extension. From size to dword. */
1697 static unsigned int dec_adds_r(DisasContext *dc)
1698 {
1699 int size = memsize_z(dc);
1700 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1701 memsize_char(size),
1702 dc->op1, dc->op2));
1703
1704 cris_cc_mask(dc, CC_MASK_NZVC);
1705 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1706 /* Size can only be qi or hi. */
1707 t_gen_sext(cpu_T[1], cpu_T[1], size);
1708 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1709
1710 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1711 return 2;
1712 }
1713
1714 /* Zero extension. From size to dword. */
1715 static unsigned int dec_subu_r(DisasContext *dc)
1716 {
1717 int size = memsize_z(dc);
1718 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1719 memsize_char(size),
1720 dc->op1, dc->op2));
1721
1722 cris_cc_mask(dc, CC_MASK_NZVC);
1723 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1724 /* Size can only be qi or hi. */
1725 t_gen_zext(cpu_T[1], cpu_T[1], size);
1726 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1727 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1728 return 2;
1729 }
1730
1731 /* Sign extension. From size to dword. */
1732 static unsigned int dec_subs_r(DisasContext *dc)
1733 {
1734 int size = memsize_z(dc);
1735 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1736 memsize_char(size),
1737 dc->op1, dc->op2));
1738
1739 cris_cc_mask(dc, CC_MASK_NZVC);
1740 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1741 /* Size can only be qi or hi. */
1742 t_gen_sext(cpu_T[1], cpu_T[1], size);
1743 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1744 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1745 return 2;
1746 }
1747
1748 static unsigned int dec_setclrf(DisasContext *dc)
1749 {
1750 uint32_t flags;
1751 int set = (~dc->opcode >> 2) & 1;
1752
1753 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1754 | EXTRACT_FIELD(dc->ir, 0, 3);
1755 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1756 if (set && flags == 0)
1757 DIS(fprintf (logfile, "nop\n"));
1758 else if (!set && (flags & 0x20))
1759 DIS(fprintf (logfile, "di\n"));
1760 else
1761 DIS(fprintf (logfile, "%sf %x\n",
1762 set ? "set" : "clr",
1763 flags));
1764
1765 if (set && (flags & X_FLAG)) {
1766 dc->flagx_live = 1;
1767 dc->flags_x = 1;
1768 }
1769
1770 /* Simply decode the flags. */
1771 cris_evaluate_flags (dc);
1772 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1773 tcg_gen_movi_tl(cc_op, dc->cc_op);
1774
1775 if (set)
1776 gen_op_setf(flags);
1777 else
1778 gen_op_clrf(flags);
1779 dc->flags_live = 1;
1780 dc->clear_x = 0;
1781 return 2;
1782 }
1783
1784 static unsigned int dec_move_rs(DisasContext *dc)
1785 {
1786 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1787 cris_cc_mask(dc, 0);
1788 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1789 gen_op_movl_sreg_T0(dc->op2);
1790
1791 #if !defined(CONFIG_USER_ONLY)
1792 if (dc->op2 == 6)
1793 gen_op_movl_tlb_hi_T0();
1794 else if (dc->op2 == 5) { /* srs is checked at runtime. */
1795 tcg_gen_helper_0_1(helper_tlb_update, cpu_T[0]);
1796 gen_op_movl_tlb_lo_T0();
1797 }
1798 #endif
1799 return 2;
1800 }
1801 static unsigned int dec_move_sr(DisasContext *dc)
1802 {
1803 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
1804 cris_cc_mask(dc, 0);
1805 gen_op_movl_T0_sreg(dc->op2);
1806 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1807 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1808 return 2;
1809 }
1810 static unsigned int dec_move_rp(DisasContext *dc)
1811 {
1812 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1813 cris_cc_mask(dc, 0);
1814
1815 if (dc->op2 == PR_CCS) {
1816 cris_evaluate_flags(dc);
1817 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1818 if (dc->user) {
1819 /* User space is not allowed to touch all flags. */
1820 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1821 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1822 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1823 }
1824 }
1825 else
1826 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1827
1828 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1829 if (dc->op2 == PR_CCS) {
1830 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1831 dc->flags_live = 1;
1832 }
1833 return 2;
1834 }
1835 static unsigned int dec_move_pr(DisasContext *dc)
1836 {
1837 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1838 cris_cc_mask(dc, 0);
1839 /* Support register 0 is hardwired to zero.
1840 Treat it specially. */
1841 if (dc->op2 == 0)
1842 tcg_gen_movi_tl(cpu_T[1], 0);
1843 else if (dc->op2 == PR_CCS) {
1844 cris_evaluate_flags(dc);
1845 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1846 } else
1847 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1848 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1849 return 2;
1850 }
1851
1852 static unsigned int dec_move_mr(DisasContext *dc)
1853 {
1854 int memsize = memsize_zz(dc);
1855 int insn_len;
1856 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
1857 memsize_char(memsize),
1858 dc->op1, dc->postinc ? "+]" : "]",
1859 dc->op2));
1860
1861 insn_len = dec_prep_alu_m(dc, 0, memsize);
1862 cris_cc_mask(dc, CC_MASK_NZ);
1863 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
1864 do_postinc(dc, memsize);
1865 return insn_len;
1866 }
1867
1868 static unsigned int dec_movs_m(DisasContext *dc)
1869 {
1870 int memsize = memsize_z(dc);
1871 int insn_len;
1872 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
1873 memsize_char(memsize),
1874 dc->op1, dc->postinc ? "+]" : "]",
1875 dc->op2));
1876
1877 /* sign extend. */
1878 insn_len = dec_prep_alu_m(dc, 1, memsize);
1879 cris_cc_mask(dc, CC_MASK_NZ);
1880 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1881 do_postinc(dc, memsize);
1882 return insn_len;
1883 }
1884
1885 static unsigned int dec_addu_m(DisasContext *dc)
1886 {
1887 int memsize = memsize_z(dc);
1888 int insn_len;
1889 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
1890 memsize_char(memsize),
1891 dc->op1, dc->postinc ? "+]" : "]",
1892 dc->op2));
1893
1894 /* sign extend. */
1895 insn_len = dec_prep_alu_m(dc, 0, memsize);
1896 cris_cc_mask(dc, CC_MASK_NZVC);
1897 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1898 do_postinc(dc, memsize);
1899 return insn_len;
1900 }
1901
1902 static unsigned int dec_adds_m(DisasContext *dc)
1903 {
1904 int memsize = memsize_z(dc);
1905 int insn_len;
1906 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
1907 memsize_char(memsize),
1908 dc->op1, dc->postinc ? "+]" : "]",
1909 dc->op2));
1910
1911 /* sign extend. */
1912 insn_len = dec_prep_alu_m(dc, 1, memsize);
1913 cris_cc_mask(dc, CC_MASK_NZVC);
1914 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1915 do_postinc(dc, memsize);
1916 return insn_len;
1917 }
1918
1919 static unsigned int dec_subu_m(DisasContext *dc)
1920 {
1921 int memsize = memsize_z(dc);
1922 int insn_len;
1923 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
1924 memsize_char(memsize),
1925 dc->op1, dc->postinc ? "+]" : "]",
1926 dc->op2));
1927
1928 /* sign extend. */
1929 insn_len = dec_prep_alu_m(dc, 0, memsize);
1930 cris_cc_mask(dc, CC_MASK_NZVC);
1931 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1932 do_postinc(dc, memsize);
1933 return insn_len;
1934 }
1935
1936 static unsigned int dec_subs_m(DisasContext *dc)
1937 {
1938 int memsize = memsize_z(dc);
1939 int insn_len;
1940 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
1941 memsize_char(memsize),
1942 dc->op1, dc->postinc ? "+]" : "]",
1943 dc->op2));
1944
1945 /* sign extend. */
1946 insn_len = dec_prep_alu_m(dc, 1, memsize);
1947 cris_cc_mask(dc, CC_MASK_NZVC);
1948 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1949 do_postinc(dc, memsize);
1950 return insn_len;
1951 }
1952
1953 static unsigned int dec_movu_m(DisasContext *dc)
1954 {
1955 int memsize = memsize_z(dc);
1956 int insn_len;
1957
1958 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
1959 memsize_char(memsize),
1960 dc->op1, dc->postinc ? "+]" : "]",
1961 dc->op2));
1962
1963 insn_len = dec_prep_alu_m(dc, 0, memsize);
1964 cris_cc_mask(dc, CC_MASK_NZ);
1965 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1966 do_postinc(dc, memsize);
1967 return insn_len;
1968 }
1969
1970 static unsigned int dec_cmpu_m(DisasContext *dc)
1971 {
1972 int memsize = memsize_z(dc);
1973 int insn_len;
1974 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
1975 memsize_char(memsize),
1976 dc->op1, dc->postinc ? "+]" : "]",
1977 dc->op2));
1978
1979 insn_len = dec_prep_alu_m(dc, 0, memsize);
1980 cris_cc_mask(dc, CC_MASK_NZVC);
1981 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1982 do_postinc(dc, memsize);
1983 return insn_len;
1984 }
1985
1986 static unsigned int dec_cmps_m(DisasContext *dc)
1987 {
1988 int memsize = memsize_z(dc);
1989 int insn_len;
1990 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
1991 memsize_char(memsize),
1992 dc->op1, dc->postinc ? "+]" : "]",
1993 dc->op2));
1994
1995 insn_len = dec_prep_alu_m(dc, 1, memsize);
1996 cris_cc_mask(dc, CC_MASK_NZVC);
1997 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1998 do_postinc(dc, memsize);
1999 return insn_len;
2000 }
2001
2002 static unsigned int dec_cmp_m(DisasContext *dc)
2003 {
2004 int memsize = memsize_zz(dc);
2005 int insn_len;
2006 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2007 memsize_char(memsize),
2008 dc->op1, dc->postinc ? "+]" : "]",
2009 dc->op2));
2010
2011 insn_len = dec_prep_alu_m(dc, 0, memsize);
2012 cris_cc_mask(dc, CC_MASK_NZVC);
2013 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2014 do_postinc(dc, memsize);
2015 return insn_len;
2016 }
2017
2018 static unsigned int dec_test_m(DisasContext *dc)
2019 {
2020 int memsize = memsize_zz(dc);
2021 int insn_len;
2022 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2023 memsize_char(memsize),
2024 dc->op1, dc->postinc ? "+]" : "]",
2025 dc->op2));
2026
2027 insn_len = dec_prep_alu_m(dc, 0, memsize);
2028 cris_cc_mask(dc, CC_MASK_NZ);
2029 gen_op_clrf(3);
2030
2031 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2032 tcg_gen_movi_tl(cpu_T[1], 0);
2033 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2034 do_postinc(dc, memsize);
2035 return insn_len;
2036 }
2037
2038 static unsigned int dec_and_m(DisasContext *dc)
2039 {
2040 int memsize = memsize_zz(dc);
2041 int insn_len;
2042 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2043 memsize_char(memsize),
2044 dc->op1, dc->postinc ? "+]" : "]",
2045 dc->op2));
2046
2047 insn_len = dec_prep_alu_m(dc, 0, memsize);
2048 cris_cc_mask(dc, CC_MASK_NZ);
2049 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
2050 do_postinc(dc, memsize);
2051 return insn_len;
2052 }
2053
2054 static unsigned int dec_add_m(DisasContext *dc)
2055 {
2056 int memsize = memsize_zz(dc);
2057 int insn_len;
2058 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2059 memsize_char(memsize),
2060 dc->op1, dc->postinc ? "+]" : "]",
2061 dc->op2));
2062
2063 insn_len = dec_prep_alu_m(dc, 0, memsize);
2064 cris_cc_mask(dc, CC_MASK_NZVC);
2065 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
2066 do_postinc(dc, memsize);
2067 return insn_len;
2068 }
2069
2070 static unsigned int dec_addo_m(DisasContext *dc)
2071 {
2072 int memsize = memsize_zz(dc);
2073 int insn_len;
2074 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2075 memsize_char(memsize),
2076 dc->op1, dc->postinc ? "+]" : "]",
2077 dc->op2));
2078
2079 insn_len = dec_prep_alu_m(dc, 1, memsize);
2080 cris_cc_mask(dc, 0);
2081 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
2082 do_postinc(dc, memsize);
2083 return insn_len;
2084 }
2085
2086 static unsigned int dec_bound_m(DisasContext *dc)
2087 {
2088 int memsize = memsize_zz(dc);
2089 int insn_len;
2090 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2091 memsize_char(memsize),
2092 dc->op1, dc->postinc ? "+]" : "]",
2093 dc->op2));
2094
2095 insn_len = dec_prep_alu_m(dc, 0, memsize);
2096 cris_cc_mask(dc, CC_MASK_NZ);
2097 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
2098 do_postinc(dc, memsize);
2099 return insn_len;
2100 }
2101
2102 static unsigned int dec_addc_mr(DisasContext *dc)
2103 {
2104 int insn_len = 2;
2105 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2106 dc->op1, dc->postinc ? "+]" : "]",
2107 dc->op2));
2108
2109 cris_evaluate_flags(dc);
2110 insn_len = dec_prep_alu_m(dc, 0, 4);
2111 cris_cc_mask(dc, CC_MASK_NZVC);
2112 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2113 do_postinc(dc, 4);
2114 return insn_len;
2115 }
2116
2117 static unsigned int dec_sub_m(DisasContext *dc)
2118 {
2119 int memsize = memsize_zz(dc);
2120 int insn_len;
2121 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2122 memsize_char(memsize),
2123 dc->op1, dc->postinc ? "+]" : "]",
2124 dc->op2, dc->ir, dc->zzsize));
2125
2126 insn_len = dec_prep_alu_m(dc, 0, memsize);
2127 cris_cc_mask(dc, CC_MASK_NZVC);
2128 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2129 do_postinc(dc, memsize);
2130 return insn_len;
2131 }
2132
2133 static unsigned int dec_or_m(DisasContext *dc)
2134 {
2135 int memsize = memsize_zz(dc);
2136 int insn_len;
2137 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2138 memsize_char(memsize),
2139 dc->op1, dc->postinc ? "+]" : "]",
2140 dc->op2, dc->pc));
2141
2142 insn_len = dec_prep_alu_m(dc, 0, memsize);
2143 cris_cc_mask(dc, CC_MASK_NZ);
2144 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2145 do_postinc(dc, memsize);
2146 return insn_len;
2147 }
2148
2149 static unsigned int dec_move_mp(DisasContext *dc)
2150 {
2151 int memsize = memsize_zz(dc);
2152 int insn_len = 2;
2153
2154 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2155 memsize_char(memsize),
2156 dc->op1,
2157 dc->postinc ? "+]" : "]",
2158 dc->op2));
2159
2160 insn_len = dec_prep_alu_m(dc, 0, memsize);
2161 cris_cc_mask(dc, 0);
2162 if (dc->op2 == PR_CCS) {
2163 cris_evaluate_flags(dc);
2164 if (dc->user) {
2165 /* User space is not allowed to touch all flags. */
2166 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2167 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2168 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2169 }
2170 }
2171
2172 t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
2173
2174 do_postinc(dc, memsize);
2175 return insn_len;
2176 }
2177
2178 static unsigned int dec_move_pm(DisasContext *dc)
2179 {
2180 int memsize;
2181
2182 memsize = preg_sizes[dc->op2];
2183
2184 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2185 memsize_char(memsize),
2186 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2187
2188 /* prepare store. Address in T0, value in T1. */
2189 if (dc->op2 == PR_CCS)
2190 cris_evaluate_flags(dc);
2191 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2192
2193 /* FIXME: qemu_st does not act as a barrier? */
2194 tcg_gen_helper_0_0(helper_dummy);
2195 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2196
2197 cris_cc_mask(dc, 0);
2198 if (dc->postinc)
2199 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2200 return 2;
2201 }
2202
2203 static unsigned int dec_movem_mr(DisasContext *dc)
2204 {
2205 TCGv tmp[16];
2206 int i;
2207
2208 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2209 dc->postinc ? "+]" : "]", dc->op2));
2210
2211 /* FIXME: qemu_ld does not act as a barrier? */
2212 tcg_gen_helper_0_0(helper_dummy);
2213
2214 /* fetch the address into T0 and T1. */
2215 for (i = 0; i <= dc->op2; i++) {
2216 tmp[i] = tcg_temp_new(TCG_TYPE_TL);
2217 /* Perform the load onto regnum i. Always dword wide. */
2218 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2219 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
2220 }
2221
2222 for (i = 0; i <= dc->op2; i++) {
2223 tcg_gen_mov_tl(cpu_R[i], tmp[i]);
2224 tcg_gen_discard_tl(tmp[i]);
2225 }
2226
2227 /* writeback the updated pointer value. */
2228 if (dc->postinc)
2229 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
2230
2231 /* gen_load might want to evaluate the previous insns flags. */
2232 cris_cc_mask(dc, 0);
2233 return 2;
2234 }
2235
2236 static unsigned int dec_movem_rm(DisasContext *dc)
2237 {
2238 int i;
2239
2240 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2241 dc->postinc ? "+]" : "]"));
2242
2243 /* FIXME: qemu_st does not act as a barrier? */
2244 tcg_gen_helper_0_0(helper_dummy);
2245
2246 for (i = 0; i <= dc->op2; i++) {
2247 /* Displace addr. */
2248 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2249 /* Perform the store. */
2250 gen_store(dc, cpu_T[0], cpu_R[i], 4);
2251 }
2252 if (dc->postinc)
2253 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
2254 cris_cc_mask(dc, 0);
2255 return 2;
2256 }
2257
2258 static unsigned int dec_move_rm(DisasContext *dc)
2259 {
2260 int memsize;
2261
2262 memsize = memsize_zz(dc);
2263
2264 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2265 memsize, dc->op2, dc->op1));
2266
2267 /* prepare store. */
2268 /* FIXME: qemu_st does not act as a barrier? */
2269 tcg_gen_helper_0_0(helper_dummy);
2270 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2271
2272 if (dc->postinc)
2273 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2274 cris_cc_mask(dc, 0);
2275 return 2;
2276 }
2277
2278 static unsigned int dec_lapcq(DisasContext *dc)
2279 {
2280 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2281 dc->pc + dc->op1*2, dc->op2));
2282 cris_cc_mask(dc, 0);
2283 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
2284 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2285 return 2;
2286 }
2287
2288 static unsigned int dec_lapc_im(DisasContext *dc)
2289 {
2290 unsigned int rd;
2291 int32_t imm;
2292 int32_t pc;
2293
2294 rd = dc->op2;
2295
2296 cris_cc_mask(dc, 0);
2297 imm = ldl_code(dc->pc + 2);
2298 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2299
2300 pc = dc->pc;
2301 pc += imm;
2302 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2303 return 6;
2304 }
2305
2306 /* Jump to special reg. */
2307 static unsigned int dec_jump_p(DisasContext *dc)
2308 {
2309 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2310
2311 if (dc->op2 == PR_CCS)
2312 cris_evaluate_flags(dc);
2313 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2314 /* rete will often have low bit set to indicate delayslot. */
2315 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2316 cris_cc_mask(dc, 0);
2317 cris_prepare_dyn_jmp(dc);
2318 return 2;
2319 }
2320
2321 /* Jump and save. */
2322 static unsigned int dec_jas_r(DisasContext *dc)
2323 {
2324 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2325 cris_cc_mask(dc, 0);
2326 /* Store the return address in Pd. */
2327 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2328 if (dc->op2 > 15)
2329 abort();
2330 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
2331 tcg_gen_mov_tl(cpu_PR[dc->op2], cpu_T[0]);
2332
2333 cris_prepare_dyn_jmp(dc);
2334 return 2;
2335 }
2336
2337 static unsigned int dec_jas_im(DisasContext *dc)
2338 {
2339 uint32_t imm;
2340
2341 imm = ldl_code(dc->pc + 2);
2342
2343 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2344 cris_cc_mask(dc, 0);
2345 /* Store the return address in Pd. */
2346 tcg_gen_movi_tl(env_btarget, imm);
2347 t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
2348 cris_prepare_dyn_jmp(dc);
2349 return 6;
2350 }
2351
2352 static unsigned int dec_jasc_im(DisasContext *dc)
2353 {
2354 uint32_t imm;
2355
2356 imm = ldl_code(dc->pc + 2);
2357
2358 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2359 cris_cc_mask(dc, 0);
2360 /* Store the return address in Pd. */
2361 tcg_gen_movi_tl(cpu_T[0], imm);
2362 t_gen_mov_env_TN(btarget, cpu_T[0]);
2363 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2364 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2365 cris_prepare_dyn_jmp(dc);
2366 return 6;
2367 }
2368
2369 static unsigned int dec_jasc_r(DisasContext *dc)
2370 {
2371 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2372 cris_cc_mask(dc, 0);
2373 /* Store the return address in Pd. */
2374 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2375 t_gen_mov_env_TN(btarget, cpu_T[0]);
2376 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2377 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2378 cris_prepare_dyn_jmp(dc);
2379 return 2;
2380 }
2381
2382 static unsigned int dec_bcc_im(DisasContext *dc)
2383 {
2384 int32_t offset;
2385 uint32_t cond = dc->op2;
2386
2387 offset = ldsw_code(dc->pc + 2);
2388
2389 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2390 cc_name(cond), offset,
2391 dc->pc, dc->pc + offset));
2392
2393 cris_cc_mask(dc, 0);
2394 /* op2 holds the condition-code. */
2395 cris_prepare_cc_branch (dc, offset, cond);
2396 return 4;
2397 }
2398
2399 static unsigned int dec_bas_im(DisasContext *dc)
2400 {
2401 int32_t simm;
2402
2403
2404 simm = ldl_code(dc->pc + 2);
2405
2406 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2407 cris_cc_mask(dc, 0);
2408 /* Stor the return address in Pd. */
2409 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2410 t_gen_mov_env_TN(btarget, cpu_T[0]);
2411 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2412 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2413 cris_prepare_dyn_jmp(dc);
2414 return 6;
2415 }
2416
2417 static unsigned int dec_basc_im(DisasContext *dc)
2418 {
2419 int32_t simm;
2420 simm = ldl_code(dc->pc + 2);
2421
2422 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2423 cris_cc_mask(dc, 0);
2424 /* Stor the return address in Pd. */
2425 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2426 t_gen_mov_env_TN(btarget, cpu_T[0]);
2427 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2428 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2429 cris_prepare_dyn_jmp(dc);
2430 return 6;
2431 }
2432
2433 static unsigned int dec_rfe_etc(DisasContext *dc)
2434 {
2435 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2436 dc->opcode, dc->pc, dc->op1, dc->op2));
2437
2438 cris_cc_mask(dc, 0);
2439
2440 if (dc->op2 == 15) /* ignore halt. */
2441 return 2;
2442
2443 switch (dc->op2 & 7) {
2444 case 2:
2445 /* rfe. */
2446 cris_evaluate_flags(dc);
2447 gen_op_ccs_rshift();
2448 /* FIXME: don't set the P-FLAG if R is set. */
2449 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], P_FLAG);
2450 /* Debug helper. */
2451 tcg_gen_helper_0_0(helper_rfe);
2452 dc->is_jmp = DISAS_UPDATE;
2453 break;
2454 case 5:
2455 /* rfn. */
2456 BUG();
2457 break;
2458 case 6:
2459 /* break. */
2460 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2461 t_gen_mov_env_TN(pc, cpu_T[0]);
2462 /* Breaks start at 16 in the exception vector. */
2463 gen_op_break_im(dc->op1 + 16);
2464 dc->is_jmp = DISAS_UPDATE;
2465 break;
2466 default:
2467 printf ("op2=%x\n", dc->op2);
2468 BUG();
2469 break;
2470
2471 }
2472 return 2;
2473 }
2474
2475 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2476 {
2477 /* Ignore D-cache flushes. */
2478 return 2;
2479 }
2480
2481 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2482 {
2483 /* Ignore I-cache flushes. */
2484 return 2;
2485 }
2486
2487 static unsigned int dec_null(DisasContext *dc)
2488 {
2489 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2490 dc->pc, dc->opcode, dc->op1, dc->op2);
2491 fflush(NULL);
2492 BUG();
2493 return 2;
2494 }
2495
2496 struct decoder_info {
2497 struct {
2498 uint32_t bits;
2499 uint32_t mask;
2500 };
2501 unsigned int (*dec)(DisasContext *dc);
2502 } decinfo[] = {
2503 /* Order matters here. */
2504 {DEC_MOVEQ, dec_moveq},
2505 {DEC_BTSTQ, dec_btstq},
2506 {DEC_CMPQ, dec_cmpq},
2507 {DEC_ADDOQ, dec_addoq},
2508 {DEC_ADDQ, dec_addq},
2509 {DEC_SUBQ, dec_subq},
2510 {DEC_ANDQ, dec_andq},
2511 {DEC_ORQ, dec_orq},
2512 {DEC_ASRQ, dec_asrq},
2513 {DEC_LSLQ, dec_lslq},
2514 {DEC_LSRQ, dec_lsrq},
2515 {DEC_BCCQ, dec_bccq},
2516
2517 {DEC_BCC_IM, dec_bcc_im},
2518 {DEC_JAS_IM, dec_jas_im},
2519 {DEC_JAS_R, dec_jas_r},
2520 {DEC_JASC_IM, dec_jasc_im},
2521 {DEC_JASC_R, dec_jasc_r},
2522 {DEC_BAS_IM, dec_bas_im},
2523 {DEC_BASC_IM, dec_basc_im},
2524 {DEC_JUMP_P, dec_jump_p},
2525 {DEC_LAPC_IM, dec_lapc_im},
2526 {DEC_LAPCQ, dec_lapcq},
2527
2528 {DEC_RFE_ETC, dec_rfe_etc},
2529 {DEC_ADDC_MR, dec_addc_mr},
2530
2531 {DEC_MOVE_MP, dec_move_mp},
2532 {DEC_MOVE_PM, dec_move_pm},
2533 {DEC_MOVEM_MR, dec_movem_mr},
2534 {DEC_MOVEM_RM, dec_movem_rm},
2535 {DEC_MOVE_PR, dec_move_pr},
2536 {DEC_SCC_R, dec_scc_r},
2537 {DEC_SETF, dec_setclrf},
2538 {DEC_CLEARF, dec_setclrf},
2539
2540 {DEC_MOVE_SR, dec_move_sr},
2541 {DEC_MOVE_RP, dec_move_rp},
2542 {DEC_SWAP_R, dec_swap_r},
2543 {DEC_ABS_R, dec_abs_r},
2544 {DEC_LZ_R, dec_lz_r},
2545 {DEC_MOVE_RS, dec_move_rs},
2546 {DEC_BTST_R, dec_btst_r},
2547 {DEC_ADDC_R, dec_addc_r},
2548
2549 {DEC_DSTEP_R, dec_dstep_r},
2550 {DEC_XOR_R, dec_xor_r},
2551 {DEC_MCP_R, dec_mcp_r},
2552 {DEC_CMP_R, dec_cmp_r},
2553
2554 {DEC_ADDI_R, dec_addi_r},
2555 {DEC_ADDI_ACR, dec_addi_acr},
2556
2557 {DEC_ADD_R, dec_add_r},
2558 {DEC_SUB_R, dec_sub_r},
2559
2560 {DEC_ADDU_R, dec_addu_r},
2561 {DEC_ADDS_R, dec_adds_r},
2562 {DEC_SUBU_R, dec_subu_r},
2563 {DEC_SUBS_R, dec_subs_r},
2564 {DEC_LSL_R, dec_lsl_r},
2565
2566 {DEC_AND_R, dec_and_r},
2567 {DEC_OR_R, dec_or_r},
2568 {DEC_BOUND_R, dec_bound_r},
2569 {DEC_ASR_R, dec_asr_r},
2570 {DEC_LSR_R, dec_lsr_r},
2571
2572 {DEC_MOVU_R, dec_movu_r},
2573 {DEC_MOVS_R, dec_movs_r},
2574 {DEC_NEG_R, dec_neg_r},
2575 {DEC_MOVE_R, dec_move_r},
2576
2577 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2578 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2579
2580 {DEC_MULS_R, dec_muls_r},
2581 {DEC_MULU_R, dec_mulu_r},
2582
2583 {DEC_ADDU_M, dec_addu_m},
2584 {DEC_ADDS_M, dec_adds_m},
2585 {DEC_SUBU_M, dec_subu_m},
2586 {DEC_SUBS_M, dec_subs_m},
2587
2588 {DEC_CMPU_M, dec_cmpu_m},
2589 {DEC_CMPS_M, dec_cmps_m},
2590 {DEC_MOVU_M, dec_movu_m},
2591 {DEC_MOVS_M, dec_movs_m},
2592
2593 {DEC_CMP_M, dec_cmp_m},
2594 {DEC_ADDO_M, dec_addo_m},
2595 {DEC_BOUND_M, dec_bound_m},
2596 {DEC_ADD_M, dec_add_m},
2597 {DEC_SUB_M, dec_sub_m},
2598 {DEC_AND_M, dec_and_m},
2599 {DEC_OR_M, dec_or_m},
2600 {DEC_MOVE_RM, dec_move_rm},
2601 {DEC_TEST_M, dec_test_m},
2602 {DEC_MOVE_MR, dec_move_mr},
2603
2604 {{0, 0}, dec_null}
2605 };
2606
2607 static inline unsigned int
2608 cris_decoder(DisasContext *dc)
2609 {
2610 unsigned int insn_len = 2;
2611 int i;
2612
2613 /* Load a halfword onto the instruction register. */
2614 dc->ir = lduw_code(dc->pc);
2615
2616 /* Now decode it. */
2617 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2618 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2619 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2620 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2621 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2622 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2623
2624 /* Large switch for all insns. */
2625 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2626 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2627 {
2628 insn_len = decinfo[i].dec(dc);
2629 break;
2630 }
2631 }
2632
2633 return insn_len;
2634 }
2635
2636 static void check_breakpoint(CPUState *env, DisasContext *dc)
2637 {
2638 int j;
2639 if (env->nb_breakpoints > 0) {
2640 for(j = 0; j < env->nb_breakpoints; j++) {
2641 if (env->breakpoints[j] == dc->pc) {
2642 cris_evaluate_flags (dc);
2643 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2644 t_gen_mov_env_TN(pc, cpu_T[0]);
2645 gen_op_debug();
2646 dc->is_jmp = DISAS_UPDATE;
2647 }
2648 }
2649 }
2650 }
2651
2652 /* generate intermediate code for basic block 'tb'. */
2653 struct DisasContext ctx;
2654 static int
2655 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2656 int search_pc)
2657 {
2658 uint16_t *gen_opc_end;
2659 uint32_t pc_start;
2660 unsigned int insn_len;
2661 int j, lj;
2662 struct DisasContext *dc = &ctx;
2663 uint32_t next_page_start;
2664
2665 if (!logfile)
2666 logfile = stderr;
2667
2668 if (tb->pc & 1)
2669 cpu_abort(env, "unaligned pc=%x erp=%x\n",
2670 env->pc, env->pregs[PR_ERP]);
2671 pc_start = tb->pc;
2672 dc->env = env;
2673 dc->tb = tb;
2674
2675 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2676
2677 dc->is_jmp = DISAS_NEXT;
2678 dc->ppc = pc_start;
2679 dc->pc = pc_start;
2680 dc->singlestep_enabled = env->singlestep_enabled;
2681 dc->flags_live = 1;
2682 dc->flagx_live = 0;
2683 dc->flags_x = 0;
2684 dc->cc_mask = 0;
2685 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2686
2687 dc->user = env->pregs[PR_CCS] & U_FLAG;
2688 dc->delayed_branch = 0;
2689
2690 if (loglevel & CPU_LOG_TB_IN_ASM) {
2691 fprintf(logfile,
2692 "search=%d pc=%x ccs=%x pid=%x usp=%x\n"
2693 "%x.%x.%x.%x\n"
2694 "%x.%x.%x.%x\n"
2695 "%x.%x.%x.%x\n"
2696 "%x.%x.%x.%x\n",
2697 search_pc, env->pc, env->pregs[PR_CCS],
2698 env->pregs[PR_PID], env->pregs[PR_USP],
2699 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2700 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2701 env->regs[8], env->regs[9],
2702 env->regs[10], env->regs[11],
2703 env->regs[12], env->regs[13],
2704 env->regs[14], env->regs[15]);
2705
2706 }
2707
2708 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2709 lj = -1;
2710 do
2711 {
2712 check_breakpoint(env, dc);
2713 if (dc->is_jmp == DISAS_JUMP
2714 || dc->is_jmp == DISAS_SWI)
2715 goto done;
2716
2717 if (search_pc) {
2718 j = gen_opc_ptr - gen_opc_buf;
2719 if (lj < j) {
2720 lj++;
2721 while (lj < j)
2722 gen_opc_instr_start[lj++] = 0;
2723 }
2724 if (dc->delayed_branch == 1) {
2725 gen_opc_pc[lj] = dc->ppc | 1;
2726 gen_opc_instr_start[lj] = 0;
2727 }
2728 else {
2729 gen_opc_pc[lj] = dc->pc;
2730 gen_opc_instr_start[lj] = 1;
2731 }
2732 }
2733
2734 dc->clear_x = 1;
2735 insn_len = cris_decoder(dc);
2736 STATS(gen_op_exec_insn());
2737 dc->ppc = dc->pc;
2738 dc->pc += insn_len;
2739 if (dc->clear_x)
2740 cris_clear_x_flag(dc);
2741
2742 /* Check for delayed branches here. If we do it before
2743 actually genereating any host code, the simulator will just
2744 loop doing nothing for on this program location. */
2745 if (dc->delayed_branch) {
2746 dc->delayed_branch--;
2747 if (dc->delayed_branch == 0)
2748 {
2749 if (dc->bcc == CC_A) {
2750 tcg_gen_mov_tl(env_pc, env_btarget);
2751 dc->is_jmp = DISAS_JUMP;
2752 }
2753 else {
2754 t_gen_cc_jmp(dc->delayed_pc, dc->pc);
2755 dc->is_jmp = DISAS_JUMP;
2756 }
2757 }
2758 }
2759
2760 if (env->singlestep_enabled)
2761 break;
2762 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
2763 && ((dc->pc < next_page_start) || dc->delayed_branch));
2764
2765 if (dc->delayed_branch == 1) {
2766 /* Reexecute the last insn. */
2767 dc->pc = dc->ppc;
2768 }
2769
2770 if (!dc->is_jmp) {
2771 D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
2772 dc->is_jmp, dc->delayed_branch));
2773 /* T0 and env_pc should hold the new pc. */
2774 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2775 tcg_gen_mov_tl(env_pc, cpu_T[0]);
2776 }
2777
2778 cris_evaluate_flags (dc);
2779 done:
2780 if (__builtin_expect(env->singlestep_enabled, 0)) {
2781 gen_op_debug();
2782 } else {
2783 switch(dc->is_jmp) {
2784 case DISAS_NEXT:
2785 gen_goto_tb(dc, 1, dc->pc);
2786 break;
2787 default:
2788 case DISAS_JUMP:
2789 case DISAS_UPDATE:
2790 /* indicate that the hash table must be used
2791 to find the next TB */
2792 tcg_gen_exit_tb(0);
2793 break;
2794 case DISAS_SWI:
2795 case DISAS_TB_JUMP:
2796 /* nothing more to generate */
2797 break;
2798 }
2799 }
2800 *gen_opc_ptr = INDEX_op_end;
2801 if (search_pc) {
2802 j = gen_opc_ptr - gen_opc_buf;
2803 lj++;
2804 while (lj <= j)
2805 gen_opc_instr_start[lj++] = 0;
2806 } else {
2807 tb->size = dc->pc - pc_start;
2808 }
2809
2810 #ifdef DEBUG_DISAS
2811 if (loglevel & CPU_LOG_TB_IN_ASM) {
2812 fprintf(logfile, "--------------\n");
2813 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2814 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
2815 fprintf(logfile, "\nisize=%d osize=%d\n",
2816 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
2817 }
2818 #endif
2819 return 0;
2820 }
2821
2822 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2823 {
2824 return gen_intermediate_code_internal(env, tb, 0);
2825 }
2826
2827 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2828 {
2829 return gen_intermediate_code_internal(env, tb, 1);
2830 }
2831
2832 void cpu_dump_state (CPUState *env, FILE *f,
2833 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2834 int flags)
2835 {
2836 int i;
2837 uint32_t srs;
2838
2839 if (!env || !f)
2840 return;
2841
2842 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2843 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2844 "debug=%x %x %x\n",
2845 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
2846 env->cc_op,
2847 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2848 env->debug1, env->debug2, env->debug3);
2849
2850 for (i = 0; i < 16; i++) {
2851 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
2852 if ((i + 1) % 4 == 0)
2853 cpu_fprintf(f, "\n");
2854 }
2855 cpu_fprintf(f, "\nspecial regs:\n");
2856 for (i = 0; i < 16; i++) {
2857 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
2858 if ((i + 1) % 4 == 0)
2859 cpu_fprintf(f, "\n");
2860 }
2861 srs = env->pregs[PR_SRS];
2862 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
2863 if (srs < 256) {
2864 for (i = 0; i < 16; i++) {
2865 cpu_fprintf(f, "s%2.2d=%8.8x ",
2866 i, env->sregs[srs][i]);
2867 if ((i + 1) % 4 == 0)
2868 cpu_fprintf(f, "\n");
2869 }
2870 }
2871 cpu_fprintf(f, "\n\n");
2872
2873 }
2874
2875 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
2876 {
2877 }
2878
2879 CPUCRISState *cpu_cris_init (const char *cpu_model)
2880 {
2881 CPUCRISState *env;
2882 int i;
2883
2884 env = qemu_mallocz(sizeof(CPUCRISState));
2885 if (!env)
2886 return NULL;
2887 cpu_exec_init(env);
2888
2889 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
2890 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
2891 #if TARGET_LONG_BITS > HOST_LONG_BITS
2892 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
2893 TCG_AREG0, offsetof(CPUState, t0), "T0");
2894 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
2895 TCG_AREG0, offsetof(CPUState, t1), "T1");
2896 #else
2897 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
2898 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
2899 #endif
2900
2901 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2902 offsetof(CPUState, cc_src), "cc_src");
2903 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2904 offsetof(CPUState, cc_dest),
2905 "cc_dest");
2906 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2907 offsetof(CPUState, cc_result),
2908 "cc_result");
2909 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2910 offsetof(CPUState, cc_op), "cc_op");
2911 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2912 offsetof(CPUState, cc_size),
2913 "cc_size");
2914 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2915 offsetof(CPUState, cc_mask),
2916 "cc_mask");
2917
2918 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2919 offsetof(CPUState, pc),
2920 "pc");
2921 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2922 offsetof(CPUState, btarget),
2923 "btarget");
2924
2925 for (i = 0; i < 16; i++) {
2926 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2927 offsetof(CPUState, regs[i]),
2928 regnames[i]);
2929 }
2930 for (i = 0; i < 16; i++) {
2931 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2932 offsetof(CPUState, pregs[i]),
2933 pregnames[i]);
2934 }
2935
2936 TCG_HELPER(helper_tlb_update);
2937 TCG_HELPER(helper_tlb_flush);
2938 TCG_HELPER(helper_rfe);
2939 TCG_HELPER(helper_store);
2940 TCG_HELPER(helper_dump);
2941 TCG_HELPER(helper_dummy);
2942
2943 TCG_HELPER(helper_evaluate_flags_muls);
2944 TCG_HELPER(helper_evaluate_flags_mulu);
2945 TCG_HELPER(helper_evaluate_flags_mcp);
2946 TCG_HELPER(helper_evaluate_flags_alu_4);
2947 TCG_HELPER(helper_evaluate_flags_move_4);
2948 TCG_HELPER(helper_evaluate_flags_move_2);
2949 TCG_HELPER(helper_evaluate_flags);
2950
2951 cpu_reset(env);
2952 return env;
2953 }
2954
2955 void cpu_reset (CPUCRISState *env)
2956 {
2957 memset(env, 0, offsetof(CPUCRISState, breakpoints));
2958 tlb_flush(env, 1);
2959
2960 #if defined(CONFIG_USER_ONLY)
2961 /* start in user mode with interrupts enabled. */
2962 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
2963 #else
2964 env->pregs[PR_CCS] = 0;
2965 #endif
2966 }
2967
2968 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
2969 unsigned long searched_pc, int pc_pos, void *puc)
2970 {
2971 env->pc = gen_opc_pc[pc_pos];
2972 }
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