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2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #include "crisv32-decode.h"
50 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51 #define BUG_ON(x) ({if (x) BUG();})
55 /* Used by the decoder. */
56 #define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
59 #define CC_MASK_NZ 0xc
60 #define CC_MASK_NZV 0xe
61 #define CC_MASK_NZVC 0xf
62 #define CC_MASK_RNZV 0x10e
64 TCGv cpu_env
, cpu_T
[2];
66 /* This is the state at translation time. */
67 typedef struct DisasContext
{
69 target_ulong pc
, insn_pc
;
76 unsigned int zsize
, zzsize
;
87 uint32_t tb_entry_flags
;
89 int memidx
; /* user or kernel mode. */
98 struct TranslationBlock
*tb
;
99 int singlestep_enabled
;
102 void cris_prepare_jmp (DisasContext
*dc
, uint32_t dst
);
103 static void gen_BUG(DisasContext
*dc
, char *file
, int line
)
105 printf ("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
106 fprintf (logfile
, "BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
107 cpu_dump_state (dc
->env
, stdout
, fprintf
, 0);
109 cris_prepare_jmp (dc
, 0x70000000 + line
);
112 #ifdef CONFIG_USER_ONLY
113 #define GEN_OP_LD(width, reg) \
114 void gen_op_ld##width##_T0_##reg (DisasContext *dc) { \
115 gen_op_ld##width##_T0_##reg##_raw(); \
117 #define GEN_OP_ST(width, reg) \
118 void gen_op_st##width##_##reg##_T1 (DisasContext *dc) { \
119 gen_op_st##width##_##reg##_T1_raw(); \
122 #define GEN_OP_LD(width, reg) \
123 void gen_op_ld##width##_T0_##reg (DisasContext *dc) { \
124 if (dc->memidx) gen_op_ld##width##_T0_##reg##_kernel(); \
125 else gen_op_ld##width##_T0_##reg##_user();\
127 #define GEN_OP_ST(width, reg) \
128 void gen_op_st##width##_##reg##_T1 (DisasContext *dc) { \
129 if (dc->memidx) gen_op_st##width##_##reg##_T1_kernel(); \
130 else gen_op_st##width##_##reg##_T1_user();\
143 /* We need this table to handle preg-moves with implicit width. */
155 #define t_gen_mov_TN_env(tn, member) \
156 _t_gen_mov_TN_env((tn), offsetof(CPUState, (member)))
157 #define t_gen_mov_env_TN(member, tn) \
158 _t_gen_mov_env_TN(offsetof(CPUState, (member)), (tn))
160 #define t_gen_mov_TN_reg(tn, regno) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, regs[regno]))
162 #define t_gen_mov_reg_TN(regno, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, regs[regno]), (tn))
165 static inline void _t_gen_mov_TN_env(TCGv tn
, int offset
)
167 tcg_gen_ld_tl(tn
, cpu_env
, offset
);
169 static inline void _t_gen_mov_env_TN(int offset
, TCGv tn
)
171 tcg_gen_st_tl(tn
, cpu_env
, offset
);
174 static inline void t_gen_mov_TN_preg(TCGv tn
, int r
)
176 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
)
177 tcg_gen_mov_tl(tn
, tcg_const_i32(0));
179 tcg_gen_mov_tl(tn
, tcg_const_i32(32));
181 tcg_gen_ld_tl(tn
, cpu_env
, offsetof(CPUState
, pregs
[r
]));
183 static inline void t_gen_mov_preg_TN(int r
, TCGv tn
)
185 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
)
188 tcg_gen_st_tl(tn
, cpu_env
, offsetof(CPUState
, pregs
[r
]));
191 static inline void t_gen_mov_TN_im(TCGv tn
, int32_t val
)
193 tcg_gen_movi_tl(tn
, val
);
196 static void t_gen_lsl(TCGv d
, TCGv a
, TCGv b
)
200 l1
= gen_new_label();
201 /* Speculative shift. */
202 tcg_gen_shl_tl(d
, a
, b
);
203 tcg_gen_brcond_tl(TCG_COND_LE
, b
, tcg_const_i32(31), l1
);
204 /* Clear dst if shift operands were to large. */
205 tcg_gen_movi_tl(d
, 0);
209 static void t_gen_lsr(TCGv d
, TCGv a
, TCGv b
)
213 l1
= gen_new_label();
214 /* Speculative shift. */
215 tcg_gen_shr_tl(d
, a
, b
);
216 tcg_gen_brcond_tl(TCG_COND_LE
, b
, tcg_const_i32(31), l1
);
217 /* Clear dst if shift operands were to large. */
218 tcg_gen_movi_tl(d
, 0);
222 static void t_gen_asr(TCGv d
, TCGv a
, TCGv b
)
226 l1
= gen_new_label();
227 /* Speculative shift. */
228 tcg_gen_sar_tl(d
, a
, b
);
229 tcg_gen_brcond_tl(TCG_COND_LE
, b
, tcg_const_i32(31), l1
);
230 /* Clear dst if shift operands were to large. */
231 tcg_gen_movi_tl(d
, 0);
232 tcg_gen_brcond_tl(TCG_COND_LT
, b
, tcg_const_i32(0x80000000), l1
);
233 tcg_gen_movi_tl(d
, 0xffffffff);
237 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
239 TranslationBlock
*tb
;
241 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
243 tcg_gen_movi_tl(cpu_T
[0], dest
);
245 tcg_gen_exit_tb((long)tb
+ n
);
252 /* Sign extend at translation time. */
253 static int sign_extend(unsigned int val
, unsigned int width
)
265 static inline void cris_clear_x_flag(DisasContext
*dc
)
269 ccs
= tcg_temp_new(TCG_TYPE_TL
);
271 t_gen_mov_TN_preg(ccs
, PR_CCS
);
272 tcg_gen_andi_i32(ccs
, ccs
, ~X_FLAG
);
273 t_gen_mov_preg_TN(PR_CCS
, ccs
);
278 static void cris_evaluate_flags(DisasContext
*dc
)
280 if (!dc
->flags_live
) {
284 gen_op_evaluate_flags_mcp ();
287 gen_op_evaluate_flags_muls ();
290 gen_op_evaluate_flags_mulu ();
296 gen_op_evaluate_flags_move_4();
299 gen_op_evaluate_flags_move_2();
302 gen_op_evaluate_flags ();
312 gen_op_evaluate_flags_alu_4 ();
315 gen_op_evaluate_flags ();
325 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
329 /* Check if we need to evaluate the condition codes due to
331 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
333 /* TODO: optimize this case. It trigs all the time. */
334 cris_evaluate_flags (dc
);
342 gen_op_update_cc_mask(mask
);
347 static void cris_update_cc_op(DisasContext
*dc
, int op
)
350 gen_op_update_cc_op(op
);
353 static void cris_update_cc_size(DisasContext
*dc
, int size
)
356 gen_op_update_cc_size_im(size
);
359 /* op is the operation.
360 T0, T1 are the operands.
361 dst is the destination reg.
363 static void crisv32_alu_op(DisasContext
*dc
, int op
, int rd
, int size
)
367 cris_update_cc_op(dc
, op
);
368 cris_update_cc_size(dc
, size
);
369 gen_op_update_cc_x(dc
->flagx_live
, dc
->flags_x
);
370 gen_op_update_cc_dest_T0();
373 /* Emit the ALU insns. */
377 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
378 /* Extended arithmetics. */
382 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
386 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
390 tcg_gen_sub_tl(cpu_T
[1], tcg_const_i32(0), cpu_T
[1]);
391 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
392 /* CRIS flag evaluation needs ~src. */
393 tcg_gen_sub_tl(cpu_T
[1], tcg_const_i32(0), cpu_T
[1]);
396 /* Extended arithmetics. */
400 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
403 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
406 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
409 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
412 t_gen_lsl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
415 t_gen_lsr(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
418 t_gen_asr(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
421 /* TCG-FIXME: this is not optimal. Many archs have
423 tcg_gen_sub_tl(cpu_T
[0], tcg_const_i32(0), cpu_T
[1]);
424 /* Extended arithmetics. */
441 gen_op_dstep_T0_T1();
444 gen_op_bound_T0_T1();
447 tcg_gen_sub_tl(cpu_T
[1], tcg_const_i32(0), cpu_T
[1]);
448 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
449 /* CRIS flag evaluation needs ~src. */
450 tcg_gen_sub_tl(cpu_T
[1], tcg_const_i32(0), cpu_T
[1]);
451 /* CRIS flag evaluation needs ~src. */
454 /* Extended arithmetics. */
459 fprintf (logfile
, "illegal ALU op.\n");
465 gen_op_update_cc_src_T1();
468 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
470 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
475 t_gen_mov_reg_TN(rd
, cpu_T
[0]);
477 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
478 t_gen_mov_TN_reg(cpu_T
[0], rd
);
480 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], ~0xff);
482 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], ~0xffff);
483 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
484 t_gen_mov_reg_TN(rd
, cpu_T
[0]);
485 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
489 gen_op_update_cc_result_T0();
492 /* TODO: Optimize this. */
494 cris_evaluate_flags(dc
);
498 static int arith_cc(DisasContext
*dc
)
502 case CC_OP_ADD
: return 1;
503 case CC_OP_SUB
: return 1;
504 case CC_OP_LSL
: return 1;
505 case CC_OP_LSR
: return 1;
506 case CC_OP_ASR
: return 1;
507 case CC_OP_CMP
: return 1;
515 static void gen_tst_cc (DisasContext
*dc
, int cond
)
519 /* TODO: optimize more condition codes. */
520 arith_opt
= arith_cc(dc
) && !dc
->flags_live
;
524 gen_op_tst_cc_eq_fast ();
526 cris_evaluate_flags(dc
);
532 gen_op_tst_cc_ne_fast ();
534 cris_evaluate_flags(dc
);
539 cris_evaluate_flags(dc
);
543 cris_evaluate_flags(dc
);
547 cris_evaluate_flags(dc
);
551 cris_evaluate_flags(dc
);
556 gen_op_tst_cc_pl_fast ();
558 cris_evaluate_flags(dc
);
564 gen_op_tst_cc_mi_fast ();
566 cris_evaluate_flags(dc
);
571 cris_evaluate_flags(dc
);
575 cris_evaluate_flags(dc
);
579 cris_evaluate_flags(dc
);
583 cris_evaluate_flags(dc
);
587 cris_evaluate_flags(dc
);
591 cris_evaluate_flags(dc
);
595 cris_evaluate_flags(dc
);
599 cris_evaluate_flags(dc
);
600 gen_op_movl_T0_im (1);
608 static void cris_prepare_cc_branch (DisasContext
*dc
, int offset
, int cond
)
610 /* This helps us re-schedule the micro-code to insns in delay-slots
611 before the actual jump. */
612 dc
->delayed_branch
= 2;
613 dc
->delayed_pc
= dc
->pc
+ offset
;
617 gen_tst_cc (dc
, cond
);
618 gen_op_evaluate_bcc ();
620 gen_op_movl_T0_im (dc
->delayed_pc
);
621 gen_op_movl_btarget_T0 ();
624 /* Dynamic jumps, when the dest is in a live reg for example. */
625 void cris_prepare_dyn_jmp (DisasContext
*dc
)
627 /* This helps us re-schedule the micro-code to insns in delay-slots
628 before the actual jump. */
629 dc
->delayed_branch
= 2;
634 void cris_prepare_jmp (DisasContext
*dc
, uint32_t dst
)
636 /* This helps us re-schedule the micro-code to insns in delay-slots
637 before the actual jump. */
638 dc
->delayed_branch
= 2;
639 dc
->delayed_pc
= dst
;
644 void gen_load_T0_T0 (DisasContext
*dc
, unsigned int size
, int sign
)
648 gen_op_ldb_T0_T0(dc
);
650 gen_op_ldub_T0_T0(dc
);
652 else if (size
== 2) {
654 gen_op_ldw_T0_T0(dc
);
656 gen_op_lduw_T0_T0(dc
);
659 gen_op_ldl_T0_T0(dc
);
663 void gen_store_T0_T1 (DisasContext
*dc
, unsigned int size
)
665 /* Remember, operands are flipped. CRIS has reversed order. */
667 gen_op_stb_T0_T1(dc
);
669 else if (size
== 2) {
670 gen_op_stw_T0_T1(dc
);
673 gen_op_stl_T0_T1(dc
);
676 static inline void t_gen_sext(TCGv d
, TCGv s
, int size
)
679 tcg_gen_ext8s_i32(d
, s
);
681 tcg_gen_ext16s_i32(d
, s
);
684 static inline void t_gen_zext(TCGv d
, TCGv s
, int size
)
686 /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
688 tcg_gen_andi_i32(d
, s
, 0xff);
690 tcg_gen_andi_i32(d
, s
, 0xffff);
694 static char memsize_char(int size
)
698 case 1: return 'b'; break;
699 case 2: return 'w'; break;
700 case 4: return 'd'; break;
708 static unsigned int memsize_z(DisasContext
*dc
)
710 return dc
->zsize
+ 1;
713 static unsigned int memsize_zz(DisasContext
*dc
)
724 static void do_postinc (DisasContext
*dc
, int size
)
728 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
729 gen_op_addl_T0_im(size
);
730 t_gen_mov_reg_TN(dc
->op1
, cpu_T
[0]);
734 static void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
737 t_gen_mov_TN_reg(cpu_T
[1], rs
);
739 t_gen_sext(cpu_T
[1], cpu_T
[1], size
);
741 t_gen_zext(cpu_T
[1], cpu_T
[1], size
);
744 /* Prepare T0 and T1 for a register alu operation.
745 s_ext decides if the operand1 should be sign-extended or zero-extended when
747 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
750 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
);
752 t_gen_mov_TN_reg(cpu_T
[0], rd
);
754 t_gen_sext(cpu_T
[0], cpu_T
[0], size
);
756 t_gen_zext(cpu_T
[0], cpu_T
[0], size
);
759 /* Prepare T0 and T1 for a memory + alu operation.
760 s_ext decides if the operand1 should be sign-extended or zero-extended when
762 static int dec_prep_alu_m(DisasContext
*dc
, int s_ext
, int memsize
)
771 is_imm
= rs
== 15 && dc
->postinc
;
773 /* Load [$rs] onto T1. */
775 insn_len
= 2 + memsize
;
779 imm
= ldl_code(dc
->pc
+ 2);
782 imm
= sign_extend(imm
, (memsize
* 8) - 1);
790 DIS(fprintf (logfile
, "imm=%x rd=%d sext=%d ms=%d\n",
791 imm
, rd
, s_ext
, memsize
));
792 tcg_gen_movi_tl(cpu_T
[1], imm
);
795 t_gen_mov_TN_reg(cpu_T
[0], rs
);
796 gen_load_T0_T0(dc
, memsize
, 0);
797 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
799 t_gen_sext(cpu_T
[1], cpu_T
[1], memsize
);
801 t_gen_zext(cpu_T
[1], cpu_T
[1], memsize
);
804 /* put dest in T0. */
805 t_gen_mov_TN_reg(cpu_T
[0], rd
);
810 static const char *cc_name(int cc
)
812 static char *cc_names
[16] = {
813 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
814 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
821 static unsigned int dec_bccq(DisasContext
*dc
)
825 uint32_t cond
= dc
->op2
;
828 offset
= EXTRACT_FIELD (dc
->ir
, 1, 7);
829 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
834 offset
= sign_extend(offset
, 8);
836 /* op2 holds the condition-code. */
838 cris_prepare_cc_branch (dc
, offset
, cond
);
841 static unsigned int dec_addoq(DisasContext
*dc
)
845 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
846 imm
= sign_extend(dc
->op1
, 7);
848 DIS(fprintf (logfile
, "addoq %d, $r%u\n", imm
, dc
->op2
));
850 /* Fetch register operand, */
851 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
852 tcg_gen_movi_tl(cpu_T
[1], imm
);
853 crisv32_alu_op(dc
, CC_OP_ADD
, R_ACR
, 4);
856 static unsigned int dec_addq(DisasContext
*dc
)
858 DIS(fprintf (logfile
, "addq %u, $r%u\n", dc
->op1
, dc
->op2
));
860 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
862 cris_cc_mask(dc
, CC_MASK_NZVC
);
863 /* Fetch register operand, */
864 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
865 tcg_gen_movi_tl(cpu_T
[1], dc
->op1
);
866 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
869 static unsigned int dec_moveq(DisasContext
*dc
)
873 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
874 imm
= sign_extend(dc
->op1
, 5);
875 DIS(fprintf (logfile
, "moveq %d, $r%u\n", imm
, dc
->op2
));
877 t_gen_mov_reg_TN(dc
->op2
, tcg_const_i32(imm
));
878 if (!dc
->flagx_live
|| dc
->flags_x
)
879 cris_clear_x_flag(dc
);
882 static unsigned int dec_subq(DisasContext
*dc
)
884 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
886 DIS(fprintf (logfile
, "subq %u, $r%u\n", dc
->op1
, dc
->op2
));
888 cris_cc_mask(dc
, CC_MASK_NZVC
);
889 /* Fetch register operand, */
890 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
891 t_gen_mov_TN_im(cpu_T
[1], dc
->op1
);
892 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
895 static unsigned int dec_cmpq(DisasContext
*dc
)
898 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
899 imm
= sign_extend(dc
->op1
, 5);
901 DIS(fprintf (logfile
, "cmpq %d, $r%d\n", imm
, dc
->op2
));
902 cris_cc_mask(dc
, CC_MASK_NZVC
);
903 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
904 t_gen_mov_TN_im(cpu_T
[1], imm
);
905 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, 4);
908 static unsigned int dec_andq(DisasContext
*dc
)
911 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
912 imm
= sign_extend(dc
->op1
, 5);
914 DIS(fprintf (logfile
, "andq %d, $r%d\n", imm
, dc
->op2
));
915 cris_cc_mask(dc
, CC_MASK_NZ
);
916 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
917 t_gen_mov_TN_im(cpu_T
[1], imm
);
918 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, 4);
921 static unsigned int dec_orq(DisasContext
*dc
)
924 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
925 imm
= sign_extend(dc
->op1
, 5);
926 DIS(fprintf (logfile
, "orq %d, $r%d\n", imm
, dc
->op2
));
927 cris_cc_mask(dc
, CC_MASK_NZ
);
928 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
929 t_gen_mov_TN_im(cpu_T
[1], imm
);
930 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, 4);
933 static unsigned int dec_btstq(DisasContext
*dc
)
935 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
936 DIS(fprintf (logfile
, "btstq %u, $r%d\n", dc
->op1
, dc
->op2
));
937 cris_cc_mask(dc
, CC_MASK_NZ
);
938 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
939 t_gen_mov_TN_im(cpu_T
[1], dc
->op1
);
940 crisv32_alu_op(dc
, CC_OP_BTST
, dc
->op2
, 4);
942 cris_update_cc_op(dc
, CC_OP_FLAGS
);
943 gen_op_movl_flags_T0();
947 static unsigned int dec_asrq(DisasContext
*dc
)
949 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
950 DIS(fprintf (logfile
, "asrq %u, $r%d\n", dc
->op1
, dc
->op2
));
951 cris_cc_mask(dc
, CC_MASK_NZ
);
952 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
953 t_gen_mov_TN_im(cpu_T
[1], dc
->op1
);
954 crisv32_alu_op(dc
, CC_OP_ASR
, dc
->op2
, 4);
957 static unsigned int dec_lslq(DisasContext
*dc
)
959 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
960 DIS(fprintf (logfile
, "lslq %u, $r%d\n", dc
->op1
, dc
->op2
));
962 cris_cc_mask(dc
, CC_MASK_NZ
);
963 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
964 t_gen_mov_TN_im(cpu_T
[1], dc
->op1
);
965 crisv32_alu_op(dc
, CC_OP_LSL
, dc
->op2
, 4);
968 static unsigned int dec_lsrq(DisasContext
*dc
)
970 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
971 DIS(fprintf (logfile
, "lsrq %u, $r%d\n", dc
->op1
, dc
->op2
));
973 cris_cc_mask(dc
, CC_MASK_NZ
);
974 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
975 t_gen_mov_TN_im(cpu_T
[1], dc
->op1
);
976 crisv32_alu_op(dc
, CC_OP_LSR
, dc
->op2
, 4);
980 static unsigned int dec_move_r(DisasContext
*dc
)
982 int size
= memsize_zz(dc
);
984 DIS(fprintf (logfile
, "move.%c $r%u, $r%u\n",
985 memsize_char(size
), dc
->op1
, dc
->op2
));
987 cris_cc_mask(dc
, CC_MASK_NZ
);
988 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
989 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, size
);
993 static unsigned int dec_scc_r(DisasContext
*dc
)
997 DIS(fprintf (logfile
, "s%s $r%u\n",
998 cc_name(cond
), dc
->op1
));
1002 gen_tst_cc (dc
, cond
);
1003 gen_op_movl_T1_T0();
1006 gen_op_movl_T1_im(1);
1008 cris_cc_mask(dc
, 0);
1009 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, 4);
1013 static unsigned int dec_and_r(DisasContext
*dc
)
1015 int size
= memsize_zz(dc
);
1017 DIS(fprintf (logfile
, "and.%c $r%u, $r%u\n",
1018 memsize_char(size
), dc
->op1
, dc
->op2
));
1019 cris_cc_mask(dc
, CC_MASK_NZ
);
1020 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1021 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, size
);
1025 static unsigned int dec_lz_r(DisasContext
*dc
)
1027 DIS(fprintf (logfile
, "lz $r%u, $r%u\n",
1029 cris_cc_mask(dc
, CC_MASK_NZ
);
1030 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1031 crisv32_alu_op(dc
, CC_OP_LZ
, dc
->op2
, 4);
1035 static unsigned int dec_lsl_r(DisasContext
*dc
)
1037 int size
= memsize_zz(dc
);
1039 DIS(fprintf (logfile
, "lsl.%c $r%u, $r%u\n",
1040 memsize_char(size
), dc
->op1
, dc
->op2
));
1041 cris_cc_mask(dc
, CC_MASK_NZ
);
1042 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1043 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], 63);
1044 crisv32_alu_op(dc
, CC_OP_LSL
, dc
->op2
, size
);
1048 static unsigned int dec_lsr_r(DisasContext
*dc
)
1050 int size
= memsize_zz(dc
);
1052 DIS(fprintf (logfile
, "lsr.%c $r%u, $r%u\n",
1053 memsize_char(size
), dc
->op1
, dc
->op2
));
1054 cris_cc_mask(dc
, CC_MASK_NZ
);
1055 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1056 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], 63);
1057 crisv32_alu_op(dc
, CC_OP_LSR
, dc
->op2
, size
);
1061 static unsigned int dec_asr_r(DisasContext
*dc
)
1063 int size
= memsize_zz(dc
);
1065 DIS(fprintf (logfile
, "asr.%c $r%u, $r%u\n",
1066 memsize_char(size
), dc
->op1
, dc
->op2
));
1067 cris_cc_mask(dc
, CC_MASK_NZ
);
1068 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1);
1069 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], 63);
1070 crisv32_alu_op(dc
, CC_OP_ASR
, dc
->op2
, size
);
1074 static unsigned int dec_muls_r(DisasContext
*dc
)
1076 int size
= memsize_zz(dc
);
1078 DIS(fprintf (logfile
, "muls.%c $r%u, $r%u\n",
1079 memsize_char(size
), dc
->op1
, dc
->op2
));
1080 cris_cc_mask(dc
, CC_MASK_NZV
);
1081 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1);
1082 t_gen_sext(cpu_T
[0], cpu_T
[0], size
);
1083 crisv32_alu_op(dc
, CC_OP_MULS
, dc
->op2
, 4);
1087 static unsigned int dec_mulu_r(DisasContext
*dc
)
1089 int size
= memsize_zz(dc
);
1091 DIS(fprintf (logfile
, "mulu.%c $r%u, $r%u\n",
1092 memsize_char(size
), dc
->op1
, dc
->op2
));
1093 cris_cc_mask(dc
, CC_MASK_NZV
);
1094 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1095 t_gen_zext(cpu_T
[0], cpu_T
[0], size
);
1096 crisv32_alu_op(dc
, CC_OP_MULU
, dc
->op2
, 4);
1101 static unsigned int dec_dstep_r(DisasContext
*dc
)
1103 DIS(fprintf (logfile
, "dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
));
1104 cris_cc_mask(dc
, CC_MASK_NZ
);
1105 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1106 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1107 crisv32_alu_op(dc
, CC_OP_DSTEP
, dc
->op2
, 4);
1111 static unsigned int dec_xor_r(DisasContext
*dc
)
1113 int size
= memsize_zz(dc
);
1114 DIS(fprintf (logfile
, "xor.%c $r%u, $r%u\n",
1115 memsize_char(size
), dc
->op1
, dc
->op2
));
1116 BUG_ON(size
!= 4); /* xor is dword. */
1117 cris_cc_mask(dc
, CC_MASK_NZ
);
1118 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1119 crisv32_alu_op(dc
, CC_OP_XOR
, dc
->op2
, 4);
1123 static unsigned int dec_bound_r(DisasContext
*dc
)
1125 int size
= memsize_zz(dc
);
1126 DIS(fprintf (logfile
, "bound.%c $r%u, $r%u\n",
1127 memsize_char(size
), dc
->op1
, dc
->op2
));
1128 cris_cc_mask(dc
, CC_MASK_NZ
);
1129 /* TODO: needs optmimization. */
1130 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1131 /* rd should be 4. */
1132 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1133 crisv32_alu_op(dc
, CC_OP_BOUND
, dc
->op2
, 4);
1137 static unsigned int dec_cmp_r(DisasContext
*dc
)
1139 int size
= memsize_zz(dc
);
1140 DIS(fprintf (logfile
, "cmp.%c $r%u, $r%u\n",
1141 memsize_char(size
), dc
->op1
, dc
->op2
));
1142 cris_cc_mask(dc
, CC_MASK_NZVC
);
1143 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1144 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, size
);
1148 static unsigned int dec_abs_r(DisasContext
*dc
)
1150 DIS(fprintf (logfile
, "abs $r%u, $r%u\n",
1152 cris_cc_mask(dc
, CC_MASK_NZ
);
1153 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1154 gen_op_absl_T1_T1();
1155 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1159 static unsigned int dec_add_r(DisasContext
*dc
)
1161 int size
= memsize_zz(dc
);
1162 DIS(fprintf (logfile
, "add.%c $r%u, $r%u\n",
1163 memsize_char(size
), dc
->op1
, dc
->op2
));
1164 cris_cc_mask(dc
, CC_MASK_NZVC
);
1165 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1166 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, size
);
1170 static unsigned int dec_addc_r(DisasContext
*dc
)
1172 DIS(fprintf (logfile
, "addc $r%u, $r%u\n",
1174 cris_evaluate_flags(dc
);
1175 cris_cc_mask(dc
, CC_MASK_NZVC
);
1176 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1177 crisv32_alu_op(dc
, CC_OP_ADDC
, dc
->op2
, 4);
1181 static unsigned int dec_mcp_r(DisasContext
*dc
)
1183 DIS(fprintf (logfile
, "mcp $p%u, $r%u\n",
1185 cris_evaluate_flags(dc
);
1186 cris_cc_mask(dc
, CC_MASK_RNZV
);
1187 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1188 t_gen_mov_TN_preg(cpu_T
[1], dc
->op2
);
1189 crisv32_alu_op(dc
, CC_OP_MCP
, dc
->op1
, 4);
1194 static char * swapmode_name(int mode
, char *modename
) {
1197 modename
[i
++] = 'n';
1199 modename
[i
++] = 'w';
1201 modename
[i
++] = 'b';
1203 modename
[i
++] = 'r';
1209 static unsigned int dec_swap_r(DisasContext
*dc
)
1211 DIS(char modename
[4]);
1212 DIS(fprintf (logfile
, "swap%s $r%u\n",
1213 swapmode_name(dc
->op2
, modename
), dc
->op1
));
1215 cris_cc_mask(dc
, CC_MASK_NZ
);
1216 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1220 gen_op_swapw_T0_T0();
1222 gen_op_swapb_T0_T0();
1224 gen_op_swapr_T0_T0();
1225 gen_op_movl_T1_T0();
1226 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, 4);
1230 static unsigned int dec_or_r(DisasContext
*dc
)
1232 int size
= memsize_zz(dc
);
1233 DIS(fprintf (logfile
, "or.%c $r%u, $r%u\n",
1234 memsize_char(size
), dc
->op1
, dc
->op2
));
1235 cris_cc_mask(dc
, CC_MASK_NZ
);
1236 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1237 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, size
);
1241 static unsigned int dec_addi_r(DisasContext
*dc
)
1243 DIS(fprintf (logfile
, "addi.%c $r%u, $r%u\n",
1244 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
));
1245 cris_cc_mask(dc
, 0);
1246 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1247 t_gen_lsl(cpu_T
[0], cpu_T
[0], tcg_const_i32(dc
->zzsize
));
1248 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1249 t_gen_mov_reg_TN(dc
->op1
, cpu_T
[0]);
1253 static unsigned int dec_addi_acr(DisasContext
*dc
)
1255 DIS(fprintf (logfile
, "addi.%c $r%u, $r%u, $acr\n",
1256 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
));
1257 cris_cc_mask(dc
, 0);
1258 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1259 t_gen_lsl(cpu_T
[0], cpu_T
[0], tcg_const_i32(dc
->zzsize
));
1261 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1262 t_gen_mov_reg_TN(R_ACR
, cpu_T
[0]);
1266 static unsigned int dec_neg_r(DisasContext
*dc
)
1268 int size
= memsize_zz(dc
);
1269 DIS(fprintf (logfile
, "neg.%c $r%u, $r%u\n",
1270 memsize_char(size
), dc
->op1
, dc
->op2
));
1271 cris_cc_mask(dc
, CC_MASK_NZVC
);
1272 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1273 crisv32_alu_op(dc
, CC_OP_NEG
, dc
->op2
, size
);
1277 static unsigned int dec_btst_r(DisasContext
*dc
)
1279 DIS(fprintf (logfile
, "btst $r%u, $r%u\n",
1281 cris_cc_mask(dc
, CC_MASK_NZ
);
1282 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1283 crisv32_alu_op(dc
, CC_OP_BTST
, dc
->op2
, 4);
1285 cris_update_cc_op(dc
, CC_OP_FLAGS
);
1286 gen_op_movl_flags_T0();
1291 static unsigned int dec_sub_r(DisasContext
*dc
)
1293 int size
= memsize_zz(dc
);
1294 DIS(fprintf (logfile
, "sub.%c $r%u, $r%u\n",
1295 memsize_char(size
), dc
->op1
, dc
->op2
));
1296 cris_cc_mask(dc
, CC_MASK_NZVC
);
1297 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1298 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, size
);
1302 /* Zero extension. From size to dword. */
1303 static unsigned int dec_movu_r(DisasContext
*dc
)
1305 int size
= memsize_z(dc
);
1306 DIS(fprintf (logfile
, "movu.%c $r%u, $r%u\n",
1310 cris_cc_mask(dc
, CC_MASK_NZ
);
1311 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1312 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1316 /* Sign extension. From size to dword. */
1317 static unsigned int dec_movs_r(DisasContext
*dc
)
1319 int size
= memsize_z(dc
);
1320 DIS(fprintf (logfile
, "movs.%c $r%u, $r%u\n",
1324 cris_cc_mask(dc
, CC_MASK_NZ
);
1325 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1326 /* Size can only be qi or hi. */
1327 t_gen_sext(cpu_T
[1], cpu_T
[0], size
);
1328 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1332 /* zero extension. From size to dword. */
1333 static unsigned int dec_addu_r(DisasContext
*dc
)
1335 int size
= memsize_z(dc
);
1336 DIS(fprintf (logfile
, "addu.%c $r%u, $r%u\n",
1340 cris_cc_mask(dc
, CC_MASK_NZVC
);
1341 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1342 /* Size can only be qi or hi. */
1343 t_gen_zext(cpu_T
[1], cpu_T
[1], size
);
1344 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1345 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1349 /* Sign extension. From size to dword. */
1350 static unsigned int dec_adds_r(DisasContext
*dc
)
1352 int size
= memsize_z(dc
);
1353 DIS(fprintf (logfile
, "adds.%c $r%u, $r%u\n",
1357 cris_cc_mask(dc
, CC_MASK_NZVC
);
1358 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1359 /* Size can only be qi or hi. */
1360 t_gen_sext(cpu_T
[1], cpu_T
[1], size
);
1361 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1363 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1367 /* Zero extension. From size to dword. */
1368 static unsigned int dec_subu_r(DisasContext
*dc
)
1370 int size
= memsize_z(dc
);
1371 DIS(fprintf (logfile
, "subu.%c $r%u, $r%u\n",
1375 cris_cc_mask(dc
, CC_MASK_NZVC
);
1376 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1377 /* Size can only be qi or hi. */
1378 t_gen_zext(cpu_T
[1], cpu_T
[1], size
);
1379 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1380 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1384 /* Sign extension. From size to dword. */
1385 static unsigned int dec_subs_r(DisasContext
*dc
)
1387 int size
= memsize_z(dc
);
1388 DIS(fprintf (logfile
, "subs.%c $r%u, $r%u\n",
1392 cris_cc_mask(dc
, CC_MASK_NZVC
);
1393 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1394 /* Size can only be qi or hi. */
1395 t_gen_sext(cpu_T
[1], cpu_T
[1], size
);
1396 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1397 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1401 static unsigned int dec_setclrf(DisasContext
*dc
)
1404 int set
= (~dc
->opcode
>> 2) & 1;
1406 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
1407 | EXTRACT_FIELD(dc
->ir
, 0, 3);
1408 DIS(fprintf (logfile
, "set=%d flags=%x\n", set
, flags
));
1409 if (set
&& flags
== 0)
1410 DIS(fprintf (logfile
, "nop\n"));
1411 else if (!set
&& (flags
& 0x20))
1412 DIS(fprintf (logfile
, "di\n"));
1414 DIS(fprintf (logfile
, "%sf %x\n",
1415 set
? "set" : "clr",
1418 if (set
&& (flags
& X_FLAG
)) {
1423 /* Simply decode the flags. */
1424 cris_evaluate_flags (dc
);
1425 cris_update_cc_op(dc
, CC_OP_FLAGS
);
1427 gen_op_setf (flags
);
1429 gen_op_clrf (flags
);
1434 static unsigned int dec_move_rs(DisasContext
*dc
)
1436 DIS(fprintf (logfile
, "move $r%u, $s%u\n", dc
->op1
, dc
->op2
));
1437 cris_cc_mask(dc
, 0);
1438 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1439 gen_op_movl_sreg_T0(dc
->op2
);
1441 #if !defined(CONFIG_USER_ONLY)
1443 gen_op_movl_tlb_hi_T0();
1444 else if (dc
->op2
== 5) { /* srs is checked at runtime. */
1445 tcg_gen_helper_0_1(helper_tlb_update
, cpu_T
[0]);
1446 gen_op_movl_tlb_lo_T0();
1451 static unsigned int dec_move_sr(DisasContext
*dc
)
1453 DIS(fprintf (logfile
, "move $s%u, $r%u\n", dc
->op2
, dc
->op1
));
1454 cris_cc_mask(dc
, 0);
1455 gen_op_movl_T0_sreg(dc
->op2
);
1456 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1457 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, 4);
1460 static unsigned int dec_move_rp(DisasContext
*dc
)
1462 DIS(fprintf (logfile
, "move $r%u, $p%u\n", dc
->op1
, dc
->op2
));
1463 cris_cc_mask(dc
, 0);
1464 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1465 t_gen_mov_preg_TN(dc
->op2
, cpu_T
[0]);
1468 static unsigned int dec_move_pr(DisasContext
*dc
)
1470 DIS(fprintf (logfile
, "move $p%u, $r%u\n", dc
->op1
, dc
->op2
));
1471 cris_cc_mask(dc
, 0);
1472 /* Support register 0 is hardwired to zero.
1473 Treat it specially. */
1475 tcg_gen_movi_tl(cpu_T
[1], 0);
1477 t_gen_mov_TN_preg(cpu_T
[1], dc
->op2
);
1478 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, preg_sizes
[dc
->op2
]);
1482 static unsigned int dec_move_mr(DisasContext
*dc
)
1484 int memsize
= memsize_zz(dc
);
1486 DIS(fprintf (logfile
, "move.%c [$r%u%s, $r%u\n",
1487 memsize_char(memsize
),
1488 dc
->op1
, dc
->postinc
? "+]" : "]",
1491 cris_cc_mask(dc
, CC_MASK_NZ
);
1492 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1493 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, memsize
);
1494 do_postinc(dc
, memsize
);
1498 static unsigned int dec_movs_m(DisasContext
*dc
)
1500 int memsize
= memsize_z(dc
);
1502 DIS(fprintf (logfile
, "movs.%c [$r%u%s, $r%u\n",
1503 memsize_char(memsize
),
1504 dc
->op1
, dc
->postinc
? "+]" : "]",
1508 cris_cc_mask(dc
, CC_MASK_NZ
);
1509 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1510 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1511 do_postinc(dc
, memsize
);
1515 static unsigned int dec_addu_m(DisasContext
*dc
)
1517 int memsize
= memsize_z(dc
);
1519 DIS(fprintf (logfile
, "addu.%c [$r%u%s, $r%u\n",
1520 memsize_char(memsize
),
1521 dc
->op1
, dc
->postinc
? "+]" : "]",
1525 cris_cc_mask(dc
, CC_MASK_NZVC
);
1526 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1527 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1528 do_postinc(dc
, memsize
);
1532 static unsigned int dec_adds_m(DisasContext
*dc
)
1534 int memsize
= memsize_z(dc
);
1536 DIS(fprintf (logfile
, "adds.%c [$r%u%s, $r%u\n",
1537 memsize_char(memsize
),
1538 dc
->op1
, dc
->postinc
? "+]" : "]",
1542 cris_cc_mask(dc
, CC_MASK_NZVC
);
1543 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1544 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1545 do_postinc(dc
, memsize
);
1549 static unsigned int dec_subu_m(DisasContext
*dc
)
1551 int memsize
= memsize_z(dc
);
1553 DIS(fprintf (logfile
, "subu.%c [$r%u%s, $r%u\n",
1554 memsize_char(memsize
),
1555 dc
->op1
, dc
->postinc
? "+]" : "]",
1559 cris_cc_mask(dc
, CC_MASK_NZVC
);
1560 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1561 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1562 do_postinc(dc
, memsize
);
1566 static unsigned int dec_subs_m(DisasContext
*dc
)
1568 int memsize
= memsize_z(dc
);
1570 DIS(fprintf (logfile
, "subs.%c [$r%u%s, $r%u\n",
1571 memsize_char(memsize
),
1572 dc
->op1
, dc
->postinc
? "+]" : "]",
1576 cris_cc_mask(dc
, CC_MASK_NZVC
);
1577 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1578 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1579 do_postinc(dc
, memsize
);
1583 static unsigned int dec_movu_m(DisasContext
*dc
)
1585 int memsize
= memsize_z(dc
);
1588 DIS(fprintf (logfile
, "movu.%c [$r%u%s, $r%u\n",
1589 memsize_char(memsize
),
1590 dc
->op1
, dc
->postinc
? "+]" : "]",
1593 cris_cc_mask(dc
, CC_MASK_NZ
);
1594 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1595 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1596 do_postinc(dc
, memsize
);
1600 static unsigned int dec_cmpu_m(DisasContext
*dc
)
1602 int memsize
= memsize_z(dc
);
1604 DIS(fprintf (logfile
, "cmpu.%c [$r%u%s, $r%u\n",
1605 memsize_char(memsize
),
1606 dc
->op1
, dc
->postinc
? "+]" : "]",
1609 cris_cc_mask(dc
, CC_MASK_NZVC
);
1610 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1611 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, 4);
1612 do_postinc(dc
, memsize
);
1616 static unsigned int dec_cmps_m(DisasContext
*dc
)
1618 int memsize
= memsize_z(dc
);
1620 DIS(fprintf (logfile
, "cmps.%c [$r%u%s, $r%u\n",
1621 memsize_char(memsize
),
1622 dc
->op1
, dc
->postinc
? "+]" : "]",
1625 cris_cc_mask(dc
, CC_MASK_NZVC
);
1626 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1627 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
1628 do_postinc(dc
, memsize
);
1632 static unsigned int dec_cmp_m(DisasContext
*dc
)
1634 int memsize
= memsize_zz(dc
);
1636 DIS(fprintf (logfile
, "cmp.%c [$r%u%s, $r%u\n",
1637 memsize_char(memsize
),
1638 dc
->op1
, dc
->postinc
? "+]" : "]",
1641 cris_cc_mask(dc
, CC_MASK_NZVC
);
1642 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1643 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
1644 do_postinc(dc
, memsize
);
1648 static unsigned int dec_test_m(DisasContext
*dc
)
1650 int memsize
= memsize_zz(dc
);
1652 DIS(fprintf (logfile
, "test.%d [$r%u%s] op2=%x\n",
1653 memsize_char(memsize
),
1654 dc
->op1
, dc
->postinc
? "+]" : "]",
1657 cris_cc_mask(dc
, CC_MASK_NZ
);
1659 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1660 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
1661 tcg_gen_movi_tl(cpu_T
[1], 0);
1662 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
1663 do_postinc(dc
, memsize
);
1667 static unsigned int dec_and_m(DisasContext
*dc
)
1669 int memsize
= memsize_zz(dc
);
1671 DIS(fprintf (logfile
, "and.%d [$r%u%s, $r%u\n",
1672 memsize_char(memsize
),
1673 dc
->op1
, dc
->postinc
? "+]" : "]",
1676 cris_cc_mask(dc
, CC_MASK_NZ
);
1677 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1678 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, memsize_zz(dc
));
1679 do_postinc(dc
, memsize
);
1683 static unsigned int dec_add_m(DisasContext
*dc
)
1685 int memsize
= memsize_zz(dc
);
1687 DIS(fprintf (logfile
, "add.%d [$r%u%s, $r%u\n",
1688 memsize_char(memsize
),
1689 dc
->op1
, dc
->postinc
? "+]" : "]",
1692 cris_cc_mask(dc
, CC_MASK_NZVC
);
1693 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1694 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, memsize_zz(dc
));
1695 do_postinc(dc
, memsize
);
1699 static unsigned int dec_addo_m(DisasContext
*dc
)
1701 int memsize
= memsize_zz(dc
);
1703 DIS(fprintf (logfile
, "add.%d [$r%u%s, $r%u\n",
1704 memsize_char(memsize
),
1705 dc
->op1
, dc
->postinc
? "+]" : "]",
1708 cris_cc_mask(dc
, 0);
1709 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
1710 crisv32_alu_op(dc
, CC_OP_ADD
, R_ACR
, 4);
1711 do_postinc(dc
, memsize
);
1715 static unsigned int dec_bound_m(DisasContext
*dc
)
1717 int memsize
= memsize_zz(dc
);
1719 DIS(fprintf (logfile
, "bound.%d [$r%u%s, $r%u\n",
1720 memsize_char(memsize
),
1721 dc
->op1
, dc
->postinc
? "+]" : "]",
1724 cris_cc_mask(dc
, CC_MASK_NZ
);
1725 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1726 crisv32_alu_op(dc
, CC_OP_BOUND
, dc
->op2
, 4);
1727 do_postinc(dc
, memsize
);
1731 static unsigned int dec_addc_mr(DisasContext
*dc
)
1734 DIS(fprintf (logfile
, "addc [$r%u%s, $r%u\n",
1735 dc
->op1
, dc
->postinc
? "+]" : "]",
1738 cris_evaluate_flags(dc
);
1739 cris_cc_mask(dc
, CC_MASK_NZVC
);
1740 insn_len
= dec_prep_alu_m(dc
, 0, 4);
1741 crisv32_alu_op(dc
, CC_OP_ADDC
, dc
->op2
, 4);
1746 static unsigned int dec_sub_m(DisasContext
*dc
)
1748 int memsize
= memsize_zz(dc
);
1750 DIS(fprintf (logfile
, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
1751 memsize_char(memsize
),
1752 dc
->op1
, dc
->postinc
? "+]" : "]",
1753 dc
->op2
, dc
->ir
, dc
->zzsize
));
1755 cris_cc_mask(dc
, CC_MASK_NZVC
);
1756 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1757 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, memsize
);
1758 do_postinc(dc
, memsize
);
1762 static unsigned int dec_or_m(DisasContext
*dc
)
1764 int memsize
= memsize_zz(dc
);
1766 DIS(fprintf (logfile
, "or.%d [$r%u%s, $r%u pc=%x\n",
1767 memsize_char(memsize
),
1768 dc
->op1
, dc
->postinc
? "+]" : "]",
1771 cris_cc_mask(dc
, CC_MASK_NZ
);
1772 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1773 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, memsize_zz(dc
));
1774 do_postinc(dc
, memsize
);
1778 static unsigned int dec_move_mp(DisasContext
*dc
)
1780 int memsize
= memsize_zz(dc
);
1783 DIS(fprintf (logfile
, "move.%c [$r%u%s, $p%u\n",
1784 memsize_char(memsize
),
1786 dc
->postinc
? "+]" : "]",
1789 cris_cc_mask(dc
, 0);
1790 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
1791 t_gen_mov_preg_TN(dc
->op2
, cpu_T
[1]);
1793 do_postinc(dc
, memsize
);
1797 static unsigned int dec_move_pm(DisasContext
*dc
)
1801 memsize
= preg_sizes
[dc
->op2
];
1803 DIS(fprintf (logfile
, "move.%c $p%u, [$r%u%s\n",
1804 memsize_char(memsize
),
1805 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]"));
1807 cris_cc_mask(dc
, 0);
1808 /* prepare store. Address in T0, value in T1. */
1809 t_gen_mov_TN_preg(cpu_T
[1], dc
->op2
);
1810 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1811 gen_store_T0_T1(dc
, memsize
);
1814 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], memsize
);
1815 t_gen_mov_reg_TN(dc
->op1
, cpu_T
[0]);
1820 static unsigned int dec_movem_mr(DisasContext
*dc
)
1824 DIS(fprintf (logfile
, "movem [$r%u%s, $r%u\n", dc
->op1
,
1825 dc
->postinc
? "+]" : "]", dc
->op2
));
1827 cris_cc_mask(dc
, 0);
1828 /* fetch the address into T0 and T1. */
1829 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1830 for (i
= 0; i
<= dc
->op2
; i
++) {
1831 /* Perform the load onto regnum i. Always dword wide. */
1832 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
1833 gen_load_T0_T0(dc
, 4, 0);
1834 t_gen_mov_reg_TN(i
, cpu_T
[0]);
1835 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 4);
1837 /* writeback the updated pointer value. */
1839 t_gen_mov_reg_TN(dc
->op1
, cpu_T
[1]);
1843 static unsigned int dec_movem_rm(DisasContext
*dc
)
1847 DIS(fprintf (logfile
, "movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
1848 dc
->postinc
? "+]" : "]"));
1850 cris_cc_mask(dc
, 0);
1851 for (i
= 0; i
<= dc
->op2
; i
++) {
1852 /* Fetch register i into T1. */
1853 t_gen_mov_TN_reg(cpu_T
[1], i
);
1854 /* Fetch the address into T0. */
1855 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1857 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], i
* 4);
1858 /* Perform the store. */
1859 gen_store_T0_T1(dc
, 4);
1862 /* T0 should point to the last written addr, advance one more
1864 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 4);
1865 /* writeback the updated pointer value. */
1866 t_gen_mov_reg_TN(dc
->op1
, cpu_T
[0]);
1871 static unsigned int dec_move_rm(DisasContext
*dc
)
1875 memsize
= memsize_zz(dc
);
1877 DIS(fprintf (logfile
, "move.%d $r%u, [$r%u]\n",
1878 memsize
, dc
->op2
, dc
->op1
));
1880 cris_cc_mask(dc
, 0);
1881 /* prepare store. */
1882 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1883 t_gen_mov_TN_reg(cpu_T
[1], dc
->op2
);
1884 gen_store_T0_T1(dc
, memsize
);
1887 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], memsize
);
1888 t_gen_mov_reg_TN(dc
->op1
, cpu_T
[0]);
1893 static unsigned int dec_lapcq(DisasContext
*dc
)
1895 DIS(fprintf (logfile
, "lapcq %x, $r%u\n",
1896 dc
->pc
+ dc
->op1
*2, dc
->op2
));
1897 cris_cc_mask(dc
, 0);
1898 tcg_gen_movi_tl(cpu_T
[1], dc
->pc
+ dc
->op1
* 2);
1899 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1903 static unsigned int dec_lapc_im(DisasContext
*dc
)
1910 cris_cc_mask(dc
, 0);
1911 imm
= ldl_code(dc
->pc
+ 2);
1912 DIS(fprintf (logfile
, "lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
));
1913 t_gen_mov_reg_TN(rd
, tcg_const_i32(dc
->pc
+ imm
));
1917 /* Jump to special reg. */
1918 static unsigned int dec_jump_p(DisasContext
*dc
)
1920 DIS(fprintf (logfile
, "jump $p%u\n", dc
->op2
));
1921 cris_cc_mask(dc
, 0);
1922 /* Store the return address in Pd. */
1923 t_gen_mov_TN_preg(cpu_T
[0], dc
->op2
);
1924 gen_op_movl_btarget_T0();
1925 cris_prepare_dyn_jmp(dc
);
1929 /* Jump and save. */
1930 static unsigned int dec_jas_r(DisasContext
*dc
)
1932 DIS(fprintf (logfile
, "jas $r%u, $p%u\n", dc
->op1
, dc
->op2
));
1933 cris_cc_mask(dc
, 0);
1934 /* Stor the return address in Pd. */
1935 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1936 gen_op_movl_btarget_T0();
1937 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 4);
1938 t_gen_mov_preg_TN(dc
->op2
, cpu_T
[0]);
1939 cris_prepare_dyn_jmp(dc
);
1943 static unsigned int dec_jas_im(DisasContext
*dc
)
1947 imm
= ldl_code(dc
->pc
+ 2);
1949 DIS(fprintf (logfile
, "jas 0x%x\n", imm
));
1950 cris_cc_mask(dc
, 0);
1951 /* Stor the return address in Pd. */
1952 tcg_gen_movi_tl(cpu_T
[0], imm
);
1953 gen_op_movl_btarget_T0();
1954 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 8);
1955 t_gen_mov_preg_TN(dc
->op2
, cpu_T
[0]);
1956 cris_prepare_dyn_jmp(dc
);
1960 static unsigned int dec_jasc_im(DisasContext
*dc
)
1964 imm
= ldl_code(dc
->pc
+ 2);
1966 DIS(fprintf (logfile
, "jasc 0x%x\n", imm
));
1967 cris_cc_mask(dc
, 0);
1968 /* Stor the return address in Pd. */
1969 tcg_gen_movi_tl(cpu_T
[0], imm
);
1970 gen_op_movl_btarget_T0();
1971 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 8 + 4);
1972 t_gen_mov_preg_TN(dc
->op2
, cpu_T
[0]);
1973 cris_prepare_dyn_jmp(dc
);
1977 static unsigned int dec_jasc_r(DisasContext
*dc
)
1979 DIS(fprintf (logfile
, "jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
));
1980 cris_cc_mask(dc
, 0);
1981 /* Stor the return address in Pd. */
1982 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1983 gen_op_movl_btarget_T0();
1984 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 4 + 4);
1985 t_gen_mov_preg_TN(dc
->op2
, cpu_T
[0]);
1986 cris_prepare_dyn_jmp(dc
);
1990 static unsigned int dec_bcc_im(DisasContext
*dc
)
1993 uint32_t cond
= dc
->op2
;
1995 offset
= ldl_code(dc
->pc
+ 2);
1996 offset
= sign_extend(offset
, 15);
1998 DIS(fprintf (logfile
, "b%s %d pc=%x dst=%x\n",
1999 cc_name(cond
), offset
,
2000 dc
->pc
, dc
->pc
+ offset
));
2002 cris_cc_mask(dc
, 0);
2003 /* op2 holds the condition-code. */
2004 cris_prepare_cc_branch (dc
, offset
, cond
);
2008 static unsigned int dec_bas_im(DisasContext
*dc
)
2013 simm
= ldl_code(dc
->pc
+ 2);
2015 DIS(fprintf (logfile
, "bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
));
2016 cris_cc_mask(dc
, 0);
2017 /* Stor the return address in Pd. */
2018 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ simm
);
2019 gen_op_movl_btarget_T0();
2020 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 8);
2021 t_gen_mov_preg_TN(dc
->op2
, cpu_T
[0]);
2022 cris_prepare_dyn_jmp(dc
);
2026 static unsigned int dec_basc_im(DisasContext
*dc
)
2029 simm
= ldl_code(dc
->pc
+ 2);
2031 DIS(fprintf (logfile
, "basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
));
2032 cris_cc_mask(dc
, 0);
2033 /* Stor the return address in Pd. */
2034 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ simm
);
2035 gen_op_movl_btarget_T0();
2036 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 12);
2037 t_gen_mov_preg_TN(dc
->op2
, cpu_T
[0]);
2038 cris_prepare_dyn_jmp(dc
);
2042 static unsigned int dec_rfe_etc(DisasContext
*dc
)
2044 DIS(fprintf (logfile
, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2045 dc
->opcode
, dc
->pc
, dc
->op1
, dc
->op2
));
2047 cris_cc_mask(dc
, 0);
2049 if (dc
->op2
== 15) /* ignore halt. */
2052 switch (dc
->op2
& 7) {
2055 cris_evaluate_flags(dc
);
2056 gen_op_ccs_rshift();
2064 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
);
2065 gen_op_movl_pc_T0();
2066 /* Breaks start at 16 in the exception vector. */
2067 gen_op_break_im(dc
->op1
+ 16);
2068 dc
->is_jmp
= DISAS_SWI
;
2071 printf ("op2=%x\n", dc
->op2
);
2079 static unsigned int dec_ftag_fidx_d_m(DisasContext
*dc
)
2081 /* Ignore D-cache flushes. */
2085 static unsigned int dec_ftag_fidx_i_m(DisasContext
*dc
)
2087 /* Ignore I-cache flushes. */
2091 static unsigned int dec_null(DisasContext
*dc
)
2093 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2094 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
2100 struct decoder_info
{
2105 unsigned int (*dec
)(DisasContext
*dc
);
2107 /* Order matters here. */
2108 {DEC_MOVEQ
, dec_moveq
},
2109 {DEC_BTSTQ
, dec_btstq
},
2110 {DEC_CMPQ
, dec_cmpq
},
2111 {DEC_ADDOQ
, dec_addoq
},
2112 {DEC_ADDQ
, dec_addq
},
2113 {DEC_SUBQ
, dec_subq
},
2114 {DEC_ANDQ
, dec_andq
},
2116 {DEC_ASRQ
, dec_asrq
},
2117 {DEC_LSLQ
, dec_lslq
},
2118 {DEC_LSRQ
, dec_lsrq
},
2119 {DEC_BCCQ
, dec_bccq
},
2121 {DEC_BCC_IM
, dec_bcc_im
},
2122 {DEC_JAS_IM
, dec_jas_im
},
2123 {DEC_JAS_R
, dec_jas_r
},
2124 {DEC_JASC_IM
, dec_jasc_im
},
2125 {DEC_JASC_R
, dec_jasc_r
},
2126 {DEC_BAS_IM
, dec_bas_im
},
2127 {DEC_BASC_IM
, dec_basc_im
},
2128 {DEC_JUMP_P
, dec_jump_p
},
2129 {DEC_LAPC_IM
, dec_lapc_im
},
2130 {DEC_LAPCQ
, dec_lapcq
},
2132 {DEC_RFE_ETC
, dec_rfe_etc
},
2133 {DEC_ADDC_MR
, dec_addc_mr
},
2135 {DEC_MOVE_MP
, dec_move_mp
},
2136 {DEC_MOVE_PM
, dec_move_pm
},
2137 {DEC_MOVEM_MR
, dec_movem_mr
},
2138 {DEC_MOVEM_RM
, dec_movem_rm
},
2139 {DEC_MOVE_PR
, dec_move_pr
},
2140 {DEC_SCC_R
, dec_scc_r
},
2141 {DEC_SETF
, dec_setclrf
},
2142 {DEC_CLEARF
, dec_setclrf
},
2144 {DEC_MOVE_SR
, dec_move_sr
},
2145 {DEC_MOVE_RP
, dec_move_rp
},
2146 {DEC_SWAP_R
, dec_swap_r
},
2147 {DEC_ABS_R
, dec_abs_r
},
2148 {DEC_LZ_R
, dec_lz_r
},
2149 {DEC_MOVE_RS
, dec_move_rs
},
2150 {DEC_BTST_R
, dec_btst_r
},
2151 {DEC_ADDC_R
, dec_addc_r
},
2153 {DEC_DSTEP_R
, dec_dstep_r
},
2154 {DEC_XOR_R
, dec_xor_r
},
2155 {DEC_MCP_R
, dec_mcp_r
},
2156 {DEC_CMP_R
, dec_cmp_r
},
2158 {DEC_ADDI_R
, dec_addi_r
},
2159 {DEC_ADDI_ACR
, dec_addi_acr
},
2161 {DEC_ADD_R
, dec_add_r
},
2162 {DEC_SUB_R
, dec_sub_r
},
2164 {DEC_ADDU_R
, dec_addu_r
},
2165 {DEC_ADDS_R
, dec_adds_r
},
2166 {DEC_SUBU_R
, dec_subu_r
},
2167 {DEC_SUBS_R
, dec_subs_r
},
2168 {DEC_LSL_R
, dec_lsl_r
},
2170 {DEC_AND_R
, dec_and_r
},
2171 {DEC_OR_R
, dec_or_r
},
2172 {DEC_BOUND_R
, dec_bound_r
},
2173 {DEC_ASR_R
, dec_asr_r
},
2174 {DEC_LSR_R
, dec_lsr_r
},
2176 {DEC_MOVU_R
, dec_movu_r
},
2177 {DEC_MOVS_R
, dec_movs_r
},
2178 {DEC_NEG_R
, dec_neg_r
},
2179 {DEC_MOVE_R
, dec_move_r
},
2181 {DEC_FTAG_FIDX_I_M
, dec_ftag_fidx_i_m
},
2182 {DEC_FTAG_FIDX_D_M
, dec_ftag_fidx_d_m
},
2184 {DEC_MULS_R
, dec_muls_r
},
2185 {DEC_MULU_R
, dec_mulu_r
},
2187 {DEC_ADDU_M
, dec_addu_m
},
2188 {DEC_ADDS_M
, dec_adds_m
},
2189 {DEC_SUBU_M
, dec_subu_m
},
2190 {DEC_SUBS_M
, dec_subs_m
},
2192 {DEC_CMPU_M
, dec_cmpu_m
},
2193 {DEC_CMPS_M
, dec_cmps_m
},
2194 {DEC_MOVU_M
, dec_movu_m
},
2195 {DEC_MOVS_M
, dec_movs_m
},
2197 {DEC_CMP_M
, dec_cmp_m
},
2198 {DEC_ADDO_M
, dec_addo_m
},
2199 {DEC_BOUND_M
, dec_bound_m
},
2200 {DEC_ADD_M
, dec_add_m
},
2201 {DEC_SUB_M
, dec_sub_m
},
2202 {DEC_AND_M
, dec_and_m
},
2203 {DEC_OR_M
, dec_or_m
},
2204 {DEC_MOVE_RM
, dec_move_rm
},
2205 {DEC_TEST_M
, dec_test_m
},
2206 {DEC_MOVE_MR
, dec_move_mr
},
2211 static inline unsigned int
2212 cris_decoder(DisasContext
*dc
)
2214 unsigned int insn_len
= 2;
2218 /* Load a halfword onto the instruction register. */
2219 tmp
= ldl_code(dc
->pc
);
2220 dc
->ir
= tmp
& 0xffff;
2222 /* Now decode it. */
2223 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
2224 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
2225 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
2226 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
2227 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
2228 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
2230 /* Large switch for all insns. */
2231 for (i
= 0; i
< sizeof decinfo
/ sizeof decinfo
[0]; i
++) {
2232 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
)
2234 insn_len
= decinfo
[i
].dec(dc
);
2242 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
2245 if (env
->nb_breakpoints
> 0) {
2246 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
2247 if (env
->breakpoints
[j
] == dc
->pc
) {
2248 cris_evaluate_flags (dc
);
2249 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
);
2250 gen_op_movl_pc_T0();
2252 dc
->is_jmp
= DISAS_UPDATE
;
2258 /* generate intermediate code for basic block 'tb'. */
2259 struct DisasContext ctx
;
2261 gen_intermediate_code_internal(CPUState
*env
, TranslationBlock
*tb
,
2264 uint16_t *gen_opc_end
;
2266 unsigned int insn_len
;
2268 struct DisasContext
*dc
= &ctx
;
2269 uint32_t next_page_start
;
2275 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2277 dc
->is_jmp
= DISAS_NEXT
;
2279 dc
->singlestep_enabled
= env
->singlestep_enabled
;
2282 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2286 check_breakpoint(env
, dc
);
2287 if (dc
->is_jmp
== DISAS_JUMP
2288 || dc
->is_jmp
== DISAS_SWI
)
2292 j
= gen_opc_ptr
- gen_opc_buf
;
2296 gen_opc_instr_start
[lj
++] = 0;
2298 gen_opc_pc
[lj
] = dc
->pc
;
2299 gen_opc_instr_start
[lj
] = 1;
2302 insn_len
= cris_decoder(dc
);
2303 STATS(gen_op_exec_insn());
2306 || (dc
->flagx_live
&&
2307 !(dc
->cc_op
== CC_OP_FLAGS
&& dc
->flags_x
))) {
2308 cris_clear_x_flag(dc
);
2311 /* Check for delayed branches here. If we do it before
2312 actually genereating any host code, the simulator will just
2313 loop doing nothing for on this program location. */
2314 if (dc
->delayed_branch
) {
2315 dc
->delayed_branch
--;
2316 if (dc
->delayed_branch
== 0)
2318 if (dc
->bcc
== CC_A
) {
2320 dc
->is_jmp
= DISAS_UPDATE
;
2323 /* Conditional jmp. */
2324 gen_op_cc_jmp (dc
->delayed_pc
, dc
->pc
);
2325 dc
->is_jmp
= DISAS_UPDATE
;
2330 if (env
->singlestep_enabled
)
2332 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
2333 && dc
->pc
< next_page_start
);
2336 gen_op_movl_T0_im((long)dc
->pc
);
2337 gen_op_movl_pc_T0();
2340 cris_evaluate_flags (dc
);
2342 if (__builtin_expect(env
->singlestep_enabled
, 0)) {
2345 switch(dc
->is_jmp
) {
2347 gen_goto_tb(dc
, 1, dc
->pc
);
2352 /* indicate that the hash table must be used
2353 to find the next TB */
2358 /* nothing more to generate */
2362 *gen_opc_ptr
= INDEX_op_end
;
2364 j
= gen_opc_ptr
- gen_opc_buf
;
2367 gen_opc_instr_start
[lj
++] = 0;
2369 tb
->size
= dc
->pc
- pc_start
;
2373 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2374 fprintf(logfile
, "--------------\n");
2375 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2376 target_disas(logfile
, pc_start
, dc
->pc
+ 4 - pc_start
, 0);
2377 fprintf(logfile
, "\n");
2383 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2385 return gen_intermediate_code_internal(env
, tb
, 0);
2388 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2390 return gen_intermediate_code_internal(env
, tb
, 1);
2393 void cpu_dump_state (CPUState
*env
, FILE *f
,
2394 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
2403 cpu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2404 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2406 env
->pc
, env
->pregs
[PR_CCS
], env
->btaken
, env
->btarget
,
2408 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
,
2409 env
->debug1
, env
->debug2
, env
->debug3
);
2411 for (i
= 0; i
< 16; i
++) {
2412 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
2413 if ((i
+ 1) % 4 == 0)
2414 cpu_fprintf(f
, "\n");
2416 cpu_fprintf(f
, "\nspecial regs:\n");
2417 for (i
= 0; i
< 16; i
++) {
2418 cpu_fprintf(f
, "p%2.2d=%8.8x ", i
, env
->pregs
[i
]);
2419 if ((i
+ 1) % 4 == 0)
2420 cpu_fprintf(f
, "\n");
2422 srs
= env
->pregs
[PR_SRS
];
2423 cpu_fprintf(f
, "\nsupport function regs bank %d:\n", srs
);
2425 for (i
= 0; i
< 16; i
++) {
2426 cpu_fprintf(f
, "s%2.2d=%8.8x ",
2427 i
, env
->sregs
[srs
][i
]);
2428 if ((i
+ 1) % 4 == 0)
2429 cpu_fprintf(f
, "\n");
2432 cpu_fprintf(f
, "\n\n");
2436 static void tcg_macro_func(TCGContext
*s
, int macro_id
, const int *dead_args
)
2440 CPUCRISState
*cpu_cris_init (const char *cpu_model
)
2444 env
= qemu_mallocz(sizeof(CPUCRISState
));
2449 tcg_set_macro_func(&tcg_ctx
, tcg_macro_func
);
2450 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
2451 #if TARGET_LONG_BITS > HOST_LONG_BITS
2452 cpu_T
[0] = tcg_global_mem_new(TCG_TYPE_TL
,
2453 TCG_AREG0
, offsetof(CPUState
, t0
), "T0");
2454 cpu_T
[1] = tcg_global_mem_new(TCG_TYPE_TL
,
2455 TCG_AREG0
, offsetof(CPUState
, t1
), "T1");
2457 cpu_T
[0] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG1
, "T0");
2458 cpu_T
[1] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG2
, "T1");
2465 void cpu_reset (CPUCRISState
*env
)
2467 memset(env
, 0, offsetof(CPUCRISState
, breakpoints
));