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Merge remote branch 'mst/for_anthony' into staging
[mirror_qemu.git] / target-cris / translate.c
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include <stdarg.h>
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <string.h>
30 #include <inttypes.h>
31
32 #include "cpu.h"
33 #include "exec-all.h"
34 #include "disas.h"
35 #include "tcg-op.h"
36 #include "helper.h"
37 #include "mmu.h"
38 #include "crisv32-decode.h"
39 #include "qemu-common.h"
40
41 #define GEN_HELPER 1
42 #include "helper.h"
43
44 #define DISAS_CRIS 0
45 #if DISAS_CRIS
46 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DIS(...) do { } while (0)
49 #endif
50
51 #define D(x)
52 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
53 #define BUG_ON(x) ({if (x) BUG();})
54
55 #define DISAS_SWI 5
56
57 /* Used by the decoder. */
58 #define EXTRACT_FIELD(src, start, end) \
59 (((src) >> start) & ((1 << (end - start + 1)) - 1))
60
61 #define CC_MASK_NZ 0xc
62 #define CC_MASK_NZV 0xe
63 #define CC_MASK_NZVC 0xf
64 #define CC_MASK_RNZV 0x10e
65
66 static TCGv_ptr cpu_env;
67 static TCGv cpu_R[16];
68 static TCGv cpu_PR[16];
69 static TCGv cc_x;
70 static TCGv cc_src;
71 static TCGv cc_dest;
72 static TCGv cc_result;
73 static TCGv cc_op;
74 static TCGv cc_size;
75 static TCGv cc_mask;
76
77 static TCGv env_btaken;
78 static TCGv env_btarget;
79 static TCGv env_pc;
80
81 #include "gen-icount.h"
82
83 /* This is the state at translation time. */
84 typedef struct DisasContext {
85 CPUState *env;
86 target_ulong pc, ppc;
87
88 /* Decoder. */
89 unsigned int (*decoder)(struct DisasContext *dc);
90 uint32_t ir;
91 uint32_t opcode;
92 unsigned int op1;
93 unsigned int op2;
94 unsigned int zsize, zzsize;
95 unsigned int mode;
96 unsigned int postinc;
97
98 unsigned int size;
99 unsigned int src;
100 unsigned int dst;
101 unsigned int cond;
102
103 int update_cc;
104 int cc_op;
105 int cc_size;
106 uint32_t cc_mask;
107
108 int cc_size_uptodate; /* -1 invalid or last written value. */
109
110 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
111 int flags_uptodate; /* Wether or not $ccs is uptodate. */
112 int flagx_known; /* Wether or not flags_x has the x flag known at
113 translation time. */
114 int flags_x;
115
116 int clear_x; /* Clear x after this insn? */
117 int clear_prefix; /* Clear prefix after this insn? */
118 int clear_locked_irq; /* Clear the irq lockout. */
119 int cpustate_changed;
120 unsigned int tb_flags; /* tb dependent flags. */
121 int is_jmp;
122
123 #define JMP_NOJMP 0
124 #define JMP_DIRECT 1
125 #define JMP_INDIRECT 2
126 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
127 uint32_t jmp_pc;
128
129 int delayed_branch;
130
131 struct TranslationBlock *tb;
132 int singlestep_enabled;
133 } DisasContext;
134
135 static void gen_BUG(DisasContext *dc, const char *file, int line)
136 {
137 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
138 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
139 cpu_abort(dc->env, "%s:%d\n", file, line);
140 }
141
142 static const char *regnames[] =
143 {
144 "$r0", "$r1", "$r2", "$r3",
145 "$r4", "$r5", "$r6", "$r7",
146 "$r8", "$r9", "$r10", "$r11",
147 "$r12", "$r13", "$sp", "$acr",
148 };
149 static const char *pregnames[] =
150 {
151 "$bz", "$vr", "$pid", "$srs",
152 "$wz", "$exs", "$eda", "$mof",
153 "$dz", "$ebp", "$erp", "$srp",
154 "$nrp", "$ccs", "$usp", "$spc",
155 };
156
157 /* We need this table to handle preg-moves with implicit width. */
158 static int preg_sizes[] = {
159 1, /* bz. */
160 1, /* vr. */
161 4, /* pid. */
162 1, /* srs. */
163 2, /* wz. */
164 4, 4, 4,
165 4, 4, 4, 4,
166 4, 4, 4, 4,
167 };
168
169 #define t_gen_mov_TN_env(tn, member) \
170 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
171 #define t_gen_mov_env_TN(member, tn) \
172 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
173
174 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
175 {
176 if (r < 0 || r > 15)
177 fprintf(stderr, "wrong register read $r%d\n", r);
178 tcg_gen_mov_tl(tn, cpu_R[r]);
179 }
180 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
181 {
182 if (r < 0 || r > 15)
183 fprintf(stderr, "wrong register write $r%d\n", r);
184 tcg_gen_mov_tl(cpu_R[r], tn);
185 }
186
187 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
188 {
189 if (offset > sizeof (CPUState))
190 fprintf(stderr, "wrong load from env from off=%d\n", offset);
191 tcg_gen_ld_tl(tn, cpu_env, offset);
192 }
193 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
194 {
195 if (offset > sizeof (CPUState))
196 fprintf(stderr, "wrong store to env at off=%d\n", offset);
197 tcg_gen_st_tl(tn, cpu_env, offset);
198 }
199
200 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
201 {
202 if (r < 0 || r > 15)
203 fprintf(stderr, "wrong register read $p%d\n", r);
204 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
205 tcg_gen_mov_tl(tn, tcg_const_tl(0));
206 else if (r == PR_VR)
207 tcg_gen_mov_tl(tn, tcg_const_tl(32));
208 else
209 tcg_gen_mov_tl(tn, cpu_PR[r]);
210 }
211 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
212 {
213 if (r < 0 || r > 15)
214 fprintf(stderr, "wrong register write $p%d\n", r);
215 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
216 return;
217 else if (r == PR_SRS)
218 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
219 else {
220 if (r == PR_PID)
221 gen_helper_tlb_flush_pid(tn);
222 if (dc->tb_flags & S_FLAG && r == PR_SPC)
223 gen_helper_spc_write(tn);
224 else if (r == PR_CCS)
225 dc->cpustate_changed = 1;
226 tcg_gen_mov_tl(cpu_PR[r], tn);
227 }
228 }
229
230 /* Sign extend at translation time. */
231 static int sign_extend(unsigned int val, unsigned int width)
232 {
233 int sval;
234
235 /* LSL. */
236 val <<= 31 - width;
237 sval = val;
238 /* ASR. */
239 sval >>= 31 - width;
240 return sval;
241 }
242
243 static int cris_fetch(DisasContext *dc, uint32_t addr,
244 unsigned int size, unsigned int sign)
245 {
246 int r;
247
248 switch (size) {
249 case 4:
250 {
251 r = ldl_code(addr);
252 break;
253 }
254 case 2:
255 {
256 if (sign) {
257 r = ldsw_code(addr);
258 } else {
259 r = lduw_code(addr);
260 }
261 break;
262 }
263 case 1:
264 {
265 if (sign) {
266 r = ldsb_code(addr);
267 } else {
268 r = ldub_code(addr);
269 }
270 break;
271 }
272 default:
273 cpu_abort(dc->env, "Invalid fetch size %d\n", size);
274 break;
275 }
276 return r;
277 }
278
279 static void cris_lock_irq(DisasContext *dc)
280 {
281 dc->clear_locked_irq = 0;
282 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
283 }
284
285 static inline void t_gen_raise_exception(uint32_t index)
286 {
287 TCGv_i32 tmp = tcg_const_i32(index);
288 gen_helper_raise_exception(tmp);
289 tcg_temp_free_i32(tmp);
290 }
291
292 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
293 {
294 TCGv t0, t_31;
295
296 t0 = tcg_temp_new();
297 t_31 = tcg_const_tl(31);
298 tcg_gen_shl_tl(d, a, b);
299
300 tcg_gen_sub_tl(t0, t_31, b);
301 tcg_gen_sar_tl(t0, t0, t_31);
302 tcg_gen_and_tl(t0, t0, d);
303 tcg_gen_xor_tl(d, d, t0);
304 tcg_temp_free(t0);
305 tcg_temp_free(t_31);
306 }
307
308 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
309 {
310 TCGv t0, t_31;
311
312 t0 = tcg_temp_new();
313 t_31 = tcg_temp_new();
314 tcg_gen_shr_tl(d, a, b);
315
316 tcg_gen_movi_tl(t_31, 31);
317 tcg_gen_sub_tl(t0, t_31, b);
318 tcg_gen_sar_tl(t0, t0, t_31);
319 tcg_gen_and_tl(t0, t0, d);
320 tcg_gen_xor_tl(d, d, t0);
321 tcg_temp_free(t0);
322 tcg_temp_free(t_31);
323 }
324
325 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
326 {
327 TCGv t0, t_31;
328
329 t0 = tcg_temp_new();
330 t_31 = tcg_temp_new();
331 tcg_gen_sar_tl(d, a, b);
332
333 tcg_gen_movi_tl(t_31, 31);
334 tcg_gen_sub_tl(t0, t_31, b);
335 tcg_gen_sar_tl(t0, t0, t_31);
336 tcg_gen_or_tl(d, d, t0);
337 tcg_temp_free(t0);
338 tcg_temp_free(t_31);
339 }
340
341 /* 64-bit signed mul, lower result in d and upper in d2. */
342 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
343 {
344 TCGv_i64 t0, t1;
345
346 t0 = tcg_temp_new_i64();
347 t1 = tcg_temp_new_i64();
348
349 tcg_gen_ext_i32_i64(t0, a);
350 tcg_gen_ext_i32_i64(t1, b);
351 tcg_gen_mul_i64(t0, t0, t1);
352
353 tcg_gen_trunc_i64_i32(d, t0);
354 tcg_gen_shri_i64(t0, t0, 32);
355 tcg_gen_trunc_i64_i32(d2, t0);
356
357 tcg_temp_free_i64(t0);
358 tcg_temp_free_i64(t1);
359 }
360
361 /* 64-bit unsigned muls, lower result in d and upper in d2. */
362 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
363 {
364 TCGv_i64 t0, t1;
365
366 t0 = tcg_temp_new_i64();
367 t1 = tcg_temp_new_i64();
368
369 tcg_gen_extu_i32_i64(t0, a);
370 tcg_gen_extu_i32_i64(t1, b);
371 tcg_gen_mul_i64(t0, t0, t1);
372
373 tcg_gen_trunc_i64_i32(d, t0);
374 tcg_gen_shri_i64(t0, t0, 32);
375 tcg_gen_trunc_i64_i32(d2, t0);
376
377 tcg_temp_free_i64(t0);
378 tcg_temp_free_i64(t1);
379 }
380
381 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
382 {
383 int l1;
384
385 l1 = gen_new_label();
386
387 /*
388 * d <<= 1
389 * if (d >= s)
390 * d -= s;
391 */
392 tcg_gen_shli_tl(d, a, 1);
393 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
394 tcg_gen_sub_tl(d, d, b);
395 gen_set_label(l1);
396 }
397
398 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
399 {
400 TCGv t;
401
402 /*
403 * d <<= 1
404 * if (n)
405 * d += s;
406 */
407 t = tcg_temp_new();
408 tcg_gen_shli_tl(d, a, 1);
409 tcg_gen_shli_tl(t, ccs, 31 - 3);
410 tcg_gen_sari_tl(t, t, 31);
411 tcg_gen_and_tl(t, t, b);
412 tcg_gen_add_tl(d, d, t);
413 tcg_temp_free(t);
414 }
415
416 /* Extended arithmetics on CRIS. */
417 static inline void t_gen_add_flag(TCGv d, int flag)
418 {
419 TCGv c;
420
421 c = tcg_temp_new();
422 t_gen_mov_TN_preg(c, PR_CCS);
423 /* Propagate carry into d. */
424 tcg_gen_andi_tl(c, c, 1 << flag);
425 if (flag)
426 tcg_gen_shri_tl(c, c, flag);
427 tcg_gen_add_tl(d, d, c);
428 tcg_temp_free(c);
429 }
430
431 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
432 {
433 if (dc->flagx_known) {
434 if (dc->flags_x) {
435 TCGv c;
436
437 c = tcg_temp_new();
438 t_gen_mov_TN_preg(c, PR_CCS);
439 /* C flag is already at bit 0. */
440 tcg_gen_andi_tl(c, c, C_FLAG);
441 tcg_gen_add_tl(d, d, c);
442 tcg_temp_free(c);
443 }
444 } else {
445 TCGv x, c;
446
447 x = tcg_temp_new();
448 c = tcg_temp_new();
449 t_gen_mov_TN_preg(x, PR_CCS);
450 tcg_gen_mov_tl(c, x);
451
452 /* Propagate carry into d if X is set. Branch free. */
453 tcg_gen_andi_tl(c, c, C_FLAG);
454 tcg_gen_andi_tl(x, x, X_FLAG);
455 tcg_gen_shri_tl(x, x, 4);
456
457 tcg_gen_and_tl(x, x, c);
458 tcg_gen_add_tl(d, d, x);
459 tcg_temp_free(x);
460 tcg_temp_free(c);
461 }
462 }
463
464 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
465 {
466 if (dc->flagx_known) {
467 if (dc->flags_x) {
468 TCGv c;
469
470 c = tcg_temp_new();
471 t_gen_mov_TN_preg(c, PR_CCS);
472 /* C flag is already at bit 0. */
473 tcg_gen_andi_tl(c, c, C_FLAG);
474 tcg_gen_sub_tl(d, d, c);
475 tcg_temp_free(c);
476 }
477 } else {
478 TCGv x, c;
479
480 x = tcg_temp_new();
481 c = tcg_temp_new();
482 t_gen_mov_TN_preg(x, PR_CCS);
483 tcg_gen_mov_tl(c, x);
484
485 /* Propagate carry into d if X is set. Branch free. */
486 tcg_gen_andi_tl(c, c, C_FLAG);
487 tcg_gen_andi_tl(x, x, X_FLAG);
488 tcg_gen_shri_tl(x, x, 4);
489
490 tcg_gen_and_tl(x, x, c);
491 tcg_gen_sub_tl(d, d, x);
492 tcg_temp_free(x);
493 tcg_temp_free(c);
494 }
495 }
496
497 /* Swap the two bytes within each half word of the s operand.
498 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
499 static inline void t_gen_swapb(TCGv d, TCGv s)
500 {
501 TCGv t, org_s;
502
503 t = tcg_temp_new();
504 org_s = tcg_temp_new();
505
506 /* d and s may refer to the same object. */
507 tcg_gen_mov_tl(org_s, s);
508 tcg_gen_shli_tl(t, org_s, 8);
509 tcg_gen_andi_tl(d, t, 0xff00ff00);
510 tcg_gen_shri_tl(t, org_s, 8);
511 tcg_gen_andi_tl(t, t, 0x00ff00ff);
512 tcg_gen_or_tl(d, d, t);
513 tcg_temp_free(t);
514 tcg_temp_free(org_s);
515 }
516
517 /* Swap the halfwords of the s operand. */
518 static inline void t_gen_swapw(TCGv d, TCGv s)
519 {
520 TCGv t;
521 /* d and s refer the same object. */
522 t = tcg_temp_new();
523 tcg_gen_mov_tl(t, s);
524 tcg_gen_shli_tl(d, t, 16);
525 tcg_gen_shri_tl(t, t, 16);
526 tcg_gen_or_tl(d, d, t);
527 tcg_temp_free(t);
528 }
529
530 /* Reverse the within each byte.
531 T0 = (((T0 << 7) & 0x80808080) |
532 ((T0 << 5) & 0x40404040) |
533 ((T0 << 3) & 0x20202020) |
534 ((T0 << 1) & 0x10101010) |
535 ((T0 >> 1) & 0x08080808) |
536 ((T0 >> 3) & 0x04040404) |
537 ((T0 >> 5) & 0x02020202) |
538 ((T0 >> 7) & 0x01010101));
539 */
540 static inline void t_gen_swapr(TCGv d, TCGv s)
541 {
542 struct {
543 int shift; /* LSL when positive, LSR when negative. */
544 uint32_t mask;
545 } bitrev [] = {
546 {7, 0x80808080},
547 {5, 0x40404040},
548 {3, 0x20202020},
549 {1, 0x10101010},
550 {-1, 0x08080808},
551 {-3, 0x04040404},
552 {-5, 0x02020202},
553 {-7, 0x01010101}
554 };
555 int i;
556 TCGv t, org_s;
557
558 /* d and s refer the same object. */
559 t = tcg_temp_new();
560 org_s = tcg_temp_new();
561 tcg_gen_mov_tl(org_s, s);
562
563 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
564 tcg_gen_andi_tl(d, t, bitrev[0].mask);
565 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
566 if (bitrev[i].shift >= 0) {
567 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
568 } else {
569 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
570 }
571 tcg_gen_andi_tl(t, t, bitrev[i].mask);
572 tcg_gen_or_tl(d, d, t);
573 }
574 tcg_temp_free(t);
575 tcg_temp_free(org_s);
576 }
577
578 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
579 {
580 int l1;
581
582 l1 = gen_new_label();
583
584 /* Conditional jmp. */
585 tcg_gen_mov_tl(env_pc, pc_false);
586 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
587 tcg_gen_mov_tl(env_pc, pc_true);
588 gen_set_label(l1);
589 }
590
591 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
592 {
593 TranslationBlock *tb;
594 tb = dc->tb;
595 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
596 tcg_gen_goto_tb(n);
597 tcg_gen_movi_tl(env_pc, dest);
598 tcg_gen_exit_tb((long)tb + n);
599 } else {
600 tcg_gen_movi_tl(env_pc, dest);
601 tcg_gen_exit_tb(0);
602 }
603 }
604
605 static inline void cris_clear_x_flag(DisasContext *dc)
606 {
607 if (dc->flagx_known && dc->flags_x)
608 dc->flags_uptodate = 0;
609
610 dc->flagx_known = 1;
611 dc->flags_x = 0;
612 }
613
614 static void cris_flush_cc_state(DisasContext *dc)
615 {
616 if (dc->cc_size_uptodate != dc->cc_size) {
617 tcg_gen_movi_tl(cc_size, dc->cc_size);
618 dc->cc_size_uptodate = dc->cc_size;
619 }
620 tcg_gen_movi_tl(cc_op, dc->cc_op);
621 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
622 }
623
624 static void cris_evaluate_flags(DisasContext *dc)
625 {
626 if (dc->flags_uptodate)
627 return;
628
629 cris_flush_cc_state(dc);
630
631 switch (dc->cc_op)
632 {
633 case CC_OP_MCP:
634 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
635 cpu_PR[PR_CCS], cc_src,
636 cc_dest, cc_result);
637 break;
638 case CC_OP_MULS:
639 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
640 cpu_PR[PR_CCS], cc_result,
641 cpu_PR[PR_MOF]);
642 break;
643 case CC_OP_MULU:
644 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
645 cpu_PR[PR_CCS], cc_result,
646 cpu_PR[PR_MOF]);
647 break;
648 case CC_OP_MOVE:
649 case CC_OP_AND:
650 case CC_OP_OR:
651 case CC_OP_XOR:
652 case CC_OP_ASR:
653 case CC_OP_LSR:
654 case CC_OP_LSL:
655 switch (dc->cc_size)
656 {
657 case 4:
658 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
659 cpu_PR[PR_CCS], cc_result);
660 break;
661 case 2:
662 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
663 cpu_PR[PR_CCS], cc_result);
664 break;
665 default:
666 gen_helper_evaluate_flags();
667 break;
668 }
669 break;
670 case CC_OP_FLAGS:
671 /* live. */
672 break;
673 case CC_OP_SUB:
674 case CC_OP_CMP:
675 if (dc->cc_size == 4)
676 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
677 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
678 else
679 gen_helper_evaluate_flags();
680
681 break;
682 default:
683 switch (dc->cc_size)
684 {
685 case 4:
686 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
687 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
688 break;
689 default:
690 gen_helper_evaluate_flags();
691 break;
692 }
693 break;
694 }
695
696 if (dc->flagx_known) {
697 if (dc->flags_x)
698 tcg_gen_ori_tl(cpu_PR[PR_CCS],
699 cpu_PR[PR_CCS], X_FLAG);
700 else if (dc->cc_op == CC_OP_FLAGS)
701 tcg_gen_andi_tl(cpu_PR[PR_CCS],
702 cpu_PR[PR_CCS], ~X_FLAG);
703 }
704 dc->flags_uptodate = 1;
705 }
706
707 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
708 {
709 uint32_t ovl;
710
711 if (!mask) {
712 dc->update_cc = 0;
713 return;
714 }
715
716 /* Check if we need to evaluate the condition codes due to
717 CC overlaying. */
718 ovl = (dc->cc_mask ^ mask) & ~mask;
719 if (ovl) {
720 /* TODO: optimize this case. It trigs all the time. */
721 cris_evaluate_flags (dc);
722 }
723 dc->cc_mask = mask;
724 dc->update_cc = 1;
725 }
726
727 static void cris_update_cc_op(DisasContext *dc, int op, int size)
728 {
729 dc->cc_op = op;
730 dc->cc_size = size;
731 dc->flags_uptodate = 0;
732 }
733
734 static inline void cris_update_cc_x(DisasContext *dc)
735 {
736 /* Save the x flag state at the time of the cc snapshot. */
737 if (dc->flagx_known) {
738 if (dc->cc_x_uptodate == (2 | dc->flags_x))
739 return;
740 tcg_gen_movi_tl(cc_x, dc->flags_x);
741 dc->cc_x_uptodate = 2 | dc->flags_x;
742 }
743 else {
744 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
745 dc->cc_x_uptodate = 1;
746 }
747 }
748
749 /* Update cc prior to executing ALU op. Needs source operands untouched. */
750 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
751 TCGv dst, TCGv src, int size)
752 {
753 if (dc->update_cc) {
754 cris_update_cc_op(dc, op, size);
755 tcg_gen_mov_tl(cc_src, src);
756
757 if (op != CC_OP_MOVE
758 && op != CC_OP_AND
759 && op != CC_OP_OR
760 && op != CC_OP_XOR
761 && op != CC_OP_ASR
762 && op != CC_OP_LSR
763 && op != CC_OP_LSL)
764 tcg_gen_mov_tl(cc_dest, dst);
765
766 cris_update_cc_x(dc);
767 }
768 }
769
770 /* Update cc after executing ALU op. needs the result. */
771 static inline void cris_update_result(DisasContext *dc, TCGv res)
772 {
773 if (dc->update_cc)
774 tcg_gen_mov_tl(cc_result, res);
775 }
776
777 /* Returns one if the write back stage should execute. */
778 static void cris_alu_op_exec(DisasContext *dc, int op,
779 TCGv dst, TCGv a, TCGv b, int size)
780 {
781 /* Emit the ALU insns. */
782 switch (op)
783 {
784 case CC_OP_ADD:
785 tcg_gen_add_tl(dst, a, b);
786 /* Extended arithmetics. */
787 t_gen_addx_carry(dc, dst);
788 break;
789 case CC_OP_ADDC:
790 tcg_gen_add_tl(dst, a, b);
791 t_gen_add_flag(dst, 0); /* C_FLAG. */
792 break;
793 case CC_OP_MCP:
794 tcg_gen_add_tl(dst, a, b);
795 t_gen_add_flag(dst, 8); /* R_FLAG. */
796 break;
797 case CC_OP_SUB:
798 tcg_gen_sub_tl(dst, a, b);
799 /* Extended arithmetics. */
800 t_gen_subx_carry(dc, dst);
801 break;
802 case CC_OP_MOVE:
803 tcg_gen_mov_tl(dst, b);
804 break;
805 case CC_OP_OR:
806 tcg_gen_or_tl(dst, a, b);
807 break;
808 case CC_OP_AND:
809 tcg_gen_and_tl(dst, a, b);
810 break;
811 case CC_OP_XOR:
812 tcg_gen_xor_tl(dst, a, b);
813 break;
814 case CC_OP_LSL:
815 t_gen_lsl(dst, a, b);
816 break;
817 case CC_OP_LSR:
818 t_gen_lsr(dst, a, b);
819 break;
820 case CC_OP_ASR:
821 t_gen_asr(dst, a, b);
822 break;
823 case CC_OP_NEG:
824 tcg_gen_neg_tl(dst, b);
825 /* Extended arithmetics. */
826 t_gen_subx_carry(dc, dst);
827 break;
828 case CC_OP_LZ:
829 gen_helper_lz(dst, b);
830 break;
831 case CC_OP_MULS:
832 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
833 break;
834 case CC_OP_MULU:
835 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
836 break;
837 case CC_OP_DSTEP:
838 t_gen_cris_dstep(dst, a, b);
839 break;
840 case CC_OP_MSTEP:
841 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
842 break;
843 case CC_OP_BOUND:
844 {
845 int l1;
846 l1 = gen_new_label();
847 tcg_gen_mov_tl(dst, a);
848 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
849 tcg_gen_mov_tl(dst, b);
850 gen_set_label(l1);
851 }
852 break;
853 case CC_OP_CMP:
854 tcg_gen_sub_tl(dst, a, b);
855 /* Extended arithmetics. */
856 t_gen_subx_carry(dc, dst);
857 break;
858 default:
859 qemu_log("illegal ALU op.\n");
860 BUG();
861 break;
862 }
863
864 if (size == 1)
865 tcg_gen_andi_tl(dst, dst, 0xff);
866 else if (size == 2)
867 tcg_gen_andi_tl(dst, dst, 0xffff);
868 }
869
870 static void cris_alu(DisasContext *dc, int op,
871 TCGv d, TCGv op_a, TCGv op_b, int size)
872 {
873 TCGv tmp;
874 int writeback;
875
876 writeback = 1;
877
878 if (op == CC_OP_CMP) {
879 tmp = tcg_temp_new();
880 writeback = 0;
881 } else if (size == 4) {
882 tmp = d;
883 writeback = 0;
884 } else
885 tmp = tcg_temp_new();
886
887
888 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
889 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
890 cris_update_result(dc, tmp);
891
892 /* Writeback. */
893 if (writeback) {
894 if (size == 1)
895 tcg_gen_andi_tl(d, d, ~0xff);
896 else
897 tcg_gen_andi_tl(d, d, ~0xffff);
898 tcg_gen_or_tl(d, d, tmp);
899 }
900 if (!TCGV_EQUAL(tmp, d))
901 tcg_temp_free(tmp);
902 }
903
904 static int arith_cc(DisasContext *dc)
905 {
906 if (dc->update_cc) {
907 switch (dc->cc_op) {
908 case CC_OP_ADDC: return 1;
909 case CC_OP_ADD: return 1;
910 case CC_OP_SUB: return 1;
911 case CC_OP_DSTEP: return 1;
912 case CC_OP_LSL: return 1;
913 case CC_OP_LSR: return 1;
914 case CC_OP_ASR: return 1;
915 case CC_OP_CMP: return 1;
916 case CC_OP_NEG: return 1;
917 case CC_OP_OR: return 1;
918 case CC_OP_AND: return 1;
919 case CC_OP_XOR: return 1;
920 case CC_OP_MULU: return 1;
921 case CC_OP_MULS: return 1;
922 default:
923 return 0;
924 }
925 }
926 return 0;
927 }
928
929 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
930 {
931 int arith_opt, move_opt;
932
933 /* TODO: optimize more condition codes. */
934
935 /*
936 * If the flags are live, we've gotta look into the bits of CCS.
937 * Otherwise, if we just did an arithmetic operation we try to
938 * evaluate the condition code faster.
939 *
940 * When this function is done, T0 should be non-zero if the condition
941 * code is true.
942 */
943 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
944 move_opt = (dc->cc_op == CC_OP_MOVE);
945 switch (cond) {
946 case CC_EQ:
947 if ((arith_opt || move_opt)
948 && dc->cc_x_uptodate != (2 | X_FLAG)) {
949 /* If cc_result is zero, T0 should be
950 non-zero otherwise T0 should be zero. */
951 int l1;
952 l1 = gen_new_label();
953 tcg_gen_movi_tl(cc, 0);
954 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
955 0, l1);
956 tcg_gen_movi_tl(cc, 1);
957 gen_set_label(l1);
958 }
959 else {
960 cris_evaluate_flags(dc);
961 tcg_gen_andi_tl(cc,
962 cpu_PR[PR_CCS], Z_FLAG);
963 }
964 break;
965 case CC_NE:
966 if ((arith_opt || move_opt)
967 && dc->cc_x_uptodate != (2 | X_FLAG)) {
968 tcg_gen_mov_tl(cc, cc_result);
969 } else {
970 cris_evaluate_flags(dc);
971 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
972 Z_FLAG);
973 tcg_gen_andi_tl(cc, cc, Z_FLAG);
974 }
975 break;
976 case CC_CS:
977 cris_evaluate_flags(dc);
978 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
979 break;
980 case CC_CC:
981 cris_evaluate_flags(dc);
982 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
983 tcg_gen_andi_tl(cc, cc, C_FLAG);
984 break;
985 case CC_VS:
986 cris_evaluate_flags(dc);
987 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
988 break;
989 case CC_VC:
990 cris_evaluate_flags(dc);
991 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
992 V_FLAG);
993 tcg_gen_andi_tl(cc, cc, V_FLAG);
994 break;
995 case CC_PL:
996 if (arith_opt || move_opt) {
997 int bits = 31;
998
999 if (dc->cc_size == 1)
1000 bits = 7;
1001 else if (dc->cc_size == 2)
1002 bits = 15;
1003
1004 tcg_gen_shri_tl(cc, cc_result, bits);
1005 tcg_gen_xori_tl(cc, cc, 1);
1006 } else {
1007 cris_evaluate_flags(dc);
1008 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1009 N_FLAG);
1010 tcg_gen_andi_tl(cc, cc, N_FLAG);
1011 }
1012 break;
1013 case CC_MI:
1014 if (arith_opt || move_opt) {
1015 int bits = 31;
1016
1017 if (dc->cc_size == 1)
1018 bits = 7;
1019 else if (dc->cc_size == 2)
1020 bits = 15;
1021
1022 tcg_gen_shri_tl(cc, cc_result, bits);
1023 tcg_gen_andi_tl(cc, cc, 1);
1024 }
1025 else {
1026 cris_evaluate_flags(dc);
1027 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1028 N_FLAG);
1029 }
1030 break;
1031 case CC_LS:
1032 cris_evaluate_flags(dc);
1033 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1034 C_FLAG | Z_FLAG);
1035 break;
1036 case CC_HI:
1037 cris_evaluate_flags(dc);
1038 {
1039 TCGv tmp;
1040
1041 tmp = tcg_temp_new();
1042 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1043 C_FLAG | Z_FLAG);
1044 /* Overlay the C flag on top of the Z. */
1045 tcg_gen_shli_tl(cc, tmp, 2);
1046 tcg_gen_and_tl(cc, tmp, cc);
1047 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1048
1049 tcg_temp_free(tmp);
1050 }
1051 break;
1052 case CC_GE:
1053 cris_evaluate_flags(dc);
1054 /* Overlay the V flag on top of the N. */
1055 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1056 tcg_gen_xor_tl(cc,
1057 cpu_PR[PR_CCS], cc);
1058 tcg_gen_andi_tl(cc, cc, N_FLAG);
1059 tcg_gen_xori_tl(cc, cc, N_FLAG);
1060 break;
1061 case CC_LT:
1062 cris_evaluate_flags(dc);
1063 /* Overlay the V flag on top of the N. */
1064 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1065 tcg_gen_xor_tl(cc,
1066 cpu_PR[PR_CCS], cc);
1067 tcg_gen_andi_tl(cc, cc, N_FLAG);
1068 break;
1069 case CC_GT:
1070 cris_evaluate_flags(dc);
1071 {
1072 TCGv n, z;
1073
1074 n = tcg_temp_new();
1075 z = tcg_temp_new();
1076
1077 /* To avoid a shift we overlay everything on
1078 the V flag. */
1079 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1080 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1081 /* invert Z. */
1082 tcg_gen_xori_tl(z, z, 2);
1083
1084 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1085 tcg_gen_xori_tl(n, n, 2);
1086 tcg_gen_and_tl(cc, z, n);
1087 tcg_gen_andi_tl(cc, cc, 2);
1088
1089 tcg_temp_free(n);
1090 tcg_temp_free(z);
1091 }
1092 break;
1093 case CC_LE:
1094 cris_evaluate_flags(dc);
1095 {
1096 TCGv n, z;
1097
1098 n = tcg_temp_new();
1099 z = tcg_temp_new();
1100
1101 /* To avoid a shift we overlay everything on
1102 the V flag. */
1103 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1104 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1105
1106 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1107 tcg_gen_or_tl(cc, z, n);
1108 tcg_gen_andi_tl(cc, cc, 2);
1109
1110 tcg_temp_free(n);
1111 tcg_temp_free(z);
1112 }
1113 break;
1114 case CC_P:
1115 cris_evaluate_flags(dc);
1116 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1117 break;
1118 case CC_A:
1119 tcg_gen_movi_tl(cc, 1);
1120 break;
1121 default:
1122 BUG();
1123 break;
1124 };
1125 }
1126
1127 static void cris_store_direct_jmp(DisasContext *dc)
1128 {
1129 /* Store the direct jmp state into the cpu-state. */
1130 if (dc->jmp == JMP_DIRECT) {
1131 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1132 dc->jmp = JMP_INDIRECT;
1133 }
1134 }
1135
1136 static void cris_prepare_cc_branch (DisasContext *dc,
1137 int offset, int cond)
1138 {
1139 /* This helps us re-schedule the micro-code to insns in delay-slots
1140 before the actual jump. */
1141 dc->delayed_branch = 2;
1142 dc->jmp = JMP_DIRECT;
1143 dc->jmp_pc = dc->pc + offset;
1144
1145 gen_tst_cc (dc, env_btaken, cond);
1146 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1147 }
1148
1149
1150 /* jumps, when the dest is in a live reg for example. Direct should be set
1151 when the dest addr is constant to allow tb chaining. */
1152 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1153 {
1154 /* This helps us re-schedule the micro-code to insns in delay-slots
1155 before the actual jump. */
1156 dc->delayed_branch = 2;
1157 dc->jmp = type;
1158 tcg_gen_movi_tl(env_btaken, 1);
1159 }
1160
1161 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1162 {
1163 int mem_index = cpu_mmu_index(dc->env);
1164
1165 /* If we get a fault on a delayslot we must keep the jmp state in
1166 the cpu-state to be able to re-execute the jmp. */
1167 if (dc->delayed_branch == 1)
1168 cris_store_direct_jmp(dc);
1169
1170 tcg_gen_qemu_ld64(dst, addr, mem_index);
1171 }
1172
1173 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1174 unsigned int size, int sign)
1175 {
1176 int mem_index = cpu_mmu_index(dc->env);
1177
1178 /* If we get a fault on a delayslot we must keep the jmp state in
1179 the cpu-state to be able to re-execute the jmp. */
1180 if (dc->delayed_branch == 1)
1181 cris_store_direct_jmp(dc);
1182
1183 if (size == 1) {
1184 if (sign)
1185 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1186 else
1187 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1188 }
1189 else if (size == 2) {
1190 if (sign)
1191 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1192 else
1193 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1194 }
1195 else if (size == 4) {
1196 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1197 }
1198 else {
1199 abort();
1200 }
1201 }
1202
1203 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1204 unsigned int size)
1205 {
1206 int mem_index = cpu_mmu_index(dc->env);
1207
1208 /* If we get a fault on a delayslot we must keep the jmp state in
1209 the cpu-state to be able to re-execute the jmp. */
1210 if (dc->delayed_branch == 1)
1211 cris_store_direct_jmp(dc);
1212
1213
1214 /* Conditional writes. We only support the kind were X and P are known
1215 at translation time. */
1216 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1217 dc->postinc = 0;
1218 cris_evaluate_flags(dc);
1219 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1220 return;
1221 }
1222
1223 if (size == 1)
1224 tcg_gen_qemu_st8(val, addr, mem_index);
1225 else if (size == 2)
1226 tcg_gen_qemu_st16(val, addr, mem_index);
1227 else
1228 tcg_gen_qemu_st32(val, addr, mem_index);
1229
1230 if (dc->flagx_known && dc->flags_x) {
1231 cris_evaluate_flags(dc);
1232 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1233 }
1234 }
1235
1236 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1237 {
1238 if (size == 1)
1239 tcg_gen_ext8s_i32(d, s);
1240 else if (size == 2)
1241 tcg_gen_ext16s_i32(d, s);
1242 else if(!TCGV_EQUAL(d, s))
1243 tcg_gen_mov_tl(d, s);
1244 }
1245
1246 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1247 {
1248 if (size == 1)
1249 tcg_gen_ext8u_i32(d, s);
1250 else if (size == 2)
1251 tcg_gen_ext16u_i32(d, s);
1252 else if (!TCGV_EQUAL(d, s))
1253 tcg_gen_mov_tl(d, s);
1254 }
1255
1256 #if DISAS_CRIS
1257 static char memsize_char(int size)
1258 {
1259 switch (size)
1260 {
1261 case 1: return 'b'; break;
1262 case 2: return 'w'; break;
1263 case 4: return 'd'; break;
1264 default:
1265 return 'x';
1266 break;
1267 }
1268 }
1269 #endif
1270
1271 static inline unsigned int memsize_z(DisasContext *dc)
1272 {
1273 return dc->zsize + 1;
1274 }
1275
1276 static inline unsigned int memsize_zz(DisasContext *dc)
1277 {
1278 switch (dc->zzsize)
1279 {
1280 case 0: return 1;
1281 case 1: return 2;
1282 default:
1283 return 4;
1284 }
1285 }
1286
1287 static inline void do_postinc (DisasContext *dc, int size)
1288 {
1289 if (dc->postinc)
1290 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1291 }
1292
1293 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1294 int size, int s_ext, TCGv dst)
1295 {
1296 if (s_ext)
1297 t_gen_sext(dst, cpu_R[rs], size);
1298 else
1299 t_gen_zext(dst, cpu_R[rs], size);
1300 }
1301
1302 /* Prepare T0 and T1 for a register alu operation.
1303 s_ext decides if the operand1 should be sign-extended or zero-extended when
1304 needed. */
1305 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1306 int size, int s_ext, TCGv dst, TCGv src)
1307 {
1308 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1309
1310 if (s_ext)
1311 t_gen_sext(dst, cpu_R[rd], size);
1312 else
1313 t_gen_zext(dst, cpu_R[rd], size);
1314 }
1315
1316 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1317 TCGv dst)
1318 {
1319 unsigned int rs;
1320 uint32_t imm;
1321 int is_imm;
1322 int insn_len = 2;
1323
1324 rs = dc->op1;
1325 is_imm = rs == 15 && dc->postinc;
1326
1327 /* Load [$rs] onto T1. */
1328 if (is_imm) {
1329 insn_len = 2 + memsize;
1330 if (memsize == 1)
1331 insn_len++;
1332
1333 imm = cris_fetch(dc, dc->pc + 2, memsize, s_ext);
1334 tcg_gen_movi_tl(dst, imm);
1335 dc->postinc = 0;
1336 } else {
1337 cris_flush_cc_state(dc);
1338 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1339 if (s_ext)
1340 t_gen_sext(dst, dst, memsize);
1341 else
1342 t_gen_zext(dst, dst, memsize);
1343 }
1344 return insn_len;
1345 }
1346
1347 /* Prepare T0 and T1 for a memory + alu operation.
1348 s_ext decides if the operand1 should be sign-extended or zero-extended when
1349 needed. */
1350 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
1351 TCGv dst, TCGv src)
1352 {
1353 int insn_len;
1354
1355 insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
1356 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1357 return insn_len;
1358 }
1359
1360 #if DISAS_CRIS
1361 static const char *cc_name(int cc)
1362 {
1363 static const char *cc_names[16] = {
1364 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1365 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1366 };
1367 assert(cc < 16);
1368 return cc_names[cc];
1369 }
1370 #endif
1371
1372 /* Start of insn decoders. */
1373
1374 static int dec_bccq(DisasContext *dc)
1375 {
1376 int32_t offset;
1377 int sign;
1378 uint32_t cond = dc->op2;
1379
1380 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1381 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1382
1383 offset *= 2;
1384 offset |= sign << 8;
1385 offset = sign_extend(offset, 8);
1386
1387 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1388
1389 /* op2 holds the condition-code. */
1390 cris_cc_mask(dc, 0);
1391 cris_prepare_cc_branch (dc, offset, cond);
1392 return 2;
1393 }
1394 static int dec_addoq(DisasContext *dc)
1395 {
1396 int32_t imm;
1397
1398 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1399 imm = sign_extend(dc->op1, 7);
1400
1401 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1402 cris_cc_mask(dc, 0);
1403 /* Fetch register operand, */
1404 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1405
1406 return 2;
1407 }
1408 static int dec_addq(DisasContext *dc)
1409 {
1410 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1411
1412 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1413
1414 cris_cc_mask(dc, CC_MASK_NZVC);
1415
1416 cris_alu(dc, CC_OP_ADD,
1417 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1418 return 2;
1419 }
1420 static int dec_moveq(DisasContext *dc)
1421 {
1422 uint32_t imm;
1423
1424 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1425 imm = sign_extend(dc->op1, 5);
1426 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1427
1428 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1429 return 2;
1430 }
1431 static int dec_subq(DisasContext *dc)
1432 {
1433 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1434
1435 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1436
1437 cris_cc_mask(dc, CC_MASK_NZVC);
1438 cris_alu(dc, CC_OP_SUB,
1439 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1440 return 2;
1441 }
1442 static int dec_cmpq(DisasContext *dc)
1443 {
1444 uint32_t imm;
1445 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1446 imm = sign_extend(dc->op1, 5);
1447
1448 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1449 cris_cc_mask(dc, CC_MASK_NZVC);
1450
1451 cris_alu(dc, CC_OP_CMP,
1452 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1453 return 2;
1454 }
1455 static int dec_andq(DisasContext *dc)
1456 {
1457 uint32_t imm;
1458 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1459 imm = sign_extend(dc->op1, 5);
1460
1461 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1462 cris_cc_mask(dc, CC_MASK_NZ);
1463
1464 cris_alu(dc, CC_OP_AND,
1465 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1466 return 2;
1467 }
1468 static int dec_orq(DisasContext *dc)
1469 {
1470 uint32_t imm;
1471 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1472 imm = sign_extend(dc->op1, 5);
1473 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1474 cris_cc_mask(dc, CC_MASK_NZ);
1475
1476 cris_alu(dc, CC_OP_OR,
1477 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1478 return 2;
1479 }
1480 static int dec_btstq(DisasContext *dc)
1481 {
1482 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1483 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1484
1485 cris_cc_mask(dc, CC_MASK_NZ);
1486 cris_evaluate_flags(dc);
1487 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1488 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1489 cris_alu(dc, CC_OP_MOVE,
1490 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1491 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1492 dc->flags_uptodate = 1;
1493 return 2;
1494 }
1495 static int dec_asrq(DisasContext *dc)
1496 {
1497 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1498 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1499 cris_cc_mask(dc, CC_MASK_NZ);
1500
1501 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1502 cris_alu(dc, CC_OP_MOVE,
1503 cpu_R[dc->op2],
1504 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1505 return 2;
1506 }
1507 static int dec_lslq(DisasContext *dc)
1508 {
1509 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1510 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1511
1512 cris_cc_mask(dc, CC_MASK_NZ);
1513
1514 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1515
1516 cris_alu(dc, CC_OP_MOVE,
1517 cpu_R[dc->op2],
1518 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1519 return 2;
1520 }
1521 static int dec_lsrq(DisasContext *dc)
1522 {
1523 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1524 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1525
1526 cris_cc_mask(dc, CC_MASK_NZ);
1527
1528 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1529 cris_alu(dc, CC_OP_MOVE,
1530 cpu_R[dc->op2],
1531 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1532 return 2;
1533 }
1534
1535 static int dec_move_r(DisasContext *dc)
1536 {
1537 int size = memsize_zz(dc);
1538
1539 LOG_DIS("move.%c $r%u, $r%u\n",
1540 memsize_char(size), dc->op1, dc->op2);
1541
1542 cris_cc_mask(dc, CC_MASK_NZ);
1543 if (size == 4) {
1544 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1545 cris_cc_mask(dc, CC_MASK_NZ);
1546 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1547 cris_update_cc_x(dc);
1548 cris_update_result(dc, cpu_R[dc->op2]);
1549 }
1550 else {
1551 TCGv t0;
1552
1553 t0 = tcg_temp_new();
1554 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1555 cris_alu(dc, CC_OP_MOVE,
1556 cpu_R[dc->op2],
1557 cpu_R[dc->op2], t0, size);
1558 tcg_temp_free(t0);
1559 }
1560 return 2;
1561 }
1562
1563 static int dec_scc_r(DisasContext *dc)
1564 {
1565 int cond = dc->op2;
1566
1567 LOG_DIS("s%s $r%u\n",
1568 cc_name(cond), dc->op1);
1569
1570 if (cond != CC_A)
1571 {
1572 int l1;
1573
1574 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1575 l1 = gen_new_label();
1576 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1577 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1578 gen_set_label(l1);
1579 }
1580 else
1581 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1582
1583 cris_cc_mask(dc, 0);
1584 return 2;
1585 }
1586
1587 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1588 {
1589 if (size == 4) {
1590 t[0] = cpu_R[dc->op2];
1591 t[1] = cpu_R[dc->op1];
1592 } else {
1593 t[0] = tcg_temp_new();
1594 t[1] = tcg_temp_new();
1595 }
1596 }
1597
1598 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1599 {
1600 if (size != 4) {
1601 tcg_temp_free(t[0]);
1602 tcg_temp_free(t[1]);
1603 }
1604 }
1605
1606 static int dec_and_r(DisasContext *dc)
1607 {
1608 TCGv t[2];
1609 int size = memsize_zz(dc);
1610
1611 LOG_DIS("and.%c $r%u, $r%u\n",
1612 memsize_char(size), dc->op1, dc->op2);
1613
1614 cris_cc_mask(dc, CC_MASK_NZ);
1615
1616 cris_alu_alloc_temps(dc, size, t);
1617 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1618 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1619 cris_alu_free_temps(dc, size, t);
1620 return 2;
1621 }
1622
1623 static int dec_lz_r(DisasContext *dc)
1624 {
1625 TCGv t0;
1626 LOG_DIS("lz $r%u, $r%u\n",
1627 dc->op1, dc->op2);
1628 cris_cc_mask(dc, CC_MASK_NZ);
1629 t0 = tcg_temp_new();
1630 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1631 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1632 tcg_temp_free(t0);
1633 return 2;
1634 }
1635
1636 static int dec_lsl_r(DisasContext *dc)
1637 {
1638 TCGv t[2];
1639 int size = memsize_zz(dc);
1640
1641 LOG_DIS("lsl.%c $r%u, $r%u\n",
1642 memsize_char(size), dc->op1, dc->op2);
1643
1644 cris_cc_mask(dc, CC_MASK_NZ);
1645 cris_alu_alloc_temps(dc, size, t);
1646 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1647 tcg_gen_andi_tl(t[1], t[1], 63);
1648 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1649 cris_alu_alloc_temps(dc, size, t);
1650 return 2;
1651 }
1652
1653 static int dec_lsr_r(DisasContext *dc)
1654 {
1655 TCGv t[2];
1656 int size = memsize_zz(dc);
1657
1658 LOG_DIS("lsr.%c $r%u, $r%u\n",
1659 memsize_char(size), dc->op1, dc->op2);
1660
1661 cris_cc_mask(dc, CC_MASK_NZ);
1662 cris_alu_alloc_temps(dc, size, t);
1663 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1664 tcg_gen_andi_tl(t[1], t[1], 63);
1665 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1666 cris_alu_free_temps(dc, size, t);
1667 return 2;
1668 }
1669
1670 static int dec_asr_r(DisasContext *dc)
1671 {
1672 TCGv t[2];
1673 int size = memsize_zz(dc);
1674
1675 LOG_DIS("asr.%c $r%u, $r%u\n",
1676 memsize_char(size), dc->op1, dc->op2);
1677
1678 cris_cc_mask(dc, CC_MASK_NZ);
1679 cris_alu_alloc_temps(dc, size, t);
1680 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1681 tcg_gen_andi_tl(t[1], t[1], 63);
1682 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1683 cris_alu_free_temps(dc, size, t);
1684 return 2;
1685 }
1686
1687 static int dec_muls_r(DisasContext *dc)
1688 {
1689 TCGv t[2];
1690 int size = memsize_zz(dc);
1691
1692 LOG_DIS("muls.%c $r%u, $r%u\n",
1693 memsize_char(size), dc->op1, dc->op2);
1694 cris_cc_mask(dc, CC_MASK_NZV);
1695 cris_alu_alloc_temps(dc, size, t);
1696 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1697
1698 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1699 cris_alu_free_temps(dc, size, t);
1700 return 2;
1701 }
1702
1703 static int dec_mulu_r(DisasContext *dc)
1704 {
1705 TCGv t[2];
1706 int size = memsize_zz(dc);
1707
1708 LOG_DIS("mulu.%c $r%u, $r%u\n",
1709 memsize_char(size), dc->op1, dc->op2);
1710 cris_cc_mask(dc, CC_MASK_NZV);
1711 cris_alu_alloc_temps(dc, size, t);
1712 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1713
1714 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1715 cris_alu_alloc_temps(dc, size, t);
1716 return 2;
1717 }
1718
1719
1720 static int dec_dstep_r(DisasContext *dc)
1721 {
1722 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1723 cris_cc_mask(dc, CC_MASK_NZ);
1724 cris_alu(dc, CC_OP_DSTEP,
1725 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1726 return 2;
1727 }
1728
1729 static int dec_xor_r(DisasContext *dc)
1730 {
1731 TCGv t[2];
1732 int size = memsize_zz(dc);
1733 LOG_DIS("xor.%c $r%u, $r%u\n",
1734 memsize_char(size), dc->op1, dc->op2);
1735 BUG_ON(size != 4); /* xor is dword. */
1736 cris_cc_mask(dc, CC_MASK_NZ);
1737 cris_alu_alloc_temps(dc, size, t);
1738 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1739
1740 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1741 cris_alu_free_temps(dc, size, t);
1742 return 2;
1743 }
1744
1745 static int dec_bound_r(DisasContext *dc)
1746 {
1747 TCGv l0;
1748 int size = memsize_zz(dc);
1749 LOG_DIS("bound.%c $r%u, $r%u\n",
1750 memsize_char(size), dc->op1, dc->op2);
1751 cris_cc_mask(dc, CC_MASK_NZ);
1752 l0 = tcg_temp_local_new();
1753 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1754 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1755 tcg_temp_free(l0);
1756 return 2;
1757 }
1758
1759 static int dec_cmp_r(DisasContext *dc)
1760 {
1761 TCGv t[2];
1762 int size = memsize_zz(dc);
1763 LOG_DIS("cmp.%c $r%u, $r%u\n",
1764 memsize_char(size), dc->op1, dc->op2);
1765 cris_cc_mask(dc, CC_MASK_NZVC);
1766 cris_alu_alloc_temps(dc, size, t);
1767 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1768
1769 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1770 cris_alu_free_temps(dc, size, t);
1771 return 2;
1772 }
1773
1774 static int dec_abs_r(DisasContext *dc)
1775 {
1776 TCGv t0;
1777
1778 LOG_DIS("abs $r%u, $r%u\n",
1779 dc->op1, dc->op2);
1780 cris_cc_mask(dc, CC_MASK_NZ);
1781
1782 t0 = tcg_temp_new();
1783 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1784 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1785 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1786 tcg_temp_free(t0);
1787
1788 cris_alu(dc, CC_OP_MOVE,
1789 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1790 return 2;
1791 }
1792
1793 static int dec_add_r(DisasContext *dc)
1794 {
1795 TCGv t[2];
1796 int size = memsize_zz(dc);
1797 LOG_DIS("add.%c $r%u, $r%u\n",
1798 memsize_char(size), dc->op1, dc->op2);
1799 cris_cc_mask(dc, CC_MASK_NZVC);
1800 cris_alu_alloc_temps(dc, size, t);
1801 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1802
1803 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1804 cris_alu_free_temps(dc, size, t);
1805 return 2;
1806 }
1807
1808 static int dec_addc_r(DisasContext *dc)
1809 {
1810 LOG_DIS("addc $r%u, $r%u\n",
1811 dc->op1, dc->op2);
1812 cris_evaluate_flags(dc);
1813 /* Set for this insn. */
1814 dc->flagx_known = 1;
1815 dc->flags_x = X_FLAG;
1816
1817 cris_cc_mask(dc, CC_MASK_NZVC);
1818 cris_alu(dc, CC_OP_ADDC,
1819 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1820 return 2;
1821 }
1822
1823 static int dec_mcp_r(DisasContext *dc)
1824 {
1825 LOG_DIS("mcp $p%u, $r%u\n",
1826 dc->op2, dc->op1);
1827 cris_evaluate_flags(dc);
1828 cris_cc_mask(dc, CC_MASK_RNZV);
1829 cris_alu(dc, CC_OP_MCP,
1830 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1831 return 2;
1832 }
1833
1834 #if DISAS_CRIS
1835 static char * swapmode_name(int mode, char *modename) {
1836 int i = 0;
1837 if (mode & 8)
1838 modename[i++] = 'n';
1839 if (mode & 4)
1840 modename[i++] = 'w';
1841 if (mode & 2)
1842 modename[i++] = 'b';
1843 if (mode & 1)
1844 modename[i++] = 'r';
1845 modename[i++] = 0;
1846 return modename;
1847 }
1848 #endif
1849
1850 static int dec_swap_r(DisasContext *dc)
1851 {
1852 TCGv t0;
1853 #if DISAS_CRIS
1854 char modename[4];
1855 #endif
1856 LOG_DIS("swap%s $r%u\n",
1857 swapmode_name(dc->op2, modename), dc->op1);
1858
1859 cris_cc_mask(dc, CC_MASK_NZ);
1860 t0 = tcg_temp_new();
1861 t_gen_mov_TN_reg(t0, dc->op1);
1862 if (dc->op2 & 8)
1863 tcg_gen_not_tl(t0, t0);
1864 if (dc->op2 & 4)
1865 t_gen_swapw(t0, t0);
1866 if (dc->op2 & 2)
1867 t_gen_swapb(t0, t0);
1868 if (dc->op2 & 1)
1869 t_gen_swapr(t0, t0);
1870 cris_alu(dc, CC_OP_MOVE,
1871 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1872 tcg_temp_free(t0);
1873 return 2;
1874 }
1875
1876 static int dec_or_r(DisasContext *dc)
1877 {
1878 TCGv t[2];
1879 int size = memsize_zz(dc);
1880 LOG_DIS("or.%c $r%u, $r%u\n",
1881 memsize_char(size), dc->op1, dc->op2);
1882 cris_cc_mask(dc, CC_MASK_NZ);
1883 cris_alu_alloc_temps(dc, size, t);
1884 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1885 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1886 cris_alu_free_temps(dc, size, t);
1887 return 2;
1888 }
1889
1890 static int dec_addi_r(DisasContext *dc)
1891 {
1892 TCGv t0;
1893 LOG_DIS("addi.%c $r%u, $r%u\n",
1894 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1895 cris_cc_mask(dc, 0);
1896 t0 = tcg_temp_new();
1897 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1898 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1899 tcg_temp_free(t0);
1900 return 2;
1901 }
1902
1903 static int dec_addi_acr(DisasContext *dc)
1904 {
1905 TCGv t0;
1906 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1907 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1908 cris_cc_mask(dc, 0);
1909 t0 = tcg_temp_new();
1910 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1911 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1912 tcg_temp_free(t0);
1913 return 2;
1914 }
1915
1916 static int dec_neg_r(DisasContext *dc)
1917 {
1918 TCGv t[2];
1919 int size = memsize_zz(dc);
1920 LOG_DIS("neg.%c $r%u, $r%u\n",
1921 memsize_char(size), dc->op1, dc->op2);
1922 cris_cc_mask(dc, CC_MASK_NZVC);
1923 cris_alu_alloc_temps(dc, size, t);
1924 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1925
1926 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1927 cris_alu_free_temps(dc, size, t);
1928 return 2;
1929 }
1930
1931 static int dec_btst_r(DisasContext *dc)
1932 {
1933 LOG_DIS("btst $r%u, $r%u\n",
1934 dc->op1, dc->op2);
1935 cris_cc_mask(dc, CC_MASK_NZ);
1936 cris_evaluate_flags(dc);
1937 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1938 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1939 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1940 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1941 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1942 dc->flags_uptodate = 1;
1943 return 2;
1944 }
1945
1946 static int dec_sub_r(DisasContext *dc)
1947 {
1948 TCGv t[2];
1949 int size = memsize_zz(dc);
1950 LOG_DIS("sub.%c $r%u, $r%u\n",
1951 memsize_char(size), dc->op1, dc->op2);
1952 cris_cc_mask(dc, CC_MASK_NZVC);
1953 cris_alu_alloc_temps(dc, size, t);
1954 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1955 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1956 cris_alu_free_temps(dc, size, t);
1957 return 2;
1958 }
1959
1960 /* Zero extension. From size to dword. */
1961 static int dec_movu_r(DisasContext *dc)
1962 {
1963 TCGv t0;
1964 int size = memsize_z(dc);
1965 LOG_DIS("movu.%c $r%u, $r%u\n",
1966 memsize_char(size),
1967 dc->op1, dc->op2);
1968
1969 cris_cc_mask(dc, CC_MASK_NZ);
1970 t0 = tcg_temp_new();
1971 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1972 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1973 tcg_temp_free(t0);
1974 return 2;
1975 }
1976
1977 /* Sign extension. From size to dword. */
1978 static int dec_movs_r(DisasContext *dc)
1979 {
1980 TCGv t0;
1981 int size = memsize_z(dc);
1982 LOG_DIS("movs.%c $r%u, $r%u\n",
1983 memsize_char(size),
1984 dc->op1, dc->op2);
1985
1986 cris_cc_mask(dc, CC_MASK_NZ);
1987 t0 = tcg_temp_new();
1988 /* Size can only be qi or hi. */
1989 t_gen_sext(t0, cpu_R[dc->op1], size);
1990 cris_alu(dc, CC_OP_MOVE,
1991 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1992 tcg_temp_free(t0);
1993 return 2;
1994 }
1995
1996 /* zero extension. From size to dword. */
1997 static int dec_addu_r(DisasContext *dc)
1998 {
1999 TCGv t0;
2000 int size = memsize_z(dc);
2001 LOG_DIS("addu.%c $r%u, $r%u\n",
2002 memsize_char(size),
2003 dc->op1, dc->op2);
2004
2005 cris_cc_mask(dc, CC_MASK_NZVC);
2006 t0 = tcg_temp_new();
2007 /* Size can only be qi or hi. */
2008 t_gen_zext(t0, cpu_R[dc->op1], size);
2009 cris_alu(dc, CC_OP_ADD,
2010 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2011 tcg_temp_free(t0);
2012 return 2;
2013 }
2014
2015 /* Sign extension. From size to dword. */
2016 static int dec_adds_r(DisasContext *dc)
2017 {
2018 TCGv t0;
2019 int size = memsize_z(dc);
2020 LOG_DIS("adds.%c $r%u, $r%u\n",
2021 memsize_char(size),
2022 dc->op1, dc->op2);
2023
2024 cris_cc_mask(dc, CC_MASK_NZVC);
2025 t0 = tcg_temp_new();
2026 /* Size can only be qi or hi. */
2027 t_gen_sext(t0, cpu_R[dc->op1], size);
2028 cris_alu(dc, CC_OP_ADD,
2029 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2030 tcg_temp_free(t0);
2031 return 2;
2032 }
2033
2034 /* Zero extension. From size to dword. */
2035 static int dec_subu_r(DisasContext *dc)
2036 {
2037 TCGv t0;
2038 int size = memsize_z(dc);
2039 LOG_DIS("subu.%c $r%u, $r%u\n",
2040 memsize_char(size),
2041 dc->op1, dc->op2);
2042
2043 cris_cc_mask(dc, CC_MASK_NZVC);
2044 t0 = tcg_temp_new();
2045 /* Size can only be qi or hi. */
2046 t_gen_zext(t0, cpu_R[dc->op1], size);
2047 cris_alu(dc, CC_OP_SUB,
2048 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2049 tcg_temp_free(t0);
2050 return 2;
2051 }
2052
2053 /* Sign extension. From size to dword. */
2054 static int dec_subs_r(DisasContext *dc)
2055 {
2056 TCGv t0;
2057 int size = memsize_z(dc);
2058 LOG_DIS("subs.%c $r%u, $r%u\n",
2059 memsize_char(size),
2060 dc->op1, dc->op2);
2061
2062 cris_cc_mask(dc, CC_MASK_NZVC);
2063 t0 = tcg_temp_new();
2064 /* Size can only be qi or hi. */
2065 t_gen_sext(t0, cpu_R[dc->op1], size);
2066 cris_alu(dc, CC_OP_SUB,
2067 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2068 tcg_temp_free(t0);
2069 return 2;
2070 }
2071
2072 static int dec_setclrf(DisasContext *dc)
2073 {
2074 uint32_t flags;
2075 int set = (~dc->opcode >> 2) & 1;
2076
2077
2078 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2079 | EXTRACT_FIELD(dc->ir, 0, 3);
2080 if (set && flags == 0) {
2081 LOG_DIS("nop\n");
2082 return 2;
2083 } else if (!set && (flags & 0x20)) {
2084 LOG_DIS("di\n");
2085 }
2086 else {
2087 LOG_DIS("%sf %x\n",
2088 set ? "set" : "clr",
2089 flags);
2090 }
2091
2092 /* User space is not allowed to touch these. Silently ignore. */
2093 if (dc->tb_flags & U_FLAG) {
2094 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2095 }
2096
2097 if (flags & X_FLAG) {
2098 dc->flagx_known = 1;
2099 if (set)
2100 dc->flags_x = X_FLAG;
2101 else
2102 dc->flags_x = 0;
2103 }
2104
2105 /* Break the TB if any of the SPI flag changes. */
2106 if (flags & (P_FLAG | S_FLAG)) {
2107 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2108 dc->is_jmp = DISAS_UPDATE;
2109 dc->cpustate_changed = 1;
2110 }
2111
2112 /* For the I flag, only act on posedge. */
2113 if ((flags & I_FLAG)) {
2114 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2115 dc->is_jmp = DISAS_UPDATE;
2116 dc->cpustate_changed = 1;
2117 }
2118
2119
2120 /* Simply decode the flags. */
2121 cris_evaluate_flags (dc);
2122 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2123 cris_update_cc_x(dc);
2124 tcg_gen_movi_tl(cc_op, dc->cc_op);
2125
2126 if (set) {
2127 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2128 /* Enter user mode. */
2129 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2130 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2131 dc->cpustate_changed = 1;
2132 }
2133 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2134 }
2135 else
2136 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2137
2138 dc->flags_uptodate = 1;
2139 dc->clear_x = 0;
2140 return 2;
2141 }
2142
2143 static int dec_move_rs(DisasContext *dc)
2144 {
2145 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2146 cris_cc_mask(dc, 0);
2147 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2148 return 2;
2149 }
2150 static int dec_move_sr(DisasContext *dc)
2151 {
2152 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2153 cris_cc_mask(dc, 0);
2154 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2155 return 2;
2156 }
2157
2158 static int dec_move_rp(DisasContext *dc)
2159 {
2160 TCGv t[2];
2161 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2162 cris_cc_mask(dc, 0);
2163
2164 t[0] = tcg_temp_new();
2165 if (dc->op2 == PR_CCS) {
2166 cris_evaluate_flags(dc);
2167 t_gen_mov_TN_reg(t[0], dc->op1);
2168 if (dc->tb_flags & U_FLAG) {
2169 t[1] = tcg_temp_new();
2170 /* User space is not allowed to touch all flags. */
2171 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2172 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2173 tcg_gen_or_tl(t[0], t[1], t[0]);
2174 tcg_temp_free(t[1]);
2175 }
2176 }
2177 else
2178 t_gen_mov_TN_reg(t[0], dc->op1);
2179
2180 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2181 if (dc->op2 == PR_CCS) {
2182 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2183 dc->flags_uptodate = 1;
2184 }
2185 tcg_temp_free(t[0]);
2186 return 2;
2187 }
2188 static int dec_move_pr(DisasContext *dc)
2189 {
2190 TCGv t0;
2191 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2192 cris_cc_mask(dc, 0);
2193
2194 if (dc->op2 == PR_CCS)
2195 cris_evaluate_flags(dc);
2196
2197 if (dc->op2 == PR_DZ) {
2198 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2199 } else {
2200 t0 = tcg_temp_new();
2201 t_gen_mov_TN_preg(t0, dc->op2);
2202 cris_alu(dc, CC_OP_MOVE,
2203 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2204 preg_sizes[dc->op2]);
2205 tcg_temp_free(t0);
2206 }
2207 return 2;
2208 }
2209
2210 static int dec_move_mr(DisasContext *dc)
2211 {
2212 int memsize = memsize_zz(dc);
2213 int insn_len;
2214 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2215 memsize_char(memsize),
2216 dc->op1, dc->postinc ? "+]" : "]",
2217 dc->op2);
2218
2219 if (memsize == 4) {
2220 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2221 cris_cc_mask(dc, CC_MASK_NZ);
2222 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2223 cris_update_cc_x(dc);
2224 cris_update_result(dc, cpu_R[dc->op2]);
2225 }
2226 else {
2227 TCGv t0;
2228
2229 t0 = tcg_temp_new();
2230 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2231 cris_cc_mask(dc, CC_MASK_NZ);
2232 cris_alu(dc, CC_OP_MOVE,
2233 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2234 tcg_temp_free(t0);
2235 }
2236 do_postinc(dc, memsize);
2237 return insn_len;
2238 }
2239
2240 static inline void cris_alu_m_alloc_temps(TCGv *t)
2241 {
2242 t[0] = tcg_temp_new();
2243 t[1] = tcg_temp_new();
2244 }
2245
2246 static inline void cris_alu_m_free_temps(TCGv *t)
2247 {
2248 tcg_temp_free(t[0]);
2249 tcg_temp_free(t[1]);
2250 }
2251
2252 static int dec_movs_m(DisasContext *dc)
2253 {
2254 TCGv t[2];
2255 int memsize = memsize_z(dc);
2256 int insn_len;
2257 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2258 memsize_char(memsize),
2259 dc->op1, dc->postinc ? "+]" : "]",
2260 dc->op2);
2261
2262 cris_alu_m_alloc_temps(t);
2263 /* sign extend. */
2264 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2265 cris_cc_mask(dc, CC_MASK_NZ);
2266 cris_alu(dc, CC_OP_MOVE,
2267 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2268 do_postinc(dc, memsize);
2269 cris_alu_m_free_temps(t);
2270 return insn_len;
2271 }
2272
2273 static int dec_addu_m(DisasContext *dc)
2274 {
2275 TCGv t[2];
2276 int memsize = memsize_z(dc);
2277 int insn_len;
2278 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2279 memsize_char(memsize),
2280 dc->op1, dc->postinc ? "+]" : "]",
2281 dc->op2);
2282
2283 cris_alu_m_alloc_temps(t);
2284 /* sign extend. */
2285 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2286 cris_cc_mask(dc, CC_MASK_NZVC);
2287 cris_alu(dc, CC_OP_ADD,
2288 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2289 do_postinc(dc, memsize);
2290 cris_alu_m_free_temps(t);
2291 return insn_len;
2292 }
2293
2294 static int dec_adds_m(DisasContext *dc)
2295 {
2296 TCGv t[2];
2297 int memsize = memsize_z(dc);
2298 int insn_len;
2299 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2300 memsize_char(memsize),
2301 dc->op1, dc->postinc ? "+]" : "]",
2302 dc->op2);
2303
2304 cris_alu_m_alloc_temps(t);
2305 /* sign extend. */
2306 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2307 cris_cc_mask(dc, CC_MASK_NZVC);
2308 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2309 do_postinc(dc, memsize);
2310 cris_alu_m_free_temps(t);
2311 return insn_len;
2312 }
2313
2314 static int dec_subu_m(DisasContext *dc)
2315 {
2316 TCGv t[2];
2317 int memsize = memsize_z(dc);
2318 int insn_len;
2319 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2320 memsize_char(memsize),
2321 dc->op1, dc->postinc ? "+]" : "]",
2322 dc->op2);
2323
2324 cris_alu_m_alloc_temps(t);
2325 /* sign extend. */
2326 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2327 cris_cc_mask(dc, CC_MASK_NZVC);
2328 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2329 do_postinc(dc, memsize);
2330 cris_alu_m_free_temps(t);
2331 return insn_len;
2332 }
2333
2334 static int dec_subs_m(DisasContext *dc)
2335 {
2336 TCGv t[2];
2337 int memsize = memsize_z(dc);
2338 int insn_len;
2339 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2340 memsize_char(memsize),
2341 dc->op1, dc->postinc ? "+]" : "]",
2342 dc->op2);
2343
2344 cris_alu_m_alloc_temps(t);
2345 /* sign extend. */
2346 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2347 cris_cc_mask(dc, CC_MASK_NZVC);
2348 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2349 do_postinc(dc, memsize);
2350 cris_alu_m_free_temps(t);
2351 return insn_len;
2352 }
2353
2354 static int dec_movu_m(DisasContext *dc)
2355 {
2356 TCGv t[2];
2357 int memsize = memsize_z(dc);
2358 int insn_len;
2359
2360 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2361 memsize_char(memsize),
2362 dc->op1, dc->postinc ? "+]" : "]",
2363 dc->op2);
2364
2365 cris_alu_m_alloc_temps(t);
2366 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2367 cris_cc_mask(dc, CC_MASK_NZ);
2368 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2369 do_postinc(dc, memsize);
2370 cris_alu_m_free_temps(t);
2371 return insn_len;
2372 }
2373
2374 static int dec_cmpu_m(DisasContext *dc)
2375 {
2376 TCGv t[2];
2377 int memsize = memsize_z(dc);
2378 int insn_len;
2379 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2380 memsize_char(memsize),
2381 dc->op1, dc->postinc ? "+]" : "]",
2382 dc->op2);
2383
2384 cris_alu_m_alloc_temps(t);
2385 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2386 cris_cc_mask(dc, CC_MASK_NZVC);
2387 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2388 do_postinc(dc, memsize);
2389 cris_alu_m_free_temps(t);
2390 return insn_len;
2391 }
2392
2393 static int dec_cmps_m(DisasContext *dc)
2394 {
2395 TCGv t[2];
2396 int memsize = memsize_z(dc);
2397 int insn_len;
2398 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2399 memsize_char(memsize),
2400 dc->op1, dc->postinc ? "+]" : "]",
2401 dc->op2);
2402
2403 cris_alu_m_alloc_temps(t);
2404 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2405 cris_cc_mask(dc, CC_MASK_NZVC);
2406 cris_alu(dc, CC_OP_CMP,
2407 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2408 memsize_zz(dc));
2409 do_postinc(dc, memsize);
2410 cris_alu_m_free_temps(t);
2411 return insn_len;
2412 }
2413
2414 static int dec_cmp_m(DisasContext *dc)
2415 {
2416 TCGv t[2];
2417 int memsize = memsize_zz(dc);
2418 int insn_len;
2419 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2420 memsize_char(memsize),
2421 dc->op1, dc->postinc ? "+]" : "]",
2422 dc->op2);
2423
2424 cris_alu_m_alloc_temps(t);
2425 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2426 cris_cc_mask(dc, CC_MASK_NZVC);
2427 cris_alu(dc, CC_OP_CMP,
2428 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2429 memsize_zz(dc));
2430 do_postinc(dc, memsize);
2431 cris_alu_m_free_temps(t);
2432 return insn_len;
2433 }
2434
2435 static int dec_test_m(DisasContext *dc)
2436 {
2437 TCGv t[2];
2438 int memsize = memsize_zz(dc);
2439 int insn_len;
2440 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2441 memsize_char(memsize),
2442 dc->op1, dc->postinc ? "+]" : "]",
2443 dc->op2);
2444
2445 cris_evaluate_flags(dc);
2446
2447 cris_alu_m_alloc_temps(t);
2448 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2449 cris_cc_mask(dc, CC_MASK_NZ);
2450 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2451
2452 cris_alu(dc, CC_OP_CMP,
2453 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2454 do_postinc(dc, memsize);
2455 cris_alu_m_free_temps(t);
2456 return insn_len;
2457 }
2458
2459 static int dec_and_m(DisasContext *dc)
2460 {
2461 TCGv t[2];
2462 int memsize = memsize_zz(dc);
2463 int insn_len;
2464 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2465 memsize_char(memsize),
2466 dc->op1, dc->postinc ? "+]" : "]",
2467 dc->op2);
2468
2469 cris_alu_m_alloc_temps(t);
2470 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2471 cris_cc_mask(dc, CC_MASK_NZ);
2472 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2473 do_postinc(dc, memsize);
2474 cris_alu_m_free_temps(t);
2475 return insn_len;
2476 }
2477
2478 static int dec_add_m(DisasContext *dc)
2479 {
2480 TCGv t[2];
2481 int memsize = memsize_zz(dc);
2482 int insn_len;
2483 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2484 memsize_char(memsize),
2485 dc->op1, dc->postinc ? "+]" : "]",
2486 dc->op2);
2487
2488 cris_alu_m_alloc_temps(t);
2489 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2490 cris_cc_mask(dc, CC_MASK_NZVC);
2491 cris_alu(dc, CC_OP_ADD,
2492 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2493 do_postinc(dc, memsize);
2494 cris_alu_m_free_temps(t);
2495 return insn_len;
2496 }
2497
2498 static int dec_addo_m(DisasContext *dc)
2499 {
2500 TCGv t[2];
2501 int memsize = memsize_zz(dc);
2502 int insn_len;
2503 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2504 memsize_char(memsize),
2505 dc->op1, dc->postinc ? "+]" : "]",
2506 dc->op2);
2507
2508 cris_alu_m_alloc_temps(t);
2509 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2510 cris_cc_mask(dc, 0);
2511 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2512 do_postinc(dc, memsize);
2513 cris_alu_m_free_temps(t);
2514 return insn_len;
2515 }
2516
2517 static int dec_bound_m(DisasContext *dc)
2518 {
2519 TCGv l[2];
2520 int memsize = memsize_zz(dc);
2521 int insn_len;
2522 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2523 memsize_char(memsize),
2524 dc->op1, dc->postinc ? "+]" : "]",
2525 dc->op2);
2526
2527 l[0] = tcg_temp_local_new();
2528 l[1] = tcg_temp_local_new();
2529 insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
2530 cris_cc_mask(dc, CC_MASK_NZ);
2531 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2532 do_postinc(dc, memsize);
2533 tcg_temp_free(l[0]);
2534 tcg_temp_free(l[1]);
2535 return insn_len;
2536 }
2537
2538 static int dec_addc_mr(DisasContext *dc)
2539 {
2540 TCGv t[2];
2541 int insn_len = 2;
2542 LOG_DIS("addc [$r%u%s, $r%u\n",
2543 dc->op1, dc->postinc ? "+]" : "]",
2544 dc->op2);
2545
2546 cris_evaluate_flags(dc);
2547
2548 /* Set for this insn. */
2549 dc->flagx_known = 1;
2550 dc->flags_x = X_FLAG;
2551
2552 cris_alu_m_alloc_temps(t);
2553 insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
2554 cris_cc_mask(dc, CC_MASK_NZVC);
2555 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2556 do_postinc(dc, 4);
2557 cris_alu_m_free_temps(t);
2558 return insn_len;
2559 }
2560
2561 static int dec_sub_m(DisasContext *dc)
2562 {
2563 TCGv t[2];
2564 int memsize = memsize_zz(dc);
2565 int insn_len;
2566 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2567 memsize_char(memsize),
2568 dc->op1, dc->postinc ? "+]" : "]",
2569 dc->op2, dc->ir, dc->zzsize);
2570
2571 cris_alu_m_alloc_temps(t);
2572 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2573 cris_cc_mask(dc, CC_MASK_NZVC);
2574 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2575 do_postinc(dc, memsize);
2576 cris_alu_m_free_temps(t);
2577 return insn_len;
2578 }
2579
2580 static int dec_or_m(DisasContext *dc)
2581 {
2582 TCGv t[2];
2583 int memsize = memsize_zz(dc);
2584 int insn_len;
2585 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2586 memsize_char(memsize),
2587 dc->op1, dc->postinc ? "+]" : "]",
2588 dc->op2, dc->pc);
2589
2590 cris_alu_m_alloc_temps(t);
2591 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2592 cris_cc_mask(dc, CC_MASK_NZ);
2593 cris_alu(dc, CC_OP_OR,
2594 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2595 do_postinc(dc, memsize);
2596 cris_alu_m_free_temps(t);
2597 return insn_len;
2598 }
2599
2600 static int dec_move_mp(DisasContext *dc)
2601 {
2602 TCGv t[2];
2603 int memsize = memsize_zz(dc);
2604 int insn_len = 2;
2605
2606 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2607 memsize_char(memsize),
2608 dc->op1,
2609 dc->postinc ? "+]" : "]",
2610 dc->op2);
2611
2612 cris_alu_m_alloc_temps(t);
2613 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2614 cris_cc_mask(dc, 0);
2615 if (dc->op2 == PR_CCS) {
2616 cris_evaluate_flags(dc);
2617 if (dc->tb_flags & U_FLAG) {
2618 /* User space is not allowed to touch all flags. */
2619 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2620 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2621 tcg_gen_or_tl(t[1], t[0], t[1]);
2622 }
2623 }
2624
2625 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2626
2627 do_postinc(dc, memsize);
2628 cris_alu_m_free_temps(t);
2629 return insn_len;
2630 }
2631
2632 static int dec_move_pm(DisasContext *dc)
2633 {
2634 TCGv t0;
2635 int memsize;
2636
2637 memsize = preg_sizes[dc->op2];
2638
2639 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2640 memsize_char(memsize),
2641 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2642
2643 /* prepare store. Address in T0, value in T1. */
2644 if (dc->op2 == PR_CCS)
2645 cris_evaluate_flags(dc);
2646 t0 = tcg_temp_new();
2647 t_gen_mov_TN_preg(t0, dc->op2);
2648 cris_flush_cc_state(dc);
2649 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2650 tcg_temp_free(t0);
2651
2652 cris_cc_mask(dc, 0);
2653 if (dc->postinc)
2654 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2655 return 2;
2656 }
2657
2658 static int dec_movem_mr(DisasContext *dc)
2659 {
2660 TCGv_i64 tmp[16];
2661 TCGv tmp32;
2662 TCGv addr;
2663 int i;
2664 int nr = dc->op2 + 1;
2665
2666 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2667 dc->postinc ? "+]" : "]", dc->op2);
2668
2669 addr = tcg_temp_new();
2670 /* There are probably better ways of doing this. */
2671 cris_flush_cc_state(dc);
2672 for (i = 0; i < (nr >> 1); i++) {
2673 tmp[i] = tcg_temp_new_i64();
2674 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2675 gen_load64(dc, tmp[i], addr);
2676 }
2677 if (nr & 1) {
2678 tmp32 = tcg_temp_new_i32();
2679 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2680 gen_load(dc, tmp32, addr, 4, 0);
2681 } else
2682 TCGV_UNUSED(tmp32);
2683 tcg_temp_free(addr);
2684
2685 for (i = 0; i < (nr >> 1); i++) {
2686 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2687 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2688 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2689 tcg_temp_free_i64(tmp[i]);
2690 }
2691 if (nr & 1) {
2692 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2693 tcg_temp_free(tmp32);
2694 }
2695
2696 /* writeback the updated pointer value. */
2697 if (dc->postinc)
2698 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2699
2700 /* gen_load might want to evaluate the previous insns flags. */
2701 cris_cc_mask(dc, 0);
2702 return 2;
2703 }
2704
2705 static int dec_movem_rm(DisasContext *dc)
2706 {
2707 TCGv tmp;
2708 TCGv addr;
2709 int i;
2710
2711 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2712 dc->postinc ? "+]" : "]");
2713
2714 cris_flush_cc_state(dc);
2715
2716 tmp = tcg_temp_new();
2717 addr = tcg_temp_new();
2718 tcg_gen_movi_tl(tmp, 4);
2719 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2720 for (i = 0; i <= dc->op2; i++) {
2721 /* Displace addr. */
2722 /* Perform the store. */
2723 gen_store(dc, addr, cpu_R[i], 4);
2724 tcg_gen_add_tl(addr, addr, tmp);
2725 }
2726 if (dc->postinc)
2727 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2728 cris_cc_mask(dc, 0);
2729 tcg_temp_free(tmp);
2730 tcg_temp_free(addr);
2731 return 2;
2732 }
2733
2734 static int dec_move_rm(DisasContext *dc)
2735 {
2736 int memsize;
2737
2738 memsize = memsize_zz(dc);
2739
2740 LOG_DIS("move.%c $r%u, [$r%u]\n",
2741 memsize_char(memsize), dc->op2, dc->op1);
2742
2743 /* prepare store. */
2744 cris_flush_cc_state(dc);
2745 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2746
2747 if (dc->postinc)
2748 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2749 cris_cc_mask(dc, 0);
2750 return 2;
2751 }
2752
2753 static int dec_lapcq(DisasContext *dc)
2754 {
2755 LOG_DIS("lapcq %x, $r%u\n",
2756 dc->pc + dc->op1*2, dc->op2);
2757 cris_cc_mask(dc, 0);
2758 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2759 return 2;
2760 }
2761
2762 static int dec_lapc_im(DisasContext *dc)
2763 {
2764 unsigned int rd;
2765 int32_t imm;
2766 int32_t pc;
2767
2768 rd = dc->op2;
2769
2770 cris_cc_mask(dc, 0);
2771 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2772 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2773
2774 pc = dc->pc;
2775 pc += imm;
2776 tcg_gen_movi_tl(cpu_R[rd], pc);
2777 return 6;
2778 }
2779
2780 /* Jump to special reg. */
2781 static int dec_jump_p(DisasContext *dc)
2782 {
2783 LOG_DIS("jump $p%u\n", dc->op2);
2784
2785 if (dc->op2 == PR_CCS)
2786 cris_evaluate_flags(dc);
2787 t_gen_mov_TN_preg(env_btarget, dc->op2);
2788 /* rete will often have low bit set to indicate delayslot. */
2789 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2790 cris_cc_mask(dc, 0);
2791 cris_prepare_jmp(dc, JMP_INDIRECT);
2792 return 2;
2793 }
2794
2795 /* Jump and save. */
2796 static int dec_jas_r(DisasContext *dc)
2797 {
2798 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2799 cris_cc_mask(dc, 0);
2800 /* Store the return address in Pd. */
2801 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2802 if (dc->op2 > 15)
2803 abort();
2804 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2805
2806 cris_prepare_jmp(dc, JMP_INDIRECT);
2807 return 2;
2808 }
2809
2810 static int dec_jas_im(DisasContext *dc)
2811 {
2812 uint32_t imm;
2813
2814 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2815
2816 LOG_DIS("jas 0x%x\n", imm);
2817 cris_cc_mask(dc, 0);
2818 /* Store the return address in Pd. */
2819 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2820
2821 dc->jmp_pc = imm;
2822 cris_prepare_jmp(dc, JMP_DIRECT);
2823 return 6;
2824 }
2825
2826 static int dec_jasc_im(DisasContext *dc)
2827 {
2828 uint32_t imm;
2829
2830 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2831
2832 LOG_DIS("jasc 0x%x\n", imm);
2833 cris_cc_mask(dc, 0);
2834 /* Store the return address in Pd. */
2835 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2836
2837 dc->jmp_pc = imm;
2838 cris_prepare_jmp(dc, JMP_DIRECT);
2839 return 6;
2840 }
2841
2842 static int dec_jasc_r(DisasContext *dc)
2843 {
2844 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2845 cris_cc_mask(dc, 0);
2846 /* Store the return address in Pd. */
2847 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2848 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2849 cris_prepare_jmp(dc, JMP_INDIRECT);
2850 return 2;
2851 }
2852
2853 static int dec_bcc_im(DisasContext *dc)
2854 {
2855 int32_t offset;
2856 uint32_t cond = dc->op2;
2857
2858 offset = cris_fetch(dc, dc->pc + 2, 2, 1);
2859
2860 LOG_DIS("b%s %d pc=%x dst=%x\n",
2861 cc_name(cond), offset,
2862 dc->pc, dc->pc + offset);
2863
2864 cris_cc_mask(dc, 0);
2865 /* op2 holds the condition-code. */
2866 cris_prepare_cc_branch (dc, offset, cond);
2867 return 4;
2868 }
2869
2870 static int dec_bas_im(DisasContext *dc)
2871 {
2872 int32_t simm;
2873
2874
2875 simm = cris_fetch(dc, dc->pc + 2, 4, 0);
2876
2877 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2878 cris_cc_mask(dc, 0);
2879 /* Store the return address in Pd. */
2880 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2881
2882 dc->jmp_pc = dc->pc + simm;
2883 cris_prepare_jmp(dc, JMP_DIRECT);
2884 return 6;
2885 }
2886
2887 static int dec_basc_im(DisasContext *dc)
2888 {
2889 int32_t simm;
2890 simm = cris_fetch(dc, dc->pc + 2, 4, 0);
2891
2892 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2893 cris_cc_mask(dc, 0);
2894 /* Store the return address in Pd. */
2895 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2896
2897 dc->jmp_pc = dc->pc + simm;
2898 cris_prepare_jmp(dc, JMP_DIRECT);
2899 return 6;
2900 }
2901
2902 static int dec_rfe_etc(DisasContext *dc)
2903 {
2904 cris_cc_mask(dc, 0);
2905
2906 if (dc->op2 == 15) {
2907 t_gen_mov_env_TN(halted, tcg_const_tl(1));
2908 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2909 t_gen_raise_exception(EXCP_HLT);
2910 return 2;
2911 }
2912
2913 switch (dc->op2 & 7) {
2914 case 2:
2915 /* rfe. */
2916 LOG_DIS("rfe\n");
2917 cris_evaluate_flags(dc);
2918 gen_helper_rfe();
2919 dc->is_jmp = DISAS_UPDATE;
2920 break;
2921 case 5:
2922 /* rfn. */
2923 LOG_DIS("rfn\n");
2924 cris_evaluate_flags(dc);
2925 gen_helper_rfn();
2926 dc->is_jmp = DISAS_UPDATE;
2927 break;
2928 case 6:
2929 LOG_DIS("break %d\n", dc->op1);
2930 cris_evaluate_flags (dc);
2931 /* break. */
2932 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2933
2934 /* Breaks start at 16 in the exception vector. */
2935 t_gen_mov_env_TN(trap_vector,
2936 tcg_const_tl(dc->op1 + 16));
2937 t_gen_raise_exception(EXCP_BREAK);
2938 dc->is_jmp = DISAS_UPDATE;
2939 break;
2940 default:
2941 printf ("op2=%x\n", dc->op2);
2942 BUG();
2943 break;
2944
2945 }
2946 return 2;
2947 }
2948
2949 static int dec_ftag_fidx_d_m(DisasContext *dc)
2950 {
2951 return 2;
2952 }
2953
2954 static int dec_ftag_fidx_i_m(DisasContext *dc)
2955 {
2956 return 2;
2957 }
2958
2959 static int dec_null(DisasContext *dc)
2960 {
2961 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2962 dc->pc, dc->opcode, dc->op1, dc->op2);
2963 fflush(NULL);
2964 BUG();
2965 return 2;
2966 }
2967
2968 static struct decoder_info {
2969 struct {
2970 uint32_t bits;
2971 uint32_t mask;
2972 };
2973 int (*dec)(DisasContext *dc);
2974 } decinfo[] = {
2975 /* Order matters here. */
2976 {DEC_MOVEQ, dec_moveq},
2977 {DEC_BTSTQ, dec_btstq},
2978 {DEC_CMPQ, dec_cmpq},
2979 {DEC_ADDOQ, dec_addoq},
2980 {DEC_ADDQ, dec_addq},
2981 {DEC_SUBQ, dec_subq},
2982 {DEC_ANDQ, dec_andq},
2983 {DEC_ORQ, dec_orq},
2984 {DEC_ASRQ, dec_asrq},
2985 {DEC_LSLQ, dec_lslq},
2986 {DEC_LSRQ, dec_lsrq},
2987 {DEC_BCCQ, dec_bccq},
2988
2989 {DEC_BCC_IM, dec_bcc_im},
2990 {DEC_JAS_IM, dec_jas_im},
2991 {DEC_JAS_R, dec_jas_r},
2992 {DEC_JASC_IM, dec_jasc_im},
2993 {DEC_JASC_R, dec_jasc_r},
2994 {DEC_BAS_IM, dec_bas_im},
2995 {DEC_BASC_IM, dec_basc_im},
2996 {DEC_JUMP_P, dec_jump_p},
2997 {DEC_LAPC_IM, dec_lapc_im},
2998 {DEC_LAPCQ, dec_lapcq},
2999
3000 {DEC_RFE_ETC, dec_rfe_etc},
3001 {DEC_ADDC_MR, dec_addc_mr},
3002
3003 {DEC_MOVE_MP, dec_move_mp},
3004 {DEC_MOVE_PM, dec_move_pm},
3005 {DEC_MOVEM_MR, dec_movem_mr},
3006 {DEC_MOVEM_RM, dec_movem_rm},
3007 {DEC_MOVE_PR, dec_move_pr},
3008 {DEC_SCC_R, dec_scc_r},
3009 {DEC_SETF, dec_setclrf},
3010 {DEC_CLEARF, dec_setclrf},
3011
3012 {DEC_MOVE_SR, dec_move_sr},
3013 {DEC_MOVE_RP, dec_move_rp},
3014 {DEC_SWAP_R, dec_swap_r},
3015 {DEC_ABS_R, dec_abs_r},
3016 {DEC_LZ_R, dec_lz_r},
3017 {DEC_MOVE_RS, dec_move_rs},
3018 {DEC_BTST_R, dec_btst_r},
3019 {DEC_ADDC_R, dec_addc_r},
3020
3021 {DEC_DSTEP_R, dec_dstep_r},
3022 {DEC_XOR_R, dec_xor_r},
3023 {DEC_MCP_R, dec_mcp_r},
3024 {DEC_CMP_R, dec_cmp_r},
3025
3026 {DEC_ADDI_R, dec_addi_r},
3027 {DEC_ADDI_ACR, dec_addi_acr},
3028
3029 {DEC_ADD_R, dec_add_r},
3030 {DEC_SUB_R, dec_sub_r},
3031
3032 {DEC_ADDU_R, dec_addu_r},
3033 {DEC_ADDS_R, dec_adds_r},
3034 {DEC_SUBU_R, dec_subu_r},
3035 {DEC_SUBS_R, dec_subs_r},
3036 {DEC_LSL_R, dec_lsl_r},
3037
3038 {DEC_AND_R, dec_and_r},
3039 {DEC_OR_R, dec_or_r},
3040 {DEC_BOUND_R, dec_bound_r},
3041 {DEC_ASR_R, dec_asr_r},
3042 {DEC_LSR_R, dec_lsr_r},
3043
3044 {DEC_MOVU_R, dec_movu_r},
3045 {DEC_MOVS_R, dec_movs_r},
3046 {DEC_NEG_R, dec_neg_r},
3047 {DEC_MOVE_R, dec_move_r},
3048
3049 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3050 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3051
3052 {DEC_MULS_R, dec_muls_r},
3053 {DEC_MULU_R, dec_mulu_r},
3054
3055 {DEC_ADDU_M, dec_addu_m},
3056 {DEC_ADDS_M, dec_adds_m},
3057 {DEC_SUBU_M, dec_subu_m},
3058 {DEC_SUBS_M, dec_subs_m},
3059
3060 {DEC_CMPU_M, dec_cmpu_m},
3061 {DEC_CMPS_M, dec_cmps_m},
3062 {DEC_MOVU_M, dec_movu_m},
3063 {DEC_MOVS_M, dec_movs_m},
3064
3065 {DEC_CMP_M, dec_cmp_m},
3066 {DEC_ADDO_M, dec_addo_m},
3067 {DEC_BOUND_M, dec_bound_m},
3068 {DEC_ADD_M, dec_add_m},
3069 {DEC_SUB_M, dec_sub_m},
3070 {DEC_AND_M, dec_and_m},
3071 {DEC_OR_M, dec_or_m},
3072 {DEC_MOVE_RM, dec_move_rm},
3073 {DEC_TEST_M, dec_test_m},
3074 {DEC_MOVE_MR, dec_move_mr},
3075
3076 {{0, 0}, dec_null}
3077 };
3078
3079 static unsigned int crisv32_decoder(DisasContext *dc)
3080 {
3081 int insn_len = 2;
3082 int i;
3083
3084 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
3085 tcg_gen_debug_insn_start(dc->pc);
3086
3087 /* Load a halfword onto the instruction register. */
3088 dc->ir = cris_fetch(dc, dc->pc, 2, 0);
3089
3090 /* Now decode it. */
3091 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3092 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3093 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3094 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3095 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3096 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3097
3098 /* Large switch for all insns. */
3099 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3100 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3101 {
3102 insn_len = decinfo[i].dec(dc);
3103 break;
3104 }
3105 }
3106
3107 #if !defined(CONFIG_USER_ONLY)
3108 /* Single-stepping ? */
3109 if (dc->tb_flags & S_FLAG) {
3110 int l1;
3111
3112 l1 = gen_new_label();
3113 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3114 /* We treat SPC as a break with an odd trap vector. */
3115 cris_evaluate_flags (dc);
3116 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3117 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3118 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3119 t_gen_raise_exception(EXCP_BREAK);
3120 gen_set_label(l1);
3121 }
3122 #endif
3123 return insn_len;
3124 }
3125
3126 static void check_breakpoint(CPUState *env, DisasContext *dc)
3127 {
3128 CPUBreakpoint *bp;
3129
3130 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
3131 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3132 if (bp->pc == dc->pc) {
3133 cris_evaluate_flags (dc);
3134 tcg_gen_movi_tl(env_pc, dc->pc);
3135 t_gen_raise_exception(EXCP_DEBUG);
3136 dc->is_jmp = DISAS_UPDATE;
3137 }
3138 }
3139 }
3140 }
3141
3142 #include "translate_v10.c"
3143
3144 /*
3145 * Delay slots on QEMU/CRIS.
3146 *
3147 * If an exception hits on a delayslot, the core will let ERP (the Exception
3148 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3149 * to give SW a hint that the exception actually hit on the dslot.
3150 *
3151 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3152 * the core and any jmp to an odd addresses will mask off that lsb. It is
3153 * simply there to let sw know there was an exception on a dslot.
3154 *
3155 * When the software returns from an exception, the branch will re-execute.
3156 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3157 * and the branch and delayslot dont share pages.
3158 *
3159 * The TB contaning the branch insn will set up env->btarget and evaluate
3160 * env->btaken. When the translation loop exits we will note that the branch
3161 * sequence is broken and let env->dslot be the size of the branch insn (those
3162 * vary in length).
3163 *
3164 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3165 * set). It will also expect to have env->dslot setup with the size of the
3166 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3167 * will execute the dslot and take the branch, either to btarget or just one
3168 * insn ahead.
3169 *
3170 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3171 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3172 * branch and set lsb). Then env->dslot gets cleared so that the exception
3173 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3174 * masked off and we will reexecute the branch insn.
3175 *
3176 */
3177
3178 /* generate intermediate code for basic block 'tb'. */
3179 static void
3180 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3181 int search_pc)
3182 {
3183 uint16_t *gen_opc_end;
3184 uint32_t pc_start;
3185 unsigned int insn_len, orig_flags;
3186 int j, lj;
3187 struct DisasContext ctx;
3188 struct DisasContext *dc = &ctx;
3189 uint32_t next_page_start;
3190 target_ulong npc;
3191 int num_insns;
3192 int max_insns;
3193
3194 qemu_log_try_set_file(stderr);
3195
3196 if (env->pregs[PR_VR] == 32)
3197 dc->decoder = crisv32_decoder;
3198 else
3199 dc->decoder = crisv10_decoder;
3200
3201 /* Odd PC indicates that branch is rexecuting due to exception in the
3202 * delayslot, like in real hw.
3203 */
3204 pc_start = tb->pc & ~1;
3205 dc->env = env;
3206 dc->tb = tb;
3207
3208 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3209
3210 dc->is_jmp = DISAS_NEXT;
3211 dc->ppc = pc_start;
3212 dc->pc = pc_start;
3213 dc->singlestep_enabled = env->singlestep_enabled;
3214 dc->flags_uptodate = 1;
3215 dc->flagx_known = 1;
3216 dc->flags_x = tb->flags & X_FLAG;
3217 dc->cc_x_uptodate = 0;
3218 dc->cc_mask = 0;
3219 dc->update_cc = 0;
3220 dc->clear_prefix = 0;
3221 dc->clear_locked_irq = 1;
3222
3223 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3224 dc->cc_size_uptodate = -1;
3225
3226 /* Decode TB flags. */
3227 orig_flags = dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3228 | X_FLAG | PFIX_FLAG);
3229 dc->delayed_branch = !!(tb->flags & 7);
3230 if (dc->delayed_branch)
3231 dc->jmp = JMP_INDIRECT;
3232 else
3233 dc->jmp = JMP_NOJMP;
3234
3235 dc->cpustate_changed = 0;
3236
3237 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3238 qemu_log(
3239 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3240 "pid=%x usp=%x\n"
3241 "%x.%x.%x.%x\n"
3242 "%x.%x.%x.%x\n"
3243 "%x.%x.%x.%x\n"
3244 "%x.%x.%x.%x\n",
3245 search_pc, dc->pc, dc->ppc,
3246 (uint64_t)tb->flags,
3247 env->btarget, (unsigned)tb->flags & 7,
3248 env->pregs[PR_CCS],
3249 env->pregs[PR_PID], env->pregs[PR_USP],
3250 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3251 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3252 env->regs[8], env->regs[9],
3253 env->regs[10], env->regs[11],
3254 env->regs[12], env->regs[13],
3255 env->regs[14], env->regs[15]);
3256 qemu_log("--------------\n");
3257 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3258 }
3259
3260 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3261 lj = -1;
3262 num_insns = 0;
3263 max_insns = tb->cflags & CF_COUNT_MASK;
3264 if (max_insns == 0)
3265 max_insns = CF_COUNT_MASK;
3266
3267 gen_icount_start();
3268 do
3269 {
3270 check_breakpoint(env, dc);
3271
3272 if (search_pc) {
3273 j = gen_opc_ptr - gen_opc_buf;
3274 if (lj < j) {
3275 lj++;
3276 while (lj < j)
3277 gen_opc_instr_start[lj++] = 0;
3278 }
3279 if (dc->delayed_branch == 1)
3280 gen_opc_pc[lj] = dc->ppc | 1;
3281 else
3282 gen_opc_pc[lj] = dc->pc;
3283 gen_opc_instr_start[lj] = 1;
3284 gen_opc_icount[lj] = num_insns;
3285 }
3286
3287 /* Pretty disas. */
3288 LOG_DIS("%8.8x:\t", dc->pc);
3289
3290 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3291 gen_io_start();
3292 dc->clear_x = 1;
3293
3294 insn_len = dc->decoder(dc);
3295 dc->ppc = dc->pc;
3296 dc->pc += insn_len;
3297 if (dc->clear_x)
3298 cris_clear_x_flag(dc);
3299
3300 num_insns++;
3301 /* Check for delayed branches here. If we do it before
3302 actually generating any host code, the simulator will just
3303 loop doing nothing for on this program location. */
3304 if (dc->delayed_branch) {
3305 dc->delayed_branch--;
3306 if (dc->delayed_branch == 0)
3307 {
3308 if (tb->flags & 7)
3309 t_gen_mov_env_TN(dslot,
3310 tcg_const_tl(0));
3311 if (dc->cpustate_changed || !dc->flagx_known
3312 || (dc->flags_x != (tb->flags & X_FLAG))) {
3313 cris_store_direct_jmp(dc);
3314 }
3315 if (dc->jmp == JMP_DIRECT) {
3316 int l1;
3317
3318 l1 = gen_new_label();
3319 cris_evaluate_flags(dc);
3320
3321 /* Conditional jmp. */
3322 tcg_gen_brcondi_tl(TCG_COND_EQ,
3323 env_btaken, 0, l1);
3324 gen_goto_tb(dc, 1, dc->jmp_pc);
3325 gen_set_label(l1);
3326 gen_goto_tb(dc, 0, dc->pc);
3327 dc->is_jmp = DISAS_TB_JUMP;
3328 dc->jmp = JMP_NOJMP;
3329 } else {
3330 t_gen_cc_jmp(env_btarget,
3331 tcg_const_tl(dc->pc));
3332 dc->is_jmp = DISAS_JUMP;
3333 }
3334 break;
3335 }
3336 }
3337
3338 /* If we are rexecuting a branch due to exceptions on
3339 delay slots dont break. */
3340 if (!(tb->pc & 1) && env->singlestep_enabled)
3341 break;
3342 } while (!dc->is_jmp && !dc->cpustate_changed
3343 && gen_opc_ptr < gen_opc_end
3344 && !singlestep
3345 && (dc->pc < next_page_start)
3346 && num_insns < max_insns);
3347
3348 if (dc->clear_locked_irq)
3349 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3350
3351 npc = dc->pc;
3352
3353 if (tb->cflags & CF_LAST_IO)
3354 gen_io_end();
3355 /* Force an update if the per-tb cpu state has changed. */
3356 if (dc->is_jmp == DISAS_NEXT
3357 && (dc->cpustate_changed || !dc->flagx_known
3358 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3359 dc->is_jmp = DISAS_UPDATE;
3360 tcg_gen_movi_tl(env_pc, npc);
3361 }
3362 /* Broken branch+delayslot sequence. */
3363 if (dc->delayed_branch == 1) {
3364 /* Set env->dslot to the size of the branch insn. */
3365 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3366 cris_store_direct_jmp(dc);
3367 }
3368
3369 cris_evaluate_flags (dc);
3370
3371 if (unlikely(env->singlestep_enabled)) {
3372 if (dc->is_jmp == DISAS_NEXT)
3373 tcg_gen_movi_tl(env_pc, npc);
3374 t_gen_raise_exception(EXCP_DEBUG);
3375 } else {
3376 switch(dc->is_jmp) {
3377 case DISAS_NEXT:
3378 gen_goto_tb(dc, 1, npc);
3379 break;
3380 default:
3381 case DISAS_JUMP:
3382 case DISAS_UPDATE:
3383 /* indicate that the hash table must be used
3384 to find the next TB */
3385 tcg_gen_exit_tb(0);
3386 break;
3387 case DISAS_SWI:
3388 case DISAS_TB_JUMP:
3389 /* nothing more to generate */
3390 break;
3391 }
3392 }
3393 gen_icount_end(tb, num_insns);
3394 *gen_opc_ptr = INDEX_op_end;
3395 if (search_pc) {
3396 j = gen_opc_ptr - gen_opc_buf;
3397 lj++;
3398 while (lj <= j)
3399 gen_opc_instr_start[lj++] = 0;
3400 } else {
3401 tb->size = dc->pc - pc_start;
3402 tb->icount = num_insns;
3403 }
3404
3405 #ifdef DEBUG_DISAS
3406 #if !DISAS_CRIS
3407 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3408 log_target_disas(pc_start, dc->pc - pc_start,
3409 dc->env->pregs[PR_VR]);
3410 qemu_log("\nisize=%d osize=%td\n",
3411 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3412 }
3413 #endif
3414 #endif
3415 }
3416
3417 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3418 {
3419 gen_intermediate_code_internal(env, tb, 0);
3420 }
3421
3422 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3423 {
3424 gen_intermediate_code_internal(env, tb, 1);
3425 }
3426
3427 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
3428 int flags)
3429 {
3430 int i;
3431 uint32_t srs;
3432
3433 if (!env || !f)
3434 return;
3435
3436 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3437 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3438 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3439 env->cc_op,
3440 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3441
3442
3443 for (i = 0; i < 16; i++) {
3444 cpu_fprintf(f, "%s=%8.8x ",regnames[i], env->regs[i]);
3445 if ((i + 1) % 4 == 0)
3446 cpu_fprintf(f, "\n");
3447 }
3448 cpu_fprintf(f, "\nspecial regs:\n");
3449 for (i = 0; i < 16; i++) {
3450 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3451 if ((i + 1) % 4 == 0)
3452 cpu_fprintf(f, "\n");
3453 }
3454 srs = env->pregs[PR_SRS];
3455 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3456 if (srs < 256) {
3457 for (i = 0; i < 16; i++) {
3458 cpu_fprintf(f, "s%2.2d=%8.8x ",
3459 i, env->sregs[srs][i]);
3460 if ((i + 1) % 4 == 0)
3461 cpu_fprintf(f, "\n");
3462 }
3463 }
3464 cpu_fprintf(f, "\n\n");
3465
3466 }
3467
3468 struct
3469 {
3470 uint32_t vr;
3471 const char *name;
3472 } cris_cores[] = {
3473 {8, "crisv8"},
3474 {9, "crisv9"},
3475 {10, "crisv10"},
3476 {11, "crisv11"},
3477 {32, "crisv32"},
3478 };
3479
3480 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3481 {
3482 unsigned int i;
3483
3484 (*cpu_fprintf)(f, "Available CPUs:\n");
3485 for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
3486 (*cpu_fprintf)(f, " %s\n", cris_cores[i].name);
3487 }
3488 }
3489
3490 static uint32_t vr_by_name(const char *name)
3491 {
3492 unsigned int i;
3493 for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
3494 if (strcmp(name, cris_cores[i].name) == 0) {
3495 return cris_cores[i].vr;
3496 }
3497 }
3498 return 32;
3499 }
3500
3501 CPUCRISState *cpu_cris_init (const char *cpu_model)
3502 {
3503 CPUCRISState *env;
3504 static int tcg_initialized = 0;
3505 int i;
3506
3507 env = qemu_mallocz(sizeof(CPUCRISState));
3508
3509 env->pregs[PR_VR] = vr_by_name(cpu_model);
3510 cpu_exec_init(env);
3511 cpu_reset(env);
3512 qemu_init_vcpu(env);
3513
3514 if (tcg_initialized)
3515 return env;
3516
3517 tcg_initialized = 1;
3518
3519 #define GEN_HELPER 2
3520 #include "helper.h"
3521
3522 if (env->pregs[PR_VR] < 32) {
3523 cpu_crisv10_init(env);
3524 return env;
3525 }
3526
3527
3528 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3529 cc_x = tcg_global_mem_new(TCG_AREG0,
3530 offsetof(CPUState, cc_x), "cc_x");
3531 cc_src = tcg_global_mem_new(TCG_AREG0,
3532 offsetof(CPUState, cc_src), "cc_src");
3533 cc_dest = tcg_global_mem_new(TCG_AREG0,
3534 offsetof(CPUState, cc_dest),
3535 "cc_dest");
3536 cc_result = tcg_global_mem_new(TCG_AREG0,
3537 offsetof(CPUState, cc_result),
3538 "cc_result");
3539 cc_op = tcg_global_mem_new(TCG_AREG0,
3540 offsetof(CPUState, cc_op), "cc_op");
3541 cc_size = tcg_global_mem_new(TCG_AREG0,
3542 offsetof(CPUState, cc_size),
3543 "cc_size");
3544 cc_mask = tcg_global_mem_new(TCG_AREG0,
3545 offsetof(CPUState, cc_mask),
3546 "cc_mask");
3547
3548 env_pc = tcg_global_mem_new(TCG_AREG0,
3549 offsetof(CPUState, pc),
3550 "pc");
3551 env_btarget = tcg_global_mem_new(TCG_AREG0,
3552 offsetof(CPUState, btarget),
3553 "btarget");
3554 env_btaken = tcg_global_mem_new(TCG_AREG0,
3555 offsetof(CPUState, btaken),
3556 "btaken");
3557 for (i = 0; i < 16; i++) {
3558 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3559 offsetof(CPUState, regs[i]),
3560 regnames[i]);
3561 }
3562 for (i = 0; i < 16; i++) {
3563 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3564 offsetof(CPUState, pregs[i]),
3565 pregnames[i]);
3566 }
3567
3568 return env;
3569 }
3570
3571 void cpu_reset (CPUCRISState *env)
3572 {
3573 uint32_t vr;
3574
3575 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
3576 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
3577 log_cpu_state(env, 0);
3578 }
3579
3580 vr = env->pregs[PR_VR];
3581 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3582 env->pregs[PR_VR] = vr;
3583 tlb_flush(env, 1);
3584
3585 #if defined(CONFIG_USER_ONLY)
3586 /* start in user mode with interrupts enabled. */
3587 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
3588 #else
3589 cris_mmu_init(env);
3590 env->pregs[PR_CCS] = 0;
3591 #endif
3592 }
3593
3594 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3595 unsigned long searched_pc, int pc_pos, void *puc)
3596 {
3597 env->pc = gen_opc_pc[pc_pos];
3598 }
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