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apic: Store X86CPU in APICCommonState
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "kvm.h"
26
27 #include "qemu-option.h"
28 #include "qemu-config.h"
29
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
32
33 #include "hyperv.h"
34
35 #include "hw/hw.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
38 #endif
39
40 #include "sysemu.h"
41 #ifndef CONFIG_USER_ONLY
42 #include "hw/xen.h"
43 #include "hw/sysbus.h"
44 #include "hw/apic_internal.h"
45 #endif
46
47 /* feature flags taken from "Intel Processor Identification and the CPUID
48 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
49 * between feature naming conventions, aliases may be added.
50 */
51 static const char *feature_name[] = {
52 "fpu", "vme", "de", "pse",
53 "tsc", "msr", "pae", "mce",
54 "cx8", "apic", NULL, "sep",
55 "mtrr", "pge", "mca", "cmov",
56 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
57 NULL, "ds" /* Intel dts */, "acpi", "mmx",
58 "fxsr", "sse", "sse2", "ss",
59 "ht" /* Intel htt */, "tm", "ia64", "pbe",
60 };
61 static const char *ext_feature_name[] = {
62 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
63 "ds_cpl", "vmx", "smx", "est",
64 "tm2", "ssse3", "cid", NULL,
65 "fma", "cx16", "xtpr", "pdcm",
66 NULL, "pcid", "dca", "sse4.1|sse4_1",
67 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
68 "tsc-deadline", "aes", "xsave", "osxsave",
69 "avx", NULL, NULL, "hypervisor",
70 };
71 /* Feature names that are already defined on feature_name[] but are set on
72 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
73 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
74 * if and only if CPU vendor is AMD.
75 */
76 static const char *ext2_feature_name[] = {
77 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
78 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
79 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
80 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
81 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
82 "nx|xd", NULL, "mmxext", NULL /* mmx */,
83 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
84 NULL, "lm|i64", "3dnowext", "3dnow",
85 };
86 static const char *ext3_feature_name[] = {
87 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
88 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
89 "3dnowprefetch", "osvw", "ibs", "xop",
90 "skinit", "wdt", NULL, NULL,
91 "fma4", NULL, "cvt16", "nodeid_msr",
92 NULL, NULL, NULL, NULL,
93 NULL, NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95 };
96
97 static const char *kvm_feature_name[] = {
98 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL,
99 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
100 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
101 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
102 };
103
104 static const char *svm_feature_name[] = {
105 "npt", "lbrv", "svm_lock", "nrip_save",
106 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
107 NULL, NULL, "pause_filter", NULL,
108 "pfthreshold", NULL, NULL, NULL,
109 NULL, NULL, NULL, NULL,
110 NULL, NULL, NULL, NULL,
111 NULL, NULL, NULL, NULL,
112 NULL, NULL, NULL, NULL,
113 };
114
115 static const char *cpuid_7_0_ebx_feature_name[] = {
116 NULL, NULL, NULL, NULL, NULL, NULL, NULL, "smep",
117 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
120 };
121
122 /* collects per-function cpuid data
123 */
124 typedef struct model_features_t {
125 uint32_t *guest_feat;
126 uint32_t *host_feat;
127 uint32_t check_feat;
128 const char **flag_names;
129 uint32_t cpuid;
130 } model_features_t;
131
132 int check_cpuid = 0;
133 int enforce_cpuid = 0;
134
135 #if defined(CONFIG_KVM)
136 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
137 (1 << KVM_FEATURE_NOP_IO_DELAY) |
138 (1 << KVM_FEATURE_MMU_OP) |
139 (1 << KVM_FEATURE_CLOCKSOURCE2) |
140 (1 << KVM_FEATURE_ASYNC_PF) |
141 (1 << KVM_FEATURE_STEAL_TIME) |
142 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
143 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
144 #else
145 static uint32_t kvm_default_features = 0;
146 static const uint32_t kvm_pv_eoi_features = 0;
147 #endif
148
149 void enable_kvm_pv_eoi(void)
150 {
151 kvm_default_features |= kvm_pv_eoi_features;
152 }
153
154 void host_cpuid(uint32_t function, uint32_t count,
155 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
156 {
157 #if defined(CONFIG_KVM)
158 uint32_t vec[4];
159
160 #ifdef __x86_64__
161 asm volatile("cpuid"
162 : "=a"(vec[0]), "=b"(vec[1]),
163 "=c"(vec[2]), "=d"(vec[3])
164 : "0"(function), "c"(count) : "cc");
165 #else
166 asm volatile("pusha \n\t"
167 "cpuid \n\t"
168 "mov %%eax, 0(%2) \n\t"
169 "mov %%ebx, 4(%2) \n\t"
170 "mov %%ecx, 8(%2) \n\t"
171 "mov %%edx, 12(%2) \n\t"
172 "popa"
173 : : "a"(function), "c"(count), "S"(vec)
174 : "memory", "cc");
175 #endif
176
177 if (eax)
178 *eax = vec[0];
179 if (ebx)
180 *ebx = vec[1];
181 if (ecx)
182 *ecx = vec[2];
183 if (edx)
184 *edx = vec[3];
185 #endif
186 }
187
188 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
189
190 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
191 * a substring. ex if !NULL points to the first char after a substring,
192 * otherwise the string is assumed to sized by a terminating nul.
193 * Return lexical ordering of *s1:*s2.
194 */
195 static int sstrcmp(const char *s1, const char *e1, const char *s2,
196 const char *e2)
197 {
198 for (;;) {
199 if (!*s1 || !*s2 || *s1 != *s2)
200 return (*s1 - *s2);
201 ++s1, ++s2;
202 if (s1 == e1 && s2 == e2)
203 return (0);
204 else if (s1 == e1)
205 return (*s2);
206 else if (s2 == e2)
207 return (*s1);
208 }
209 }
210
211 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
212 * '|' delimited (possibly empty) strings in which case search for a match
213 * within the alternatives proceeds left to right. Return 0 for success,
214 * non-zero otherwise.
215 */
216 static int altcmp(const char *s, const char *e, const char *altstr)
217 {
218 const char *p, *q;
219
220 for (q = p = altstr; ; ) {
221 while (*p && *p != '|')
222 ++p;
223 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
224 return (0);
225 if (!*p)
226 return (1);
227 else
228 q = ++p;
229 }
230 }
231
232 /* search featureset for flag *[s..e), if found set corresponding bit in
233 * *pval and return true, otherwise return false
234 */
235 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
236 const char **featureset)
237 {
238 uint32_t mask;
239 const char **ppc;
240 bool found = false;
241
242 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
243 if (*ppc && !altcmp(s, e, *ppc)) {
244 *pval |= mask;
245 found = true;
246 }
247 }
248 return found;
249 }
250
251 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
252 uint32_t *ext_features,
253 uint32_t *ext2_features,
254 uint32_t *ext3_features,
255 uint32_t *kvm_features,
256 uint32_t *svm_features,
257 uint32_t *cpuid_7_0_ebx_features)
258 {
259 if (!lookup_feature(features, flagname, NULL, feature_name) &&
260 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
261 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
262 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
263 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
264 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
265 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
266 cpuid_7_0_ebx_feature_name))
267 fprintf(stderr, "CPU feature %s not found\n", flagname);
268 }
269
270 typedef struct x86_def_t {
271 struct x86_def_t *next;
272 const char *name;
273 uint32_t level;
274 uint32_t vendor1, vendor2, vendor3;
275 int family;
276 int model;
277 int stepping;
278 int tsc_khz;
279 uint32_t features, ext_features, ext2_features, ext3_features;
280 uint32_t kvm_features, svm_features;
281 uint32_t xlevel;
282 char model_id[48];
283 int vendor_override;
284 /* Store the results of Centaur's CPUID instructions */
285 uint32_t ext4_features;
286 uint32_t xlevel2;
287 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
288 uint32_t cpuid_7_0_ebx_features;
289 } x86_def_t;
290
291 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
292 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
293 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
294 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
295 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
296 CPUID_PSE36 | CPUID_FXSR)
297 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
298 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
299 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
300 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
301 CPUID_PAE | CPUID_SEP | CPUID_APIC)
302
303 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
304 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
305 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
306 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
307 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
308 /* partly implemented:
309 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
310 CPUID_PSE36 (needed for Solaris) */
311 /* missing:
312 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
313 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
314 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
315 CPUID_EXT_HYPERVISOR)
316 /* missing:
317 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
318 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
319 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
320 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
321 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
322 /* missing:
323 CPUID_EXT2_PDPE1GB */
324 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
325 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
326 #define TCG_SVM_FEATURES 0
327 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
328
329 /* maintains list of cpu model definitions
330 */
331 static x86_def_t *x86_defs = {NULL};
332
333 /* built-in cpu model definitions (deprecated)
334 */
335 static x86_def_t builtin_x86_defs[] = {
336 {
337 .name = "qemu64",
338 .level = 4,
339 .vendor1 = CPUID_VENDOR_AMD_1,
340 .vendor2 = CPUID_VENDOR_AMD_2,
341 .vendor3 = CPUID_VENDOR_AMD_3,
342 .family = 6,
343 .model = 2,
344 .stepping = 3,
345 .features = PPRO_FEATURES |
346 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
347 CPUID_PSE36,
348 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
349 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
350 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
351 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
352 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
353 .xlevel = 0x8000000A,
354 },
355 {
356 .name = "phenom",
357 .level = 5,
358 .vendor1 = CPUID_VENDOR_AMD_1,
359 .vendor2 = CPUID_VENDOR_AMD_2,
360 .vendor3 = CPUID_VENDOR_AMD_3,
361 .family = 16,
362 .model = 2,
363 .stepping = 3,
364 .features = PPRO_FEATURES |
365 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
366 CPUID_PSE36 | CPUID_VME | CPUID_HT,
367 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
368 CPUID_EXT_POPCNT,
369 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
370 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
371 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
372 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
373 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
374 CPUID_EXT3_CR8LEG,
375 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
376 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
377 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
378 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
379 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
380 .xlevel = 0x8000001A,
381 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
382 },
383 {
384 .name = "core2duo",
385 .level = 10,
386 .family = 6,
387 .model = 15,
388 .stepping = 11,
389 .features = PPRO_FEATURES |
390 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
391 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
392 CPUID_HT | CPUID_TM | CPUID_PBE,
393 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
394 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
395 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
396 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
397 .ext3_features = CPUID_EXT3_LAHF_LM,
398 .xlevel = 0x80000008,
399 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
400 },
401 {
402 .name = "kvm64",
403 .level = 5,
404 .vendor1 = CPUID_VENDOR_INTEL_1,
405 .vendor2 = CPUID_VENDOR_INTEL_2,
406 .vendor3 = CPUID_VENDOR_INTEL_3,
407 .family = 15,
408 .model = 6,
409 .stepping = 1,
410 /* Missing: CPUID_VME, CPUID_HT */
411 .features = PPRO_FEATURES |
412 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
413 CPUID_PSE36,
414 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
415 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
416 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
417 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
418 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
419 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
420 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
421 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
422 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
423 .ext3_features = 0,
424 .xlevel = 0x80000008,
425 .model_id = "Common KVM processor"
426 },
427 {
428 .name = "qemu32",
429 .level = 4,
430 .family = 6,
431 .model = 3,
432 .stepping = 3,
433 .features = PPRO_FEATURES,
434 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
435 .xlevel = 0x80000004,
436 },
437 {
438 .name = "kvm32",
439 .level = 5,
440 .family = 15,
441 .model = 6,
442 .stepping = 1,
443 .features = PPRO_FEATURES |
444 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
445 .ext_features = CPUID_EXT_SSE3,
446 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
447 .ext3_features = 0,
448 .xlevel = 0x80000008,
449 .model_id = "Common 32-bit KVM processor"
450 },
451 {
452 .name = "coreduo",
453 .level = 10,
454 .family = 6,
455 .model = 14,
456 .stepping = 8,
457 .features = PPRO_FEATURES | CPUID_VME |
458 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
459 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
460 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
461 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
462 .ext2_features = CPUID_EXT2_NX,
463 .xlevel = 0x80000008,
464 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
465 },
466 {
467 .name = "486",
468 .level = 1,
469 .family = 4,
470 .model = 0,
471 .stepping = 0,
472 .features = I486_FEATURES,
473 .xlevel = 0,
474 },
475 {
476 .name = "pentium",
477 .level = 1,
478 .family = 5,
479 .model = 4,
480 .stepping = 3,
481 .features = PENTIUM_FEATURES,
482 .xlevel = 0,
483 },
484 {
485 .name = "pentium2",
486 .level = 2,
487 .family = 6,
488 .model = 5,
489 .stepping = 2,
490 .features = PENTIUM2_FEATURES,
491 .xlevel = 0,
492 },
493 {
494 .name = "pentium3",
495 .level = 2,
496 .family = 6,
497 .model = 7,
498 .stepping = 3,
499 .features = PENTIUM3_FEATURES,
500 .xlevel = 0,
501 },
502 {
503 .name = "athlon",
504 .level = 2,
505 .vendor1 = CPUID_VENDOR_AMD_1,
506 .vendor2 = CPUID_VENDOR_AMD_2,
507 .vendor3 = CPUID_VENDOR_AMD_3,
508 .family = 6,
509 .model = 2,
510 .stepping = 3,
511 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
512 CPUID_MCA,
513 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
514 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
515 .xlevel = 0x80000008,
516 },
517 {
518 .name = "n270",
519 /* original is on level 10 */
520 .level = 5,
521 .family = 6,
522 .model = 28,
523 .stepping = 2,
524 .features = PPRO_FEATURES |
525 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
526 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
527 /* Some CPUs got no CPUID_SEP */
528 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
529 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
530 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
531 CPUID_EXT2_NX,
532 .ext3_features = CPUID_EXT3_LAHF_LM,
533 .xlevel = 0x8000000A,
534 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
535 },
536 {
537 .name = "Conroe",
538 .level = 2,
539 .vendor1 = CPUID_VENDOR_INTEL_1,
540 .vendor2 = CPUID_VENDOR_INTEL_2,
541 .vendor3 = CPUID_VENDOR_INTEL_3,
542 .family = 6,
543 .model = 2,
544 .stepping = 3,
545 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
546 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
547 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
548 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
549 CPUID_DE | CPUID_FP87,
550 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
551 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
552 .ext3_features = CPUID_EXT3_LAHF_LM,
553 .xlevel = 0x8000000A,
554 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
555 },
556 {
557 .name = "Penryn",
558 .level = 2,
559 .vendor1 = CPUID_VENDOR_INTEL_1,
560 .vendor2 = CPUID_VENDOR_INTEL_2,
561 .vendor3 = CPUID_VENDOR_INTEL_3,
562 .family = 6,
563 .model = 2,
564 .stepping = 3,
565 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
566 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
567 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
568 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
569 CPUID_DE | CPUID_FP87,
570 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
571 CPUID_EXT_SSE3,
572 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
573 .ext3_features = CPUID_EXT3_LAHF_LM,
574 .xlevel = 0x8000000A,
575 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
576 },
577 {
578 .name = "Nehalem",
579 .level = 2,
580 .vendor1 = CPUID_VENDOR_INTEL_1,
581 .vendor2 = CPUID_VENDOR_INTEL_2,
582 .vendor3 = CPUID_VENDOR_INTEL_3,
583 .family = 6,
584 .model = 2,
585 .stepping = 3,
586 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
587 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
588 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
589 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
590 CPUID_DE | CPUID_FP87,
591 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
592 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
593 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
594 .ext3_features = CPUID_EXT3_LAHF_LM,
595 .xlevel = 0x8000000A,
596 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
597 },
598 {
599 .name = "Westmere",
600 .level = 11,
601 .vendor1 = CPUID_VENDOR_INTEL_1,
602 .vendor2 = CPUID_VENDOR_INTEL_2,
603 .vendor3 = CPUID_VENDOR_INTEL_3,
604 .family = 6,
605 .model = 44,
606 .stepping = 1,
607 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
608 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
609 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
610 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
611 CPUID_DE | CPUID_FP87,
612 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
613 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
614 CPUID_EXT_SSE3,
615 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
616 .ext3_features = CPUID_EXT3_LAHF_LM,
617 .xlevel = 0x8000000A,
618 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
619 },
620 {
621 .name = "SandyBridge",
622 .level = 0xd,
623 .vendor1 = CPUID_VENDOR_INTEL_1,
624 .vendor2 = CPUID_VENDOR_INTEL_2,
625 .vendor3 = CPUID_VENDOR_INTEL_3,
626 .family = 6,
627 .model = 42,
628 .stepping = 1,
629 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
630 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
631 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
632 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
633 CPUID_DE | CPUID_FP87,
634 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
635 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
636 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
637 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
638 CPUID_EXT_SSE3,
639 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
640 CPUID_EXT2_SYSCALL,
641 .ext3_features = CPUID_EXT3_LAHF_LM,
642 .xlevel = 0x8000000A,
643 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
644 },
645 {
646 .name = "Opteron_G1",
647 .level = 5,
648 .vendor1 = CPUID_VENDOR_AMD_1,
649 .vendor2 = CPUID_VENDOR_AMD_2,
650 .vendor3 = CPUID_VENDOR_AMD_3,
651 .family = 15,
652 .model = 6,
653 .stepping = 1,
654 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
655 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
656 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
657 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
658 CPUID_DE | CPUID_FP87,
659 .ext_features = CPUID_EXT_SSE3,
660 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
661 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
662 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
663 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
664 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
665 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
666 .xlevel = 0x80000008,
667 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
668 },
669 {
670 .name = "Opteron_G2",
671 .level = 5,
672 .vendor1 = CPUID_VENDOR_AMD_1,
673 .vendor2 = CPUID_VENDOR_AMD_2,
674 .vendor3 = CPUID_VENDOR_AMD_3,
675 .family = 15,
676 .model = 6,
677 .stepping = 1,
678 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
679 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
680 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
681 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
682 CPUID_DE | CPUID_FP87,
683 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
684 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
685 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
686 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
687 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
688 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
689 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
690 CPUID_EXT2_DE | CPUID_EXT2_FPU,
691 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
692 .xlevel = 0x80000008,
693 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
694 },
695 {
696 .name = "Opteron_G3",
697 .level = 5,
698 .vendor1 = CPUID_VENDOR_AMD_1,
699 .vendor2 = CPUID_VENDOR_AMD_2,
700 .vendor3 = CPUID_VENDOR_AMD_3,
701 .family = 15,
702 .model = 6,
703 .stepping = 1,
704 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
705 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
706 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
707 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
708 CPUID_DE | CPUID_FP87,
709 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
710 CPUID_EXT_SSE3,
711 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
712 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
713 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
714 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
715 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
716 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
717 CPUID_EXT2_DE | CPUID_EXT2_FPU,
718 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
719 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
720 .xlevel = 0x80000008,
721 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
722 },
723 {
724 .name = "Opteron_G4",
725 .level = 0xd,
726 .vendor1 = CPUID_VENDOR_AMD_1,
727 .vendor2 = CPUID_VENDOR_AMD_2,
728 .vendor3 = CPUID_VENDOR_AMD_3,
729 .family = 21,
730 .model = 1,
731 .stepping = 2,
732 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
733 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
734 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
735 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
736 CPUID_DE | CPUID_FP87,
737 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
738 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
739 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
740 CPUID_EXT_SSE3,
741 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
742 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
743 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
744 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
745 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
746 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
747 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
748 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
749 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
750 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
751 CPUID_EXT3_LAHF_LM,
752 .xlevel = 0x8000001A,
753 .model_id = "AMD Opteron 62xx class CPU",
754 },
755 };
756
757 static int cpu_x86_fill_model_id(char *str)
758 {
759 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
760 int i;
761
762 for (i = 0; i < 3; i++) {
763 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
764 memcpy(str + i * 16 + 0, &eax, 4);
765 memcpy(str + i * 16 + 4, &ebx, 4);
766 memcpy(str + i * 16 + 8, &ecx, 4);
767 memcpy(str + i * 16 + 12, &edx, 4);
768 }
769 return 0;
770 }
771
772 static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
773 {
774 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
775
776 x86_cpu_def->name = "host";
777 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
778 x86_cpu_def->level = eax;
779 x86_cpu_def->vendor1 = ebx;
780 x86_cpu_def->vendor2 = edx;
781 x86_cpu_def->vendor3 = ecx;
782
783 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
784 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
785 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
786 x86_cpu_def->stepping = eax & 0x0F;
787 x86_cpu_def->ext_features = ecx;
788 x86_cpu_def->features = edx;
789
790 if (kvm_enabled() && x86_cpu_def->level >= 7) {
791 x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);
792 } else {
793 x86_cpu_def->cpuid_7_0_ebx_features = 0;
794 }
795
796 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
797 x86_cpu_def->xlevel = eax;
798
799 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
800 x86_cpu_def->ext2_features = edx;
801 x86_cpu_def->ext3_features = ecx;
802 cpu_x86_fill_model_id(x86_cpu_def->model_id);
803 x86_cpu_def->vendor_override = 0;
804
805 /* Call Centaur's CPUID instruction. */
806 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
807 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
808 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
809 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
810 if (eax >= 0xC0000001) {
811 /* Support VIA max extended level */
812 x86_cpu_def->xlevel2 = eax;
813 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
814 x86_cpu_def->ext4_features = edx;
815 }
816 }
817
818 /*
819 * Every SVM feature requires emulation support in KVM - so we can't just
820 * read the host features here. KVM might even support SVM features not
821 * available on the host hardware. Just set all bits and mask out the
822 * unsupported ones later.
823 */
824 x86_cpu_def->svm_features = -1;
825
826 return 0;
827 }
828
829 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
830 {
831 int i;
832
833 for (i = 0; i < 32; ++i)
834 if (1 << i & mask) {
835 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
836 " flag '%s' [0x%08x]\n",
837 f->cpuid >> 16, f->cpuid & 0xffff,
838 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
839 break;
840 }
841 return 0;
842 }
843
844 /* best effort attempt to inform user requested cpu flags aren't making
845 * their way to the guest. Note: ft[].check_feat ideally should be
846 * specified via a guest_def field to suppress report of extraneous flags.
847 */
848 static int check_features_against_host(x86_def_t *guest_def)
849 {
850 x86_def_t host_def;
851 uint32_t mask;
852 int rv, i;
853 struct model_features_t ft[] = {
854 {&guest_def->features, &host_def.features,
855 ~0, feature_name, 0x00000000},
856 {&guest_def->ext_features, &host_def.ext_features,
857 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
858 {&guest_def->ext2_features, &host_def.ext2_features,
859 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
860 {&guest_def->ext3_features, &host_def.ext3_features,
861 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
862
863 cpu_x86_fill_host(&host_def);
864 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
865 for (mask = 1; mask; mask <<= 1)
866 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
867 !(*ft[i].host_feat & mask)) {
868 unavailable_host_feature(&ft[i], mask);
869 rv = 1;
870 }
871 return rv;
872 }
873
874 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
875 const char *name, Error **errp)
876 {
877 X86CPU *cpu = X86_CPU(obj);
878 CPUX86State *env = &cpu->env;
879 int64_t value;
880
881 value = (env->cpuid_version >> 8) & 0xf;
882 if (value == 0xf) {
883 value += (env->cpuid_version >> 20) & 0xff;
884 }
885 visit_type_int(v, &value, name, errp);
886 }
887
888 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
889 const char *name, Error **errp)
890 {
891 X86CPU *cpu = X86_CPU(obj);
892 CPUX86State *env = &cpu->env;
893 const int64_t min = 0;
894 const int64_t max = 0xff + 0xf;
895 int64_t value;
896
897 visit_type_int(v, &value, name, errp);
898 if (error_is_set(errp)) {
899 return;
900 }
901 if (value < min || value > max) {
902 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
903 name ? name : "null", value, min, max);
904 return;
905 }
906
907 env->cpuid_version &= ~0xff00f00;
908 if (value > 0x0f) {
909 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
910 } else {
911 env->cpuid_version |= value << 8;
912 }
913 }
914
915 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
916 const char *name, Error **errp)
917 {
918 X86CPU *cpu = X86_CPU(obj);
919 CPUX86State *env = &cpu->env;
920 int64_t value;
921
922 value = (env->cpuid_version >> 4) & 0xf;
923 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
924 visit_type_int(v, &value, name, errp);
925 }
926
927 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
928 const char *name, Error **errp)
929 {
930 X86CPU *cpu = X86_CPU(obj);
931 CPUX86State *env = &cpu->env;
932 const int64_t min = 0;
933 const int64_t max = 0xff;
934 int64_t value;
935
936 visit_type_int(v, &value, name, errp);
937 if (error_is_set(errp)) {
938 return;
939 }
940 if (value < min || value > max) {
941 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
942 name ? name : "null", value, min, max);
943 return;
944 }
945
946 env->cpuid_version &= ~0xf00f0;
947 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
948 }
949
950 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
951 void *opaque, const char *name,
952 Error **errp)
953 {
954 X86CPU *cpu = X86_CPU(obj);
955 CPUX86State *env = &cpu->env;
956 int64_t value;
957
958 value = env->cpuid_version & 0xf;
959 visit_type_int(v, &value, name, errp);
960 }
961
962 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
963 void *opaque, const char *name,
964 Error **errp)
965 {
966 X86CPU *cpu = X86_CPU(obj);
967 CPUX86State *env = &cpu->env;
968 const int64_t min = 0;
969 const int64_t max = 0xf;
970 int64_t value;
971
972 visit_type_int(v, &value, name, errp);
973 if (error_is_set(errp)) {
974 return;
975 }
976 if (value < min || value > max) {
977 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
978 name ? name : "null", value, min, max);
979 return;
980 }
981
982 env->cpuid_version &= ~0xf;
983 env->cpuid_version |= value & 0xf;
984 }
985
986 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
987 const char *name, Error **errp)
988 {
989 X86CPU *cpu = X86_CPU(obj);
990
991 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
992 }
993
994 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
995 const char *name, Error **errp)
996 {
997 X86CPU *cpu = X86_CPU(obj);
998
999 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1000 }
1001
1002 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1003 const char *name, Error **errp)
1004 {
1005 X86CPU *cpu = X86_CPU(obj);
1006
1007 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1008 }
1009
1010 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1011 const char *name, Error **errp)
1012 {
1013 X86CPU *cpu = X86_CPU(obj);
1014
1015 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1016 }
1017
1018 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1019 {
1020 X86CPU *cpu = X86_CPU(obj);
1021 CPUX86State *env = &cpu->env;
1022 char *value;
1023 int i;
1024
1025 value = (char *)g_malloc(12 + 1);
1026 for (i = 0; i < 4; i++) {
1027 value[i ] = env->cpuid_vendor1 >> (8 * i);
1028 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1029 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1030 }
1031 value[12] = '\0';
1032 return value;
1033 }
1034
1035 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1036 Error **errp)
1037 {
1038 X86CPU *cpu = X86_CPU(obj);
1039 CPUX86State *env = &cpu->env;
1040 int i;
1041
1042 if (strlen(value) != 12) {
1043 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1044 "vendor", value);
1045 return;
1046 }
1047
1048 env->cpuid_vendor1 = 0;
1049 env->cpuid_vendor2 = 0;
1050 env->cpuid_vendor3 = 0;
1051 for (i = 0; i < 4; i++) {
1052 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1053 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1054 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1055 }
1056 env->cpuid_vendor_override = 1;
1057 }
1058
1059 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1060 {
1061 X86CPU *cpu = X86_CPU(obj);
1062 CPUX86State *env = &cpu->env;
1063 char *value;
1064 int i;
1065
1066 value = g_malloc(48 + 1);
1067 for (i = 0; i < 48; i++) {
1068 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1069 }
1070 value[48] = '\0';
1071 return value;
1072 }
1073
1074 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1075 Error **errp)
1076 {
1077 X86CPU *cpu = X86_CPU(obj);
1078 CPUX86State *env = &cpu->env;
1079 int c, len, i;
1080
1081 if (model_id == NULL) {
1082 model_id = "";
1083 }
1084 len = strlen(model_id);
1085 memset(env->cpuid_model, 0, 48);
1086 for (i = 0; i < 48; i++) {
1087 if (i >= len) {
1088 c = '\0';
1089 } else {
1090 c = (uint8_t)model_id[i];
1091 }
1092 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1093 }
1094 }
1095
1096 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1097 const char *name, Error **errp)
1098 {
1099 X86CPU *cpu = X86_CPU(obj);
1100 int64_t value;
1101
1102 value = cpu->env.tsc_khz * 1000;
1103 visit_type_int(v, &value, name, errp);
1104 }
1105
1106 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1107 const char *name, Error **errp)
1108 {
1109 X86CPU *cpu = X86_CPU(obj);
1110 const int64_t min = 0;
1111 const int64_t max = INT64_MAX;
1112 int64_t value;
1113
1114 visit_type_int(v, &value, name, errp);
1115 if (error_is_set(errp)) {
1116 return;
1117 }
1118 if (value < min || value > max) {
1119 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1120 name ? name : "null", value, min, max);
1121 return;
1122 }
1123
1124 cpu->env.tsc_khz = value / 1000;
1125 }
1126
1127 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1128 {
1129 unsigned int i;
1130 x86_def_t *def;
1131
1132 char *s = g_strdup(cpu_model);
1133 char *featurestr, *name = strtok(s, ",");
1134 /* Features to be added*/
1135 uint32_t plus_features = 0, plus_ext_features = 0;
1136 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1137 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1138 uint32_t plus_7_0_ebx_features = 0;
1139 /* Features to be removed */
1140 uint32_t minus_features = 0, minus_ext_features = 0;
1141 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1142 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1143 uint32_t minus_7_0_ebx_features = 0;
1144 uint32_t numvalue;
1145
1146 for (def = x86_defs; def; def = def->next)
1147 if (name && !strcmp(name, def->name))
1148 break;
1149 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1150 cpu_x86_fill_host(x86_cpu_def);
1151 } else if (!def) {
1152 goto error;
1153 } else {
1154 memcpy(x86_cpu_def, def, sizeof(*def));
1155 }
1156
1157 add_flagname_to_bitmaps("hypervisor", &plus_features,
1158 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1159 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1160
1161 featurestr = strtok(NULL, ",");
1162
1163 while (featurestr) {
1164 char *val;
1165 if (featurestr[0] == '+') {
1166 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1167 &plus_ext_features, &plus_ext2_features,
1168 &plus_ext3_features, &plus_kvm_features,
1169 &plus_svm_features, &plus_7_0_ebx_features);
1170 } else if (featurestr[0] == '-') {
1171 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1172 &minus_ext_features, &minus_ext2_features,
1173 &minus_ext3_features, &minus_kvm_features,
1174 &minus_svm_features, &minus_7_0_ebx_features);
1175 } else if ((val = strchr(featurestr, '='))) {
1176 *val = 0; val++;
1177 if (!strcmp(featurestr, "family")) {
1178 char *err;
1179 numvalue = strtoul(val, &err, 0);
1180 if (!*val || *err || numvalue > 0xff + 0xf) {
1181 fprintf(stderr, "bad numerical value %s\n", val);
1182 goto error;
1183 }
1184 x86_cpu_def->family = numvalue;
1185 } else if (!strcmp(featurestr, "model")) {
1186 char *err;
1187 numvalue = strtoul(val, &err, 0);
1188 if (!*val || *err || numvalue > 0xff) {
1189 fprintf(stderr, "bad numerical value %s\n", val);
1190 goto error;
1191 }
1192 x86_cpu_def->model = numvalue;
1193 } else if (!strcmp(featurestr, "stepping")) {
1194 char *err;
1195 numvalue = strtoul(val, &err, 0);
1196 if (!*val || *err || numvalue > 0xf) {
1197 fprintf(stderr, "bad numerical value %s\n", val);
1198 goto error;
1199 }
1200 x86_cpu_def->stepping = numvalue ;
1201 } else if (!strcmp(featurestr, "level")) {
1202 char *err;
1203 numvalue = strtoul(val, &err, 0);
1204 if (!*val || *err) {
1205 fprintf(stderr, "bad numerical value %s\n", val);
1206 goto error;
1207 }
1208 x86_cpu_def->level = numvalue;
1209 } else if (!strcmp(featurestr, "xlevel")) {
1210 char *err;
1211 numvalue = strtoul(val, &err, 0);
1212 if (!*val || *err) {
1213 fprintf(stderr, "bad numerical value %s\n", val);
1214 goto error;
1215 }
1216 if (numvalue < 0x80000000) {
1217 numvalue += 0x80000000;
1218 }
1219 x86_cpu_def->xlevel = numvalue;
1220 } else if (!strcmp(featurestr, "vendor")) {
1221 if (strlen(val) != 12) {
1222 fprintf(stderr, "vendor string must be 12 chars long\n");
1223 goto error;
1224 }
1225 x86_cpu_def->vendor1 = 0;
1226 x86_cpu_def->vendor2 = 0;
1227 x86_cpu_def->vendor3 = 0;
1228 for(i = 0; i < 4; i++) {
1229 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1230 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1231 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1232 }
1233 x86_cpu_def->vendor_override = 1;
1234 } else if (!strcmp(featurestr, "model_id")) {
1235 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1236 val);
1237 } else if (!strcmp(featurestr, "tsc_freq")) {
1238 int64_t tsc_freq;
1239 char *err;
1240
1241 tsc_freq = strtosz_suffix_unit(val, &err,
1242 STRTOSZ_DEFSUFFIX_B, 1000);
1243 if (tsc_freq < 0 || *err) {
1244 fprintf(stderr, "bad numerical value %s\n", val);
1245 goto error;
1246 }
1247 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1248 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1249 char *err;
1250 numvalue = strtoul(val, &err, 0);
1251 if (!*val || *err) {
1252 fprintf(stderr, "bad numerical value %s\n", val);
1253 goto error;
1254 }
1255 hyperv_set_spinlock_retries(numvalue);
1256 } else {
1257 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1258 goto error;
1259 }
1260 } else if (!strcmp(featurestr, "check")) {
1261 check_cpuid = 1;
1262 } else if (!strcmp(featurestr, "enforce")) {
1263 check_cpuid = enforce_cpuid = 1;
1264 } else if (!strcmp(featurestr, "hv_relaxed")) {
1265 hyperv_enable_relaxed_timing(true);
1266 } else if (!strcmp(featurestr, "hv_vapic")) {
1267 hyperv_enable_vapic_recommended(true);
1268 } else {
1269 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1270 goto error;
1271 }
1272 featurestr = strtok(NULL, ",");
1273 }
1274 x86_cpu_def->features |= plus_features;
1275 x86_cpu_def->ext_features |= plus_ext_features;
1276 x86_cpu_def->ext2_features |= plus_ext2_features;
1277 x86_cpu_def->ext3_features |= plus_ext3_features;
1278 x86_cpu_def->kvm_features |= plus_kvm_features;
1279 x86_cpu_def->svm_features |= plus_svm_features;
1280 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1281 x86_cpu_def->features &= ~minus_features;
1282 x86_cpu_def->ext_features &= ~minus_ext_features;
1283 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1284 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1285 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1286 x86_cpu_def->svm_features &= ~minus_svm_features;
1287 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1288 if (check_cpuid) {
1289 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1290 goto error;
1291 }
1292 if (x86_cpu_def->cpuid_7_0_ebx_features && x86_cpu_def->level < 7) {
1293 x86_cpu_def->level = 7;
1294 }
1295 g_free(s);
1296 return 0;
1297
1298 error:
1299 g_free(s);
1300 return -1;
1301 }
1302
1303 /* generate a composite string into buf of all cpuid names in featureset
1304 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1305 * if flags, suppress names undefined in featureset.
1306 */
1307 static void listflags(char *buf, int bufsize, uint32_t fbits,
1308 const char **featureset, uint32_t flags)
1309 {
1310 const char **p = &featureset[31];
1311 char *q, *b, bit;
1312 int nc;
1313
1314 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1315 *buf = '\0';
1316 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1317 if (fbits & 1 << bit && (*p || !flags)) {
1318 if (*p)
1319 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1320 else
1321 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1322 if (bufsize <= nc) {
1323 if (b) {
1324 memcpy(b, "...", sizeof("..."));
1325 }
1326 return;
1327 }
1328 q += nc;
1329 bufsize -= nc;
1330 }
1331 }
1332
1333 /* generate CPU information. */
1334 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1335 {
1336 x86_def_t *def;
1337 char buf[256];
1338
1339 for (def = x86_defs; def; def = def->next) {
1340 snprintf(buf, sizeof(buf), "%s", def->name);
1341 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1342 }
1343 if (kvm_enabled()) {
1344 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1345 }
1346 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1347 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1348 (*cpu_fprintf)(f, " %s\n", buf);
1349 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1350 (*cpu_fprintf)(f, " %s\n", buf);
1351 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1352 (*cpu_fprintf)(f, " %s\n", buf);
1353 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1354 (*cpu_fprintf)(f, " %s\n", buf);
1355 }
1356
1357 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1358 {
1359 CpuDefinitionInfoList *cpu_list = NULL;
1360 x86_def_t *def;
1361
1362 for (def = x86_defs; def; def = def->next) {
1363 CpuDefinitionInfoList *entry;
1364 CpuDefinitionInfo *info;
1365
1366 info = g_malloc0(sizeof(*info));
1367 info->name = g_strdup(def->name);
1368
1369 entry = g_malloc0(sizeof(*entry));
1370 entry->value = info;
1371 entry->next = cpu_list;
1372 cpu_list = entry;
1373 }
1374
1375 return cpu_list;
1376 }
1377
1378 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1379 {
1380 CPUX86State *env = &cpu->env;
1381 x86_def_t def1, *def = &def1;
1382 Error *error = NULL;
1383
1384 memset(def, 0, sizeof(*def));
1385
1386 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1387 return -1;
1388 if (def->vendor1) {
1389 env->cpuid_vendor1 = def->vendor1;
1390 env->cpuid_vendor2 = def->vendor2;
1391 env->cpuid_vendor3 = def->vendor3;
1392 } else {
1393 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1394 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1395 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1396 }
1397 env->cpuid_vendor_override = def->vendor_override;
1398 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1399 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1400 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1401 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1402 env->cpuid_features = def->features;
1403 env->cpuid_ext_features = def->ext_features;
1404 env->cpuid_ext2_features = def->ext2_features;
1405 env->cpuid_ext3_features = def->ext3_features;
1406 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1407 env->cpuid_kvm_features = def->kvm_features;
1408 env->cpuid_svm_features = def->svm_features;
1409 env->cpuid_ext4_features = def->ext4_features;
1410 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1411 env->cpuid_xlevel2 = def->xlevel2;
1412 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1413 "tsc-frequency", &error);
1414
1415 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1416 * CPUID[1].EDX.
1417 */
1418 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1419 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1420 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1421 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1422 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1423 }
1424
1425 if (!kvm_enabled()) {
1426 env->cpuid_features &= TCG_FEATURES;
1427 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1428 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1429 #ifdef TARGET_X86_64
1430 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1431 #endif
1432 );
1433 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1434 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1435 }
1436 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1437 if (error) {
1438 fprintf(stderr, "%s\n", error_get_pretty(error));
1439 error_free(error);
1440 return -1;
1441 }
1442 return 0;
1443 }
1444
1445 #if !defined(CONFIG_USER_ONLY)
1446
1447 void cpu_clear_apic_feature(CPUX86State *env)
1448 {
1449 env->cpuid_features &= ~CPUID_APIC;
1450 }
1451
1452 #endif /* !CONFIG_USER_ONLY */
1453
1454 /* Initialize list of CPU models, filling some non-static fields if necessary
1455 */
1456 void x86_cpudef_setup(void)
1457 {
1458 int i, j;
1459 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1460
1461 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1462 x86_def_t *def = &builtin_x86_defs[i];
1463 def->next = x86_defs;
1464
1465 /* Look for specific "cpudef" models that */
1466 /* have the QEMU version in .model_id */
1467 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1468 if (strcmp(model_with_versions[j], def->name) == 0) {
1469 pstrcpy(def->model_id, sizeof(def->model_id),
1470 "QEMU Virtual CPU version ");
1471 pstrcat(def->model_id, sizeof(def->model_id),
1472 qemu_get_version());
1473 break;
1474 }
1475 }
1476
1477 x86_defs = def;
1478 }
1479 }
1480
1481 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1482 uint32_t *ecx, uint32_t *edx)
1483 {
1484 *ebx = env->cpuid_vendor1;
1485 *edx = env->cpuid_vendor2;
1486 *ecx = env->cpuid_vendor3;
1487
1488 /* sysenter isn't supported on compatibility mode on AMD, syscall
1489 * isn't supported in compatibility mode on Intel.
1490 * Normally we advertise the actual cpu vendor, but you can override
1491 * this if you want to use KVM's sysenter/syscall emulation
1492 * in compatibility mode and when doing cross vendor migration
1493 */
1494 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1495 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1496 }
1497 }
1498
1499 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1500 uint32_t *eax, uint32_t *ebx,
1501 uint32_t *ecx, uint32_t *edx)
1502 {
1503 /* test if maximum index reached */
1504 if (index & 0x80000000) {
1505 if (index > env->cpuid_xlevel) {
1506 if (env->cpuid_xlevel2 > 0) {
1507 /* Handle the Centaur's CPUID instruction. */
1508 if (index > env->cpuid_xlevel2) {
1509 index = env->cpuid_xlevel2;
1510 } else if (index < 0xC0000000) {
1511 index = env->cpuid_xlevel;
1512 }
1513 } else {
1514 index = env->cpuid_xlevel;
1515 }
1516 }
1517 } else {
1518 if (index > env->cpuid_level)
1519 index = env->cpuid_level;
1520 }
1521
1522 switch(index) {
1523 case 0:
1524 *eax = env->cpuid_level;
1525 get_cpuid_vendor(env, ebx, ecx, edx);
1526 break;
1527 case 1:
1528 *eax = env->cpuid_version;
1529 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1530 *ecx = env->cpuid_ext_features;
1531 *edx = env->cpuid_features;
1532 if (env->nr_cores * env->nr_threads > 1) {
1533 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1534 *edx |= 1 << 28; /* HTT bit */
1535 }
1536 break;
1537 case 2:
1538 /* cache info: needed for Pentium Pro compatibility */
1539 *eax = 1;
1540 *ebx = 0;
1541 *ecx = 0;
1542 *edx = 0x2c307d;
1543 break;
1544 case 4:
1545 /* cache info: needed for Core compatibility */
1546 if (env->nr_cores > 1) {
1547 *eax = (env->nr_cores - 1) << 26;
1548 } else {
1549 *eax = 0;
1550 }
1551 switch (count) {
1552 case 0: /* L1 dcache info */
1553 *eax |= 0x0000121;
1554 *ebx = 0x1c0003f;
1555 *ecx = 0x000003f;
1556 *edx = 0x0000001;
1557 break;
1558 case 1: /* L1 icache info */
1559 *eax |= 0x0000122;
1560 *ebx = 0x1c0003f;
1561 *ecx = 0x000003f;
1562 *edx = 0x0000001;
1563 break;
1564 case 2: /* L2 cache info */
1565 *eax |= 0x0000143;
1566 if (env->nr_threads > 1) {
1567 *eax |= (env->nr_threads - 1) << 14;
1568 }
1569 *ebx = 0x3c0003f;
1570 *ecx = 0x0000fff;
1571 *edx = 0x0000001;
1572 break;
1573 default: /* end of info */
1574 *eax = 0;
1575 *ebx = 0;
1576 *ecx = 0;
1577 *edx = 0;
1578 break;
1579 }
1580 break;
1581 case 5:
1582 /* mwait info: needed for Core compatibility */
1583 *eax = 0; /* Smallest monitor-line size in bytes */
1584 *ebx = 0; /* Largest monitor-line size in bytes */
1585 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1586 *edx = 0;
1587 break;
1588 case 6:
1589 /* Thermal and Power Leaf */
1590 *eax = 0;
1591 *ebx = 0;
1592 *ecx = 0;
1593 *edx = 0;
1594 break;
1595 case 7:
1596 /* Structured Extended Feature Flags Enumeration Leaf */
1597 if (count == 0) {
1598 *eax = 0; /* Maximum ECX value for sub-leaves */
1599 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1600 *ecx = 0; /* Reserved */
1601 *edx = 0; /* Reserved */
1602 } else {
1603 *eax = 0;
1604 *ebx = 0;
1605 *ecx = 0;
1606 *edx = 0;
1607 }
1608 break;
1609 case 9:
1610 /* Direct Cache Access Information Leaf */
1611 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1612 *ebx = 0;
1613 *ecx = 0;
1614 *edx = 0;
1615 break;
1616 case 0xA:
1617 /* Architectural Performance Monitoring Leaf */
1618 if (kvm_enabled()) {
1619 KVMState *s = env->kvm_state;
1620
1621 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1622 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1623 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1624 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1625 } else {
1626 *eax = 0;
1627 *ebx = 0;
1628 *ecx = 0;
1629 *edx = 0;
1630 }
1631 break;
1632 case 0xD:
1633 /* Processor Extended State */
1634 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1635 *eax = 0;
1636 *ebx = 0;
1637 *ecx = 0;
1638 *edx = 0;
1639 break;
1640 }
1641 if (kvm_enabled()) {
1642 KVMState *s = env->kvm_state;
1643
1644 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1645 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1646 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1647 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1648 } else {
1649 *eax = 0;
1650 *ebx = 0;
1651 *ecx = 0;
1652 *edx = 0;
1653 }
1654 break;
1655 case 0x80000000:
1656 *eax = env->cpuid_xlevel;
1657 *ebx = env->cpuid_vendor1;
1658 *edx = env->cpuid_vendor2;
1659 *ecx = env->cpuid_vendor3;
1660 break;
1661 case 0x80000001:
1662 *eax = env->cpuid_version;
1663 *ebx = 0;
1664 *ecx = env->cpuid_ext3_features;
1665 *edx = env->cpuid_ext2_features;
1666
1667 /* The Linux kernel checks for the CMPLegacy bit and
1668 * discards multiple thread information if it is set.
1669 * So dont set it here for Intel to make Linux guests happy.
1670 */
1671 if (env->nr_cores * env->nr_threads > 1) {
1672 uint32_t tebx, tecx, tedx;
1673 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1674 if (tebx != CPUID_VENDOR_INTEL_1 ||
1675 tedx != CPUID_VENDOR_INTEL_2 ||
1676 tecx != CPUID_VENDOR_INTEL_3) {
1677 *ecx |= 1 << 1; /* CmpLegacy bit */
1678 }
1679 }
1680 break;
1681 case 0x80000002:
1682 case 0x80000003:
1683 case 0x80000004:
1684 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1685 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1686 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1687 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1688 break;
1689 case 0x80000005:
1690 /* cache info (L1 cache) */
1691 *eax = 0x01ff01ff;
1692 *ebx = 0x01ff01ff;
1693 *ecx = 0x40020140;
1694 *edx = 0x40020140;
1695 break;
1696 case 0x80000006:
1697 /* cache info (L2 cache) */
1698 *eax = 0;
1699 *ebx = 0x42004200;
1700 *ecx = 0x02008140;
1701 *edx = 0;
1702 break;
1703 case 0x80000008:
1704 /* virtual & phys address size in low 2 bytes. */
1705 /* XXX: This value must match the one used in the MMU code. */
1706 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1707 /* 64 bit processor */
1708 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1709 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1710 } else {
1711 if (env->cpuid_features & CPUID_PSE36)
1712 *eax = 0x00000024; /* 36 bits physical */
1713 else
1714 *eax = 0x00000020; /* 32 bits physical */
1715 }
1716 *ebx = 0;
1717 *ecx = 0;
1718 *edx = 0;
1719 if (env->nr_cores * env->nr_threads > 1) {
1720 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1721 }
1722 break;
1723 case 0x8000000A:
1724 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1725 *eax = 0x00000001; /* SVM Revision */
1726 *ebx = 0x00000010; /* nr of ASIDs */
1727 *ecx = 0;
1728 *edx = env->cpuid_svm_features; /* optional features */
1729 } else {
1730 *eax = 0;
1731 *ebx = 0;
1732 *ecx = 0;
1733 *edx = 0;
1734 }
1735 break;
1736 case 0xC0000000:
1737 *eax = env->cpuid_xlevel2;
1738 *ebx = 0;
1739 *ecx = 0;
1740 *edx = 0;
1741 break;
1742 case 0xC0000001:
1743 /* Support for VIA CPU's CPUID instruction */
1744 *eax = env->cpuid_version;
1745 *ebx = 0;
1746 *ecx = 0;
1747 *edx = env->cpuid_ext4_features;
1748 break;
1749 case 0xC0000002:
1750 case 0xC0000003:
1751 case 0xC0000004:
1752 /* Reserved for the future, and now filled with zero */
1753 *eax = 0;
1754 *ebx = 0;
1755 *ecx = 0;
1756 *edx = 0;
1757 break;
1758 default:
1759 /* reserved values: zero */
1760 *eax = 0;
1761 *ebx = 0;
1762 *ecx = 0;
1763 *edx = 0;
1764 break;
1765 }
1766 }
1767
1768 /* CPUClass::reset() */
1769 static void x86_cpu_reset(CPUState *s)
1770 {
1771 X86CPU *cpu = X86_CPU(s);
1772 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1773 CPUX86State *env = &cpu->env;
1774 int i;
1775
1776 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1777 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1778 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1779 }
1780
1781 xcc->parent_reset(s);
1782
1783
1784 memset(env, 0, offsetof(CPUX86State, breakpoints));
1785
1786 tlb_flush(env, 1);
1787
1788 env->old_exception = -1;
1789
1790 /* init to reset state */
1791
1792 #ifdef CONFIG_SOFTMMU
1793 env->hflags |= HF_SOFTMMU_MASK;
1794 #endif
1795 env->hflags2 |= HF2_GIF_MASK;
1796
1797 cpu_x86_update_cr0(env, 0x60000010);
1798 env->a20_mask = ~0x0;
1799 env->smbase = 0x30000;
1800
1801 env->idt.limit = 0xffff;
1802 env->gdt.limit = 0xffff;
1803 env->ldt.limit = 0xffff;
1804 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1805 env->tr.limit = 0xffff;
1806 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1807
1808 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1809 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1810 DESC_R_MASK | DESC_A_MASK);
1811 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1812 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1813 DESC_A_MASK);
1814 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1815 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1816 DESC_A_MASK);
1817 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1818 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1819 DESC_A_MASK);
1820 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1821 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1822 DESC_A_MASK);
1823 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1824 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1825 DESC_A_MASK);
1826
1827 env->eip = 0xfff0;
1828 env->regs[R_EDX] = env->cpuid_version;
1829
1830 env->eflags = 0x2;
1831
1832 /* FPU init */
1833 for (i = 0; i < 8; i++) {
1834 env->fptags[i] = 1;
1835 }
1836 env->fpuc = 0x37f;
1837
1838 env->mxcsr = 0x1f80;
1839
1840 env->pat = 0x0007040600070406ULL;
1841 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1842
1843 memset(env->dr, 0, sizeof(env->dr));
1844 env->dr[6] = DR6_FIXED_1;
1845 env->dr[7] = DR7_FIXED_1;
1846 cpu_breakpoint_remove_all(env, BP_CPU);
1847 cpu_watchpoint_remove_all(env, BP_CPU);
1848
1849 #if !defined(CONFIG_USER_ONLY)
1850 /* We hard-wire the BSP to the first CPU. */
1851 if (env->cpu_index == 0) {
1852 apic_designate_bsp(env->apic_state);
1853 }
1854
1855 env->halted = !cpu_is_bsp(cpu);
1856 #endif
1857 }
1858
1859 #ifndef CONFIG_USER_ONLY
1860 bool cpu_is_bsp(X86CPU *cpu)
1861 {
1862 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1863 }
1864
1865 /* TODO: remove me, when reset over QOM tree is implemented */
1866 static void x86_cpu_machine_reset_cb(void *opaque)
1867 {
1868 X86CPU *cpu = opaque;
1869 cpu_reset(CPU(cpu));
1870 }
1871 #endif
1872
1873 static void mce_init(X86CPU *cpu)
1874 {
1875 CPUX86State *cenv = &cpu->env;
1876 unsigned int bank;
1877
1878 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1879 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1880 (CPUID_MCE | CPUID_MCA)) {
1881 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1882 cenv->mcg_ctl = ~(uint64_t)0;
1883 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1884 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1885 }
1886 }
1887 }
1888
1889 #define MSI_ADDR_BASE 0xfee00000
1890
1891 #ifndef CONFIG_USER_ONLY
1892 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
1893 {
1894 static int apic_mapped;
1895 CPUX86State *env = &cpu->env;
1896 APICCommonState *apic;
1897 const char *apic_type = "apic";
1898
1899 if (kvm_irqchip_in_kernel()) {
1900 apic_type = "kvm-apic";
1901 } else if (xen_enabled()) {
1902 apic_type = "xen-apic";
1903 }
1904
1905 env->apic_state = qdev_try_create(NULL, apic_type);
1906 if (env->apic_state == NULL) {
1907 error_setg(errp, "APIC device '%s' could not be created", apic_type);
1908 return;
1909 }
1910
1911 object_property_add_child(OBJECT(cpu), "apic",
1912 OBJECT(env->apic_state), NULL);
1913 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
1914 /* TODO: convert to link<> */
1915 apic = APIC_COMMON(env->apic_state);
1916 apic->cpu = cpu;
1917
1918 if (qdev_init(env->apic_state)) {
1919 error_setg(errp, "APIC device '%s' could not be initialized",
1920 object_get_typename(OBJECT(env->apic_state)));
1921 return;
1922 }
1923
1924 /* XXX: mapping more APICs at the same memory location */
1925 if (apic_mapped == 0) {
1926 /* NOTE: the APIC is directly connected to the CPU - it is not
1927 on the global memory bus. */
1928 /* XXX: what if the base changes? */
1929 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
1930 apic_mapped = 1;
1931 }
1932 }
1933 #endif
1934
1935 void x86_cpu_realize(Object *obj, Error **errp)
1936 {
1937 X86CPU *cpu = X86_CPU(obj);
1938
1939 #ifndef CONFIG_USER_ONLY
1940 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1941
1942 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
1943 x86_cpu_apic_init(cpu, errp);
1944 if (error_is_set(errp)) {
1945 return;
1946 }
1947 }
1948 #endif
1949
1950 mce_init(cpu);
1951 qemu_init_vcpu(&cpu->env);
1952 cpu_reset(CPU(cpu));
1953 }
1954
1955 static void x86_cpu_initfn(Object *obj)
1956 {
1957 X86CPU *cpu = X86_CPU(obj);
1958 CPUX86State *env = &cpu->env;
1959 static int inited;
1960
1961 cpu_exec_init(env);
1962
1963 object_property_add(obj, "family", "int",
1964 x86_cpuid_version_get_family,
1965 x86_cpuid_version_set_family, NULL, NULL, NULL);
1966 object_property_add(obj, "model", "int",
1967 x86_cpuid_version_get_model,
1968 x86_cpuid_version_set_model, NULL, NULL, NULL);
1969 object_property_add(obj, "stepping", "int",
1970 x86_cpuid_version_get_stepping,
1971 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
1972 object_property_add(obj, "level", "int",
1973 x86_cpuid_get_level,
1974 x86_cpuid_set_level, NULL, NULL, NULL);
1975 object_property_add(obj, "xlevel", "int",
1976 x86_cpuid_get_xlevel,
1977 x86_cpuid_set_xlevel, NULL, NULL, NULL);
1978 object_property_add_str(obj, "vendor",
1979 x86_cpuid_get_vendor,
1980 x86_cpuid_set_vendor, NULL);
1981 object_property_add_str(obj, "model-id",
1982 x86_cpuid_get_model_id,
1983 x86_cpuid_set_model_id, NULL);
1984 object_property_add(obj, "tsc-frequency", "int",
1985 x86_cpuid_get_tsc_freq,
1986 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
1987
1988 env->cpuid_apic_id = env->cpu_index;
1989
1990 /* init various static tables used in TCG mode */
1991 if (tcg_enabled() && !inited) {
1992 inited = 1;
1993 optimize_flags_init();
1994 #ifndef CONFIG_USER_ONLY
1995 cpu_set_debug_excp_handler(breakpoint_handler);
1996 #endif
1997 }
1998 }
1999
2000 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2001 {
2002 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2003 CPUClass *cc = CPU_CLASS(oc);
2004
2005 xcc->parent_reset = cc->reset;
2006 cc->reset = x86_cpu_reset;
2007 }
2008
2009 static const TypeInfo x86_cpu_type_info = {
2010 .name = TYPE_X86_CPU,
2011 .parent = TYPE_CPU,
2012 .instance_size = sizeof(X86CPU),
2013 .instance_init = x86_cpu_initfn,
2014 .abstract = false,
2015 .class_size = sizeof(X86CPUClass),
2016 .class_init = x86_cpu_common_class_init,
2017 };
2018
2019 static void x86_cpu_register_types(void)
2020 {
2021 type_register_static(&x86_cpu_type_info);
2022 }
2023
2024 type_init(x86_cpu_register_types)
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