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target-i386: Introduce feat2prop() for CPU properties
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "hw/xen/xen.h"
46 #include "hw/sysbus.h"
47 #include "hw/i386/apic_internal.h"
48 #endif
49
50 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
51 uint32_t vendor2, uint32_t vendor3)
52 {
53 int i;
54 for (i = 0; i < 4; i++) {
55 dst[i] = vendor1 >> (8 * i);
56 dst[i + 4] = vendor2 >> (8 * i);
57 dst[i + 8] = vendor3 >> (8 * i);
58 }
59 dst[CPUID_VENDOR_SZ] = '\0';
60 }
61
62 /* feature flags taken from "Intel Processor Identification and the CPUID
63 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
64 * between feature naming conventions, aliases may be added.
65 */
66 static const char *feature_name[] = {
67 "fpu", "vme", "de", "pse",
68 "tsc", "msr", "pae", "mce",
69 "cx8", "apic", NULL, "sep",
70 "mtrr", "pge", "mca", "cmov",
71 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
72 NULL, "ds" /* Intel dts */, "acpi", "mmx",
73 "fxsr", "sse", "sse2", "ss",
74 "ht" /* Intel htt */, "tm", "ia64", "pbe",
75 };
76 static const char *ext_feature_name[] = {
77 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
78 "ds_cpl", "vmx", "smx", "est",
79 "tm2", "ssse3", "cid", NULL,
80 "fma", "cx16", "xtpr", "pdcm",
81 NULL, "pcid", "dca", "sse4.1|sse4_1",
82 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
83 "tsc-deadline", "aes", "xsave", "osxsave",
84 "avx", "f16c", "rdrand", "hypervisor",
85 };
86 /* Feature names that are already defined on feature_name[] but are set on
87 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
88 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
89 * if and only if CPU vendor is AMD.
90 */
91 static const char *ext2_feature_name[] = {
92 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
93 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
94 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
95 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
96 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
97 "nx|xd", NULL, "mmxext", NULL /* mmx */,
98 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
99 NULL, "lm|i64", "3dnowext", "3dnow",
100 };
101 static const char *ext3_feature_name[] = {
102 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
103 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
104 "3dnowprefetch", "osvw", "ibs", "xop",
105 "skinit", "wdt", NULL, "lwp",
106 "fma4", "tce", NULL, "nodeid_msr",
107 NULL, "tbm", "topoext", "perfctr_core",
108 "perfctr_nb", NULL, NULL, NULL,
109 NULL, NULL, NULL, NULL,
110 };
111
112 static const char *ext4_feature_name[] = {
113 NULL, NULL, "xstore", "xstore-en",
114 NULL, NULL, "xcrypt", "xcrypt-en",
115 "ace2", "ace2-en", "phe", "phe-en",
116 "pmm", "pmm-en", NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 };
122
123 static const char *kvm_feature_name[] = {
124 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
125 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 };
133
134 static const char *svm_feature_name[] = {
135 "npt", "lbrv", "svm_lock", "nrip_save",
136 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
137 NULL, NULL, "pause_filter", NULL,
138 "pfthreshold", NULL, NULL, NULL,
139 NULL, NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 };
144
145 static const char *cpuid_7_0_ebx_feature_name[] = {
146 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
147 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
148 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
149 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
150 };
151
152 typedef struct FeatureWordInfo {
153 const char **feat_names;
154 uint32_t cpuid_eax; /* Input EAX for CPUID */
155 int cpuid_reg; /* R_* register constant */
156 } FeatureWordInfo;
157
158 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
159 [FEAT_1_EDX] = {
160 .feat_names = feature_name,
161 .cpuid_eax = 1, .cpuid_reg = R_EDX,
162 },
163 [FEAT_1_ECX] = {
164 .feat_names = ext_feature_name,
165 .cpuid_eax = 1, .cpuid_reg = R_ECX,
166 },
167 [FEAT_8000_0001_EDX] = {
168 .feat_names = ext2_feature_name,
169 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
170 },
171 [FEAT_8000_0001_ECX] = {
172 .feat_names = ext3_feature_name,
173 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
174 },
175 [FEAT_C000_0001_EDX] = {
176 .feat_names = ext4_feature_name,
177 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
178 },
179 [FEAT_KVM] = {
180 .feat_names = kvm_feature_name,
181 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
182 },
183 [FEAT_SVM] = {
184 .feat_names = svm_feature_name,
185 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
186 },
187 [FEAT_7_0_EBX] = {
188 .feat_names = cpuid_7_0_ebx_feature_name,
189 .cpuid_eax = 7, .cpuid_reg = R_EBX,
190 },
191 };
192
193 const char *get_register_name_32(unsigned int reg)
194 {
195 static const char *reg_names[CPU_NB_REGS32] = {
196 [R_EAX] = "EAX",
197 [R_ECX] = "ECX",
198 [R_EDX] = "EDX",
199 [R_EBX] = "EBX",
200 [R_ESP] = "ESP",
201 [R_EBP] = "EBP",
202 [R_ESI] = "ESI",
203 [R_EDI] = "EDI",
204 };
205
206 if (reg > CPU_NB_REGS32) {
207 return NULL;
208 }
209 return reg_names[reg];
210 }
211
212 /* collects per-function cpuid data
213 */
214 typedef struct model_features_t {
215 uint32_t *guest_feat;
216 uint32_t *host_feat;
217 FeatureWord feat_word;
218 } model_features_t;
219
220 int check_cpuid = 0;
221 int enforce_cpuid = 0;
222
223 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
224 (1 << KVM_FEATURE_NOP_IO_DELAY) |
225 (1 << KVM_FEATURE_CLOCKSOURCE2) |
226 (1 << KVM_FEATURE_ASYNC_PF) |
227 (1 << KVM_FEATURE_STEAL_TIME) |
228 (1 << KVM_FEATURE_PV_EOI) |
229 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
230
231 void disable_kvm_pv_eoi(void)
232 {
233 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
234 }
235
236 void host_cpuid(uint32_t function, uint32_t count,
237 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
238 {
239 #if defined(CONFIG_KVM)
240 uint32_t vec[4];
241
242 #ifdef __x86_64__
243 asm volatile("cpuid"
244 : "=a"(vec[0]), "=b"(vec[1]),
245 "=c"(vec[2]), "=d"(vec[3])
246 : "0"(function), "c"(count) : "cc");
247 #else
248 asm volatile("pusha \n\t"
249 "cpuid \n\t"
250 "mov %%eax, 0(%2) \n\t"
251 "mov %%ebx, 4(%2) \n\t"
252 "mov %%ecx, 8(%2) \n\t"
253 "mov %%edx, 12(%2) \n\t"
254 "popa"
255 : : "a"(function), "c"(count), "S"(vec)
256 : "memory", "cc");
257 #endif
258
259 if (eax)
260 *eax = vec[0];
261 if (ebx)
262 *ebx = vec[1];
263 if (ecx)
264 *ecx = vec[2];
265 if (edx)
266 *edx = vec[3];
267 #endif
268 }
269
270 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
271
272 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
273 * a substring. ex if !NULL points to the first char after a substring,
274 * otherwise the string is assumed to sized by a terminating nul.
275 * Return lexical ordering of *s1:*s2.
276 */
277 static int sstrcmp(const char *s1, const char *e1, const char *s2,
278 const char *e2)
279 {
280 for (;;) {
281 if (!*s1 || !*s2 || *s1 != *s2)
282 return (*s1 - *s2);
283 ++s1, ++s2;
284 if (s1 == e1 && s2 == e2)
285 return (0);
286 else if (s1 == e1)
287 return (*s2);
288 else if (s2 == e2)
289 return (*s1);
290 }
291 }
292
293 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
294 * '|' delimited (possibly empty) strings in which case search for a match
295 * within the alternatives proceeds left to right. Return 0 for success,
296 * non-zero otherwise.
297 */
298 static int altcmp(const char *s, const char *e, const char *altstr)
299 {
300 const char *p, *q;
301
302 for (q = p = altstr; ; ) {
303 while (*p && *p != '|')
304 ++p;
305 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
306 return (0);
307 if (!*p)
308 return (1);
309 else
310 q = ++p;
311 }
312 }
313
314 /* search featureset for flag *[s..e), if found set corresponding bit in
315 * *pval and return true, otherwise return false
316 */
317 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
318 const char **featureset)
319 {
320 uint32_t mask;
321 const char **ppc;
322 bool found = false;
323
324 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
325 if (*ppc && !altcmp(s, e, *ppc)) {
326 *pval |= mask;
327 found = true;
328 }
329 }
330 return found;
331 }
332
333 static void add_flagname_to_bitmaps(const char *flagname,
334 FeatureWordArray words)
335 {
336 FeatureWord w;
337 for (w = 0; w < FEATURE_WORDS; w++) {
338 FeatureWordInfo *wi = &feature_word_info[w];
339 if (wi->feat_names &&
340 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
341 break;
342 }
343 }
344 if (w == FEATURE_WORDS) {
345 fprintf(stderr, "CPU feature %s not found\n", flagname);
346 }
347 }
348
349 typedef struct x86_def_t {
350 const char *name;
351 uint32_t level;
352 /* vendor is zero-terminated, 12 character ASCII string */
353 char vendor[CPUID_VENDOR_SZ + 1];
354 int family;
355 int model;
356 int stepping;
357 uint32_t features, ext_features, ext2_features, ext3_features;
358 uint32_t kvm_features, svm_features;
359 uint32_t xlevel;
360 char model_id[48];
361 /* Store the results of Centaur's CPUID instructions */
362 uint32_t ext4_features;
363 uint32_t xlevel2;
364 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
365 uint32_t cpuid_7_0_ebx_features;
366 } x86_def_t;
367
368 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
369 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
370 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
371 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
372 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
373 CPUID_PSE36 | CPUID_FXSR)
374 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
375 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
376 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
377 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
378 CPUID_PAE | CPUID_SEP | CPUID_APIC)
379
380 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
381 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
382 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
383 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
384 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
385 /* partly implemented:
386 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
387 CPUID_PSE36 (needed for Solaris) */
388 /* missing:
389 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
390 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
391 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
392 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
393 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
394 /* missing:
395 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
396 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
397 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
398 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
399 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
400 CPUID_EXT_RDRAND */
401 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
402 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
403 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
404 /* missing:
405 CPUID_EXT2_PDPE1GB */
406 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
407 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
408 #define TCG_SVM_FEATURES 0
409 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
410 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
411 /* missing:
412 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
413 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
414 CPUID_7_0_EBX_RDSEED */
415
416 /* built-in CPU model definitions
417 */
418 static x86_def_t builtin_x86_defs[] = {
419 {
420 .name = "qemu64",
421 .level = 4,
422 .vendor = CPUID_VENDOR_AMD,
423 .family = 6,
424 .model = 2,
425 .stepping = 3,
426 .features = PPRO_FEATURES |
427 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
428 CPUID_PSE36,
429 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
430 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
431 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
432 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
433 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
434 .xlevel = 0x8000000A,
435 },
436 {
437 .name = "phenom",
438 .level = 5,
439 .vendor = CPUID_VENDOR_AMD,
440 .family = 16,
441 .model = 2,
442 .stepping = 3,
443 .features = PPRO_FEATURES |
444 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
445 CPUID_PSE36 | CPUID_VME | CPUID_HT,
446 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
447 CPUID_EXT_POPCNT,
448 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
449 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
450 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
451 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
452 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
453 CPUID_EXT3_CR8LEG,
454 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
455 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
456 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
457 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
458 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
459 .xlevel = 0x8000001A,
460 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
461 },
462 {
463 .name = "core2duo",
464 .level = 10,
465 .vendor = CPUID_VENDOR_INTEL,
466 .family = 6,
467 .model = 15,
468 .stepping = 11,
469 .features = PPRO_FEATURES |
470 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
471 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
472 CPUID_HT | CPUID_TM | CPUID_PBE,
473 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
474 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
475 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
476 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
477 .ext3_features = CPUID_EXT3_LAHF_LM,
478 .xlevel = 0x80000008,
479 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
480 },
481 {
482 .name = "kvm64",
483 .level = 5,
484 .vendor = CPUID_VENDOR_INTEL,
485 .family = 15,
486 .model = 6,
487 .stepping = 1,
488 /* Missing: CPUID_VME, CPUID_HT */
489 .features = PPRO_FEATURES |
490 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
491 CPUID_PSE36,
492 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
493 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
494 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
495 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
496 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
497 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
498 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
499 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
500 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
501 .ext3_features = 0,
502 .xlevel = 0x80000008,
503 .model_id = "Common KVM processor"
504 },
505 {
506 .name = "qemu32",
507 .level = 4,
508 .vendor = CPUID_VENDOR_INTEL,
509 .family = 6,
510 .model = 3,
511 .stepping = 3,
512 .features = PPRO_FEATURES,
513 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
514 .xlevel = 0x80000004,
515 },
516 {
517 .name = "kvm32",
518 .level = 5,
519 .vendor = CPUID_VENDOR_INTEL,
520 .family = 15,
521 .model = 6,
522 .stepping = 1,
523 .features = PPRO_FEATURES |
524 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
525 .ext_features = CPUID_EXT_SSE3,
526 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
527 .ext3_features = 0,
528 .xlevel = 0x80000008,
529 .model_id = "Common 32-bit KVM processor"
530 },
531 {
532 .name = "coreduo",
533 .level = 10,
534 .vendor = CPUID_VENDOR_INTEL,
535 .family = 6,
536 .model = 14,
537 .stepping = 8,
538 .features = PPRO_FEATURES | CPUID_VME |
539 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
540 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
541 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
542 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
543 .ext2_features = CPUID_EXT2_NX,
544 .xlevel = 0x80000008,
545 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
546 },
547 {
548 .name = "486",
549 .level = 1,
550 .vendor = CPUID_VENDOR_INTEL,
551 .family = 4,
552 .model = 0,
553 .stepping = 0,
554 .features = I486_FEATURES,
555 .xlevel = 0,
556 },
557 {
558 .name = "pentium",
559 .level = 1,
560 .vendor = CPUID_VENDOR_INTEL,
561 .family = 5,
562 .model = 4,
563 .stepping = 3,
564 .features = PENTIUM_FEATURES,
565 .xlevel = 0,
566 },
567 {
568 .name = "pentium2",
569 .level = 2,
570 .vendor = CPUID_VENDOR_INTEL,
571 .family = 6,
572 .model = 5,
573 .stepping = 2,
574 .features = PENTIUM2_FEATURES,
575 .xlevel = 0,
576 },
577 {
578 .name = "pentium3",
579 .level = 2,
580 .vendor = CPUID_VENDOR_INTEL,
581 .family = 6,
582 .model = 7,
583 .stepping = 3,
584 .features = PENTIUM3_FEATURES,
585 .xlevel = 0,
586 },
587 {
588 .name = "athlon",
589 .level = 2,
590 .vendor = CPUID_VENDOR_AMD,
591 .family = 6,
592 .model = 2,
593 .stepping = 3,
594 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
595 CPUID_MCA,
596 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
597 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
598 .xlevel = 0x80000008,
599 },
600 {
601 .name = "n270",
602 /* original is on level 10 */
603 .level = 5,
604 .vendor = CPUID_VENDOR_INTEL,
605 .family = 6,
606 .model = 28,
607 .stepping = 2,
608 .features = PPRO_FEATURES |
609 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
610 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
611 /* Some CPUs got no CPUID_SEP */
612 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
613 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
614 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
615 CPUID_EXT2_NX,
616 .ext3_features = CPUID_EXT3_LAHF_LM,
617 .xlevel = 0x8000000A,
618 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
619 },
620 {
621 .name = "Conroe",
622 .level = 2,
623 .vendor = CPUID_VENDOR_INTEL,
624 .family = 6,
625 .model = 2,
626 .stepping = 3,
627 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
628 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
629 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
630 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
631 CPUID_DE | CPUID_FP87,
632 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
633 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
634 .ext3_features = CPUID_EXT3_LAHF_LM,
635 .xlevel = 0x8000000A,
636 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
637 },
638 {
639 .name = "Penryn",
640 .level = 2,
641 .vendor = CPUID_VENDOR_INTEL,
642 .family = 6,
643 .model = 2,
644 .stepping = 3,
645 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
646 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
647 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
648 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
649 CPUID_DE | CPUID_FP87,
650 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
651 CPUID_EXT_SSE3,
652 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
653 .ext3_features = CPUID_EXT3_LAHF_LM,
654 .xlevel = 0x8000000A,
655 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
656 },
657 {
658 .name = "Nehalem",
659 .level = 2,
660 .vendor = CPUID_VENDOR_INTEL,
661 .family = 6,
662 .model = 2,
663 .stepping = 3,
664 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
665 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
666 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
667 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
668 CPUID_DE | CPUID_FP87,
669 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
670 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
671 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
672 .ext3_features = CPUID_EXT3_LAHF_LM,
673 .xlevel = 0x8000000A,
674 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
675 },
676 {
677 .name = "Westmere",
678 .level = 11,
679 .vendor = CPUID_VENDOR_INTEL,
680 .family = 6,
681 .model = 44,
682 .stepping = 1,
683 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
684 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
685 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
686 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
687 CPUID_DE | CPUID_FP87,
688 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
689 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
690 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
691 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
692 .ext3_features = CPUID_EXT3_LAHF_LM,
693 .xlevel = 0x8000000A,
694 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
695 },
696 {
697 .name = "SandyBridge",
698 .level = 0xd,
699 .vendor = CPUID_VENDOR_INTEL,
700 .family = 6,
701 .model = 42,
702 .stepping = 1,
703 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
704 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
705 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
706 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
707 CPUID_DE | CPUID_FP87,
708 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
709 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
710 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
711 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
712 CPUID_EXT_SSE3,
713 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
714 CPUID_EXT2_SYSCALL,
715 .ext3_features = CPUID_EXT3_LAHF_LM,
716 .xlevel = 0x8000000A,
717 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
718 },
719 {
720 .name = "Haswell",
721 .level = 0xd,
722 .vendor = CPUID_VENDOR_INTEL,
723 .family = 6,
724 .model = 60,
725 .stepping = 1,
726 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
727 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
728 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
729 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
730 CPUID_DE | CPUID_FP87,
731 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
732 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
733 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
734 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
735 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
736 CPUID_EXT_PCID,
737 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
738 CPUID_EXT2_SYSCALL,
739 .ext3_features = CPUID_EXT3_LAHF_LM,
740 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
741 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
742 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
743 CPUID_7_0_EBX_RTM,
744 .xlevel = 0x8000000A,
745 .model_id = "Intel Core Processor (Haswell)",
746 },
747 {
748 .name = "Opteron_G1",
749 .level = 5,
750 .vendor = CPUID_VENDOR_AMD,
751 .family = 15,
752 .model = 6,
753 .stepping = 1,
754 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
755 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
756 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
757 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
758 CPUID_DE | CPUID_FP87,
759 .ext_features = CPUID_EXT_SSE3,
760 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
761 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
762 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
763 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
764 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
765 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
766 .xlevel = 0x80000008,
767 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
768 },
769 {
770 .name = "Opteron_G2",
771 .level = 5,
772 .vendor = CPUID_VENDOR_AMD,
773 .family = 15,
774 .model = 6,
775 .stepping = 1,
776 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
777 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
778 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
779 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
780 CPUID_DE | CPUID_FP87,
781 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
782 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
783 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
784 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
785 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
786 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
787 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
788 CPUID_EXT2_DE | CPUID_EXT2_FPU,
789 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
790 .xlevel = 0x80000008,
791 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
792 },
793 {
794 .name = "Opteron_G3",
795 .level = 5,
796 .vendor = CPUID_VENDOR_AMD,
797 .family = 15,
798 .model = 6,
799 .stepping = 1,
800 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
801 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
802 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
803 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
804 CPUID_DE | CPUID_FP87,
805 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
806 CPUID_EXT_SSE3,
807 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
808 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
809 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
810 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
811 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
812 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
813 CPUID_EXT2_DE | CPUID_EXT2_FPU,
814 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
815 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
816 .xlevel = 0x80000008,
817 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
818 },
819 {
820 .name = "Opteron_G4",
821 .level = 0xd,
822 .vendor = CPUID_VENDOR_AMD,
823 .family = 21,
824 .model = 1,
825 .stepping = 2,
826 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
827 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
828 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
829 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
830 CPUID_DE | CPUID_FP87,
831 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
832 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
833 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
834 CPUID_EXT_SSE3,
835 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
836 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
837 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
838 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
839 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
840 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
841 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
842 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
843 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
844 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
845 CPUID_EXT3_LAHF_LM,
846 .xlevel = 0x8000001A,
847 .model_id = "AMD Opteron 62xx class CPU",
848 },
849 {
850 .name = "Opteron_G5",
851 .level = 0xd,
852 .vendor = CPUID_VENDOR_AMD,
853 .family = 21,
854 .model = 2,
855 .stepping = 0,
856 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
860 CPUID_DE | CPUID_FP87,
861 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
862 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
863 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
864 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
865 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
866 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
867 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
868 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
869 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
870 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
871 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
872 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
873 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
874 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
875 CPUID_EXT3_LAHF_LM,
876 .xlevel = 0x8000001A,
877 .model_id = "AMD Opteron 63xx class CPU",
878 },
879 };
880
881 #ifdef CONFIG_KVM
882 static int cpu_x86_fill_model_id(char *str)
883 {
884 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
885 int i;
886
887 for (i = 0; i < 3; i++) {
888 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
889 memcpy(str + i * 16 + 0, &eax, 4);
890 memcpy(str + i * 16 + 4, &ebx, 4);
891 memcpy(str + i * 16 + 8, &ecx, 4);
892 memcpy(str + i * 16 + 12, &edx, 4);
893 }
894 return 0;
895 }
896 #endif
897
898 /* Fill a x86_def_t struct with information about the host CPU, and
899 * the CPU features supported by the host hardware + host kernel
900 *
901 * This function may be called only if KVM is enabled.
902 */
903 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
904 {
905 #ifdef CONFIG_KVM
906 KVMState *s = kvm_state;
907 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
908
909 assert(kvm_enabled());
910
911 x86_cpu_def->name = "host";
912 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
913 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
914
915 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
916 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
917 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
918 x86_cpu_def->stepping = eax & 0x0F;
919
920 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
921 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
922 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
923
924 if (x86_cpu_def->level >= 7) {
925 x86_cpu_def->cpuid_7_0_ebx_features =
926 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
927 } else {
928 x86_cpu_def->cpuid_7_0_ebx_features = 0;
929 }
930
931 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
932 x86_cpu_def->ext2_features =
933 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
934 x86_cpu_def->ext3_features =
935 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
936
937 cpu_x86_fill_model_id(x86_cpu_def->model_id);
938
939 /* Call Centaur's CPUID instruction. */
940 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
941 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
942 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
943 if (eax >= 0xC0000001) {
944 /* Support VIA max extended level */
945 x86_cpu_def->xlevel2 = eax;
946 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
947 x86_cpu_def->ext4_features =
948 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
949 }
950 }
951
952 /* Other KVM-specific feature fields: */
953 x86_cpu_def->svm_features =
954 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
955 x86_cpu_def->kvm_features =
956 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
957
958 #endif /* CONFIG_KVM */
959 }
960
961 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
962 {
963 int i;
964
965 for (i = 0; i < 32; ++i)
966 if (1 << i & mask) {
967 const char *reg = get_register_name_32(f->cpuid_reg);
968 assert(reg);
969 fprintf(stderr, "warning: host doesn't support requested feature: "
970 "CPUID.%02XH:%s%s%s [bit %d]\n",
971 f->cpuid_eax, reg,
972 f->feat_names[i] ? "." : "",
973 f->feat_names[i] ? f->feat_names[i] : "", i);
974 break;
975 }
976 return 0;
977 }
978
979 /* Check if all requested cpu flags are making their way to the guest
980 *
981 * Returns 0 if all flags are supported by the host, non-zero otherwise.
982 *
983 * This function may be called only if KVM is enabled.
984 */
985 static int kvm_check_features_against_host(X86CPU *cpu)
986 {
987 CPUX86State *env = &cpu->env;
988 x86_def_t host_def;
989 uint32_t mask;
990 int rv, i;
991 struct model_features_t ft[] = {
992 {&env->cpuid_features, &host_def.features,
993 FEAT_1_EDX },
994 {&env->cpuid_ext_features, &host_def.ext_features,
995 FEAT_1_ECX },
996 {&env->cpuid_ext2_features, &host_def.ext2_features,
997 FEAT_8000_0001_EDX },
998 {&env->cpuid_ext3_features, &host_def.ext3_features,
999 FEAT_8000_0001_ECX },
1000 {&env->cpuid_ext4_features, &host_def.ext4_features,
1001 FEAT_C000_0001_EDX },
1002 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
1003 FEAT_7_0_EBX },
1004 {&env->cpuid_svm_features, &host_def.svm_features,
1005 FEAT_SVM },
1006 {&env->cpuid_kvm_features, &host_def.kvm_features,
1007 FEAT_KVM },
1008 };
1009
1010 assert(kvm_enabled());
1011
1012 kvm_cpu_fill_host(&host_def);
1013 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1014 FeatureWord w = ft[i].feat_word;
1015 FeatureWordInfo *wi = &feature_word_info[w];
1016 for (mask = 1; mask; mask <<= 1) {
1017 if (*ft[i].guest_feat & mask &&
1018 !(*ft[i].host_feat & mask)) {
1019 unavailable_host_feature(wi, mask);
1020 rv = 1;
1021 }
1022 }
1023 }
1024 return rv;
1025 }
1026
1027 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1028 const char *name, Error **errp)
1029 {
1030 X86CPU *cpu = X86_CPU(obj);
1031 CPUX86State *env = &cpu->env;
1032 int64_t value;
1033
1034 value = (env->cpuid_version >> 8) & 0xf;
1035 if (value == 0xf) {
1036 value += (env->cpuid_version >> 20) & 0xff;
1037 }
1038 visit_type_int(v, &value, name, errp);
1039 }
1040
1041 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1042 const char *name, Error **errp)
1043 {
1044 X86CPU *cpu = X86_CPU(obj);
1045 CPUX86State *env = &cpu->env;
1046 const int64_t min = 0;
1047 const int64_t max = 0xff + 0xf;
1048 int64_t value;
1049
1050 visit_type_int(v, &value, name, errp);
1051 if (error_is_set(errp)) {
1052 return;
1053 }
1054 if (value < min || value > max) {
1055 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1056 name ? name : "null", value, min, max);
1057 return;
1058 }
1059
1060 env->cpuid_version &= ~0xff00f00;
1061 if (value > 0x0f) {
1062 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1063 } else {
1064 env->cpuid_version |= value << 8;
1065 }
1066 }
1067
1068 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1069 const char *name, Error **errp)
1070 {
1071 X86CPU *cpu = X86_CPU(obj);
1072 CPUX86State *env = &cpu->env;
1073 int64_t value;
1074
1075 value = (env->cpuid_version >> 4) & 0xf;
1076 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1077 visit_type_int(v, &value, name, errp);
1078 }
1079
1080 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1081 const char *name, Error **errp)
1082 {
1083 X86CPU *cpu = X86_CPU(obj);
1084 CPUX86State *env = &cpu->env;
1085 const int64_t min = 0;
1086 const int64_t max = 0xff;
1087 int64_t value;
1088
1089 visit_type_int(v, &value, name, errp);
1090 if (error_is_set(errp)) {
1091 return;
1092 }
1093 if (value < min || value > max) {
1094 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1095 name ? name : "null", value, min, max);
1096 return;
1097 }
1098
1099 env->cpuid_version &= ~0xf00f0;
1100 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1101 }
1102
1103 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1104 void *opaque, const char *name,
1105 Error **errp)
1106 {
1107 X86CPU *cpu = X86_CPU(obj);
1108 CPUX86State *env = &cpu->env;
1109 int64_t value;
1110
1111 value = env->cpuid_version & 0xf;
1112 visit_type_int(v, &value, name, errp);
1113 }
1114
1115 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1116 void *opaque, const char *name,
1117 Error **errp)
1118 {
1119 X86CPU *cpu = X86_CPU(obj);
1120 CPUX86State *env = &cpu->env;
1121 const int64_t min = 0;
1122 const int64_t max = 0xf;
1123 int64_t value;
1124
1125 visit_type_int(v, &value, name, errp);
1126 if (error_is_set(errp)) {
1127 return;
1128 }
1129 if (value < min || value > max) {
1130 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1131 name ? name : "null", value, min, max);
1132 return;
1133 }
1134
1135 env->cpuid_version &= ~0xf;
1136 env->cpuid_version |= value & 0xf;
1137 }
1138
1139 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1140 const char *name, Error **errp)
1141 {
1142 X86CPU *cpu = X86_CPU(obj);
1143
1144 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1145 }
1146
1147 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1148 const char *name, Error **errp)
1149 {
1150 X86CPU *cpu = X86_CPU(obj);
1151
1152 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1153 }
1154
1155 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1156 const char *name, Error **errp)
1157 {
1158 X86CPU *cpu = X86_CPU(obj);
1159
1160 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1161 }
1162
1163 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1164 const char *name, Error **errp)
1165 {
1166 X86CPU *cpu = X86_CPU(obj);
1167
1168 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1169 }
1170
1171 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1172 {
1173 X86CPU *cpu = X86_CPU(obj);
1174 CPUX86State *env = &cpu->env;
1175 char *value;
1176
1177 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1178 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1179 env->cpuid_vendor3);
1180 return value;
1181 }
1182
1183 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1184 Error **errp)
1185 {
1186 X86CPU *cpu = X86_CPU(obj);
1187 CPUX86State *env = &cpu->env;
1188 int i;
1189
1190 if (strlen(value) != CPUID_VENDOR_SZ) {
1191 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1192 "vendor", value);
1193 return;
1194 }
1195
1196 env->cpuid_vendor1 = 0;
1197 env->cpuid_vendor2 = 0;
1198 env->cpuid_vendor3 = 0;
1199 for (i = 0; i < 4; i++) {
1200 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1201 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1202 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1203 }
1204 }
1205
1206 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1207 {
1208 X86CPU *cpu = X86_CPU(obj);
1209 CPUX86State *env = &cpu->env;
1210 char *value;
1211 int i;
1212
1213 value = g_malloc(48 + 1);
1214 for (i = 0; i < 48; i++) {
1215 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1216 }
1217 value[48] = '\0';
1218 return value;
1219 }
1220
1221 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1222 Error **errp)
1223 {
1224 X86CPU *cpu = X86_CPU(obj);
1225 CPUX86State *env = &cpu->env;
1226 int c, len, i;
1227
1228 if (model_id == NULL) {
1229 model_id = "";
1230 }
1231 len = strlen(model_id);
1232 memset(env->cpuid_model, 0, 48);
1233 for (i = 0; i < 48; i++) {
1234 if (i >= len) {
1235 c = '\0';
1236 } else {
1237 c = (uint8_t)model_id[i];
1238 }
1239 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1240 }
1241 }
1242
1243 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1244 const char *name, Error **errp)
1245 {
1246 X86CPU *cpu = X86_CPU(obj);
1247 int64_t value;
1248
1249 value = cpu->env.tsc_khz * 1000;
1250 visit_type_int(v, &value, name, errp);
1251 }
1252
1253 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1254 const char *name, Error **errp)
1255 {
1256 X86CPU *cpu = X86_CPU(obj);
1257 const int64_t min = 0;
1258 const int64_t max = INT64_MAX;
1259 int64_t value;
1260
1261 visit_type_int(v, &value, name, errp);
1262 if (error_is_set(errp)) {
1263 return;
1264 }
1265 if (value < min || value > max) {
1266 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1267 name ? name : "null", value, min, max);
1268 return;
1269 }
1270
1271 cpu->env.tsc_khz = value / 1000;
1272 }
1273
1274 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1275 {
1276 x86_def_t *def;
1277 int i;
1278
1279 if (name == NULL) {
1280 return -1;
1281 }
1282 if (kvm_enabled() && strcmp(name, "host") == 0) {
1283 kvm_cpu_fill_host(x86_cpu_def);
1284 return 0;
1285 }
1286
1287 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1288 def = &builtin_x86_defs[i];
1289 if (strcmp(name, def->name) == 0) {
1290 memcpy(x86_cpu_def, def, sizeof(*def));
1291 /* sysenter isn't supported in compatibility mode on AMD,
1292 * syscall isn't supported in compatibility mode on Intel.
1293 * Normally we advertise the actual CPU vendor, but you can
1294 * override this using the 'vendor' property if you want to use
1295 * KVM's sysenter/syscall emulation in compatibility mode and
1296 * when doing cross vendor migration
1297 */
1298 if (kvm_enabled()) {
1299 uint32_t ebx = 0, ecx = 0, edx = 0;
1300 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1301 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1302 }
1303 return 0;
1304 }
1305 }
1306
1307 return -1;
1308 }
1309
1310 /* Convert all '_' in a feature string option name to '-', to make feature
1311 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1312 */
1313 static inline void feat2prop(char *s)
1314 {
1315 while ((s = strchr(s, '_'))) {
1316 *s = '-';
1317 }
1318 }
1319
1320 /* Parse "+feature,-feature,feature=foo" CPU feature string
1321 */
1322 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1323 {
1324 char *featurestr; /* Single 'key=value" string being parsed */
1325 /* Features to be added */
1326 FeatureWordArray plus_features = { 0 };
1327 /* Features to be removed */
1328 FeatureWordArray minus_features = { 0 };
1329 uint32_t numvalue;
1330 CPUX86State *env = &cpu->env;
1331
1332 featurestr = features ? strtok(features, ",") : NULL;
1333
1334 while (featurestr) {
1335 char *val;
1336 if (featurestr[0] == '+') {
1337 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1338 } else if (featurestr[0] == '-') {
1339 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1340 } else if ((val = strchr(featurestr, '='))) {
1341 *val = 0; val++;
1342 feat2prop(featurestr);
1343 if (!strcmp(featurestr, "family")) {
1344 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1345 } else if (!strcmp(featurestr, "model")) {
1346 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1347 } else if (!strcmp(featurestr, "stepping")) {
1348 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1349 } else if (!strcmp(featurestr, "level")) {
1350 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1351 } else if (!strcmp(featurestr, "xlevel")) {
1352 char *err;
1353 char num[32];
1354
1355 numvalue = strtoul(val, &err, 0);
1356 if (!*val || *err) {
1357 error_setg(errp, "bad numerical value %s", val);
1358 goto out;
1359 }
1360 if (numvalue < 0x80000000) {
1361 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1362 ", fixup will be removed in future versions\n");
1363 numvalue += 0x80000000;
1364 }
1365 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1366 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1367 } else if (!strcmp(featurestr, "vendor")) {
1368 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1369 } else if (!strcmp(featurestr, "model-id")) {
1370 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1371 } else if (!strcmp(featurestr, "tsc-freq")) {
1372 int64_t tsc_freq;
1373 char *err;
1374 char num[32];
1375
1376 tsc_freq = strtosz_suffix_unit(val, &err,
1377 STRTOSZ_DEFSUFFIX_B, 1000);
1378 if (tsc_freq < 0 || *err) {
1379 error_setg(errp, "bad numerical value %s", val);
1380 goto out;
1381 }
1382 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1383 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1384 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1385 char *err;
1386 numvalue = strtoul(val, &err, 0);
1387 if (!*val || *err) {
1388 error_setg(errp, "bad numerical value %s", val);
1389 goto out;
1390 }
1391 hyperv_set_spinlock_retries(numvalue);
1392 } else {
1393 error_setg(errp, "unrecognized feature %s", featurestr);
1394 goto out;
1395 }
1396 } else if (!strcmp(featurestr, "check")) {
1397 check_cpuid = 1;
1398 } else if (!strcmp(featurestr, "enforce")) {
1399 check_cpuid = enforce_cpuid = 1;
1400 } else if (!strcmp(featurestr, "hv_relaxed")) {
1401 hyperv_enable_relaxed_timing(true);
1402 } else if (!strcmp(featurestr, "hv_vapic")) {
1403 hyperv_enable_vapic_recommended(true);
1404 } else {
1405 error_setg(errp, "feature string `%s' not in format (+feature|"
1406 "-feature|feature=xyz)", featurestr);
1407 goto out;
1408 }
1409 if (error_is_set(errp)) {
1410 goto out;
1411 }
1412 featurestr = strtok(NULL, ",");
1413 }
1414 env->cpuid_features |= plus_features[FEAT_1_EDX];
1415 env->cpuid_ext_features |= plus_features[FEAT_1_ECX];
1416 env->cpuid_ext2_features |= plus_features[FEAT_8000_0001_EDX];
1417 env->cpuid_ext3_features |= plus_features[FEAT_8000_0001_ECX];
1418 env->cpuid_ext4_features |= plus_features[FEAT_C000_0001_EDX];
1419 env->cpuid_kvm_features |= plus_features[FEAT_KVM];
1420 env->cpuid_svm_features |= plus_features[FEAT_SVM];
1421 env->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1422 env->cpuid_features &= ~minus_features[FEAT_1_EDX];
1423 env->cpuid_ext_features &= ~minus_features[FEAT_1_ECX];
1424 env->cpuid_ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1425 env->cpuid_ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1426 env->cpuid_ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1427 env->cpuid_kvm_features &= ~minus_features[FEAT_KVM];
1428 env->cpuid_svm_features &= ~minus_features[FEAT_SVM];
1429 env->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1430
1431 out:
1432 return;
1433 }
1434
1435 /* generate a composite string into buf of all cpuid names in featureset
1436 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1437 * if flags, suppress names undefined in featureset.
1438 */
1439 static void listflags(char *buf, int bufsize, uint32_t fbits,
1440 const char **featureset, uint32_t flags)
1441 {
1442 const char **p = &featureset[31];
1443 char *q, *b, bit;
1444 int nc;
1445
1446 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1447 *buf = '\0';
1448 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1449 if (fbits & 1 << bit && (*p || !flags)) {
1450 if (*p)
1451 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1452 else
1453 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1454 if (bufsize <= nc) {
1455 if (b) {
1456 memcpy(b, "...", sizeof("..."));
1457 }
1458 return;
1459 }
1460 q += nc;
1461 bufsize -= nc;
1462 }
1463 }
1464
1465 /* generate CPU information. */
1466 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1467 {
1468 x86_def_t *def;
1469 char buf[256];
1470 int i;
1471
1472 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1473 def = &builtin_x86_defs[i];
1474 snprintf(buf, sizeof(buf), "%s", def->name);
1475 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1476 }
1477 #ifdef CONFIG_KVM
1478 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1479 "KVM processor with all supported host features "
1480 "(only available in KVM mode)");
1481 #endif
1482
1483 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1484 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1485 FeatureWordInfo *fw = &feature_word_info[i];
1486
1487 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1488 (*cpu_fprintf)(f, " %s\n", buf);
1489 }
1490 }
1491
1492 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1493 {
1494 CpuDefinitionInfoList *cpu_list = NULL;
1495 x86_def_t *def;
1496 int i;
1497
1498 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1499 CpuDefinitionInfoList *entry;
1500 CpuDefinitionInfo *info;
1501
1502 def = &builtin_x86_defs[i];
1503 info = g_malloc0(sizeof(*info));
1504 info->name = g_strdup(def->name);
1505
1506 entry = g_malloc0(sizeof(*entry));
1507 entry->value = info;
1508 entry->next = cpu_list;
1509 cpu_list = entry;
1510 }
1511
1512 return cpu_list;
1513 }
1514
1515 #ifdef CONFIG_KVM
1516 static void filter_features_for_kvm(X86CPU *cpu)
1517 {
1518 CPUX86State *env = &cpu->env;
1519 KVMState *s = kvm_state;
1520
1521 env->cpuid_features &=
1522 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1523 env->cpuid_ext_features &=
1524 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1525 env->cpuid_ext2_features &=
1526 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1527 env->cpuid_ext3_features &=
1528 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1529 env->cpuid_svm_features &=
1530 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1531 env->cpuid_7_0_ebx_features &=
1532 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1533 env->cpuid_kvm_features &=
1534 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1535 env->cpuid_ext4_features &=
1536 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1537
1538 }
1539 #endif
1540
1541 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1542 {
1543 CPUX86State *env = &cpu->env;
1544 x86_def_t def1, *def = &def1;
1545
1546 memset(def, 0, sizeof(*def));
1547
1548 if (cpu_x86_find_by_name(def, name) < 0) {
1549 error_setg(errp, "Unable to find CPU definition: %s", name);
1550 return;
1551 }
1552
1553 if (kvm_enabled()) {
1554 def->kvm_features |= kvm_default_features;
1555 }
1556 def->ext_features |= CPUID_EXT_HYPERVISOR;
1557
1558 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1559 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1560 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1561 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1562 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1563 env->cpuid_features = def->features;
1564 env->cpuid_ext_features = def->ext_features;
1565 env->cpuid_ext2_features = def->ext2_features;
1566 env->cpuid_ext3_features = def->ext3_features;
1567 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1568 env->cpuid_kvm_features = def->kvm_features;
1569 env->cpuid_svm_features = def->svm_features;
1570 env->cpuid_ext4_features = def->ext4_features;
1571 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1572 env->cpuid_xlevel2 = def->xlevel2;
1573
1574 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1575 }
1576
1577 X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
1578 {
1579 X86CPU *cpu = NULL;
1580 CPUX86State *env;
1581 gchar **model_pieces;
1582 char *name, *features;
1583 Error *error = NULL;
1584
1585 model_pieces = g_strsplit(cpu_model, ",", 2);
1586 if (!model_pieces[0]) {
1587 error_setg(&error, "Invalid/empty CPU model name");
1588 goto out;
1589 }
1590 name = model_pieces[0];
1591 features = model_pieces[1];
1592
1593 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1594 env = &cpu->env;
1595 env->cpu_model_str = cpu_model;
1596
1597 cpu_x86_register(cpu, name, &error);
1598 if (error) {
1599 goto out;
1600 }
1601
1602 cpu_x86_parse_featurestr(cpu, features, &error);
1603 if (error) {
1604 goto out;
1605 }
1606
1607 out:
1608 error_propagate(errp, error);
1609 g_strfreev(model_pieces);
1610 return cpu;
1611 }
1612
1613 X86CPU *cpu_x86_init(const char *cpu_model)
1614 {
1615 Error *error = NULL;
1616 X86CPU *cpu;
1617
1618 cpu = cpu_x86_create(cpu_model, &error);
1619 if (error) {
1620 goto out;
1621 }
1622
1623 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1624
1625 out:
1626 if (error) {
1627 fprintf(stderr, "%s\n", error_get_pretty(error));
1628 error_free(error);
1629 if (cpu != NULL) {
1630 object_unref(OBJECT(cpu));
1631 cpu = NULL;
1632 }
1633 }
1634 return cpu;
1635 }
1636
1637 #if !defined(CONFIG_USER_ONLY)
1638
1639 void cpu_clear_apic_feature(CPUX86State *env)
1640 {
1641 env->cpuid_features &= ~CPUID_APIC;
1642 }
1643
1644 #endif /* !CONFIG_USER_ONLY */
1645
1646 /* Initialize list of CPU models, filling some non-static fields if necessary
1647 */
1648 void x86_cpudef_setup(void)
1649 {
1650 int i, j;
1651 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1652
1653 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1654 x86_def_t *def = &builtin_x86_defs[i];
1655
1656 /* Look for specific "cpudef" models that */
1657 /* have the QEMU version in .model_id */
1658 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1659 if (strcmp(model_with_versions[j], def->name) == 0) {
1660 pstrcpy(def->model_id, sizeof(def->model_id),
1661 "QEMU Virtual CPU version ");
1662 pstrcat(def->model_id, sizeof(def->model_id),
1663 qemu_get_version());
1664 break;
1665 }
1666 }
1667 }
1668 }
1669
1670 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1671 uint32_t *ecx, uint32_t *edx)
1672 {
1673 *ebx = env->cpuid_vendor1;
1674 *edx = env->cpuid_vendor2;
1675 *ecx = env->cpuid_vendor3;
1676 }
1677
1678 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1679 uint32_t *eax, uint32_t *ebx,
1680 uint32_t *ecx, uint32_t *edx)
1681 {
1682 X86CPU *cpu = x86_env_get_cpu(env);
1683 CPUState *cs = CPU(cpu);
1684
1685 /* test if maximum index reached */
1686 if (index & 0x80000000) {
1687 if (index > env->cpuid_xlevel) {
1688 if (env->cpuid_xlevel2 > 0) {
1689 /* Handle the Centaur's CPUID instruction. */
1690 if (index > env->cpuid_xlevel2) {
1691 index = env->cpuid_xlevel2;
1692 } else if (index < 0xC0000000) {
1693 index = env->cpuid_xlevel;
1694 }
1695 } else {
1696 /* Intel documentation states that invalid EAX input will
1697 * return the same information as EAX=cpuid_level
1698 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1699 */
1700 index = env->cpuid_level;
1701 }
1702 }
1703 } else {
1704 if (index > env->cpuid_level)
1705 index = env->cpuid_level;
1706 }
1707
1708 switch(index) {
1709 case 0:
1710 *eax = env->cpuid_level;
1711 get_cpuid_vendor(env, ebx, ecx, edx);
1712 break;
1713 case 1:
1714 *eax = env->cpuid_version;
1715 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1716 *ecx = env->cpuid_ext_features;
1717 *edx = env->cpuid_features;
1718 if (cs->nr_cores * cs->nr_threads > 1) {
1719 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1720 *edx |= 1 << 28; /* HTT bit */
1721 }
1722 break;
1723 case 2:
1724 /* cache info: needed for Pentium Pro compatibility */
1725 *eax = 1;
1726 *ebx = 0;
1727 *ecx = 0;
1728 *edx = 0x2c307d;
1729 break;
1730 case 4:
1731 /* cache info: needed for Core compatibility */
1732 if (cs->nr_cores > 1) {
1733 *eax = (cs->nr_cores - 1) << 26;
1734 } else {
1735 *eax = 0;
1736 }
1737 switch (count) {
1738 case 0: /* L1 dcache info */
1739 *eax |= 0x0000121;
1740 *ebx = 0x1c0003f;
1741 *ecx = 0x000003f;
1742 *edx = 0x0000001;
1743 break;
1744 case 1: /* L1 icache info */
1745 *eax |= 0x0000122;
1746 *ebx = 0x1c0003f;
1747 *ecx = 0x000003f;
1748 *edx = 0x0000001;
1749 break;
1750 case 2: /* L2 cache info */
1751 *eax |= 0x0000143;
1752 if (cs->nr_threads > 1) {
1753 *eax |= (cs->nr_threads - 1) << 14;
1754 }
1755 *ebx = 0x3c0003f;
1756 *ecx = 0x0000fff;
1757 *edx = 0x0000001;
1758 break;
1759 default: /* end of info */
1760 *eax = 0;
1761 *ebx = 0;
1762 *ecx = 0;
1763 *edx = 0;
1764 break;
1765 }
1766 break;
1767 case 5:
1768 /* mwait info: needed for Core compatibility */
1769 *eax = 0; /* Smallest monitor-line size in bytes */
1770 *ebx = 0; /* Largest monitor-line size in bytes */
1771 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1772 *edx = 0;
1773 break;
1774 case 6:
1775 /* Thermal and Power Leaf */
1776 *eax = 0;
1777 *ebx = 0;
1778 *ecx = 0;
1779 *edx = 0;
1780 break;
1781 case 7:
1782 /* Structured Extended Feature Flags Enumeration Leaf */
1783 if (count == 0) {
1784 *eax = 0; /* Maximum ECX value for sub-leaves */
1785 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1786 *ecx = 0; /* Reserved */
1787 *edx = 0; /* Reserved */
1788 } else {
1789 *eax = 0;
1790 *ebx = 0;
1791 *ecx = 0;
1792 *edx = 0;
1793 }
1794 break;
1795 case 9:
1796 /* Direct Cache Access Information Leaf */
1797 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1798 *ebx = 0;
1799 *ecx = 0;
1800 *edx = 0;
1801 break;
1802 case 0xA:
1803 /* Architectural Performance Monitoring Leaf */
1804 if (kvm_enabled()) {
1805 KVMState *s = cs->kvm_state;
1806
1807 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1808 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1809 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1810 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1811 } else {
1812 *eax = 0;
1813 *ebx = 0;
1814 *ecx = 0;
1815 *edx = 0;
1816 }
1817 break;
1818 case 0xD:
1819 /* Processor Extended State */
1820 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1821 *eax = 0;
1822 *ebx = 0;
1823 *ecx = 0;
1824 *edx = 0;
1825 break;
1826 }
1827 if (kvm_enabled()) {
1828 KVMState *s = cs->kvm_state;
1829
1830 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1831 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1832 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1833 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1834 } else {
1835 *eax = 0;
1836 *ebx = 0;
1837 *ecx = 0;
1838 *edx = 0;
1839 }
1840 break;
1841 case 0x80000000:
1842 *eax = env->cpuid_xlevel;
1843 *ebx = env->cpuid_vendor1;
1844 *edx = env->cpuid_vendor2;
1845 *ecx = env->cpuid_vendor3;
1846 break;
1847 case 0x80000001:
1848 *eax = env->cpuid_version;
1849 *ebx = 0;
1850 *ecx = env->cpuid_ext3_features;
1851 *edx = env->cpuid_ext2_features;
1852
1853 /* The Linux kernel checks for the CMPLegacy bit and
1854 * discards multiple thread information if it is set.
1855 * So dont set it here for Intel to make Linux guests happy.
1856 */
1857 if (cs->nr_cores * cs->nr_threads > 1) {
1858 uint32_t tebx, tecx, tedx;
1859 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1860 if (tebx != CPUID_VENDOR_INTEL_1 ||
1861 tedx != CPUID_VENDOR_INTEL_2 ||
1862 tecx != CPUID_VENDOR_INTEL_3) {
1863 *ecx |= 1 << 1; /* CmpLegacy bit */
1864 }
1865 }
1866 break;
1867 case 0x80000002:
1868 case 0x80000003:
1869 case 0x80000004:
1870 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1871 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1872 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1873 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1874 break;
1875 case 0x80000005:
1876 /* cache info (L1 cache) */
1877 *eax = 0x01ff01ff;
1878 *ebx = 0x01ff01ff;
1879 *ecx = 0x40020140;
1880 *edx = 0x40020140;
1881 break;
1882 case 0x80000006:
1883 /* cache info (L2 cache) */
1884 *eax = 0;
1885 *ebx = 0x42004200;
1886 *ecx = 0x02008140;
1887 *edx = 0;
1888 break;
1889 case 0x80000008:
1890 /* virtual & phys address size in low 2 bytes. */
1891 /* XXX: This value must match the one used in the MMU code. */
1892 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1893 /* 64 bit processor */
1894 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1895 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1896 } else {
1897 if (env->cpuid_features & CPUID_PSE36) {
1898 *eax = 0x00000024; /* 36 bits physical */
1899 } else {
1900 *eax = 0x00000020; /* 32 bits physical */
1901 }
1902 }
1903 *ebx = 0;
1904 *ecx = 0;
1905 *edx = 0;
1906 if (cs->nr_cores * cs->nr_threads > 1) {
1907 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1908 }
1909 break;
1910 case 0x8000000A:
1911 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1912 *eax = 0x00000001; /* SVM Revision */
1913 *ebx = 0x00000010; /* nr of ASIDs */
1914 *ecx = 0;
1915 *edx = env->cpuid_svm_features; /* optional features */
1916 } else {
1917 *eax = 0;
1918 *ebx = 0;
1919 *ecx = 0;
1920 *edx = 0;
1921 }
1922 break;
1923 case 0xC0000000:
1924 *eax = env->cpuid_xlevel2;
1925 *ebx = 0;
1926 *ecx = 0;
1927 *edx = 0;
1928 break;
1929 case 0xC0000001:
1930 /* Support for VIA CPU's CPUID instruction */
1931 *eax = env->cpuid_version;
1932 *ebx = 0;
1933 *ecx = 0;
1934 *edx = env->cpuid_ext4_features;
1935 break;
1936 case 0xC0000002:
1937 case 0xC0000003:
1938 case 0xC0000004:
1939 /* Reserved for the future, and now filled with zero */
1940 *eax = 0;
1941 *ebx = 0;
1942 *ecx = 0;
1943 *edx = 0;
1944 break;
1945 default:
1946 /* reserved values: zero */
1947 *eax = 0;
1948 *ebx = 0;
1949 *ecx = 0;
1950 *edx = 0;
1951 break;
1952 }
1953 }
1954
1955 /* CPUClass::reset() */
1956 static void x86_cpu_reset(CPUState *s)
1957 {
1958 X86CPU *cpu = X86_CPU(s);
1959 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1960 CPUX86State *env = &cpu->env;
1961 int i;
1962
1963 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1964 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1965 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1966 }
1967
1968 xcc->parent_reset(s);
1969
1970
1971 memset(env, 0, offsetof(CPUX86State, breakpoints));
1972
1973 tlb_flush(env, 1);
1974
1975 env->old_exception = -1;
1976
1977 /* init to reset state */
1978
1979 #ifdef CONFIG_SOFTMMU
1980 env->hflags |= HF_SOFTMMU_MASK;
1981 #endif
1982 env->hflags2 |= HF2_GIF_MASK;
1983
1984 cpu_x86_update_cr0(env, 0x60000010);
1985 env->a20_mask = ~0x0;
1986 env->smbase = 0x30000;
1987
1988 env->idt.limit = 0xffff;
1989 env->gdt.limit = 0xffff;
1990 env->ldt.limit = 0xffff;
1991 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1992 env->tr.limit = 0xffff;
1993 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1994
1995 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1996 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1997 DESC_R_MASK | DESC_A_MASK);
1998 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1999 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2000 DESC_A_MASK);
2001 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2002 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2003 DESC_A_MASK);
2004 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2005 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2006 DESC_A_MASK);
2007 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2008 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2009 DESC_A_MASK);
2010 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2011 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2012 DESC_A_MASK);
2013
2014 env->eip = 0xfff0;
2015 env->regs[R_EDX] = env->cpuid_version;
2016
2017 env->eflags = 0x2;
2018
2019 /* FPU init */
2020 for (i = 0; i < 8; i++) {
2021 env->fptags[i] = 1;
2022 }
2023 env->fpuc = 0x37f;
2024
2025 env->mxcsr = 0x1f80;
2026
2027 env->pat = 0x0007040600070406ULL;
2028 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2029
2030 memset(env->dr, 0, sizeof(env->dr));
2031 env->dr[6] = DR6_FIXED_1;
2032 env->dr[7] = DR7_FIXED_1;
2033 cpu_breakpoint_remove_all(env, BP_CPU);
2034 cpu_watchpoint_remove_all(env, BP_CPU);
2035
2036 #if !defined(CONFIG_USER_ONLY)
2037 /* We hard-wire the BSP to the first CPU. */
2038 if (s->cpu_index == 0) {
2039 apic_designate_bsp(env->apic_state);
2040 }
2041
2042 s->halted = !cpu_is_bsp(cpu);
2043 #endif
2044 }
2045
2046 #ifndef CONFIG_USER_ONLY
2047 bool cpu_is_bsp(X86CPU *cpu)
2048 {
2049 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2050 }
2051
2052 /* TODO: remove me, when reset over QOM tree is implemented */
2053 static void x86_cpu_machine_reset_cb(void *opaque)
2054 {
2055 X86CPU *cpu = opaque;
2056 cpu_reset(CPU(cpu));
2057 }
2058 #endif
2059
2060 static void mce_init(X86CPU *cpu)
2061 {
2062 CPUX86State *cenv = &cpu->env;
2063 unsigned int bank;
2064
2065 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2066 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2067 (CPUID_MCE | CPUID_MCA)) {
2068 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2069 cenv->mcg_ctl = ~(uint64_t)0;
2070 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2071 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2072 }
2073 }
2074 }
2075
2076 #ifndef CONFIG_USER_ONLY
2077 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2078 {
2079 CPUX86State *env = &cpu->env;
2080 APICCommonState *apic;
2081 const char *apic_type = "apic";
2082
2083 if (kvm_irqchip_in_kernel()) {
2084 apic_type = "kvm-apic";
2085 } else if (xen_enabled()) {
2086 apic_type = "xen-apic";
2087 }
2088
2089 env->apic_state = qdev_try_create(NULL, apic_type);
2090 if (env->apic_state == NULL) {
2091 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2092 return;
2093 }
2094
2095 object_property_add_child(OBJECT(cpu), "apic",
2096 OBJECT(env->apic_state), NULL);
2097 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2098 /* TODO: convert to link<> */
2099 apic = APIC_COMMON(env->apic_state);
2100 apic->cpu = cpu;
2101 }
2102
2103 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2104 {
2105 CPUX86State *env = &cpu->env;
2106 static int apic_mapped;
2107
2108 if (env->apic_state == NULL) {
2109 return;
2110 }
2111
2112 if (qdev_init(env->apic_state)) {
2113 error_setg(errp, "APIC device '%s' could not be initialized",
2114 object_get_typename(OBJECT(env->apic_state)));
2115 return;
2116 }
2117
2118 /* XXX: mapping more APICs at the same memory location */
2119 if (apic_mapped == 0) {
2120 /* NOTE: the APIC is directly connected to the CPU - it is not
2121 on the global memory bus. */
2122 /* XXX: what if the base changes? */
2123 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(env->apic_state), 0,
2124 APIC_DEFAULT_ADDRESS, 0x1000);
2125 apic_mapped = 1;
2126 }
2127 }
2128 #else
2129 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2130 {
2131 }
2132 #endif
2133
2134 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2135 {
2136 X86CPU *cpu = X86_CPU(dev);
2137 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2138 CPUX86State *env = &cpu->env;
2139 Error *local_err = NULL;
2140
2141 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2142 env->cpuid_level = 7;
2143 }
2144
2145 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2146 * CPUID[1].EDX.
2147 */
2148 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2149 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2150 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2151 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2152 env->cpuid_ext2_features |= (env->cpuid_features
2153 & CPUID_EXT2_AMD_ALIASES);
2154 }
2155
2156 if (!kvm_enabled()) {
2157 env->cpuid_features &= TCG_FEATURES;
2158 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2159 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2160 #ifdef TARGET_X86_64
2161 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2162 #endif
2163 );
2164 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2165 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2166 } else {
2167 if (check_cpuid && kvm_check_features_against_host(cpu)
2168 && enforce_cpuid) {
2169 error_setg(&local_err,
2170 "Host's CPU doesn't support requested features");
2171 goto out;
2172 }
2173 #ifdef CONFIG_KVM
2174 filter_features_for_kvm(cpu);
2175 #endif
2176 }
2177
2178 #ifndef CONFIG_USER_ONLY
2179 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2180
2181 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2182 x86_cpu_apic_create(cpu, &local_err);
2183 if (local_err != NULL) {
2184 goto out;
2185 }
2186 }
2187 #endif
2188
2189 mce_init(cpu);
2190 qemu_init_vcpu(&cpu->env);
2191
2192 x86_cpu_apic_realize(cpu, &local_err);
2193 if (local_err != NULL) {
2194 goto out;
2195 }
2196 cpu_reset(CPU(cpu));
2197
2198 xcc->parent_realize(dev, &local_err);
2199 out:
2200 if (local_err != NULL) {
2201 error_propagate(errp, local_err);
2202 return;
2203 }
2204 }
2205
2206 /* Enables contiguous-apic-ID mode, for compatibility */
2207 static bool compat_apic_id_mode;
2208
2209 void enable_compat_apic_id_mode(void)
2210 {
2211 compat_apic_id_mode = true;
2212 }
2213
2214 /* Calculates initial APIC ID for a specific CPU index
2215 *
2216 * Currently we need to be able to calculate the APIC ID from the CPU index
2217 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2218 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2219 * all CPUs up to max_cpus.
2220 */
2221 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2222 {
2223 uint32_t correct_id;
2224 static bool warned;
2225
2226 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2227 if (compat_apic_id_mode) {
2228 if (cpu_index != correct_id && !warned) {
2229 error_report("APIC IDs set in compatibility mode, "
2230 "CPU topology won't match the configuration");
2231 warned = true;
2232 }
2233 return cpu_index;
2234 } else {
2235 return correct_id;
2236 }
2237 }
2238
2239 static void x86_cpu_initfn(Object *obj)
2240 {
2241 CPUState *cs = CPU(obj);
2242 X86CPU *cpu = X86_CPU(obj);
2243 CPUX86State *env = &cpu->env;
2244 static int inited;
2245
2246 cs->env_ptr = env;
2247 cpu_exec_init(env);
2248
2249 object_property_add(obj, "family", "int",
2250 x86_cpuid_version_get_family,
2251 x86_cpuid_version_set_family, NULL, NULL, NULL);
2252 object_property_add(obj, "model", "int",
2253 x86_cpuid_version_get_model,
2254 x86_cpuid_version_set_model, NULL, NULL, NULL);
2255 object_property_add(obj, "stepping", "int",
2256 x86_cpuid_version_get_stepping,
2257 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2258 object_property_add(obj, "level", "int",
2259 x86_cpuid_get_level,
2260 x86_cpuid_set_level, NULL, NULL, NULL);
2261 object_property_add(obj, "xlevel", "int",
2262 x86_cpuid_get_xlevel,
2263 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2264 object_property_add_str(obj, "vendor",
2265 x86_cpuid_get_vendor,
2266 x86_cpuid_set_vendor, NULL);
2267 object_property_add_str(obj, "model-id",
2268 x86_cpuid_get_model_id,
2269 x86_cpuid_set_model_id, NULL);
2270 object_property_add(obj, "tsc-frequency", "int",
2271 x86_cpuid_get_tsc_freq,
2272 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2273
2274 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2275
2276 /* init various static tables used in TCG mode */
2277 if (tcg_enabled() && !inited) {
2278 inited = 1;
2279 optimize_flags_init();
2280 #ifndef CONFIG_USER_ONLY
2281 cpu_set_debug_excp_handler(breakpoint_handler);
2282 #endif
2283 }
2284 }
2285
2286 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2287 {
2288 X86CPU *cpu = X86_CPU(cs);
2289 CPUX86State *env = &cpu->env;
2290
2291 return env->cpuid_apic_id;
2292 }
2293
2294 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2295 {
2296 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2297 CPUClass *cc = CPU_CLASS(oc);
2298 DeviceClass *dc = DEVICE_CLASS(oc);
2299
2300 xcc->parent_realize = dc->realize;
2301 dc->realize = x86_cpu_realizefn;
2302
2303 xcc->parent_reset = cc->reset;
2304 cc->reset = x86_cpu_reset;
2305
2306 cc->do_interrupt = x86_cpu_do_interrupt;
2307 cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
2308
2309 cc->get_arch_id = x86_cpu_get_arch_id;
2310 }
2311
2312 static const TypeInfo x86_cpu_type_info = {
2313 .name = TYPE_X86_CPU,
2314 .parent = TYPE_CPU,
2315 .instance_size = sizeof(X86CPU),
2316 .instance_init = x86_cpu_initfn,
2317 .abstract = false,
2318 .class_size = sizeof(X86CPUClass),
2319 .class_init = x86_cpu_common_class_init,
2320 };
2321
2322 static void x86_cpu_register_types(void)
2323 {
2324 type_register_static(&x86_cpu_type_info);
2325 }
2326
2327 type_init(x86_cpu_register_types)
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