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1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "kvm.h"
26
27 #include "qemu-option.h"
28 #include "qemu-config.h"
29
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
32
33 #include "hyperv.h"
34
35 #include "hw/hw.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
38 #endif
39
40 #include "sysemu.h"
41 #ifndef CONFIG_USER_ONLY
42 #include "hw/xen.h"
43 #include "hw/sysbus.h"
44 #include "hw/apic_internal.h"
45 #endif
46
47 /* feature flags taken from "Intel Processor Identification and the CPUID
48 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
49 * between feature naming conventions, aliases may be added.
50 */
51 static const char *feature_name[] = {
52 "fpu", "vme", "de", "pse",
53 "tsc", "msr", "pae", "mce",
54 "cx8", "apic", NULL, "sep",
55 "mtrr", "pge", "mca", "cmov",
56 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
57 NULL, "ds" /* Intel dts */, "acpi", "mmx",
58 "fxsr", "sse", "sse2", "ss",
59 "ht" /* Intel htt */, "tm", "ia64", "pbe",
60 };
61 static const char *ext_feature_name[] = {
62 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
63 "ds_cpl", "vmx", "smx", "est",
64 "tm2", "ssse3", "cid", NULL,
65 "fma", "cx16", "xtpr", "pdcm",
66 NULL, "pcid", "dca", "sse4.1|sse4_1",
67 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
68 "tsc-deadline", "aes", "xsave", "osxsave",
69 "avx", "f16c", "rdrand", "hypervisor",
70 };
71 /* Feature names that are already defined on feature_name[] but are set on
72 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
73 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
74 * if and only if CPU vendor is AMD.
75 */
76 static const char *ext2_feature_name[] = {
77 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
78 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
79 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
80 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
81 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
82 "nx|xd", NULL, "mmxext", NULL /* mmx */,
83 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
84 NULL, "lm|i64", "3dnowext", "3dnow",
85 };
86 static const char *ext3_feature_name[] = {
87 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
88 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
89 "3dnowprefetch", "osvw", "ibs", "xop",
90 "skinit", "wdt", NULL, "lwp",
91 "fma4", "tce", NULL, "nodeid_msr",
92 NULL, "tbm", "topoext", "perfctr_core",
93 "perfctr_nb", NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95 };
96
97 static const char *kvm_feature_name[] = {
98 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
99 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
100 NULL, NULL, NULL, NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 };
107
108 static const char *svm_feature_name[] = {
109 "npt", "lbrv", "svm_lock", "nrip_save",
110 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
111 NULL, NULL, "pause_filter", NULL,
112 "pfthreshold", NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 };
118
119 static const char *cpuid_7_0_ebx_feature_name[] = {
120 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
121 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
122 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
123 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
124 };
125
126 /* collects per-function cpuid data
127 */
128 typedef struct model_features_t {
129 uint32_t *guest_feat;
130 uint32_t *host_feat;
131 uint32_t check_feat;
132 const char **flag_names;
133 uint32_t cpuid;
134 } model_features_t;
135
136 int check_cpuid = 0;
137 int enforce_cpuid = 0;
138
139 #if defined(CONFIG_KVM)
140 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
141 (1 << KVM_FEATURE_NOP_IO_DELAY) |
142 (1 << KVM_FEATURE_MMU_OP) |
143 (1 << KVM_FEATURE_CLOCKSOURCE2) |
144 (1 << KVM_FEATURE_ASYNC_PF) |
145 (1 << KVM_FEATURE_STEAL_TIME) |
146 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
147 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
148 #else
149 static uint32_t kvm_default_features = 0;
150 static const uint32_t kvm_pv_eoi_features = 0;
151 #endif
152
153 void enable_kvm_pv_eoi(void)
154 {
155 kvm_default_features |= kvm_pv_eoi_features;
156 }
157
158 void host_cpuid(uint32_t function, uint32_t count,
159 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
160 {
161 #if defined(CONFIG_KVM)
162 uint32_t vec[4];
163
164 #ifdef __x86_64__
165 asm volatile("cpuid"
166 : "=a"(vec[0]), "=b"(vec[1]),
167 "=c"(vec[2]), "=d"(vec[3])
168 : "0"(function), "c"(count) : "cc");
169 #else
170 asm volatile("pusha \n\t"
171 "cpuid \n\t"
172 "mov %%eax, 0(%2) \n\t"
173 "mov %%ebx, 4(%2) \n\t"
174 "mov %%ecx, 8(%2) \n\t"
175 "mov %%edx, 12(%2) \n\t"
176 "popa"
177 : : "a"(function), "c"(count), "S"(vec)
178 : "memory", "cc");
179 #endif
180
181 if (eax)
182 *eax = vec[0];
183 if (ebx)
184 *ebx = vec[1];
185 if (ecx)
186 *ecx = vec[2];
187 if (edx)
188 *edx = vec[3];
189 #endif
190 }
191
192 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
193
194 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
195 * a substring. ex if !NULL points to the first char after a substring,
196 * otherwise the string is assumed to sized by a terminating nul.
197 * Return lexical ordering of *s1:*s2.
198 */
199 static int sstrcmp(const char *s1, const char *e1, const char *s2,
200 const char *e2)
201 {
202 for (;;) {
203 if (!*s1 || !*s2 || *s1 != *s2)
204 return (*s1 - *s2);
205 ++s1, ++s2;
206 if (s1 == e1 && s2 == e2)
207 return (0);
208 else if (s1 == e1)
209 return (*s2);
210 else if (s2 == e2)
211 return (*s1);
212 }
213 }
214
215 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
216 * '|' delimited (possibly empty) strings in which case search for a match
217 * within the alternatives proceeds left to right. Return 0 for success,
218 * non-zero otherwise.
219 */
220 static int altcmp(const char *s, const char *e, const char *altstr)
221 {
222 const char *p, *q;
223
224 for (q = p = altstr; ; ) {
225 while (*p && *p != '|')
226 ++p;
227 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
228 return (0);
229 if (!*p)
230 return (1);
231 else
232 q = ++p;
233 }
234 }
235
236 /* search featureset for flag *[s..e), if found set corresponding bit in
237 * *pval and return true, otherwise return false
238 */
239 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
240 const char **featureset)
241 {
242 uint32_t mask;
243 const char **ppc;
244 bool found = false;
245
246 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
247 if (*ppc && !altcmp(s, e, *ppc)) {
248 *pval |= mask;
249 found = true;
250 }
251 }
252 return found;
253 }
254
255 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
256 uint32_t *ext_features,
257 uint32_t *ext2_features,
258 uint32_t *ext3_features,
259 uint32_t *kvm_features,
260 uint32_t *svm_features,
261 uint32_t *cpuid_7_0_ebx_features)
262 {
263 if (!lookup_feature(features, flagname, NULL, feature_name) &&
264 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
265 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
266 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
267 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
268 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
269 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
270 cpuid_7_0_ebx_feature_name))
271 fprintf(stderr, "CPU feature %s not found\n", flagname);
272 }
273
274 typedef struct x86_def_t {
275 struct x86_def_t *next;
276 const char *name;
277 uint32_t level;
278 uint32_t vendor1, vendor2, vendor3;
279 int family;
280 int model;
281 int stepping;
282 int tsc_khz;
283 uint32_t features, ext_features, ext2_features, ext3_features;
284 uint32_t kvm_features, svm_features;
285 uint32_t xlevel;
286 char model_id[48];
287 int vendor_override;
288 /* Store the results of Centaur's CPUID instructions */
289 uint32_t ext4_features;
290 uint32_t xlevel2;
291 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
292 uint32_t cpuid_7_0_ebx_features;
293 } x86_def_t;
294
295 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
296 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
297 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
298 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
299 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
300 CPUID_PSE36 | CPUID_FXSR)
301 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
302 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
303 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
304 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
305 CPUID_PAE | CPUID_SEP | CPUID_APIC)
306
307 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
308 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
309 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
310 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
311 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
312 /* partly implemented:
313 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
314 CPUID_PSE36 (needed for Solaris) */
315 /* missing:
316 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
317 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
318 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
319 CPUID_EXT_HYPERVISOR)
320 /* missing:
321 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
322 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
323 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
324 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
325 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
326 /* missing:
327 CPUID_EXT2_PDPE1GB */
328 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
329 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
330 #define TCG_SVM_FEATURES 0
331 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
332
333 /* maintains list of cpu model definitions
334 */
335 static x86_def_t *x86_defs = {NULL};
336
337 /* built-in cpu model definitions (deprecated)
338 */
339 static x86_def_t builtin_x86_defs[] = {
340 {
341 .name = "qemu64",
342 .level = 4,
343 .vendor1 = CPUID_VENDOR_AMD_1,
344 .vendor2 = CPUID_VENDOR_AMD_2,
345 .vendor3 = CPUID_VENDOR_AMD_3,
346 .family = 6,
347 .model = 2,
348 .stepping = 3,
349 .features = PPRO_FEATURES |
350 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
351 CPUID_PSE36,
352 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
353 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
354 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
355 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
356 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
357 .xlevel = 0x8000000A,
358 },
359 {
360 .name = "phenom",
361 .level = 5,
362 .vendor1 = CPUID_VENDOR_AMD_1,
363 .vendor2 = CPUID_VENDOR_AMD_2,
364 .vendor3 = CPUID_VENDOR_AMD_3,
365 .family = 16,
366 .model = 2,
367 .stepping = 3,
368 .features = PPRO_FEATURES |
369 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
370 CPUID_PSE36 | CPUID_VME | CPUID_HT,
371 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
372 CPUID_EXT_POPCNT,
373 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
374 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
375 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
376 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
377 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
378 CPUID_EXT3_CR8LEG,
379 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
380 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
381 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
382 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
383 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
384 .xlevel = 0x8000001A,
385 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
386 },
387 {
388 .name = "core2duo",
389 .level = 10,
390 .family = 6,
391 .model = 15,
392 .stepping = 11,
393 .features = PPRO_FEATURES |
394 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
395 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
396 CPUID_HT | CPUID_TM | CPUID_PBE,
397 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
398 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
399 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
400 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
401 .ext3_features = CPUID_EXT3_LAHF_LM,
402 .xlevel = 0x80000008,
403 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
404 },
405 {
406 .name = "kvm64",
407 .level = 5,
408 .vendor1 = CPUID_VENDOR_INTEL_1,
409 .vendor2 = CPUID_VENDOR_INTEL_2,
410 .vendor3 = CPUID_VENDOR_INTEL_3,
411 .family = 15,
412 .model = 6,
413 .stepping = 1,
414 /* Missing: CPUID_VME, CPUID_HT */
415 .features = PPRO_FEATURES |
416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
417 CPUID_PSE36,
418 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
420 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
421 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
422 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
423 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
424 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
425 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
426 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
427 .ext3_features = 0,
428 .xlevel = 0x80000008,
429 .model_id = "Common KVM processor"
430 },
431 {
432 .name = "qemu32",
433 .level = 4,
434 .family = 6,
435 .model = 3,
436 .stepping = 3,
437 .features = PPRO_FEATURES,
438 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
439 .xlevel = 0x80000004,
440 },
441 {
442 .name = "kvm32",
443 .level = 5,
444 .family = 15,
445 .model = 6,
446 .stepping = 1,
447 .features = PPRO_FEATURES |
448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
449 .ext_features = CPUID_EXT_SSE3,
450 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
451 .ext3_features = 0,
452 .xlevel = 0x80000008,
453 .model_id = "Common 32-bit KVM processor"
454 },
455 {
456 .name = "coreduo",
457 .level = 10,
458 .family = 6,
459 .model = 14,
460 .stepping = 8,
461 .features = PPRO_FEATURES | CPUID_VME |
462 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
463 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
464 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
465 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
466 .ext2_features = CPUID_EXT2_NX,
467 .xlevel = 0x80000008,
468 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
469 },
470 {
471 .name = "486",
472 .level = 1,
473 .family = 4,
474 .model = 0,
475 .stepping = 0,
476 .features = I486_FEATURES,
477 .xlevel = 0,
478 },
479 {
480 .name = "pentium",
481 .level = 1,
482 .family = 5,
483 .model = 4,
484 .stepping = 3,
485 .features = PENTIUM_FEATURES,
486 .xlevel = 0,
487 },
488 {
489 .name = "pentium2",
490 .level = 2,
491 .family = 6,
492 .model = 5,
493 .stepping = 2,
494 .features = PENTIUM2_FEATURES,
495 .xlevel = 0,
496 },
497 {
498 .name = "pentium3",
499 .level = 2,
500 .family = 6,
501 .model = 7,
502 .stepping = 3,
503 .features = PENTIUM3_FEATURES,
504 .xlevel = 0,
505 },
506 {
507 .name = "athlon",
508 .level = 2,
509 .vendor1 = CPUID_VENDOR_AMD_1,
510 .vendor2 = CPUID_VENDOR_AMD_2,
511 .vendor3 = CPUID_VENDOR_AMD_3,
512 .family = 6,
513 .model = 2,
514 .stepping = 3,
515 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
516 CPUID_MCA,
517 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
518 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
519 .xlevel = 0x80000008,
520 },
521 {
522 .name = "n270",
523 /* original is on level 10 */
524 .level = 5,
525 .family = 6,
526 .model = 28,
527 .stepping = 2,
528 .features = PPRO_FEATURES |
529 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
530 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
531 /* Some CPUs got no CPUID_SEP */
532 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
533 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
534 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
535 CPUID_EXT2_NX,
536 .ext3_features = CPUID_EXT3_LAHF_LM,
537 .xlevel = 0x8000000A,
538 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
539 },
540 {
541 .name = "Conroe",
542 .level = 2,
543 .vendor1 = CPUID_VENDOR_INTEL_1,
544 .vendor2 = CPUID_VENDOR_INTEL_2,
545 .vendor3 = CPUID_VENDOR_INTEL_3,
546 .family = 6,
547 .model = 2,
548 .stepping = 3,
549 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
550 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
551 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
552 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
553 CPUID_DE | CPUID_FP87,
554 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
555 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
556 .ext3_features = CPUID_EXT3_LAHF_LM,
557 .xlevel = 0x8000000A,
558 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
559 },
560 {
561 .name = "Penryn",
562 .level = 2,
563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
566 .family = 6,
567 .model = 2,
568 .stepping = 3,
569 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
570 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
571 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
572 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
573 CPUID_DE | CPUID_FP87,
574 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
575 CPUID_EXT_SSE3,
576 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
577 .ext3_features = CPUID_EXT3_LAHF_LM,
578 .xlevel = 0x8000000A,
579 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
580 },
581 {
582 .name = "Nehalem",
583 .level = 2,
584 .vendor1 = CPUID_VENDOR_INTEL_1,
585 .vendor2 = CPUID_VENDOR_INTEL_2,
586 .vendor3 = CPUID_VENDOR_INTEL_3,
587 .family = 6,
588 .model = 2,
589 .stepping = 3,
590 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
591 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
592 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
593 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
594 CPUID_DE | CPUID_FP87,
595 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
596 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
597 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
598 .ext3_features = CPUID_EXT3_LAHF_LM,
599 .xlevel = 0x8000000A,
600 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
601 },
602 {
603 .name = "Westmere",
604 .level = 11,
605 .vendor1 = CPUID_VENDOR_INTEL_1,
606 .vendor2 = CPUID_VENDOR_INTEL_2,
607 .vendor3 = CPUID_VENDOR_INTEL_3,
608 .family = 6,
609 .model = 44,
610 .stepping = 1,
611 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
612 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
613 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
614 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
615 CPUID_DE | CPUID_FP87,
616 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
617 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
618 CPUID_EXT_SSE3,
619 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
620 .ext3_features = CPUID_EXT3_LAHF_LM,
621 .xlevel = 0x8000000A,
622 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
623 },
624 {
625 .name = "SandyBridge",
626 .level = 0xd,
627 .vendor1 = CPUID_VENDOR_INTEL_1,
628 .vendor2 = CPUID_VENDOR_INTEL_2,
629 .vendor3 = CPUID_VENDOR_INTEL_3,
630 .family = 6,
631 .model = 42,
632 .stepping = 1,
633 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
634 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
635 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
636 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
637 CPUID_DE | CPUID_FP87,
638 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
639 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
640 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
641 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
642 CPUID_EXT_SSE3,
643 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
644 CPUID_EXT2_SYSCALL,
645 .ext3_features = CPUID_EXT3_LAHF_LM,
646 .xlevel = 0x8000000A,
647 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
648 },
649 {
650 .name = "Haswell",
651 .level = 0xd,
652 .vendor1 = CPUID_VENDOR_INTEL_1,
653 .vendor2 = CPUID_VENDOR_INTEL_2,
654 .vendor3 = CPUID_VENDOR_INTEL_3,
655 .family = 6,
656 .model = 60,
657 .stepping = 1,
658 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
662 CPUID_DE | CPUID_FP87,
663 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
664 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
665 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
666 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
667 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
668 CPUID_EXT_PCID,
669 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
670 CPUID_EXT2_SYSCALL,
671 .ext3_features = CPUID_EXT3_LAHF_LM,
672 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
673 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
674 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
675 CPUID_7_0_EBX_RTM,
676 .xlevel = 0x8000000A,
677 .model_id = "Intel Core Processor (Haswell)",
678 },
679 {
680 .name = "Opteron_G1",
681 .level = 5,
682 .vendor1 = CPUID_VENDOR_AMD_1,
683 .vendor2 = CPUID_VENDOR_AMD_2,
684 .vendor3 = CPUID_VENDOR_AMD_3,
685 .family = 15,
686 .model = 6,
687 .stepping = 1,
688 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
689 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
690 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
691 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
692 CPUID_DE | CPUID_FP87,
693 .ext_features = CPUID_EXT_SSE3,
694 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
695 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
696 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
697 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
698 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
699 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
700 .xlevel = 0x80000008,
701 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
702 },
703 {
704 .name = "Opteron_G2",
705 .level = 5,
706 .vendor1 = CPUID_VENDOR_AMD_1,
707 .vendor2 = CPUID_VENDOR_AMD_2,
708 .vendor3 = CPUID_VENDOR_AMD_3,
709 .family = 15,
710 .model = 6,
711 .stepping = 1,
712 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
713 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
714 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
715 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
716 CPUID_DE | CPUID_FP87,
717 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
718 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
719 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
720 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
721 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
722 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
723 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
724 CPUID_EXT2_DE | CPUID_EXT2_FPU,
725 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
726 .xlevel = 0x80000008,
727 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
728 },
729 {
730 .name = "Opteron_G3",
731 .level = 5,
732 .vendor1 = CPUID_VENDOR_AMD_1,
733 .vendor2 = CPUID_VENDOR_AMD_2,
734 .vendor3 = CPUID_VENDOR_AMD_3,
735 .family = 15,
736 .model = 6,
737 .stepping = 1,
738 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
739 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
740 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
741 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
742 CPUID_DE | CPUID_FP87,
743 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
744 CPUID_EXT_SSE3,
745 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
746 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
747 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
748 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
749 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
750 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
751 CPUID_EXT2_DE | CPUID_EXT2_FPU,
752 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
753 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
754 .xlevel = 0x80000008,
755 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
756 },
757 {
758 .name = "Opteron_G4",
759 .level = 0xd,
760 .vendor1 = CPUID_VENDOR_AMD_1,
761 .vendor2 = CPUID_VENDOR_AMD_2,
762 .vendor3 = CPUID_VENDOR_AMD_3,
763 .family = 21,
764 .model = 1,
765 .stepping = 2,
766 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
767 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
768 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
769 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
770 CPUID_DE | CPUID_FP87,
771 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
772 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
773 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
774 CPUID_EXT_SSE3,
775 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
776 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
777 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
778 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
779 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
780 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
781 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
782 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
783 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
784 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
785 CPUID_EXT3_LAHF_LM,
786 .xlevel = 0x8000001A,
787 .model_id = "AMD Opteron 62xx class CPU",
788 },
789 {
790 .name = "Opteron_G5",
791 .level = 0xd,
792 .vendor1 = CPUID_VENDOR_AMD_1,
793 .vendor2 = CPUID_VENDOR_AMD_2,
794 .vendor3 = CPUID_VENDOR_AMD_3,
795 .family = 21,
796 .model = 2,
797 .stepping = 0,
798 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
799 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
800 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
801 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
802 CPUID_DE | CPUID_FP87,
803 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
804 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
805 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
806 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
807 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
808 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
809 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
810 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
811 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
812 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
813 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
814 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
815 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
816 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
817 CPUID_EXT3_LAHF_LM,
818 .xlevel = 0x8000001A,
819 .model_id = "AMD Opteron 63xx class CPU",
820 },
821 };
822
823 #ifdef CONFIG_KVM
824 static int cpu_x86_fill_model_id(char *str)
825 {
826 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
827 int i;
828
829 for (i = 0; i < 3; i++) {
830 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
831 memcpy(str + i * 16 + 0, &eax, 4);
832 memcpy(str + i * 16 + 4, &ebx, 4);
833 memcpy(str + i * 16 + 8, &ecx, 4);
834 memcpy(str + i * 16 + 12, &edx, 4);
835 }
836 return 0;
837 }
838 #endif
839
840 /* Fill a x86_def_t struct with information about the host CPU, and
841 * the CPU features supported by the host hardware + host kernel
842 *
843 * This function may be called only if KVM is enabled.
844 */
845 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
846 {
847 #ifdef CONFIG_KVM
848 KVMState *s = kvm_state;
849 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
850
851 assert(kvm_enabled());
852
853 x86_cpu_def->name = "host";
854 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
855 x86_cpu_def->vendor1 = ebx;
856 x86_cpu_def->vendor2 = edx;
857 x86_cpu_def->vendor3 = ecx;
858
859 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
860 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
861 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
862 x86_cpu_def->stepping = eax & 0x0F;
863
864 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
865 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
866 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
867
868 if (x86_cpu_def->level >= 7) {
869 x86_cpu_def->cpuid_7_0_ebx_features =
870 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
871 } else {
872 x86_cpu_def->cpuid_7_0_ebx_features = 0;
873 }
874
875 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
876 x86_cpu_def->ext2_features =
877 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
878 x86_cpu_def->ext3_features =
879 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
880
881 cpu_x86_fill_model_id(x86_cpu_def->model_id);
882 x86_cpu_def->vendor_override = 0;
883
884 /* Call Centaur's CPUID instruction. */
885 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
886 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
887 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
888 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
889 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
890 if (eax >= 0xC0000001) {
891 /* Support VIA max extended level */
892 x86_cpu_def->xlevel2 = eax;
893 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
894 x86_cpu_def->ext4_features =
895 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
896 }
897 }
898
899 /*
900 * Every SVM feature requires emulation support in KVM - so we can't just
901 * read the host features here. KVM might even support SVM features not
902 * available on the host hardware. Just set all bits and mask out the
903 * unsupported ones later.
904 */
905 x86_cpu_def->svm_features = -1;
906 #endif /* CONFIG_KVM */
907 }
908
909 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
910 {
911 int i;
912
913 for (i = 0; i < 32; ++i)
914 if (1 << i & mask) {
915 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
916 " flag '%s' [0x%08x]\n",
917 f->cpuid >> 16, f->cpuid & 0xffff,
918 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
919 break;
920 }
921 return 0;
922 }
923
924 /* best effort attempt to inform user requested cpu flags aren't making
925 * their way to the guest. Note: ft[].check_feat ideally should be
926 * specified via a guest_def field to suppress report of extraneous flags.
927 *
928 * This function may be called only if KVM is enabled.
929 */
930 static int kvm_check_features_against_host(x86_def_t *guest_def)
931 {
932 x86_def_t host_def;
933 uint32_t mask;
934 int rv, i;
935 struct model_features_t ft[] = {
936 {&guest_def->features, &host_def.features,
937 ~0, feature_name, 0x00000000},
938 {&guest_def->ext_features, &host_def.ext_features,
939 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
940 {&guest_def->ext2_features, &host_def.ext2_features,
941 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
942 {&guest_def->ext3_features, &host_def.ext3_features,
943 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
944
945 assert(kvm_enabled());
946
947 kvm_cpu_fill_host(&host_def);
948 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
949 for (mask = 1; mask; mask <<= 1)
950 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
951 !(*ft[i].host_feat & mask)) {
952 unavailable_host_feature(&ft[i], mask);
953 rv = 1;
954 }
955 return rv;
956 }
957
958 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
959 const char *name, Error **errp)
960 {
961 X86CPU *cpu = X86_CPU(obj);
962 CPUX86State *env = &cpu->env;
963 int64_t value;
964
965 value = (env->cpuid_version >> 8) & 0xf;
966 if (value == 0xf) {
967 value += (env->cpuid_version >> 20) & 0xff;
968 }
969 visit_type_int(v, &value, name, errp);
970 }
971
972 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
973 const char *name, Error **errp)
974 {
975 X86CPU *cpu = X86_CPU(obj);
976 CPUX86State *env = &cpu->env;
977 const int64_t min = 0;
978 const int64_t max = 0xff + 0xf;
979 int64_t value;
980
981 visit_type_int(v, &value, name, errp);
982 if (error_is_set(errp)) {
983 return;
984 }
985 if (value < min || value > max) {
986 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
987 name ? name : "null", value, min, max);
988 return;
989 }
990
991 env->cpuid_version &= ~0xff00f00;
992 if (value > 0x0f) {
993 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
994 } else {
995 env->cpuid_version |= value << 8;
996 }
997 }
998
999 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1000 const char *name, Error **errp)
1001 {
1002 X86CPU *cpu = X86_CPU(obj);
1003 CPUX86State *env = &cpu->env;
1004 int64_t value;
1005
1006 value = (env->cpuid_version >> 4) & 0xf;
1007 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1008 visit_type_int(v, &value, name, errp);
1009 }
1010
1011 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1012 const char *name, Error **errp)
1013 {
1014 X86CPU *cpu = X86_CPU(obj);
1015 CPUX86State *env = &cpu->env;
1016 const int64_t min = 0;
1017 const int64_t max = 0xff;
1018 int64_t value;
1019
1020 visit_type_int(v, &value, name, errp);
1021 if (error_is_set(errp)) {
1022 return;
1023 }
1024 if (value < min || value > max) {
1025 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1026 name ? name : "null", value, min, max);
1027 return;
1028 }
1029
1030 env->cpuid_version &= ~0xf00f0;
1031 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1032 }
1033
1034 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1035 void *opaque, const char *name,
1036 Error **errp)
1037 {
1038 X86CPU *cpu = X86_CPU(obj);
1039 CPUX86State *env = &cpu->env;
1040 int64_t value;
1041
1042 value = env->cpuid_version & 0xf;
1043 visit_type_int(v, &value, name, errp);
1044 }
1045
1046 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1047 void *opaque, const char *name,
1048 Error **errp)
1049 {
1050 X86CPU *cpu = X86_CPU(obj);
1051 CPUX86State *env = &cpu->env;
1052 const int64_t min = 0;
1053 const int64_t max = 0xf;
1054 int64_t value;
1055
1056 visit_type_int(v, &value, name, errp);
1057 if (error_is_set(errp)) {
1058 return;
1059 }
1060 if (value < min || value > max) {
1061 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1062 name ? name : "null", value, min, max);
1063 return;
1064 }
1065
1066 env->cpuid_version &= ~0xf;
1067 env->cpuid_version |= value & 0xf;
1068 }
1069
1070 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1071 const char *name, Error **errp)
1072 {
1073 X86CPU *cpu = X86_CPU(obj);
1074
1075 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1076 }
1077
1078 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1079 const char *name, Error **errp)
1080 {
1081 X86CPU *cpu = X86_CPU(obj);
1082
1083 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1084 }
1085
1086 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1087 const char *name, Error **errp)
1088 {
1089 X86CPU *cpu = X86_CPU(obj);
1090
1091 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1092 }
1093
1094 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1095 const char *name, Error **errp)
1096 {
1097 X86CPU *cpu = X86_CPU(obj);
1098
1099 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1100 }
1101
1102 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1103 {
1104 X86CPU *cpu = X86_CPU(obj);
1105 CPUX86State *env = &cpu->env;
1106 char *value;
1107 int i;
1108
1109 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1110 for (i = 0; i < 4; i++) {
1111 value[i ] = env->cpuid_vendor1 >> (8 * i);
1112 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1113 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1114 }
1115 value[CPUID_VENDOR_SZ] = '\0';
1116 return value;
1117 }
1118
1119 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1120 Error **errp)
1121 {
1122 X86CPU *cpu = X86_CPU(obj);
1123 CPUX86State *env = &cpu->env;
1124 int i;
1125
1126 if (strlen(value) != CPUID_VENDOR_SZ) {
1127 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1128 "vendor", value);
1129 return;
1130 }
1131
1132 env->cpuid_vendor1 = 0;
1133 env->cpuid_vendor2 = 0;
1134 env->cpuid_vendor3 = 0;
1135 for (i = 0; i < 4; i++) {
1136 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1137 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1138 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1139 }
1140 env->cpuid_vendor_override = 1;
1141 }
1142
1143 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1144 {
1145 X86CPU *cpu = X86_CPU(obj);
1146 CPUX86State *env = &cpu->env;
1147 char *value;
1148 int i;
1149
1150 value = g_malloc(48 + 1);
1151 for (i = 0; i < 48; i++) {
1152 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1153 }
1154 value[48] = '\0';
1155 return value;
1156 }
1157
1158 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1159 Error **errp)
1160 {
1161 X86CPU *cpu = X86_CPU(obj);
1162 CPUX86State *env = &cpu->env;
1163 int c, len, i;
1164
1165 if (model_id == NULL) {
1166 model_id = "";
1167 }
1168 len = strlen(model_id);
1169 memset(env->cpuid_model, 0, 48);
1170 for (i = 0; i < 48; i++) {
1171 if (i >= len) {
1172 c = '\0';
1173 } else {
1174 c = (uint8_t)model_id[i];
1175 }
1176 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1177 }
1178 }
1179
1180 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1181 const char *name, Error **errp)
1182 {
1183 X86CPU *cpu = X86_CPU(obj);
1184 int64_t value;
1185
1186 value = cpu->env.tsc_khz * 1000;
1187 visit_type_int(v, &value, name, errp);
1188 }
1189
1190 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1191 const char *name, Error **errp)
1192 {
1193 X86CPU *cpu = X86_CPU(obj);
1194 const int64_t min = 0;
1195 const int64_t max = INT64_MAX;
1196 int64_t value;
1197
1198 visit_type_int(v, &value, name, errp);
1199 if (error_is_set(errp)) {
1200 return;
1201 }
1202 if (value < min || value > max) {
1203 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1204 name ? name : "null", value, min, max);
1205 return;
1206 }
1207
1208 cpu->env.tsc_khz = value / 1000;
1209 }
1210
1211 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1212 {
1213 x86_def_t *def;
1214
1215 for (def = x86_defs; def; def = def->next) {
1216 if (name && !strcmp(name, def->name)) {
1217 break;
1218 }
1219 }
1220 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1221 kvm_cpu_fill_host(x86_cpu_def);
1222 } else if (!def) {
1223 return -1;
1224 } else {
1225 memcpy(x86_cpu_def, def, sizeof(*def));
1226 }
1227
1228 return 0;
1229 }
1230
1231 /* Parse "+feature,-feature,feature=foo" CPU feature string
1232 */
1233 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1234 {
1235 unsigned int i;
1236 char *featurestr; /* Single 'key=value" string being parsed */
1237 /* Features to be added */
1238 uint32_t plus_features = 0, plus_ext_features = 0;
1239 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1240 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1241 uint32_t plus_7_0_ebx_features = 0;
1242 /* Features to be removed */
1243 uint32_t minus_features = 0, minus_ext_features = 0;
1244 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1245 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1246 uint32_t minus_7_0_ebx_features = 0;
1247 uint32_t numvalue;
1248
1249 add_flagname_to_bitmaps("hypervisor", &plus_features,
1250 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1251 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1252
1253 featurestr = features ? strtok(features, ",") : NULL;
1254
1255 while (featurestr) {
1256 char *val;
1257 if (featurestr[0] == '+') {
1258 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1259 &plus_ext_features, &plus_ext2_features,
1260 &plus_ext3_features, &plus_kvm_features,
1261 &plus_svm_features, &plus_7_0_ebx_features);
1262 } else if (featurestr[0] == '-') {
1263 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1264 &minus_ext_features, &minus_ext2_features,
1265 &minus_ext3_features, &minus_kvm_features,
1266 &minus_svm_features, &minus_7_0_ebx_features);
1267 } else if ((val = strchr(featurestr, '='))) {
1268 *val = 0; val++;
1269 if (!strcmp(featurestr, "family")) {
1270 char *err;
1271 numvalue = strtoul(val, &err, 0);
1272 if (!*val || *err || numvalue > 0xff + 0xf) {
1273 fprintf(stderr, "bad numerical value %s\n", val);
1274 goto error;
1275 }
1276 x86_cpu_def->family = numvalue;
1277 } else if (!strcmp(featurestr, "model")) {
1278 char *err;
1279 numvalue = strtoul(val, &err, 0);
1280 if (!*val || *err || numvalue > 0xff) {
1281 fprintf(stderr, "bad numerical value %s\n", val);
1282 goto error;
1283 }
1284 x86_cpu_def->model = numvalue;
1285 } else if (!strcmp(featurestr, "stepping")) {
1286 char *err;
1287 numvalue = strtoul(val, &err, 0);
1288 if (!*val || *err || numvalue > 0xf) {
1289 fprintf(stderr, "bad numerical value %s\n", val);
1290 goto error;
1291 }
1292 x86_cpu_def->stepping = numvalue ;
1293 } else if (!strcmp(featurestr, "level")) {
1294 char *err;
1295 numvalue = strtoul(val, &err, 0);
1296 if (!*val || *err) {
1297 fprintf(stderr, "bad numerical value %s\n", val);
1298 goto error;
1299 }
1300 x86_cpu_def->level = numvalue;
1301 } else if (!strcmp(featurestr, "xlevel")) {
1302 char *err;
1303 numvalue = strtoul(val, &err, 0);
1304 if (!*val || *err) {
1305 fprintf(stderr, "bad numerical value %s\n", val);
1306 goto error;
1307 }
1308 if (numvalue < 0x80000000) {
1309 numvalue += 0x80000000;
1310 }
1311 x86_cpu_def->xlevel = numvalue;
1312 } else if (!strcmp(featurestr, "vendor")) {
1313 if (strlen(val) != 12) {
1314 fprintf(stderr, "vendor string must be 12 chars long\n");
1315 goto error;
1316 }
1317 x86_cpu_def->vendor1 = 0;
1318 x86_cpu_def->vendor2 = 0;
1319 x86_cpu_def->vendor3 = 0;
1320 for(i = 0; i < 4; i++) {
1321 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1322 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1323 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1324 }
1325 x86_cpu_def->vendor_override = 1;
1326 } else if (!strcmp(featurestr, "model_id")) {
1327 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1328 val);
1329 } else if (!strcmp(featurestr, "tsc_freq")) {
1330 int64_t tsc_freq;
1331 char *err;
1332
1333 tsc_freq = strtosz_suffix_unit(val, &err,
1334 STRTOSZ_DEFSUFFIX_B, 1000);
1335 if (tsc_freq < 0 || *err) {
1336 fprintf(stderr, "bad numerical value %s\n", val);
1337 goto error;
1338 }
1339 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1340 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1341 char *err;
1342 numvalue = strtoul(val, &err, 0);
1343 if (!*val || *err) {
1344 fprintf(stderr, "bad numerical value %s\n", val);
1345 goto error;
1346 }
1347 hyperv_set_spinlock_retries(numvalue);
1348 } else {
1349 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1350 goto error;
1351 }
1352 } else if (!strcmp(featurestr, "check")) {
1353 check_cpuid = 1;
1354 } else if (!strcmp(featurestr, "enforce")) {
1355 check_cpuid = enforce_cpuid = 1;
1356 } else if (!strcmp(featurestr, "hv_relaxed")) {
1357 hyperv_enable_relaxed_timing(true);
1358 } else if (!strcmp(featurestr, "hv_vapic")) {
1359 hyperv_enable_vapic_recommended(true);
1360 } else {
1361 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1362 goto error;
1363 }
1364 featurestr = strtok(NULL, ",");
1365 }
1366 x86_cpu_def->features |= plus_features;
1367 x86_cpu_def->ext_features |= plus_ext_features;
1368 x86_cpu_def->ext2_features |= plus_ext2_features;
1369 x86_cpu_def->ext3_features |= plus_ext3_features;
1370 x86_cpu_def->kvm_features |= plus_kvm_features;
1371 x86_cpu_def->svm_features |= plus_svm_features;
1372 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1373 x86_cpu_def->features &= ~minus_features;
1374 x86_cpu_def->ext_features &= ~minus_ext_features;
1375 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1376 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1377 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1378 x86_cpu_def->svm_features &= ~minus_svm_features;
1379 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1380 if (check_cpuid && kvm_enabled()) {
1381 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1382 goto error;
1383 }
1384 if (x86_cpu_def->cpuid_7_0_ebx_features && x86_cpu_def->level < 7) {
1385 x86_cpu_def->level = 7;
1386 }
1387 return 0;
1388
1389 error:
1390 return -1;
1391 }
1392
1393 /* generate a composite string into buf of all cpuid names in featureset
1394 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1395 * if flags, suppress names undefined in featureset.
1396 */
1397 static void listflags(char *buf, int bufsize, uint32_t fbits,
1398 const char **featureset, uint32_t flags)
1399 {
1400 const char **p = &featureset[31];
1401 char *q, *b, bit;
1402 int nc;
1403
1404 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1405 *buf = '\0';
1406 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1407 if (fbits & 1 << bit && (*p || !flags)) {
1408 if (*p)
1409 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1410 else
1411 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1412 if (bufsize <= nc) {
1413 if (b) {
1414 memcpy(b, "...", sizeof("..."));
1415 }
1416 return;
1417 }
1418 q += nc;
1419 bufsize -= nc;
1420 }
1421 }
1422
1423 /* generate CPU information. */
1424 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1425 {
1426 x86_def_t *def;
1427 char buf[256];
1428
1429 for (def = x86_defs; def; def = def->next) {
1430 snprintf(buf, sizeof(buf), "%s", def->name);
1431 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1432 }
1433 if (kvm_enabled()) {
1434 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1435 }
1436 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1437 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1438 (*cpu_fprintf)(f, " %s\n", buf);
1439 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1440 (*cpu_fprintf)(f, " %s\n", buf);
1441 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1442 (*cpu_fprintf)(f, " %s\n", buf);
1443 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1444 (*cpu_fprintf)(f, " %s\n", buf);
1445 }
1446
1447 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1448 {
1449 CpuDefinitionInfoList *cpu_list = NULL;
1450 x86_def_t *def;
1451
1452 for (def = x86_defs; def; def = def->next) {
1453 CpuDefinitionInfoList *entry;
1454 CpuDefinitionInfo *info;
1455
1456 info = g_malloc0(sizeof(*info));
1457 info->name = g_strdup(def->name);
1458
1459 entry = g_malloc0(sizeof(*entry));
1460 entry->value = info;
1461 entry->next = cpu_list;
1462 cpu_list = entry;
1463 }
1464
1465 return cpu_list;
1466 }
1467
1468 #ifdef CONFIG_KVM
1469 static void filter_features_for_kvm(X86CPU *cpu)
1470 {
1471 CPUX86State *env = &cpu->env;
1472 KVMState *s = kvm_state;
1473
1474 env->cpuid_features &=
1475 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1476 env->cpuid_ext_features &=
1477 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1478 env->cpuid_ext2_features &=
1479 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1480 env->cpuid_ext3_features &=
1481 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1482 env->cpuid_svm_features &=
1483 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1484 env->cpuid_7_0_ebx_features &=
1485 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1486 env->cpuid_kvm_features &=
1487 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1488 env->cpuid_ext4_features &=
1489 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1490
1491 }
1492 #endif
1493
1494 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1495 {
1496 CPUX86State *env = &cpu->env;
1497 x86_def_t def1, *def = &def1;
1498 Error *error = NULL;
1499 char *name, *features;
1500 gchar **model_pieces;
1501
1502 memset(def, 0, sizeof(*def));
1503
1504 model_pieces = g_strsplit(cpu_model, ",", 2);
1505 if (!model_pieces[0]) {
1506 goto error;
1507 }
1508 name = model_pieces[0];
1509 features = model_pieces[1];
1510
1511 if (cpu_x86_find_by_name(def, name) < 0) {
1512 goto error;
1513 }
1514
1515 if (cpu_x86_parse_featurestr(def, features) < 0) {
1516 goto error;
1517 }
1518 if (def->vendor1) {
1519 env->cpuid_vendor1 = def->vendor1;
1520 env->cpuid_vendor2 = def->vendor2;
1521 env->cpuid_vendor3 = def->vendor3;
1522 } else {
1523 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1524 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1525 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1526 }
1527 env->cpuid_vendor_override = def->vendor_override;
1528 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1529 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1530 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1531 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1532 env->cpuid_features = def->features;
1533 env->cpuid_ext_features = def->ext_features;
1534 env->cpuid_ext2_features = def->ext2_features;
1535 env->cpuid_ext3_features = def->ext3_features;
1536 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1537 env->cpuid_kvm_features = def->kvm_features;
1538 env->cpuid_svm_features = def->svm_features;
1539 env->cpuid_ext4_features = def->ext4_features;
1540 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1541 env->cpuid_xlevel2 = def->xlevel2;
1542 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1543 "tsc-frequency", &error);
1544
1545 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1546 * CPUID[1].EDX.
1547 */
1548 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1549 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1550 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1551 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1552 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1553 }
1554
1555 if (!kvm_enabled()) {
1556 env->cpuid_features &= TCG_FEATURES;
1557 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1558 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1559 #ifdef TARGET_X86_64
1560 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1561 #endif
1562 );
1563 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1564 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1565 } else {
1566 #ifdef CONFIG_KVM
1567 filter_features_for_kvm(cpu);
1568 #endif
1569 }
1570 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1571 if (error) {
1572 fprintf(stderr, "%s\n", error_get_pretty(error));
1573 error_free(error);
1574 goto error;
1575 }
1576
1577 g_strfreev(model_pieces);
1578 return 0;
1579 error:
1580 g_strfreev(model_pieces);
1581 return -1;
1582 }
1583
1584 #if !defined(CONFIG_USER_ONLY)
1585
1586 void cpu_clear_apic_feature(CPUX86State *env)
1587 {
1588 env->cpuid_features &= ~CPUID_APIC;
1589 }
1590
1591 #endif /* !CONFIG_USER_ONLY */
1592
1593 /* Initialize list of CPU models, filling some non-static fields if necessary
1594 */
1595 void x86_cpudef_setup(void)
1596 {
1597 int i, j;
1598 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1599
1600 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1601 x86_def_t *def = &builtin_x86_defs[i];
1602 def->next = x86_defs;
1603
1604 /* Look for specific "cpudef" models that */
1605 /* have the QEMU version in .model_id */
1606 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1607 if (strcmp(model_with_versions[j], def->name) == 0) {
1608 pstrcpy(def->model_id, sizeof(def->model_id),
1609 "QEMU Virtual CPU version ");
1610 pstrcat(def->model_id, sizeof(def->model_id),
1611 qemu_get_version());
1612 break;
1613 }
1614 }
1615
1616 x86_defs = def;
1617 }
1618 }
1619
1620 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1621 uint32_t *ecx, uint32_t *edx)
1622 {
1623 *ebx = env->cpuid_vendor1;
1624 *edx = env->cpuid_vendor2;
1625 *ecx = env->cpuid_vendor3;
1626
1627 /* sysenter isn't supported on compatibility mode on AMD, syscall
1628 * isn't supported in compatibility mode on Intel.
1629 * Normally we advertise the actual cpu vendor, but you can override
1630 * this if you want to use KVM's sysenter/syscall emulation
1631 * in compatibility mode and when doing cross vendor migration
1632 */
1633 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1634 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1635 }
1636 }
1637
1638 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1639 uint32_t *eax, uint32_t *ebx,
1640 uint32_t *ecx, uint32_t *edx)
1641 {
1642 /* test if maximum index reached */
1643 if (index & 0x80000000) {
1644 if (index > env->cpuid_xlevel) {
1645 if (env->cpuid_xlevel2 > 0) {
1646 /* Handle the Centaur's CPUID instruction. */
1647 if (index > env->cpuid_xlevel2) {
1648 index = env->cpuid_xlevel2;
1649 } else if (index < 0xC0000000) {
1650 index = env->cpuid_xlevel;
1651 }
1652 } else {
1653 index = env->cpuid_xlevel;
1654 }
1655 }
1656 } else {
1657 if (index > env->cpuid_level)
1658 index = env->cpuid_level;
1659 }
1660
1661 switch(index) {
1662 case 0:
1663 *eax = env->cpuid_level;
1664 get_cpuid_vendor(env, ebx, ecx, edx);
1665 break;
1666 case 1:
1667 *eax = env->cpuid_version;
1668 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1669 *ecx = env->cpuid_ext_features;
1670 *edx = env->cpuid_features;
1671 if (env->nr_cores * env->nr_threads > 1) {
1672 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1673 *edx |= 1 << 28; /* HTT bit */
1674 }
1675 break;
1676 case 2:
1677 /* cache info: needed for Pentium Pro compatibility */
1678 *eax = 1;
1679 *ebx = 0;
1680 *ecx = 0;
1681 *edx = 0x2c307d;
1682 break;
1683 case 4:
1684 /* cache info: needed for Core compatibility */
1685 if (env->nr_cores > 1) {
1686 *eax = (env->nr_cores - 1) << 26;
1687 } else {
1688 *eax = 0;
1689 }
1690 switch (count) {
1691 case 0: /* L1 dcache info */
1692 *eax |= 0x0000121;
1693 *ebx = 0x1c0003f;
1694 *ecx = 0x000003f;
1695 *edx = 0x0000001;
1696 break;
1697 case 1: /* L1 icache info */
1698 *eax |= 0x0000122;
1699 *ebx = 0x1c0003f;
1700 *ecx = 0x000003f;
1701 *edx = 0x0000001;
1702 break;
1703 case 2: /* L2 cache info */
1704 *eax |= 0x0000143;
1705 if (env->nr_threads > 1) {
1706 *eax |= (env->nr_threads - 1) << 14;
1707 }
1708 *ebx = 0x3c0003f;
1709 *ecx = 0x0000fff;
1710 *edx = 0x0000001;
1711 break;
1712 default: /* end of info */
1713 *eax = 0;
1714 *ebx = 0;
1715 *ecx = 0;
1716 *edx = 0;
1717 break;
1718 }
1719 break;
1720 case 5:
1721 /* mwait info: needed for Core compatibility */
1722 *eax = 0; /* Smallest monitor-line size in bytes */
1723 *ebx = 0; /* Largest monitor-line size in bytes */
1724 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1725 *edx = 0;
1726 break;
1727 case 6:
1728 /* Thermal and Power Leaf */
1729 *eax = 0;
1730 *ebx = 0;
1731 *ecx = 0;
1732 *edx = 0;
1733 break;
1734 case 7:
1735 /* Structured Extended Feature Flags Enumeration Leaf */
1736 if (count == 0) {
1737 *eax = 0; /* Maximum ECX value for sub-leaves */
1738 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1739 *ecx = 0; /* Reserved */
1740 *edx = 0; /* Reserved */
1741 } else {
1742 *eax = 0;
1743 *ebx = 0;
1744 *ecx = 0;
1745 *edx = 0;
1746 }
1747 break;
1748 case 9:
1749 /* Direct Cache Access Information Leaf */
1750 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1751 *ebx = 0;
1752 *ecx = 0;
1753 *edx = 0;
1754 break;
1755 case 0xA:
1756 /* Architectural Performance Monitoring Leaf */
1757 if (kvm_enabled()) {
1758 KVMState *s = env->kvm_state;
1759
1760 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1761 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1762 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1763 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1764 } else {
1765 *eax = 0;
1766 *ebx = 0;
1767 *ecx = 0;
1768 *edx = 0;
1769 }
1770 break;
1771 case 0xD:
1772 /* Processor Extended State */
1773 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1774 *eax = 0;
1775 *ebx = 0;
1776 *ecx = 0;
1777 *edx = 0;
1778 break;
1779 }
1780 if (kvm_enabled()) {
1781 KVMState *s = env->kvm_state;
1782
1783 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1784 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1785 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1786 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1787 } else {
1788 *eax = 0;
1789 *ebx = 0;
1790 *ecx = 0;
1791 *edx = 0;
1792 }
1793 break;
1794 case 0x80000000:
1795 *eax = env->cpuid_xlevel;
1796 *ebx = env->cpuid_vendor1;
1797 *edx = env->cpuid_vendor2;
1798 *ecx = env->cpuid_vendor3;
1799 break;
1800 case 0x80000001:
1801 *eax = env->cpuid_version;
1802 *ebx = 0;
1803 *ecx = env->cpuid_ext3_features;
1804 *edx = env->cpuid_ext2_features;
1805
1806 /* The Linux kernel checks for the CMPLegacy bit and
1807 * discards multiple thread information if it is set.
1808 * So dont set it here for Intel to make Linux guests happy.
1809 */
1810 if (env->nr_cores * env->nr_threads > 1) {
1811 uint32_t tebx, tecx, tedx;
1812 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1813 if (tebx != CPUID_VENDOR_INTEL_1 ||
1814 tedx != CPUID_VENDOR_INTEL_2 ||
1815 tecx != CPUID_VENDOR_INTEL_3) {
1816 *ecx |= 1 << 1; /* CmpLegacy bit */
1817 }
1818 }
1819 break;
1820 case 0x80000002:
1821 case 0x80000003:
1822 case 0x80000004:
1823 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1824 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1825 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1826 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1827 break;
1828 case 0x80000005:
1829 /* cache info (L1 cache) */
1830 *eax = 0x01ff01ff;
1831 *ebx = 0x01ff01ff;
1832 *ecx = 0x40020140;
1833 *edx = 0x40020140;
1834 break;
1835 case 0x80000006:
1836 /* cache info (L2 cache) */
1837 *eax = 0;
1838 *ebx = 0x42004200;
1839 *ecx = 0x02008140;
1840 *edx = 0;
1841 break;
1842 case 0x80000008:
1843 /* virtual & phys address size in low 2 bytes. */
1844 /* XXX: This value must match the one used in the MMU code. */
1845 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1846 /* 64 bit processor */
1847 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1848 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1849 } else {
1850 if (env->cpuid_features & CPUID_PSE36)
1851 *eax = 0x00000024; /* 36 bits physical */
1852 else
1853 *eax = 0x00000020; /* 32 bits physical */
1854 }
1855 *ebx = 0;
1856 *ecx = 0;
1857 *edx = 0;
1858 if (env->nr_cores * env->nr_threads > 1) {
1859 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1860 }
1861 break;
1862 case 0x8000000A:
1863 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1864 *eax = 0x00000001; /* SVM Revision */
1865 *ebx = 0x00000010; /* nr of ASIDs */
1866 *ecx = 0;
1867 *edx = env->cpuid_svm_features; /* optional features */
1868 } else {
1869 *eax = 0;
1870 *ebx = 0;
1871 *ecx = 0;
1872 *edx = 0;
1873 }
1874 break;
1875 case 0xC0000000:
1876 *eax = env->cpuid_xlevel2;
1877 *ebx = 0;
1878 *ecx = 0;
1879 *edx = 0;
1880 break;
1881 case 0xC0000001:
1882 /* Support for VIA CPU's CPUID instruction */
1883 *eax = env->cpuid_version;
1884 *ebx = 0;
1885 *ecx = 0;
1886 *edx = env->cpuid_ext4_features;
1887 break;
1888 case 0xC0000002:
1889 case 0xC0000003:
1890 case 0xC0000004:
1891 /* Reserved for the future, and now filled with zero */
1892 *eax = 0;
1893 *ebx = 0;
1894 *ecx = 0;
1895 *edx = 0;
1896 break;
1897 default:
1898 /* reserved values: zero */
1899 *eax = 0;
1900 *ebx = 0;
1901 *ecx = 0;
1902 *edx = 0;
1903 break;
1904 }
1905 }
1906
1907 /* CPUClass::reset() */
1908 static void x86_cpu_reset(CPUState *s)
1909 {
1910 X86CPU *cpu = X86_CPU(s);
1911 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1912 CPUX86State *env = &cpu->env;
1913 int i;
1914
1915 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1916 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1917 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1918 }
1919
1920 xcc->parent_reset(s);
1921
1922
1923 memset(env, 0, offsetof(CPUX86State, breakpoints));
1924
1925 tlb_flush(env, 1);
1926
1927 env->old_exception = -1;
1928
1929 /* init to reset state */
1930
1931 #ifdef CONFIG_SOFTMMU
1932 env->hflags |= HF_SOFTMMU_MASK;
1933 #endif
1934 env->hflags2 |= HF2_GIF_MASK;
1935
1936 cpu_x86_update_cr0(env, 0x60000010);
1937 env->a20_mask = ~0x0;
1938 env->smbase = 0x30000;
1939
1940 env->idt.limit = 0xffff;
1941 env->gdt.limit = 0xffff;
1942 env->ldt.limit = 0xffff;
1943 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1944 env->tr.limit = 0xffff;
1945 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1946
1947 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1948 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1949 DESC_R_MASK | DESC_A_MASK);
1950 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1951 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1952 DESC_A_MASK);
1953 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1954 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1955 DESC_A_MASK);
1956 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1957 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1958 DESC_A_MASK);
1959 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1960 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1961 DESC_A_MASK);
1962 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1963 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1964 DESC_A_MASK);
1965
1966 env->eip = 0xfff0;
1967 env->regs[R_EDX] = env->cpuid_version;
1968
1969 env->eflags = 0x2;
1970
1971 /* FPU init */
1972 for (i = 0; i < 8; i++) {
1973 env->fptags[i] = 1;
1974 }
1975 env->fpuc = 0x37f;
1976
1977 env->mxcsr = 0x1f80;
1978
1979 env->pat = 0x0007040600070406ULL;
1980 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1981
1982 memset(env->dr, 0, sizeof(env->dr));
1983 env->dr[6] = DR6_FIXED_1;
1984 env->dr[7] = DR7_FIXED_1;
1985 cpu_breakpoint_remove_all(env, BP_CPU);
1986 cpu_watchpoint_remove_all(env, BP_CPU);
1987
1988 #if !defined(CONFIG_USER_ONLY)
1989 /* We hard-wire the BSP to the first CPU. */
1990 if (env->cpu_index == 0) {
1991 apic_designate_bsp(env->apic_state);
1992 }
1993
1994 env->halted = !cpu_is_bsp(cpu);
1995 #endif
1996 }
1997
1998 #ifndef CONFIG_USER_ONLY
1999 bool cpu_is_bsp(X86CPU *cpu)
2000 {
2001 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2002 }
2003
2004 /* TODO: remove me, when reset over QOM tree is implemented */
2005 static void x86_cpu_machine_reset_cb(void *opaque)
2006 {
2007 X86CPU *cpu = opaque;
2008 cpu_reset(CPU(cpu));
2009 }
2010 #endif
2011
2012 static void mce_init(X86CPU *cpu)
2013 {
2014 CPUX86State *cenv = &cpu->env;
2015 unsigned int bank;
2016
2017 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2018 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2019 (CPUID_MCE | CPUID_MCA)) {
2020 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2021 cenv->mcg_ctl = ~(uint64_t)0;
2022 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2023 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2024 }
2025 }
2026 }
2027
2028 #define MSI_ADDR_BASE 0xfee00000
2029
2030 #ifndef CONFIG_USER_ONLY
2031 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2032 {
2033 static int apic_mapped;
2034 CPUX86State *env = &cpu->env;
2035 APICCommonState *apic;
2036 const char *apic_type = "apic";
2037
2038 if (kvm_irqchip_in_kernel()) {
2039 apic_type = "kvm-apic";
2040 } else if (xen_enabled()) {
2041 apic_type = "xen-apic";
2042 }
2043
2044 env->apic_state = qdev_try_create(NULL, apic_type);
2045 if (env->apic_state == NULL) {
2046 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2047 return;
2048 }
2049
2050 object_property_add_child(OBJECT(cpu), "apic",
2051 OBJECT(env->apic_state), NULL);
2052 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2053 /* TODO: convert to link<> */
2054 apic = APIC_COMMON(env->apic_state);
2055 apic->cpu = cpu;
2056
2057 if (qdev_init(env->apic_state)) {
2058 error_setg(errp, "APIC device '%s' could not be initialized",
2059 object_get_typename(OBJECT(env->apic_state)));
2060 return;
2061 }
2062
2063 /* XXX: mapping more APICs at the same memory location */
2064 if (apic_mapped == 0) {
2065 /* NOTE: the APIC is directly connected to the CPU - it is not
2066 on the global memory bus. */
2067 /* XXX: what if the base changes? */
2068 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2069 apic_mapped = 1;
2070 }
2071 }
2072 #endif
2073
2074 void x86_cpu_realize(Object *obj, Error **errp)
2075 {
2076 X86CPU *cpu = X86_CPU(obj);
2077
2078 #ifndef CONFIG_USER_ONLY
2079 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2080
2081 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2082 x86_cpu_apic_init(cpu, errp);
2083 if (error_is_set(errp)) {
2084 return;
2085 }
2086 }
2087 #endif
2088
2089 mce_init(cpu);
2090 qemu_init_vcpu(&cpu->env);
2091 cpu_reset(CPU(cpu));
2092 }
2093
2094 static void x86_cpu_initfn(Object *obj)
2095 {
2096 X86CPU *cpu = X86_CPU(obj);
2097 CPUX86State *env = &cpu->env;
2098 static int inited;
2099
2100 cpu_exec_init(env);
2101
2102 object_property_add(obj, "family", "int",
2103 x86_cpuid_version_get_family,
2104 x86_cpuid_version_set_family, NULL, NULL, NULL);
2105 object_property_add(obj, "model", "int",
2106 x86_cpuid_version_get_model,
2107 x86_cpuid_version_set_model, NULL, NULL, NULL);
2108 object_property_add(obj, "stepping", "int",
2109 x86_cpuid_version_get_stepping,
2110 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2111 object_property_add(obj, "level", "int",
2112 x86_cpuid_get_level,
2113 x86_cpuid_set_level, NULL, NULL, NULL);
2114 object_property_add(obj, "xlevel", "int",
2115 x86_cpuid_get_xlevel,
2116 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2117 object_property_add_str(obj, "vendor",
2118 x86_cpuid_get_vendor,
2119 x86_cpuid_set_vendor, NULL);
2120 object_property_add_str(obj, "model-id",
2121 x86_cpuid_get_model_id,
2122 x86_cpuid_set_model_id, NULL);
2123 object_property_add(obj, "tsc-frequency", "int",
2124 x86_cpuid_get_tsc_freq,
2125 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2126
2127 env->cpuid_apic_id = env->cpu_index;
2128
2129 /* init various static tables used in TCG mode */
2130 if (tcg_enabled() && !inited) {
2131 inited = 1;
2132 optimize_flags_init();
2133 #ifndef CONFIG_USER_ONLY
2134 cpu_set_debug_excp_handler(breakpoint_handler);
2135 #endif
2136 }
2137 }
2138
2139 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2140 {
2141 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2142 CPUClass *cc = CPU_CLASS(oc);
2143
2144 xcc->parent_reset = cc->reset;
2145 cc->reset = x86_cpu_reset;
2146 }
2147
2148 static const TypeInfo x86_cpu_type_info = {
2149 .name = TYPE_X86_CPU,
2150 .parent = TYPE_CPU,
2151 .instance_size = sizeof(X86CPU),
2152 .instance_init = x86_cpu_initfn,
2153 .abstract = false,
2154 .class_size = sizeof(X86CPUClass),
2155 .class_init = x86_cpu_common_class_init,
2156 };
2157
2158 static void x86_cpu_register_types(void)
2159 {
2160 type_register_static(&x86_cpu_type_info);
2161 }
2162
2163 type_init(x86_cpu_register_types)
Qemu copy for testing