2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "qemu-option.h"
28 #include "qemu-config.h"
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
40 /* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
44 static const char *feature_name
[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL
, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
54 static const char *ext_feature_name
[] = {
55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
56 "ds_cpl", "vmx", "smx", "est",
57 "tm2", "ssse3", "cid", NULL
,
58 "fma", "cx16", "xtpr", "pdcm",
59 NULL
, "pcid", "dca", "sse4.1|sse4_1",
60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
61 "tsc-deadline", "aes", "xsave", "osxsave",
62 "avx", NULL
, NULL
, "hypervisor",
64 /* Feature names that are already defined on feature_name[] but are set on
65 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
66 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
67 * if and only if CPU vendor is AMD.
69 static const char *ext2_feature_name
[] = {
70 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
71 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
72 NULL
/* cx8 */ /* AMD CMPXCHG8B */, NULL
/* apic */, NULL
, "syscall",
73 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
74 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
75 "nx|xd", NULL
, "mmxext", NULL
/* mmx */,
76 NULL
/* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
78 static const char *ext3_feature_name
[] = {
79 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
80 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
81 "3dnowprefetch", "osvw", "ibs", "xop",
82 "skinit", "wdt", NULL
, NULL
,
83 "fma4", NULL
, "cvt16", "nodeid_msr",
84 NULL
, NULL
, NULL
, NULL
,
85 NULL
, NULL
, NULL
, NULL
,
86 NULL
, NULL
, NULL
, NULL
,
89 static const char *kvm_feature_name
[] = {
90 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL
, "kvm_pv_eoi", NULL
,
91 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
92 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
93 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
96 static const char *svm_feature_name
[] = {
97 "npt", "lbrv", "svm_lock", "nrip_save",
98 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
99 NULL
, NULL
, "pause_filter", NULL
,
100 "pfthreshold", NULL
, NULL
, NULL
,
101 NULL
, NULL
, NULL
, NULL
,
102 NULL
, NULL
, NULL
, NULL
,
103 NULL
, NULL
, NULL
, NULL
,
104 NULL
, NULL
, NULL
, NULL
,
107 /* collects per-function cpuid data
109 typedef struct model_features_t
{
110 uint32_t *guest_feat
;
113 const char **flag_names
;
118 int enforce_cpuid
= 0;
120 void host_cpuid(uint32_t function
, uint32_t count
,
121 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
123 #if defined(CONFIG_KVM)
128 : "=a"(vec
[0]), "=b"(vec
[1]),
129 "=c"(vec
[2]), "=d"(vec
[3])
130 : "0"(function
), "c"(count
) : "cc");
132 asm volatile("pusha \n\t"
134 "mov %%eax, 0(%2) \n\t"
135 "mov %%ebx, 4(%2) \n\t"
136 "mov %%ecx, 8(%2) \n\t"
137 "mov %%edx, 12(%2) \n\t"
139 : : "a"(function
), "c"(count
), "S"(vec
)
154 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
156 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
157 * a substring. ex if !NULL points to the first char after a substring,
158 * otherwise the string is assumed to sized by a terminating nul.
159 * Return lexical ordering of *s1:*s2.
161 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
165 if (!*s1
|| !*s2
|| *s1
!= *s2
)
168 if (s1
== e1
&& s2
== e2
)
177 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
178 * '|' delimited (possibly empty) strings in which case search for a match
179 * within the alternatives proceeds left to right. Return 0 for success,
180 * non-zero otherwise.
182 static int altcmp(const char *s
, const char *e
, const char *altstr
)
186 for (q
= p
= altstr
; ; ) {
187 while (*p
&& *p
!= '|')
189 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
198 /* search featureset for flag *[s..e), if found set corresponding bit in
199 * *pval and return true, otherwise return false
201 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
202 const char **featureset
)
208 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
209 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
217 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
,
218 uint32_t *ext_features
,
219 uint32_t *ext2_features
,
220 uint32_t *ext3_features
,
221 uint32_t *kvm_features
,
222 uint32_t *svm_features
)
224 if (!lookup_feature(features
, flagname
, NULL
, feature_name
) &&
225 !lookup_feature(ext_features
, flagname
, NULL
, ext_feature_name
) &&
226 !lookup_feature(ext2_features
, flagname
, NULL
, ext2_feature_name
) &&
227 !lookup_feature(ext3_features
, flagname
, NULL
, ext3_feature_name
) &&
228 !lookup_feature(kvm_features
, flagname
, NULL
, kvm_feature_name
) &&
229 !lookup_feature(svm_features
, flagname
, NULL
, svm_feature_name
))
230 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
233 typedef struct x86_def_t
{
234 struct x86_def_t
*next
;
237 uint32_t vendor1
, vendor2
, vendor3
;
242 uint32_t features
, ext_features
, ext2_features
, ext3_features
;
243 uint32_t kvm_features
, svm_features
;
247 /* Store the results of Centaur's CPUID instructions */
248 uint32_t ext4_features
;
250 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
251 uint32_t cpuid_7_0_ebx_features
;
254 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
255 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
256 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
257 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
258 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
259 CPUID_PSE36 | CPUID_FXSR)
260 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
261 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
262 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
263 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
264 CPUID_PAE | CPUID_SEP | CPUID_APIC)
266 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
267 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
268 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
269 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
270 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
271 /* partly implemented:
272 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
273 CPUID_PSE36 (needed for Solaris) */
275 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
276 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
277 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
278 CPUID_EXT_HYPERVISOR)
280 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
281 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
282 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
283 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
284 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
286 CPUID_EXT2_PDPE1GB */
287 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
288 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
289 #define TCG_SVM_FEATURES 0
291 /* maintains list of cpu model definitions
293 static x86_def_t
*x86_defs
= {NULL
};
295 /* built-in cpu model definitions (deprecated)
297 static x86_def_t builtin_x86_defs
[] = {
301 .vendor1
= CPUID_VENDOR_AMD_1
,
302 .vendor2
= CPUID_VENDOR_AMD_2
,
303 .vendor3
= CPUID_VENDOR_AMD_3
,
307 .features
= PPRO_FEATURES
|
308 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
310 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
311 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
312 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
313 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
314 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
315 .xlevel
= 0x8000000A,
320 .vendor1
= CPUID_VENDOR_AMD_1
,
321 .vendor2
= CPUID_VENDOR_AMD_2
,
322 .vendor3
= CPUID_VENDOR_AMD_3
,
326 .features
= PPRO_FEATURES
|
327 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
328 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
329 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
331 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
332 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
333 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
334 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
335 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
337 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
338 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
339 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
340 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
341 .svm_features
= CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
342 .xlevel
= 0x8000001A,
343 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
351 .features
= PPRO_FEATURES
|
352 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
353 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
354 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
355 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
356 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
357 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
358 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
359 .ext3_features
= CPUID_EXT3_LAHF_LM
,
360 .xlevel
= 0x80000008,
361 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
366 .vendor1
= CPUID_VENDOR_INTEL_1
,
367 .vendor2
= CPUID_VENDOR_INTEL_2
,
368 .vendor3
= CPUID_VENDOR_INTEL_3
,
372 /* Missing: CPUID_VME, CPUID_HT */
373 .features
= PPRO_FEATURES
|
374 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
376 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
377 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
378 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
379 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
380 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
381 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
382 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
383 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
384 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
386 .xlevel
= 0x80000008,
387 .model_id
= "Common KVM processor"
395 .features
= PPRO_FEATURES
,
396 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
397 .xlevel
= 0x80000004,
405 .features
= PPRO_FEATURES
|
406 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
407 .ext_features
= CPUID_EXT_SSE3
,
408 .ext2_features
= PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
,
410 .xlevel
= 0x80000008,
411 .model_id
= "Common 32-bit KVM processor"
419 .features
= PPRO_FEATURES
| CPUID_VME
|
420 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
421 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
422 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
423 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
424 .ext2_features
= CPUID_EXT2_NX
,
425 .xlevel
= 0x80000008,
426 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
434 .features
= I486_FEATURES
,
443 .features
= PENTIUM_FEATURES
,
452 .features
= PENTIUM2_FEATURES
,
461 .features
= PENTIUM3_FEATURES
,
467 .vendor1
= CPUID_VENDOR_AMD_1
,
468 .vendor2
= CPUID_VENDOR_AMD_2
,
469 .vendor3
= CPUID_VENDOR_AMD_3
,
473 .features
= PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
475 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
476 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
477 .xlevel
= 0x80000008,
481 /* original is on level 10 */
486 .features
= PPRO_FEATURES
|
487 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
488 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
489 /* Some CPUs got no CPUID_SEP */
490 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
491 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
,
492 .ext2_features
= (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
494 .ext3_features
= CPUID_EXT3_LAHF_LM
,
495 .xlevel
= 0x8000000A,
496 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
501 .vendor1
= CPUID_VENDOR_INTEL_1
,
502 .vendor2
= CPUID_VENDOR_INTEL_2
,
503 .vendor3
= CPUID_VENDOR_INTEL_3
,
507 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
508 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
509 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
510 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
511 CPUID_DE
| CPUID_FP87
,
512 .ext_features
= CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
513 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
514 .ext3_features
= CPUID_EXT3_LAHF_LM
,
515 .xlevel
= 0x8000000A,
516 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
521 .vendor1
= CPUID_VENDOR_INTEL_1
,
522 .vendor2
= CPUID_VENDOR_INTEL_2
,
523 .vendor3
= CPUID_VENDOR_INTEL_3
,
527 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
528 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
529 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
530 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
531 CPUID_DE
| CPUID_FP87
,
532 .ext_features
= CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
534 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
535 .ext3_features
= CPUID_EXT3_LAHF_LM
,
536 .xlevel
= 0x8000000A,
537 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
542 .vendor1
= CPUID_VENDOR_INTEL_1
,
543 .vendor2
= CPUID_VENDOR_INTEL_2
,
544 .vendor3
= CPUID_VENDOR_INTEL_3
,
548 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
549 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
550 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
551 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
552 CPUID_DE
| CPUID_FP87
,
553 .ext_features
= CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
554 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
555 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
556 .ext3_features
= CPUID_EXT3_LAHF_LM
,
557 .xlevel
= 0x8000000A,
558 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
563 .vendor1
= CPUID_VENDOR_INTEL_1
,
564 .vendor2
= CPUID_VENDOR_INTEL_2
,
565 .vendor3
= CPUID_VENDOR_INTEL_3
,
569 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
570 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
571 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
572 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
573 CPUID_DE
| CPUID_FP87
,
574 .ext_features
= CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
575 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
577 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
578 .ext3_features
= CPUID_EXT3_LAHF_LM
,
579 .xlevel
= 0x8000000A,
580 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
583 .name
= "SandyBridge",
585 .vendor1
= CPUID_VENDOR_INTEL_1
,
586 .vendor2
= CPUID_VENDOR_INTEL_2
,
587 .vendor3
= CPUID_VENDOR_INTEL_3
,
591 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
592 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
593 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
594 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
595 CPUID_DE
| CPUID_FP87
,
596 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
597 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
598 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
599 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
601 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
603 .ext3_features
= CPUID_EXT3_LAHF_LM
,
604 .xlevel
= 0x8000000A,
605 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
608 .name
= "Opteron_G1",
610 .vendor1
= CPUID_VENDOR_AMD_1
,
611 .vendor2
= CPUID_VENDOR_AMD_2
,
612 .vendor3
= CPUID_VENDOR_AMD_3
,
616 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
617 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
618 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
619 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
620 CPUID_DE
| CPUID_FP87
,
621 .ext_features
= CPUID_EXT_SSE3
,
622 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
623 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
624 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
625 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
626 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
627 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
628 .xlevel
= 0x80000008,
629 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
632 .name
= "Opteron_G2",
634 .vendor1
= CPUID_VENDOR_AMD_1
,
635 .vendor2
= CPUID_VENDOR_AMD_2
,
636 .vendor3
= CPUID_VENDOR_AMD_3
,
640 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
641 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
642 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
643 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
644 CPUID_DE
| CPUID_FP87
,
645 .ext_features
= CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
646 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
647 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
648 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
649 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
650 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
651 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
652 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
653 .ext3_features
= CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
654 .xlevel
= 0x80000008,
655 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
658 .name
= "Opteron_G3",
660 .vendor1
= CPUID_VENDOR_AMD_1
,
661 .vendor2
= CPUID_VENDOR_AMD_2
,
662 .vendor3
= CPUID_VENDOR_AMD_3
,
666 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
667 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
668 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
669 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
670 CPUID_DE
| CPUID_FP87
,
671 .ext_features
= CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
673 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
674 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
675 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
676 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
677 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
678 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
679 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
680 .ext3_features
= CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
681 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
682 .xlevel
= 0x80000008,
683 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
686 .name
= "Opteron_G4",
688 .vendor1
= CPUID_VENDOR_AMD_1
,
689 .vendor2
= CPUID_VENDOR_AMD_2
,
690 .vendor3
= CPUID_VENDOR_AMD_3
,
694 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
695 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
696 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
697 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
698 CPUID_DE
| CPUID_FP87
,
699 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
700 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
701 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
703 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
704 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
705 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
706 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
707 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
708 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
709 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
710 .ext3_features
= CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
711 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
712 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
714 .xlevel
= 0x8000001A,
715 .model_id
= "AMD Opteron 62xx class CPU",
719 static int cpu_x86_fill_model_id(char *str
)
721 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
724 for (i
= 0; i
< 3; i
++) {
725 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
726 memcpy(str
+ i
* 16 + 0, &eax
, 4);
727 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
728 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
729 memcpy(str
+ i
* 16 + 12, &edx
, 4);
734 static int cpu_x86_fill_host(x86_def_t
*x86_cpu_def
)
736 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
738 x86_cpu_def
->name
= "host";
739 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
740 x86_cpu_def
->level
= eax
;
741 x86_cpu_def
->vendor1
= ebx
;
742 x86_cpu_def
->vendor2
= edx
;
743 x86_cpu_def
->vendor3
= ecx
;
745 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
746 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
747 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
748 x86_cpu_def
->stepping
= eax
& 0x0F;
749 x86_cpu_def
->ext_features
= ecx
;
750 x86_cpu_def
->features
= edx
;
752 if (kvm_enabled() && x86_cpu_def
->level
>= 7) {
753 x86_cpu_def
->cpuid_7_0_ebx_features
= kvm_arch_get_supported_cpuid(kvm_state
, 0x7, 0, R_EBX
);
755 x86_cpu_def
->cpuid_7_0_ebx_features
= 0;
758 host_cpuid(0x80000000, 0, &eax
, &ebx
, &ecx
, &edx
);
759 x86_cpu_def
->xlevel
= eax
;
761 host_cpuid(0x80000001, 0, &eax
, &ebx
, &ecx
, &edx
);
762 x86_cpu_def
->ext2_features
= edx
;
763 x86_cpu_def
->ext3_features
= ecx
;
764 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
765 x86_cpu_def
->vendor_override
= 0;
767 /* Call Centaur's CPUID instruction. */
768 if (x86_cpu_def
->vendor1
== CPUID_VENDOR_VIA_1
&&
769 x86_cpu_def
->vendor2
== CPUID_VENDOR_VIA_2
&&
770 x86_cpu_def
->vendor3
== CPUID_VENDOR_VIA_3
) {
771 host_cpuid(0xC0000000, 0, &eax
, &ebx
, &ecx
, &edx
);
772 if (eax
>= 0xC0000001) {
773 /* Support VIA max extended level */
774 x86_cpu_def
->xlevel2
= eax
;
775 host_cpuid(0xC0000001, 0, &eax
, &ebx
, &ecx
, &edx
);
776 x86_cpu_def
->ext4_features
= edx
;
781 * Every SVM feature requires emulation support in KVM - so we can't just
782 * read the host features here. KVM might even support SVM features not
783 * available on the host hardware. Just set all bits and mask out the
784 * unsupported ones later.
786 x86_cpu_def
->svm_features
= -1;
791 static int unavailable_host_feature(struct model_features_t
*f
, uint32_t mask
)
795 for (i
= 0; i
< 32; ++i
)
797 fprintf(stderr
, "warning: host cpuid %04x_%04x lacks requested"
798 " flag '%s' [0x%08x]\n",
799 f
->cpuid
>> 16, f
->cpuid
& 0xffff,
800 f
->flag_names
[i
] ? f
->flag_names
[i
] : "[reserved]", mask
);
806 /* best effort attempt to inform user requested cpu flags aren't making
807 * their way to the guest. Note: ft[].check_feat ideally should be
808 * specified via a guest_def field to suppress report of extraneous flags.
810 static int check_features_against_host(x86_def_t
*guest_def
)
815 struct model_features_t ft
[] = {
816 {&guest_def
->features
, &host_def
.features
,
817 ~0, feature_name
, 0x00000000},
818 {&guest_def
->ext_features
, &host_def
.ext_features
,
819 ~CPUID_EXT_HYPERVISOR
, ext_feature_name
, 0x00000001},
820 {&guest_def
->ext2_features
, &host_def
.ext2_features
,
821 ~PPRO_FEATURES
, ext2_feature_name
, 0x80000000},
822 {&guest_def
->ext3_features
, &host_def
.ext3_features
,
823 ~CPUID_EXT3_SVM
, ext3_feature_name
, 0x80000001}};
825 cpu_x86_fill_host(&host_def
);
826 for (rv
= 0, i
= 0; i
< ARRAY_SIZE(ft
); ++i
)
827 for (mask
= 1; mask
; mask
<<= 1)
828 if (ft
[i
].check_feat
& mask
&& *ft
[i
].guest_feat
& mask
&&
829 !(*ft
[i
].host_feat
& mask
)) {
830 unavailable_host_feature(&ft
[i
], mask
);
836 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
837 const char *name
, Error
**errp
)
839 X86CPU
*cpu
= X86_CPU(obj
);
840 CPUX86State
*env
= &cpu
->env
;
843 value
= (env
->cpuid_version
>> 8) & 0xf;
845 value
+= (env
->cpuid_version
>> 20) & 0xff;
847 visit_type_int(v
, &value
, name
, errp
);
850 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
851 const char *name
, Error
**errp
)
853 X86CPU
*cpu
= X86_CPU(obj
);
854 CPUX86State
*env
= &cpu
->env
;
855 const int64_t min
= 0;
856 const int64_t max
= 0xff + 0xf;
859 visit_type_int(v
, &value
, name
, errp
);
860 if (error_is_set(errp
)) {
863 if (value
< min
|| value
> max
) {
864 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
865 name
? name
: "null", value
, min
, max
);
869 env
->cpuid_version
&= ~0xff00f00;
871 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
873 env
->cpuid_version
|= value
<< 8;
877 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
878 const char *name
, Error
**errp
)
880 X86CPU
*cpu
= X86_CPU(obj
);
881 CPUX86State
*env
= &cpu
->env
;
884 value
= (env
->cpuid_version
>> 4) & 0xf;
885 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
886 visit_type_int(v
, &value
, name
, errp
);
889 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
890 const char *name
, Error
**errp
)
892 X86CPU
*cpu
= X86_CPU(obj
);
893 CPUX86State
*env
= &cpu
->env
;
894 const int64_t min
= 0;
895 const int64_t max
= 0xff;
898 visit_type_int(v
, &value
, name
, errp
);
899 if (error_is_set(errp
)) {
902 if (value
< min
|| value
> max
) {
903 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
904 name
? name
: "null", value
, min
, max
);
908 env
->cpuid_version
&= ~0xf00f0;
909 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
912 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
913 void *opaque
, const char *name
,
916 X86CPU
*cpu
= X86_CPU(obj
);
917 CPUX86State
*env
= &cpu
->env
;
920 value
= env
->cpuid_version
& 0xf;
921 visit_type_int(v
, &value
, name
, errp
);
924 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
925 void *opaque
, const char *name
,
928 X86CPU
*cpu
= X86_CPU(obj
);
929 CPUX86State
*env
= &cpu
->env
;
930 const int64_t min
= 0;
931 const int64_t max
= 0xf;
934 visit_type_int(v
, &value
, name
, errp
);
935 if (error_is_set(errp
)) {
938 if (value
< min
|| value
> max
) {
939 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
940 name
? name
: "null", value
, min
, max
);
944 env
->cpuid_version
&= ~0xf;
945 env
->cpuid_version
|= value
& 0xf;
948 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
949 const char *name
, Error
**errp
)
951 X86CPU
*cpu
= X86_CPU(obj
);
953 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
956 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
957 const char *name
, Error
**errp
)
959 X86CPU
*cpu
= X86_CPU(obj
);
961 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
964 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
965 const char *name
, Error
**errp
)
967 X86CPU
*cpu
= X86_CPU(obj
);
969 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
972 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
973 const char *name
, Error
**errp
)
975 X86CPU
*cpu
= X86_CPU(obj
);
977 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
980 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
982 X86CPU
*cpu
= X86_CPU(obj
);
983 CPUX86State
*env
= &cpu
->env
;
987 value
= (char *)g_malloc(12 + 1);
988 for (i
= 0; i
< 4; i
++) {
989 value
[i
] = env
->cpuid_vendor1
>> (8 * i
);
990 value
[i
+ 4] = env
->cpuid_vendor2
>> (8 * i
);
991 value
[i
+ 8] = env
->cpuid_vendor3
>> (8 * i
);
997 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1000 X86CPU
*cpu
= X86_CPU(obj
);
1001 CPUX86State
*env
= &cpu
->env
;
1004 if (strlen(value
) != 12) {
1005 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1010 env
->cpuid_vendor1
= 0;
1011 env
->cpuid_vendor2
= 0;
1012 env
->cpuid_vendor3
= 0;
1013 for (i
= 0; i
< 4; i
++) {
1014 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1015 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1016 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1018 env
->cpuid_vendor_override
= 1;
1021 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1023 X86CPU
*cpu
= X86_CPU(obj
);
1024 CPUX86State
*env
= &cpu
->env
;
1028 value
= g_malloc(48 + 1);
1029 for (i
= 0; i
< 48; i
++) {
1030 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1036 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1039 X86CPU
*cpu
= X86_CPU(obj
);
1040 CPUX86State
*env
= &cpu
->env
;
1043 if (model_id
== NULL
) {
1046 len
= strlen(model_id
);
1047 memset(env
->cpuid_model
, 0, 48);
1048 for (i
= 0; i
< 48; i
++) {
1052 c
= (uint8_t)model_id
[i
];
1054 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1058 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1059 const char *name
, Error
**errp
)
1061 X86CPU
*cpu
= X86_CPU(obj
);
1064 value
= cpu
->env
.tsc_khz
* 1000;
1065 visit_type_int(v
, &value
, name
, errp
);
1068 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1069 const char *name
, Error
**errp
)
1071 X86CPU
*cpu
= X86_CPU(obj
);
1072 const int64_t min
= 0;
1073 const int64_t max
= INT64_MAX
;
1076 visit_type_int(v
, &value
, name
, errp
);
1077 if (error_is_set(errp
)) {
1080 if (value
< min
|| value
> max
) {
1081 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1082 name
? name
: "null", value
, min
, max
);
1086 cpu
->env
.tsc_khz
= value
/ 1000;
1089 static int cpu_x86_find_by_name(x86_def_t
*x86_cpu_def
, const char *cpu_model
)
1094 char *s
= g_strdup(cpu_model
);
1095 char *featurestr
, *name
= strtok(s
, ",");
1096 /* Features to be added*/
1097 uint32_t plus_features
= 0, plus_ext_features
= 0;
1098 uint32_t plus_ext2_features
= 0, plus_ext3_features
= 0;
1099 uint32_t plus_kvm_features
= 0, plus_svm_features
= 0;
1100 /* Features to be removed */
1101 uint32_t minus_features
= 0, minus_ext_features
= 0;
1102 uint32_t minus_ext2_features
= 0, minus_ext3_features
= 0;
1103 uint32_t minus_kvm_features
= 0, minus_svm_features
= 0;
1106 for (def
= x86_defs
; def
; def
= def
->next
)
1107 if (name
&& !strcmp(name
, def
->name
))
1109 if (kvm_enabled() && name
&& strcmp(name
, "host") == 0) {
1110 cpu_x86_fill_host(x86_cpu_def
);
1114 memcpy(x86_cpu_def
, def
, sizeof(*def
));
1117 #if defined(CONFIG_KVM)
1118 plus_kvm_features
= (1 << KVM_FEATURE_CLOCKSOURCE
) |
1119 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
1120 (1 << KVM_FEATURE_MMU_OP
) |
1121 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
1122 (1 << KVM_FEATURE_ASYNC_PF
) |
1123 (1 << KVM_FEATURE_STEAL_TIME
) |
1124 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
);
1126 plus_kvm_features
= 0;
1129 add_flagname_to_bitmaps("hypervisor", &plus_features
,
1130 &plus_ext_features
, &plus_ext2_features
, &plus_ext3_features
,
1131 &plus_kvm_features
, &plus_svm_features
);
1133 featurestr
= strtok(NULL
, ",");
1135 while (featurestr
) {
1137 if (featurestr
[0] == '+') {
1138 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
,
1139 &plus_ext_features
, &plus_ext2_features
,
1140 &plus_ext3_features
, &plus_kvm_features
,
1141 &plus_svm_features
);
1142 } else if (featurestr
[0] == '-') {
1143 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
,
1144 &minus_ext_features
, &minus_ext2_features
,
1145 &minus_ext3_features
, &minus_kvm_features
,
1146 &minus_svm_features
);
1147 } else if ((val
= strchr(featurestr
, '='))) {
1149 if (!strcmp(featurestr
, "family")) {
1151 numvalue
= strtoul(val
, &err
, 0);
1152 if (!*val
|| *err
|| numvalue
> 0xff + 0xf) {
1153 fprintf(stderr
, "bad numerical value %s\n", val
);
1156 x86_cpu_def
->family
= numvalue
;
1157 } else if (!strcmp(featurestr
, "model")) {
1159 numvalue
= strtoul(val
, &err
, 0);
1160 if (!*val
|| *err
|| numvalue
> 0xff) {
1161 fprintf(stderr
, "bad numerical value %s\n", val
);
1164 x86_cpu_def
->model
= numvalue
;
1165 } else if (!strcmp(featurestr
, "stepping")) {
1167 numvalue
= strtoul(val
, &err
, 0);
1168 if (!*val
|| *err
|| numvalue
> 0xf) {
1169 fprintf(stderr
, "bad numerical value %s\n", val
);
1172 x86_cpu_def
->stepping
= numvalue
;
1173 } else if (!strcmp(featurestr
, "level")) {
1175 numvalue
= strtoul(val
, &err
, 0);
1176 if (!*val
|| *err
) {
1177 fprintf(stderr
, "bad numerical value %s\n", val
);
1180 x86_cpu_def
->level
= numvalue
;
1181 } else if (!strcmp(featurestr
, "xlevel")) {
1183 numvalue
= strtoul(val
, &err
, 0);
1184 if (!*val
|| *err
) {
1185 fprintf(stderr
, "bad numerical value %s\n", val
);
1188 if (numvalue
< 0x80000000) {
1189 numvalue
+= 0x80000000;
1191 x86_cpu_def
->xlevel
= numvalue
;
1192 } else if (!strcmp(featurestr
, "vendor")) {
1193 if (strlen(val
) != 12) {
1194 fprintf(stderr
, "vendor string must be 12 chars long\n");
1197 x86_cpu_def
->vendor1
= 0;
1198 x86_cpu_def
->vendor2
= 0;
1199 x86_cpu_def
->vendor3
= 0;
1200 for(i
= 0; i
< 4; i
++) {
1201 x86_cpu_def
->vendor1
|= ((uint8_t)val
[i
]) << (8 * i
);
1202 x86_cpu_def
->vendor2
|= ((uint8_t)val
[i
+ 4]) << (8 * i
);
1203 x86_cpu_def
->vendor3
|= ((uint8_t)val
[i
+ 8]) << (8 * i
);
1205 x86_cpu_def
->vendor_override
= 1;
1206 } else if (!strcmp(featurestr
, "model_id")) {
1207 pstrcpy(x86_cpu_def
->model_id
, sizeof(x86_cpu_def
->model_id
),
1209 } else if (!strcmp(featurestr
, "tsc_freq")) {
1213 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1214 STRTOSZ_DEFSUFFIX_B
, 1000);
1215 if (tsc_freq
< 0 || *err
) {
1216 fprintf(stderr
, "bad numerical value %s\n", val
);
1219 x86_cpu_def
->tsc_khz
= tsc_freq
/ 1000;
1220 } else if (!strcmp(featurestr
, "hv_spinlocks")) {
1222 numvalue
= strtoul(val
, &err
, 0);
1223 if (!*val
|| *err
) {
1224 fprintf(stderr
, "bad numerical value %s\n", val
);
1227 hyperv_set_spinlock_retries(numvalue
);
1229 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
1232 } else if (!strcmp(featurestr
, "check")) {
1234 } else if (!strcmp(featurestr
, "enforce")) {
1235 check_cpuid
= enforce_cpuid
= 1;
1236 } else if (!strcmp(featurestr
, "hv_relaxed")) {
1237 hyperv_enable_relaxed_timing(true);
1238 } else if (!strcmp(featurestr
, "hv_vapic")) {
1239 hyperv_enable_vapic_recommended(true);
1241 fprintf(stderr
, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr
);
1244 featurestr
= strtok(NULL
, ",");
1246 x86_cpu_def
->features
|= plus_features
;
1247 x86_cpu_def
->ext_features
|= plus_ext_features
;
1248 x86_cpu_def
->ext2_features
|= plus_ext2_features
;
1249 x86_cpu_def
->ext3_features
|= plus_ext3_features
;
1250 x86_cpu_def
->kvm_features
|= plus_kvm_features
;
1251 x86_cpu_def
->svm_features
|= plus_svm_features
;
1252 x86_cpu_def
->features
&= ~minus_features
;
1253 x86_cpu_def
->ext_features
&= ~minus_ext_features
;
1254 x86_cpu_def
->ext2_features
&= ~minus_ext2_features
;
1255 x86_cpu_def
->ext3_features
&= ~minus_ext3_features
;
1256 x86_cpu_def
->kvm_features
&= ~minus_kvm_features
;
1257 x86_cpu_def
->svm_features
&= ~minus_svm_features
;
1259 if (check_features_against_host(x86_cpu_def
) && enforce_cpuid
)
1270 /* generate a composite string into buf of all cpuid names in featureset
1271 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1272 * if flags, suppress names undefined in featureset.
1274 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1275 const char **featureset
, uint32_t flags
)
1277 const char **p
= &featureset
[31];
1281 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1283 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1284 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1286 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1288 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1289 if (bufsize
<= nc
) {
1291 memcpy(b
, "...", sizeof("..."));
1300 /* generate CPU information. */
1301 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1306 for (def
= x86_defs
; def
; def
= def
->next
) {
1307 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
1308 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1310 if (kvm_enabled()) {
1311 (*cpu_fprintf
)(f
, "x86 %16s\n", "[host]");
1313 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1314 listflags(buf
, sizeof(buf
), (uint32_t)~0, feature_name
, 1);
1315 (*cpu_fprintf
)(f
, " %s\n", buf
);
1316 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext_feature_name
, 1);
1317 (*cpu_fprintf
)(f
, " %s\n", buf
);
1318 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext2_feature_name
, 1);
1319 (*cpu_fprintf
)(f
, " %s\n", buf
);
1320 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext3_feature_name
, 1);
1321 (*cpu_fprintf
)(f
, " %s\n", buf
);
1324 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1326 CpuDefinitionInfoList
*cpu_list
= NULL
;
1329 for (def
= x86_defs
; def
; def
= def
->next
) {
1330 CpuDefinitionInfoList
*entry
;
1331 CpuDefinitionInfo
*info
;
1333 info
= g_malloc0(sizeof(*info
));
1334 info
->name
= g_strdup(def
->name
);
1336 entry
= g_malloc0(sizeof(*entry
));
1337 entry
->value
= info
;
1338 entry
->next
= cpu_list
;
1345 int cpu_x86_register(X86CPU
*cpu
, const char *cpu_model
)
1347 CPUX86State
*env
= &cpu
->env
;
1348 x86_def_t def1
, *def
= &def1
;
1349 Error
*error
= NULL
;
1351 memset(def
, 0, sizeof(*def
));
1353 if (cpu_x86_find_by_name(def
, cpu_model
) < 0)
1356 env
->cpuid_vendor1
= def
->vendor1
;
1357 env
->cpuid_vendor2
= def
->vendor2
;
1358 env
->cpuid_vendor3
= def
->vendor3
;
1360 env
->cpuid_vendor1
= CPUID_VENDOR_INTEL_1
;
1361 env
->cpuid_vendor2
= CPUID_VENDOR_INTEL_2
;
1362 env
->cpuid_vendor3
= CPUID_VENDOR_INTEL_3
;
1364 env
->cpuid_vendor_override
= def
->vendor_override
;
1365 object_property_set_int(OBJECT(cpu
), def
->level
, "level", &error
);
1366 object_property_set_int(OBJECT(cpu
), def
->family
, "family", &error
);
1367 object_property_set_int(OBJECT(cpu
), def
->model
, "model", &error
);
1368 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", &error
);
1369 env
->cpuid_features
= def
->features
;
1370 env
->cpuid_ext_features
= def
->ext_features
;
1371 env
->cpuid_ext2_features
= def
->ext2_features
;
1372 env
->cpuid_ext3_features
= def
->ext3_features
;
1373 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", &error
);
1374 env
->cpuid_kvm_features
= def
->kvm_features
;
1375 env
->cpuid_svm_features
= def
->svm_features
;
1376 env
->cpuid_ext4_features
= def
->ext4_features
;
1377 env
->cpuid_7_0_ebx
= def
->cpuid_7_0_ebx_features
;
1378 env
->cpuid_xlevel2
= def
->xlevel2
;
1379 object_property_set_int(OBJECT(cpu
), (int64_t)def
->tsc_khz
* 1000,
1380 "tsc-frequency", &error
);
1382 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1385 if (env
->cpuid_vendor1
== CPUID_VENDOR_AMD_1
&&
1386 env
->cpuid_vendor2
== CPUID_VENDOR_AMD_2
&&
1387 env
->cpuid_vendor3
== CPUID_VENDOR_AMD_3
) {
1388 env
->cpuid_ext2_features
&= ~CPUID_EXT2_AMD_ALIASES
;
1389 env
->cpuid_ext2_features
|= (def
->features
& CPUID_EXT2_AMD_ALIASES
);
1392 if (!kvm_enabled()) {
1393 env
->cpuid_features
&= TCG_FEATURES
;
1394 env
->cpuid_ext_features
&= TCG_EXT_FEATURES
;
1395 env
->cpuid_ext2_features
&= (TCG_EXT2_FEATURES
1396 #ifdef TARGET_X86_64
1397 | CPUID_EXT2_SYSCALL
| CPUID_EXT2_LM
1400 env
->cpuid_ext3_features
&= TCG_EXT3_FEATURES
;
1401 env
->cpuid_svm_features
&= TCG_SVM_FEATURES
;
1403 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", &error
);
1404 if (error_is_set(&error
)) {
1411 #if !defined(CONFIG_USER_ONLY)
1413 void cpu_clear_apic_feature(CPUX86State
*env
)
1415 env
->cpuid_features
&= ~CPUID_APIC
;
1418 #endif /* !CONFIG_USER_ONLY */
1420 /* Initialize list of CPU models, filling some non-static fields if necessary
1422 void x86_cpudef_setup(void)
1425 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
1427 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
1428 x86_def_t
*def
= &builtin_x86_defs
[i
];
1429 def
->next
= x86_defs
;
1431 /* Look for specific "cpudef" models that */
1432 /* have the QEMU version in .model_id */
1433 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
1434 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
1435 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
1436 "QEMU Virtual CPU version ");
1437 pstrcat(def
->model_id
, sizeof(def
->model_id
),
1438 qemu_get_version());
1447 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
1448 uint32_t *ecx
, uint32_t *edx
)
1450 *ebx
= env
->cpuid_vendor1
;
1451 *edx
= env
->cpuid_vendor2
;
1452 *ecx
= env
->cpuid_vendor3
;
1454 /* sysenter isn't supported on compatibility mode on AMD, syscall
1455 * isn't supported in compatibility mode on Intel.
1456 * Normally we advertise the actual cpu vendor, but you can override
1457 * this if you want to use KVM's sysenter/syscall emulation
1458 * in compatibility mode and when doing cross vendor migration
1460 if (kvm_enabled() && ! env
->cpuid_vendor_override
) {
1461 host_cpuid(0, 0, NULL
, ebx
, ecx
, edx
);
1465 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
1466 uint32_t *eax
, uint32_t *ebx
,
1467 uint32_t *ecx
, uint32_t *edx
)
1469 /* test if maximum index reached */
1470 if (index
& 0x80000000) {
1471 if (index
> env
->cpuid_xlevel
) {
1472 if (env
->cpuid_xlevel2
> 0) {
1473 /* Handle the Centaur's CPUID instruction. */
1474 if (index
> env
->cpuid_xlevel2
) {
1475 index
= env
->cpuid_xlevel2
;
1476 } else if (index
< 0xC0000000) {
1477 index
= env
->cpuid_xlevel
;
1480 index
= env
->cpuid_xlevel
;
1484 if (index
> env
->cpuid_level
)
1485 index
= env
->cpuid_level
;
1490 *eax
= env
->cpuid_level
;
1491 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
1494 *eax
= env
->cpuid_version
;
1495 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1496 *ecx
= env
->cpuid_ext_features
;
1497 *edx
= env
->cpuid_features
;
1498 if (env
->nr_cores
* env
->nr_threads
> 1) {
1499 *ebx
|= (env
->nr_cores
* env
->nr_threads
) << 16;
1500 *edx
|= 1 << 28; /* HTT bit */
1504 /* cache info: needed for Pentium Pro compatibility */
1511 /* cache info: needed for Core compatibility */
1512 if (env
->nr_cores
> 1) {
1513 *eax
= (env
->nr_cores
- 1) << 26;
1518 case 0: /* L1 dcache info */
1524 case 1: /* L1 icache info */
1530 case 2: /* L2 cache info */
1532 if (env
->nr_threads
> 1) {
1533 *eax
|= (env
->nr_threads
- 1) << 14;
1539 default: /* end of info */
1548 /* mwait info: needed for Core compatibility */
1549 *eax
= 0; /* Smallest monitor-line size in bytes */
1550 *ebx
= 0; /* Largest monitor-line size in bytes */
1551 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
1555 /* Thermal and Power Leaf */
1562 /* Structured Extended Feature Flags Enumeration Leaf */
1564 *eax
= 0; /* Maximum ECX value for sub-leaves */
1565 *ebx
= env
->cpuid_7_0_ebx
; /* Feature flags */
1566 *ecx
= 0; /* Reserved */
1567 *edx
= 0; /* Reserved */
1576 /* Direct Cache Access Information Leaf */
1577 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
1583 /* Architectural Performance Monitoring Leaf */
1584 if (kvm_enabled()) {
1585 KVMState
*s
= env
->kvm_state
;
1587 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
1588 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
1589 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
1590 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
1599 /* Processor Extended State */
1600 if (!(env
->cpuid_ext_features
& CPUID_EXT_XSAVE
)) {
1607 if (kvm_enabled()) {
1608 KVMState
*s
= env
->kvm_state
;
1610 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EAX
);
1611 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EBX
);
1612 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_ECX
);
1613 *edx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EDX
);
1622 *eax
= env
->cpuid_xlevel
;
1623 *ebx
= env
->cpuid_vendor1
;
1624 *edx
= env
->cpuid_vendor2
;
1625 *ecx
= env
->cpuid_vendor3
;
1628 *eax
= env
->cpuid_version
;
1630 *ecx
= env
->cpuid_ext3_features
;
1631 *edx
= env
->cpuid_ext2_features
;
1633 /* The Linux kernel checks for the CMPLegacy bit and
1634 * discards multiple thread information if it is set.
1635 * So dont set it here for Intel to make Linux guests happy.
1637 if (env
->nr_cores
* env
->nr_threads
> 1) {
1638 uint32_t tebx
, tecx
, tedx
;
1639 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
1640 if (tebx
!= CPUID_VENDOR_INTEL_1
||
1641 tedx
!= CPUID_VENDOR_INTEL_2
||
1642 tecx
!= CPUID_VENDOR_INTEL_3
) {
1643 *ecx
|= 1 << 1; /* CmpLegacy bit */
1650 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
1651 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
1652 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
1653 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
1656 /* cache info (L1 cache) */
1663 /* cache info (L2 cache) */
1670 /* virtual & phys address size in low 2 bytes. */
1671 /* XXX: This value must match the one used in the MMU code. */
1672 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
) {
1673 /* 64 bit processor */
1674 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1675 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
1677 if (env
->cpuid_features
& CPUID_PSE36
)
1678 *eax
= 0x00000024; /* 36 bits physical */
1680 *eax
= 0x00000020; /* 32 bits physical */
1685 if (env
->nr_cores
* env
->nr_threads
> 1) {
1686 *ecx
|= (env
->nr_cores
* env
->nr_threads
) - 1;
1690 if (env
->cpuid_ext3_features
& CPUID_EXT3_SVM
) {
1691 *eax
= 0x00000001; /* SVM Revision */
1692 *ebx
= 0x00000010; /* nr of ASIDs */
1694 *edx
= env
->cpuid_svm_features
; /* optional features */
1703 *eax
= env
->cpuid_xlevel2
;
1709 /* Support for VIA CPU's CPUID instruction */
1710 *eax
= env
->cpuid_version
;
1713 *edx
= env
->cpuid_ext4_features
;
1718 /* Reserved for the future, and now filled with zero */
1725 /* reserved values: zero */
1734 /* CPUClass::reset() */
1735 static void x86_cpu_reset(CPUState
*s
)
1737 X86CPU
*cpu
= X86_CPU(s
);
1738 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
1739 CPUX86State
*env
= &cpu
->env
;
1742 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1743 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1744 log_cpu_state(env
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
1747 xcc
->parent_reset(s
);
1750 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
1754 env
->old_exception
= -1;
1756 /* init to reset state */
1758 #ifdef CONFIG_SOFTMMU
1759 env
->hflags
|= HF_SOFTMMU_MASK
;
1761 env
->hflags2
|= HF2_GIF_MASK
;
1763 cpu_x86_update_cr0(env
, 0x60000010);
1764 env
->a20_mask
= ~0x0;
1765 env
->smbase
= 0x30000;
1767 env
->idt
.limit
= 0xffff;
1768 env
->gdt
.limit
= 0xffff;
1769 env
->ldt
.limit
= 0xffff;
1770 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
1771 env
->tr
.limit
= 0xffff;
1772 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
1774 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
1775 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
1776 DESC_R_MASK
| DESC_A_MASK
);
1777 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
1778 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1780 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
1781 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1783 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
1784 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1786 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
1787 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1789 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
1790 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1794 env
->regs
[R_EDX
] = env
->cpuid_version
;
1799 for (i
= 0; i
< 8; i
++) {
1804 env
->mxcsr
= 0x1f80;
1806 env
->pat
= 0x0007040600070406ULL
;
1807 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
1809 memset(env
->dr
, 0, sizeof(env
->dr
));
1810 env
->dr
[6] = DR6_FIXED_1
;
1811 env
->dr
[7] = DR7_FIXED_1
;
1812 cpu_breakpoint_remove_all(env
, BP_CPU
);
1813 cpu_watchpoint_remove_all(env
, BP_CPU
);
1815 #if !defined(CONFIG_USER_ONLY)
1816 /* We hard-wire the BSP to the first CPU. */
1817 if (env
->cpu_index
== 0) {
1818 apic_designate_bsp(env
->apic_state
);
1821 env
->halted
= !cpu_is_bsp(cpu
);
1825 #ifndef CONFIG_USER_ONLY
1826 bool cpu_is_bsp(X86CPU
*cpu
)
1828 return cpu_get_apic_base(cpu
->env
.apic_state
) & MSR_IA32_APICBASE_BSP
;
1831 /* TODO: remove me, when reset over QOM tree is implemented */
1832 static void x86_cpu_machine_reset_cb(void *opaque
)
1834 X86CPU
*cpu
= opaque
;
1835 cpu_reset(CPU(cpu
));
1839 static void mce_init(X86CPU
*cpu
)
1841 CPUX86State
*cenv
= &cpu
->env
;
1844 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
1845 && (cenv
->cpuid_features
& (CPUID_MCE
| CPUID_MCA
)) ==
1846 (CPUID_MCE
| CPUID_MCA
)) {
1847 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
1848 cenv
->mcg_ctl
= ~(uint64_t)0;
1849 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
1850 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
1855 void x86_cpu_realize(Object
*obj
, Error
**errp
)
1857 X86CPU
*cpu
= X86_CPU(obj
);
1859 #ifndef CONFIG_USER_ONLY
1860 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
1864 qemu_init_vcpu(&cpu
->env
);
1865 cpu_reset(CPU(cpu
));
1868 static void x86_cpu_initfn(Object
*obj
)
1870 X86CPU
*cpu
= X86_CPU(obj
);
1871 CPUX86State
*env
= &cpu
->env
;
1876 object_property_add(obj
, "family", "int",
1877 x86_cpuid_version_get_family
,
1878 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
1879 object_property_add(obj
, "model", "int",
1880 x86_cpuid_version_get_model
,
1881 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
1882 object_property_add(obj
, "stepping", "int",
1883 x86_cpuid_version_get_stepping
,
1884 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
1885 object_property_add(obj
, "level", "int",
1886 x86_cpuid_get_level
,
1887 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
1888 object_property_add(obj
, "xlevel", "int",
1889 x86_cpuid_get_xlevel
,
1890 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
1891 object_property_add_str(obj
, "vendor",
1892 x86_cpuid_get_vendor
,
1893 x86_cpuid_set_vendor
, NULL
);
1894 object_property_add_str(obj
, "model-id",
1895 x86_cpuid_get_model_id
,
1896 x86_cpuid_set_model_id
, NULL
);
1897 object_property_add(obj
, "tsc-frequency", "int",
1898 x86_cpuid_get_tsc_freq
,
1899 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
1901 env
->cpuid_apic_id
= env
->cpu_index
;
1903 /* init various static tables used in TCG mode */
1904 if (tcg_enabled() && !inited
) {
1906 optimize_flags_init();
1907 #ifndef CONFIG_USER_ONLY
1908 cpu_set_debug_excp_handler(breakpoint_handler
);
1913 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
1915 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1916 CPUClass
*cc
= CPU_CLASS(oc
);
1918 xcc
->parent_reset
= cc
->reset
;
1919 cc
->reset
= x86_cpu_reset
;
1922 static const TypeInfo x86_cpu_type_info
= {
1923 .name
= TYPE_X86_CPU
,
1925 .instance_size
= sizeof(X86CPU
),
1926 .instance_init
= x86_cpu_initfn
,
1928 .class_size
= sizeof(X86CPUClass
),
1929 .class_init
= x86_cpu_common_class_init
,
1932 static void x86_cpu_register_types(void)
1934 type_register_static(&x86_cpu_type_info
);
1937 type_init(x86_cpu_register_types
)