2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "qemu-option.h"
28 #include "qemu-config.h"
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
40 /* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
44 static const char *feature_name
[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL
, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
54 static const char *ext_feature_name
[] = {
55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
56 "ds_cpl", "vmx", "smx", "est",
57 "tm2", "ssse3", "cid", NULL
,
58 "fma", "cx16", "xtpr", "pdcm",
59 NULL
, "pcid", "dca", "sse4.1|sse4_1",
60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
61 "tsc-deadline", "aes", "xsave", "osxsave",
62 "avx", NULL
, NULL
, "hypervisor",
64 static const char *ext2_feature_name
[] = {
65 "fpu", "vme", "de", "pse",
66 "tsc", "msr", "pae", "mce",
67 "cx8" /* AMD CMPXCHG8B */, "apic", NULL
, "syscall",
68 "mtrr", "pge", "mca", "cmov",
69 "pat", "pse36", NULL
, NULL
/* Linux mp */,
70 "nx|xd", NULL
, "mmxext", "mmx",
71 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
72 NULL
, "lm|i64", "3dnowext", "3dnow",
74 static const char *ext3_feature_name
[] = {
75 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
76 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
77 "3dnowprefetch", "osvw", "ibs", "xop",
78 "skinit", "wdt", NULL
, NULL
,
79 "fma4", NULL
, "cvt16", "nodeid_msr",
80 NULL
, NULL
, NULL
, NULL
,
81 NULL
, NULL
, NULL
, NULL
,
82 NULL
, NULL
, NULL
, NULL
,
85 static const char *kvm_feature_name
[] = {
86 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL
, "kvm_pv_eoi", NULL
,
87 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
88 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
89 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
92 static const char *svm_feature_name
[] = {
93 "npt", "lbrv", "svm_lock", "nrip_save",
94 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
95 NULL
, NULL
, "pause_filter", NULL
,
96 "pfthreshold", NULL
, NULL
, NULL
,
97 NULL
, NULL
, NULL
, NULL
,
98 NULL
, NULL
, NULL
, NULL
,
99 NULL
, NULL
, NULL
, NULL
,
100 NULL
, NULL
, NULL
, NULL
,
103 /* collects per-function cpuid data
105 typedef struct model_features_t
{
106 uint32_t *guest_feat
;
109 const char **flag_names
;
114 int enforce_cpuid
= 0;
116 void host_cpuid(uint32_t function
, uint32_t count
,
117 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
119 #if defined(CONFIG_KVM)
124 : "=a"(vec
[0]), "=b"(vec
[1]),
125 "=c"(vec
[2]), "=d"(vec
[3])
126 : "0"(function
), "c"(count
) : "cc");
128 asm volatile("pusha \n\t"
130 "mov %%eax, 0(%2) \n\t"
131 "mov %%ebx, 4(%2) \n\t"
132 "mov %%ecx, 8(%2) \n\t"
133 "mov %%edx, 12(%2) \n\t"
135 : : "a"(function
), "c"(count
), "S"(vec
)
150 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
152 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
153 * a substring. ex if !NULL points to the first char after a substring,
154 * otherwise the string is assumed to sized by a terminating nul.
155 * Return lexical ordering of *s1:*s2.
157 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
161 if (!*s1
|| !*s2
|| *s1
!= *s2
)
164 if (s1
== e1
&& s2
== e2
)
173 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
174 * '|' delimited (possibly empty) strings in which case search for a match
175 * within the alternatives proceeds left to right. Return 0 for success,
176 * non-zero otherwise.
178 static int altcmp(const char *s
, const char *e
, const char *altstr
)
182 for (q
= p
= altstr
; ; ) {
183 while (*p
&& *p
!= '|')
185 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
194 /* search featureset for flag *[s..e), if found set corresponding bit in
195 * *pval and return true, otherwise return false
197 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
198 const char **featureset
)
204 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
205 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
213 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
,
214 uint32_t *ext_features
,
215 uint32_t *ext2_features
,
216 uint32_t *ext3_features
,
217 uint32_t *kvm_features
,
218 uint32_t *svm_features
)
220 if (!lookup_feature(features
, flagname
, NULL
, feature_name
) &&
221 !lookup_feature(ext_features
, flagname
, NULL
, ext_feature_name
) &&
222 !lookup_feature(ext2_features
, flagname
, NULL
, ext2_feature_name
) &&
223 !lookup_feature(ext3_features
, flagname
, NULL
, ext3_feature_name
) &&
224 !lookup_feature(kvm_features
, flagname
, NULL
, kvm_feature_name
) &&
225 !lookup_feature(svm_features
, flagname
, NULL
, svm_feature_name
))
226 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
229 typedef struct x86_def_t
{
230 struct x86_def_t
*next
;
233 uint32_t vendor1
, vendor2
, vendor3
;
238 uint32_t features
, ext_features
, ext2_features
, ext3_features
;
239 uint32_t kvm_features
, svm_features
;
244 /* Store the results of Centaur's CPUID instructions */
245 uint32_t ext4_features
;
247 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
248 uint32_t cpuid_7_0_ebx_features
;
251 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
252 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
253 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
254 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
255 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
256 CPUID_PSE36 | CPUID_FXSR)
257 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
258 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
259 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
260 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
261 CPUID_PAE | CPUID_SEP | CPUID_APIC)
262 #define EXT2_FEATURE_MASK 0x0183F3FF
264 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
265 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
266 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
267 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
268 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
269 /* partly implemented:
270 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
271 CPUID_PSE36 (needed for Solaris) */
273 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
274 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
275 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
276 CPUID_EXT_HYPERVISOR)
278 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
279 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
280 #define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
281 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
282 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
284 CPUID_EXT2_PDPE1GB */
285 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
286 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
287 #define TCG_SVM_FEATURES 0
289 /* maintains list of cpu model definitions
291 static x86_def_t
*x86_defs
= {NULL
};
293 /* built-in cpu model definitions (deprecated)
295 static x86_def_t builtin_x86_defs
[] = {
299 .vendor1
= CPUID_VENDOR_AMD_1
,
300 .vendor2
= CPUID_VENDOR_AMD_2
,
301 .vendor3
= CPUID_VENDOR_AMD_3
,
305 .features
= PPRO_FEATURES
|
306 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
308 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
309 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
310 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
311 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
312 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
313 .xlevel
= 0x8000000A,
318 .vendor1
= CPUID_VENDOR_AMD_1
,
319 .vendor2
= CPUID_VENDOR_AMD_2
,
320 .vendor3
= CPUID_VENDOR_AMD_3
,
324 .features
= PPRO_FEATURES
|
325 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
326 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
327 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
329 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
330 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
331 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
332 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
333 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
335 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
336 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
337 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
338 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
339 .svm_features
= CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
340 .xlevel
= 0x8000001A,
341 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
349 .features
= PPRO_FEATURES
|
350 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
351 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
352 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
353 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
354 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
355 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
356 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
357 .ext3_features
= CPUID_EXT3_LAHF_LM
,
358 .xlevel
= 0x80000008,
359 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
364 .vendor1
= CPUID_VENDOR_INTEL_1
,
365 .vendor2
= CPUID_VENDOR_INTEL_2
,
366 .vendor3
= CPUID_VENDOR_INTEL_3
,
370 /* Missing: CPUID_VME, CPUID_HT */
371 .features
= PPRO_FEATURES
|
372 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
374 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
375 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
376 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
377 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
378 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
379 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
380 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
381 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
382 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
384 .xlevel
= 0x80000008,
385 .model_id
= "Common KVM processor"
393 .features
= PPRO_FEATURES
,
394 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
395 .xlevel
= 0x80000004,
403 .features
= PPRO_FEATURES
|
404 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
405 .ext_features
= CPUID_EXT_SSE3
,
406 .ext2_features
= PPRO_FEATURES
& EXT2_FEATURE_MASK
,
408 .xlevel
= 0x80000008,
409 .model_id
= "Common 32-bit KVM processor"
417 .features
= PPRO_FEATURES
| CPUID_VME
|
418 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
419 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
420 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
421 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
422 .ext2_features
= CPUID_EXT2_NX
,
423 .xlevel
= 0x80000008,
424 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
432 .features
= I486_FEATURES
,
441 .features
= PENTIUM_FEATURES
,
450 .features
= PENTIUM2_FEATURES
,
459 .features
= PENTIUM3_FEATURES
,
465 .vendor1
= CPUID_VENDOR_AMD_1
,
466 .vendor2
= CPUID_VENDOR_AMD_2
,
467 .vendor3
= CPUID_VENDOR_AMD_3
,
471 .features
= PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
| CPUID_MCA
,
472 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) | CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
473 .xlevel
= 0x80000008,
477 /* original is on level 10 */
482 .features
= PPRO_FEATURES
|
483 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
484 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
485 /* Some CPUs got no CPUID_SEP */
486 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
487 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
,
488 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) | CPUID_EXT2_NX
,
489 .ext3_features
= CPUID_EXT3_LAHF_LM
,
490 .xlevel
= 0x8000000A,
491 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
495 static int cpu_x86_fill_model_id(char *str
)
497 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
500 for (i
= 0; i
< 3; i
++) {
501 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
502 memcpy(str
+ i
* 16 + 0, &eax
, 4);
503 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
504 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
505 memcpy(str
+ i
* 16 + 12, &edx
, 4);
510 static int cpu_x86_fill_host(x86_def_t
*x86_cpu_def
)
512 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
514 x86_cpu_def
->name
= "host";
515 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
516 x86_cpu_def
->level
= eax
;
517 x86_cpu_def
->vendor1
= ebx
;
518 x86_cpu_def
->vendor2
= edx
;
519 x86_cpu_def
->vendor3
= ecx
;
521 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
522 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
523 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
524 x86_cpu_def
->stepping
= eax
& 0x0F;
525 x86_cpu_def
->ext_features
= ecx
;
526 x86_cpu_def
->features
= edx
;
528 if (kvm_enabled() && x86_cpu_def
->level
>= 7) {
529 x86_cpu_def
->cpuid_7_0_ebx_features
= kvm_arch_get_supported_cpuid(kvm_state
, 0x7, 0, R_EBX
);
531 x86_cpu_def
->cpuid_7_0_ebx_features
= 0;
534 host_cpuid(0x80000000, 0, &eax
, &ebx
, &ecx
, &edx
);
535 x86_cpu_def
->xlevel
= eax
;
537 host_cpuid(0x80000001, 0, &eax
, &ebx
, &ecx
, &edx
);
538 x86_cpu_def
->ext2_features
= edx
;
539 x86_cpu_def
->ext3_features
= ecx
;
540 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
541 x86_cpu_def
->vendor_override
= 0;
543 /* Call Centaur's CPUID instruction. */
544 if (x86_cpu_def
->vendor1
== CPUID_VENDOR_VIA_1
&&
545 x86_cpu_def
->vendor2
== CPUID_VENDOR_VIA_2
&&
546 x86_cpu_def
->vendor3
== CPUID_VENDOR_VIA_3
) {
547 host_cpuid(0xC0000000, 0, &eax
, &ebx
, &ecx
, &edx
);
548 if (eax
>= 0xC0000001) {
549 /* Support VIA max extended level */
550 x86_cpu_def
->xlevel2
= eax
;
551 host_cpuid(0xC0000001, 0, &eax
, &ebx
, &ecx
, &edx
);
552 x86_cpu_def
->ext4_features
= edx
;
557 * Every SVM feature requires emulation support in KVM - so we can't just
558 * read the host features here. KVM might even support SVM features not
559 * available on the host hardware. Just set all bits and mask out the
560 * unsupported ones later.
562 x86_cpu_def
->svm_features
= -1;
567 static int unavailable_host_feature(struct model_features_t
*f
, uint32_t mask
)
571 for (i
= 0; i
< 32; ++i
)
573 fprintf(stderr
, "warning: host cpuid %04x_%04x lacks requested"
574 " flag '%s' [0x%08x]\n",
575 f
->cpuid
>> 16, f
->cpuid
& 0xffff,
576 f
->flag_names
[i
] ? f
->flag_names
[i
] : "[reserved]", mask
);
582 /* best effort attempt to inform user requested cpu flags aren't making
583 * their way to the guest. Note: ft[].check_feat ideally should be
584 * specified via a guest_def field to suppress report of extraneous flags.
586 static int check_features_against_host(x86_def_t
*guest_def
)
591 struct model_features_t ft
[] = {
592 {&guest_def
->features
, &host_def
.features
,
593 ~0, feature_name
, 0x00000000},
594 {&guest_def
->ext_features
, &host_def
.ext_features
,
595 ~CPUID_EXT_HYPERVISOR
, ext_feature_name
, 0x00000001},
596 {&guest_def
->ext2_features
, &host_def
.ext2_features
,
597 ~PPRO_FEATURES
, ext2_feature_name
, 0x80000000},
598 {&guest_def
->ext3_features
, &host_def
.ext3_features
,
599 ~CPUID_EXT3_SVM
, ext3_feature_name
, 0x80000001}};
601 cpu_x86_fill_host(&host_def
);
602 for (rv
= 0, i
= 0; i
< ARRAY_SIZE(ft
); ++i
)
603 for (mask
= 1; mask
; mask
<<= 1)
604 if (ft
[i
].check_feat
& mask
&& *ft
[i
].guest_feat
& mask
&&
605 !(*ft
[i
].host_feat
& mask
)) {
606 unavailable_host_feature(&ft
[i
], mask
);
612 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
613 const char *name
, Error
**errp
)
615 X86CPU
*cpu
= X86_CPU(obj
);
616 CPUX86State
*env
= &cpu
->env
;
619 value
= (env
->cpuid_version
>> 8) & 0xf;
621 value
+= (env
->cpuid_version
>> 20) & 0xff;
623 visit_type_int(v
, &value
, name
, errp
);
626 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
627 const char *name
, Error
**errp
)
629 X86CPU
*cpu
= X86_CPU(obj
);
630 CPUX86State
*env
= &cpu
->env
;
631 const int64_t min
= 0;
632 const int64_t max
= 0xff + 0xf;
635 visit_type_int(v
, &value
, name
, errp
);
636 if (error_is_set(errp
)) {
639 if (value
< min
|| value
> max
) {
640 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
641 name
? name
: "null", value
, min
, max
);
645 env
->cpuid_version
&= ~0xff00f00;
647 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
649 env
->cpuid_version
|= value
<< 8;
653 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
654 const char *name
, Error
**errp
)
656 X86CPU
*cpu
= X86_CPU(obj
);
657 CPUX86State
*env
= &cpu
->env
;
660 value
= (env
->cpuid_version
>> 4) & 0xf;
661 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
662 visit_type_int(v
, &value
, name
, errp
);
665 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
666 const char *name
, Error
**errp
)
668 X86CPU
*cpu
= X86_CPU(obj
);
669 CPUX86State
*env
= &cpu
->env
;
670 const int64_t min
= 0;
671 const int64_t max
= 0xff;
674 visit_type_int(v
, &value
, name
, errp
);
675 if (error_is_set(errp
)) {
678 if (value
< min
|| value
> max
) {
679 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
680 name
? name
: "null", value
, min
, max
);
684 env
->cpuid_version
&= ~0xf00f0;
685 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
688 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
689 void *opaque
, const char *name
,
692 X86CPU
*cpu
= X86_CPU(obj
);
693 CPUX86State
*env
= &cpu
->env
;
696 value
= env
->cpuid_version
& 0xf;
697 visit_type_int(v
, &value
, name
, errp
);
700 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
701 void *opaque
, const char *name
,
704 X86CPU
*cpu
= X86_CPU(obj
);
705 CPUX86State
*env
= &cpu
->env
;
706 const int64_t min
= 0;
707 const int64_t max
= 0xf;
710 visit_type_int(v
, &value
, name
, errp
);
711 if (error_is_set(errp
)) {
714 if (value
< min
|| value
> max
) {
715 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
716 name
? name
: "null", value
, min
, max
);
720 env
->cpuid_version
&= ~0xf;
721 env
->cpuid_version
|= value
& 0xf;
724 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
725 const char *name
, Error
**errp
)
727 X86CPU
*cpu
= X86_CPU(obj
);
729 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
732 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
733 const char *name
, Error
**errp
)
735 X86CPU
*cpu
= X86_CPU(obj
);
737 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
740 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
741 const char *name
, Error
**errp
)
743 X86CPU
*cpu
= X86_CPU(obj
);
745 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
748 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
749 const char *name
, Error
**errp
)
751 X86CPU
*cpu
= X86_CPU(obj
);
753 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
756 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
758 X86CPU
*cpu
= X86_CPU(obj
);
759 CPUX86State
*env
= &cpu
->env
;
763 value
= (char *)g_malloc(12 + 1);
764 for (i
= 0; i
< 4; i
++) {
765 value
[i
] = env
->cpuid_vendor1
>> (8 * i
);
766 value
[i
+ 4] = env
->cpuid_vendor2
>> (8 * i
);
767 value
[i
+ 8] = env
->cpuid_vendor3
>> (8 * i
);
773 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
776 X86CPU
*cpu
= X86_CPU(obj
);
777 CPUX86State
*env
= &cpu
->env
;
780 if (strlen(value
) != 12) {
781 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
786 env
->cpuid_vendor1
= 0;
787 env
->cpuid_vendor2
= 0;
788 env
->cpuid_vendor3
= 0;
789 for (i
= 0; i
< 4; i
++) {
790 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
791 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
792 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
794 env
->cpuid_vendor_override
= 1;
797 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
799 X86CPU
*cpu
= X86_CPU(obj
);
800 CPUX86State
*env
= &cpu
->env
;
804 value
= g_malloc(48 + 1);
805 for (i
= 0; i
< 48; i
++) {
806 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
812 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
815 X86CPU
*cpu
= X86_CPU(obj
);
816 CPUX86State
*env
= &cpu
->env
;
819 if (model_id
== NULL
) {
822 len
= strlen(model_id
);
823 memset(env
->cpuid_model
, 0, 48);
824 for (i
= 0; i
< 48; i
++) {
828 c
= (uint8_t)model_id
[i
];
830 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
834 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
835 const char *name
, Error
**errp
)
837 X86CPU
*cpu
= X86_CPU(obj
);
840 value
= cpu
->env
.tsc_khz
* 1000;
841 visit_type_int(v
, &value
, name
, errp
);
844 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
845 const char *name
, Error
**errp
)
847 X86CPU
*cpu
= X86_CPU(obj
);
848 const int64_t min
= 0;
849 const int64_t max
= INT64_MAX
;
852 visit_type_int(v
, &value
, name
, errp
);
853 if (error_is_set(errp
)) {
856 if (value
< min
|| value
> max
) {
857 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
858 name
? name
: "null", value
, min
, max
);
862 cpu
->env
.tsc_khz
= value
/ 1000;
865 static int cpu_x86_find_by_name(x86_def_t
*x86_cpu_def
, const char *cpu_model
)
870 char *s
= g_strdup(cpu_model
);
871 char *featurestr
, *name
= strtok(s
, ",");
872 /* Features to be added*/
873 uint32_t plus_features
= 0, plus_ext_features
= 0;
874 uint32_t plus_ext2_features
= 0, plus_ext3_features
= 0;
875 uint32_t plus_kvm_features
= 0, plus_svm_features
= 0;
876 /* Features to be removed */
877 uint32_t minus_features
= 0, minus_ext_features
= 0;
878 uint32_t minus_ext2_features
= 0, minus_ext3_features
= 0;
879 uint32_t minus_kvm_features
= 0, minus_svm_features
= 0;
882 for (def
= x86_defs
; def
; def
= def
->next
)
883 if (name
&& !strcmp(name
, def
->name
))
885 if (kvm_enabled() && name
&& strcmp(name
, "host") == 0) {
886 cpu_x86_fill_host(x86_cpu_def
);
890 memcpy(x86_cpu_def
, def
, sizeof(*def
));
893 #if defined(CONFIG_KVM)
894 plus_kvm_features
= (1 << KVM_FEATURE_CLOCKSOURCE
) |
895 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
896 (1 << KVM_FEATURE_MMU_OP
) |
897 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
898 (1 << KVM_FEATURE_ASYNC_PF
) |
899 (1 << KVM_FEATURE_STEAL_TIME
) |
900 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
);
902 plus_kvm_features
= 0;
905 add_flagname_to_bitmaps("hypervisor", &plus_features
,
906 &plus_ext_features
, &plus_ext2_features
, &plus_ext3_features
,
907 &plus_kvm_features
, &plus_svm_features
);
909 featurestr
= strtok(NULL
, ",");
913 if (featurestr
[0] == '+') {
914 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
,
915 &plus_ext_features
, &plus_ext2_features
,
916 &plus_ext3_features
, &plus_kvm_features
,
918 } else if (featurestr
[0] == '-') {
919 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
,
920 &minus_ext_features
, &minus_ext2_features
,
921 &minus_ext3_features
, &minus_kvm_features
,
922 &minus_svm_features
);
923 } else if ((val
= strchr(featurestr
, '='))) {
925 if (!strcmp(featurestr
, "family")) {
927 numvalue
= strtoul(val
, &err
, 0);
928 if (!*val
|| *err
|| numvalue
> 0xff + 0xf) {
929 fprintf(stderr
, "bad numerical value %s\n", val
);
932 x86_cpu_def
->family
= numvalue
;
933 } else if (!strcmp(featurestr
, "model")) {
935 numvalue
= strtoul(val
, &err
, 0);
936 if (!*val
|| *err
|| numvalue
> 0xff) {
937 fprintf(stderr
, "bad numerical value %s\n", val
);
940 x86_cpu_def
->model
= numvalue
;
941 } else if (!strcmp(featurestr
, "stepping")) {
943 numvalue
= strtoul(val
, &err
, 0);
944 if (!*val
|| *err
|| numvalue
> 0xf) {
945 fprintf(stderr
, "bad numerical value %s\n", val
);
948 x86_cpu_def
->stepping
= numvalue
;
949 } else if (!strcmp(featurestr
, "level")) {
951 numvalue
= strtoul(val
, &err
, 0);
953 fprintf(stderr
, "bad numerical value %s\n", val
);
956 x86_cpu_def
->level
= numvalue
;
957 } else if (!strcmp(featurestr
, "xlevel")) {
959 numvalue
= strtoul(val
, &err
, 0);
961 fprintf(stderr
, "bad numerical value %s\n", val
);
964 if (numvalue
< 0x80000000) {
965 numvalue
+= 0x80000000;
967 x86_cpu_def
->xlevel
= numvalue
;
968 } else if (!strcmp(featurestr
, "vendor")) {
969 if (strlen(val
) != 12) {
970 fprintf(stderr
, "vendor string must be 12 chars long\n");
973 x86_cpu_def
->vendor1
= 0;
974 x86_cpu_def
->vendor2
= 0;
975 x86_cpu_def
->vendor3
= 0;
976 for(i
= 0; i
< 4; i
++) {
977 x86_cpu_def
->vendor1
|= ((uint8_t)val
[i
]) << (8 * i
);
978 x86_cpu_def
->vendor2
|= ((uint8_t)val
[i
+ 4]) << (8 * i
);
979 x86_cpu_def
->vendor3
|= ((uint8_t)val
[i
+ 8]) << (8 * i
);
981 x86_cpu_def
->vendor_override
= 1;
982 } else if (!strcmp(featurestr
, "model_id")) {
983 pstrcpy(x86_cpu_def
->model_id
, sizeof(x86_cpu_def
->model_id
),
985 } else if (!strcmp(featurestr
, "tsc_freq")) {
989 tsc_freq
= strtosz_suffix_unit(val
, &err
,
990 STRTOSZ_DEFSUFFIX_B
, 1000);
991 if (tsc_freq
< 0 || *err
) {
992 fprintf(stderr
, "bad numerical value %s\n", val
);
995 x86_cpu_def
->tsc_khz
= tsc_freq
/ 1000;
996 } else if (!strcmp(featurestr
, "hv_spinlocks")) {
998 numvalue
= strtoul(val
, &err
, 0);
1000 fprintf(stderr
, "bad numerical value %s\n", val
);
1003 hyperv_set_spinlock_retries(numvalue
);
1005 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
1008 } else if (!strcmp(featurestr
, "check")) {
1010 } else if (!strcmp(featurestr
, "enforce")) {
1011 check_cpuid
= enforce_cpuid
= 1;
1012 } else if (!strcmp(featurestr
, "hv_relaxed")) {
1013 hyperv_enable_relaxed_timing(true);
1014 } else if (!strcmp(featurestr
, "hv_vapic")) {
1015 hyperv_enable_vapic_recommended(true);
1017 fprintf(stderr
, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr
);
1020 featurestr
= strtok(NULL
, ",");
1022 x86_cpu_def
->features
|= plus_features
;
1023 x86_cpu_def
->ext_features
|= plus_ext_features
;
1024 x86_cpu_def
->ext2_features
|= plus_ext2_features
;
1025 x86_cpu_def
->ext3_features
|= plus_ext3_features
;
1026 x86_cpu_def
->kvm_features
|= plus_kvm_features
;
1027 x86_cpu_def
->svm_features
|= plus_svm_features
;
1028 x86_cpu_def
->features
&= ~minus_features
;
1029 x86_cpu_def
->ext_features
&= ~minus_ext_features
;
1030 x86_cpu_def
->ext2_features
&= ~minus_ext2_features
;
1031 x86_cpu_def
->ext3_features
&= ~minus_ext3_features
;
1032 x86_cpu_def
->kvm_features
&= ~minus_kvm_features
;
1033 x86_cpu_def
->svm_features
&= ~minus_svm_features
;
1035 if (check_features_against_host(x86_cpu_def
) && enforce_cpuid
)
1046 /* generate a composite string into buf of all cpuid names in featureset
1047 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1048 * if flags, suppress names undefined in featureset.
1050 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1051 const char **featureset
, uint32_t flags
)
1053 const char **p
= &featureset
[31];
1057 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1059 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1060 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1062 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1064 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1065 if (bufsize
<= nc
) {
1067 memcpy(b
, "...", sizeof("..."));
1076 /* generate CPU information:
1077 * -? list model names
1078 * -?model list model names/IDs
1079 * -?dump output all model (x86_def_t) data
1080 * -?cpuid list all recognized cpuid flag names
1082 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
, const char *optarg
)
1084 unsigned char model
= !strcmp("?model", optarg
);
1085 unsigned char dump
= !strcmp("?dump", optarg
);
1086 unsigned char cpuid
= !strcmp("?cpuid", optarg
);
1091 (*cpu_fprintf
)(f
, "Recognized CPUID flags:\n");
1092 listflags(buf
, sizeof (buf
), (uint32_t)~0, feature_name
, 1);
1093 (*cpu_fprintf
)(f
, " f_edx: %s\n", buf
);
1094 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext_feature_name
, 1);
1095 (*cpu_fprintf
)(f
, " f_ecx: %s\n", buf
);
1096 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext2_feature_name
, 1);
1097 (*cpu_fprintf
)(f
, " extf_edx: %s\n", buf
);
1098 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext3_feature_name
, 1);
1099 (*cpu_fprintf
)(f
, " extf_ecx: %s\n", buf
);
1102 for (def
= x86_defs
; def
; def
= def
->next
) {
1103 snprintf(buf
, sizeof (buf
), def
->flags
? "[%s]": "%s", def
->name
);
1104 if (model
|| dump
) {
1105 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1107 (*cpu_fprintf
)(f
, "x86 %16s\n", buf
);
1110 memcpy(buf
, &def
->vendor1
, sizeof (def
->vendor1
));
1111 memcpy(buf
+ 4, &def
->vendor2
, sizeof (def
->vendor2
));
1112 memcpy(buf
+ 8, &def
->vendor3
, sizeof (def
->vendor3
));
1115 " family %d model %d stepping %d level %d xlevel 0x%x"
1117 def
->family
, def
->model
, def
->stepping
, def
->level
,
1119 listflags(buf
, sizeof (buf
), def
->features
, feature_name
, 0);
1120 (*cpu_fprintf
)(f
, " feature_edx %08x (%s)\n", def
->features
,
1122 listflags(buf
, sizeof (buf
), def
->ext_features
, ext_feature_name
,
1124 (*cpu_fprintf
)(f
, " feature_ecx %08x (%s)\n", def
->ext_features
,
1126 listflags(buf
, sizeof (buf
), def
->ext2_features
, ext2_feature_name
,
1128 (*cpu_fprintf
)(f
, " extfeature_edx %08x (%s)\n",
1129 def
->ext2_features
, buf
);
1130 listflags(buf
, sizeof (buf
), def
->ext3_features
, ext3_feature_name
,
1132 (*cpu_fprintf
)(f
, " extfeature_ecx %08x (%s)\n",
1133 def
->ext3_features
, buf
);
1134 (*cpu_fprintf
)(f
, "\n");
1137 if (kvm_enabled()) {
1138 (*cpu_fprintf
)(f
, "x86 %16s\n", "[host]");
1142 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1144 CpuDefinitionInfoList
*cpu_list
= NULL
;
1147 for (def
= x86_defs
; def
; def
= def
->next
) {
1148 CpuDefinitionInfoList
*entry
;
1149 CpuDefinitionInfo
*info
;
1151 info
= g_malloc0(sizeof(*info
));
1152 info
->name
= g_strdup(def
->name
);
1154 entry
= g_malloc0(sizeof(*entry
));
1155 entry
->value
= info
;
1156 entry
->next
= cpu_list
;
1163 int cpu_x86_register(X86CPU
*cpu
, const char *cpu_model
)
1165 CPUX86State
*env
= &cpu
->env
;
1166 x86_def_t def1
, *def
= &def1
;
1167 Error
*error
= NULL
;
1169 memset(def
, 0, sizeof(*def
));
1171 if (cpu_x86_find_by_name(def
, cpu_model
) < 0)
1174 env
->cpuid_vendor1
= def
->vendor1
;
1175 env
->cpuid_vendor2
= def
->vendor2
;
1176 env
->cpuid_vendor3
= def
->vendor3
;
1178 env
->cpuid_vendor1
= CPUID_VENDOR_INTEL_1
;
1179 env
->cpuid_vendor2
= CPUID_VENDOR_INTEL_2
;
1180 env
->cpuid_vendor3
= CPUID_VENDOR_INTEL_3
;
1182 env
->cpuid_vendor_override
= def
->vendor_override
;
1183 object_property_set_int(OBJECT(cpu
), def
->level
, "level", &error
);
1184 object_property_set_int(OBJECT(cpu
), def
->family
, "family", &error
);
1185 object_property_set_int(OBJECT(cpu
), def
->model
, "model", &error
);
1186 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", &error
);
1187 env
->cpuid_features
= def
->features
;
1188 env
->cpuid_ext_features
= def
->ext_features
;
1189 env
->cpuid_ext2_features
= def
->ext2_features
;
1190 env
->cpuid_ext3_features
= def
->ext3_features
;
1191 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", &error
);
1192 env
->cpuid_kvm_features
= def
->kvm_features
;
1193 env
->cpuid_svm_features
= def
->svm_features
;
1194 env
->cpuid_ext4_features
= def
->ext4_features
;
1195 env
->cpuid_7_0_ebx
= def
->cpuid_7_0_ebx_features
;
1196 env
->cpuid_xlevel2
= def
->xlevel2
;
1197 object_property_set_int(OBJECT(cpu
), (int64_t)def
->tsc_khz
* 1000,
1198 "tsc-frequency", &error
);
1199 if (!kvm_enabled()) {
1200 env
->cpuid_features
&= TCG_FEATURES
;
1201 env
->cpuid_ext_features
&= TCG_EXT_FEATURES
;
1202 env
->cpuid_ext2_features
&= (TCG_EXT2_FEATURES
1203 #ifdef TARGET_X86_64
1204 | CPUID_EXT2_SYSCALL
| CPUID_EXT2_LM
1207 env
->cpuid_ext3_features
&= TCG_EXT3_FEATURES
;
1208 env
->cpuid_svm_features
&= TCG_SVM_FEATURES
;
1210 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", &error
);
1211 if (error_is_set(&error
)) {
1218 #if !defined(CONFIG_USER_ONLY)
1219 /* copy vendor id string to 32 bit register, nul pad as needed
1221 static void cpyid(const char *s
, uint32_t *id
)
1223 char *d
= (char *)id
;
1226 for (i
= sizeof (*id
); i
--; )
1227 *d
++ = *s
? *s
++ : '\0';
1230 /* interpret radix and convert from string to arbitrary scalar,
1231 * otherwise flag failure
1233 #define setscalar(pval, str, perr) \
1238 ul = strtoul(str, &pend, 0); \
1239 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1242 /* map cpuid options to feature bits, otherwise return failure
1243 * (option tags in *str are delimited by whitespace)
1245 static void setfeatures(uint32_t *pval
, const char *str
,
1246 const char **featureset
, int *perr
)
1250 for (q
= p
= str
; *p
|| *q
; q
= p
) {
1253 while (*p
&& !iswhite(*p
))
1257 if (!lookup_feature(pval
, q
, p
, featureset
)) {
1258 fprintf(stderr
, "error: feature \"%.*s\" not available in set\n",
1266 /* map config file options to x86_def_t form
1268 static int cpudef_setfield(const char *name
, const char *str
, void *opaque
)
1270 x86_def_t
*def
= opaque
;
1273 if (!strcmp(name
, "name")) {
1274 g_free((void *)def
->name
);
1275 def
->name
= g_strdup(str
);
1276 } else if (!strcmp(name
, "model_id")) {
1277 strncpy(def
->model_id
, str
, sizeof (def
->model_id
));
1278 } else if (!strcmp(name
, "level")) {
1279 setscalar(&def
->level
, str
, &err
)
1280 } else if (!strcmp(name
, "vendor")) {
1281 cpyid(&str
[0], &def
->vendor1
);
1282 cpyid(&str
[4], &def
->vendor2
);
1283 cpyid(&str
[8], &def
->vendor3
);
1284 } else if (!strcmp(name
, "family")) {
1285 setscalar(&def
->family
, str
, &err
)
1286 } else if (!strcmp(name
, "model")) {
1287 setscalar(&def
->model
, str
, &err
)
1288 } else if (!strcmp(name
, "stepping")) {
1289 setscalar(&def
->stepping
, str
, &err
)
1290 } else if (!strcmp(name
, "feature_edx")) {
1291 setfeatures(&def
->features
, str
, feature_name
, &err
);
1292 } else if (!strcmp(name
, "feature_ecx")) {
1293 setfeatures(&def
->ext_features
, str
, ext_feature_name
, &err
);
1294 } else if (!strcmp(name
, "extfeature_edx")) {
1295 setfeatures(&def
->ext2_features
, str
, ext2_feature_name
, &err
);
1296 } else if (!strcmp(name
, "extfeature_ecx")) {
1297 setfeatures(&def
->ext3_features
, str
, ext3_feature_name
, &err
);
1298 } else if (!strcmp(name
, "xlevel")) {
1299 setscalar(&def
->xlevel
, str
, &err
)
1301 fprintf(stderr
, "error: unknown option [%s = %s]\n", name
, str
);
1305 fprintf(stderr
, "error: bad option value [%s = %s]\n", name
, str
);
1311 /* register config file entry as x86_def_t
1313 static int cpudef_register(QemuOpts
*opts
, void *opaque
)
1315 x86_def_t
*def
= g_malloc0(sizeof (x86_def_t
));
1317 qemu_opt_foreach(opts
, cpudef_setfield
, def
, 1);
1318 def
->next
= x86_defs
;
1323 void cpu_clear_apic_feature(CPUX86State
*env
)
1325 env
->cpuid_features
&= ~CPUID_APIC
;
1328 #endif /* !CONFIG_USER_ONLY */
1330 /* register "cpudef" models defined in configuration file. Here we first
1331 * preload any built-in definitions
1333 void x86_cpudef_setup(void)
1336 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
1338 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
1339 builtin_x86_defs
[i
].next
= x86_defs
;
1340 builtin_x86_defs
[i
].flags
= 1;
1342 /* Look for specific "cpudef" models that */
1343 /* have the QEMU version in .model_id */
1344 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
1345 if (strcmp(model_with_versions
[j
], builtin_x86_defs
[i
].name
) == 0) {
1346 pstrcpy(builtin_x86_defs
[i
].model_id
, sizeof(builtin_x86_defs
[i
].model_id
), "QEMU Virtual CPU version ");
1347 pstrcat(builtin_x86_defs
[i
].model_id
, sizeof(builtin_x86_defs
[i
].model_id
), qemu_get_version());
1352 x86_defs
= &builtin_x86_defs
[i
];
1354 #if !defined(CONFIG_USER_ONLY)
1355 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register
, NULL
, 0);
1359 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
1360 uint32_t *ecx
, uint32_t *edx
)
1362 *ebx
= env
->cpuid_vendor1
;
1363 *edx
= env
->cpuid_vendor2
;
1364 *ecx
= env
->cpuid_vendor3
;
1366 /* sysenter isn't supported on compatibility mode on AMD, syscall
1367 * isn't supported in compatibility mode on Intel.
1368 * Normally we advertise the actual cpu vendor, but you can override
1369 * this if you want to use KVM's sysenter/syscall emulation
1370 * in compatibility mode and when doing cross vendor migration
1372 if (kvm_enabled() && ! env
->cpuid_vendor_override
) {
1373 host_cpuid(0, 0, NULL
, ebx
, ecx
, edx
);
1377 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
1378 uint32_t *eax
, uint32_t *ebx
,
1379 uint32_t *ecx
, uint32_t *edx
)
1381 /* test if maximum index reached */
1382 if (index
& 0x80000000) {
1383 if (index
> env
->cpuid_xlevel
) {
1384 if (env
->cpuid_xlevel2
> 0) {
1385 /* Handle the Centaur's CPUID instruction. */
1386 if (index
> env
->cpuid_xlevel2
) {
1387 index
= env
->cpuid_xlevel2
;
1388 } else if (index
< 0xC0000000) {
1389 index
= env
->cpuid_xlevel
;
1392 index
= env
->cpuid_xlevel
;
1396 if (index
> env
->cpuid_level
)
1397 index
= env
->cpuid_level
;
1402 *eax
= env
->cpuid_level
;
1403 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
1406 *eax
= env
->cpuid_version
;
1407 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1408 *ecx
= env
->cpuid_ext_features
;
1409 *edx
= env
->cpuid_features
;
1410 if (env
->nr_cores
* env
->nr_threads
> 1) {
1411 *ebx
|= (env
->nr_cores
* env
->nr_threads
) << 16;
1412 *edx
|= 1 << 28; /* HTT bit */
1416 /* cache info: needed for Pentium Pro compatibility */
1423 /* cache info: needed for Core compatibility */
1424 if (env
->nr_cores
> 1) {
1425 *eax
= (env
->nr_cores
- 1) << 26;
1430 case 0: /* L1 dcache info */
1436 case 1: /* L1 icache info */
1442 case 2: /* L2 cache info */
1444 if (env
->nr_threads
> 1) {
1445 *eax
|= (env
->nr_threads
- 1) << 14;
1451 default: /* end of info */
1460 /* mwait info: needed for Core compatibility */
1461 *eax
= 0; /* Smallest monitor-line size in bytes */
1462 *ebx
= 0; /* Largest monitor-line size in bytes */
1463 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
1467 /* Thermal and Power Leaf */
1474 /* Structured Extended Feature Flags Enumeration Leaf */
1476 *eax
= 0; /* Maximum ECX value for sub-leaves */
1477 *ebx
= env
->cpuid_7_0_ebx
; /* Feature flags */
1478 *ecx
= 0; /* Reserved */
1479 *edx
= 0; /* Reserved */
1488 /* Direct Cache Access Information Leaf */
1489 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
1495 /* Architectural Performance Monitoring Leaf */
1496 if (kvm_enabled()) {
1497 KVMState
*s
= env
->kvm_state
;
1499 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
1500 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
1501 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
1502 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
1511 /* Processor Extended State */
1512 if (!(env
->cpuid_ext_features
& CPUID_EXT_XSAVE
)) {
1519 if (kvm_enabled()) {
1520 KVMState
*s
= env
->kvm_state
;
1522 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EAX
);
1523 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EBX
);
1524 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_ECX
);
1525 *edx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EDX
);
1534 *eax
= env
->cpuid_xlevel
;
1535 *ebx
= env
->cpuid_vendor1
;
1536 *edx
= env
->cpuid_vendor2
;
1537 *ecx
= env
->cpuid_vendor3
;
1540 *eax
= env
->cpuid_version
;
1542 *ecx
= env
->cpuid_ext3_features
;
1543 *edx
= env
->cpuid_ext2_features
;
1545 /* The Linux kernel checks for the CMPLegacy bit and
1546 * discards multiple thread information if it is set.
1547 * So dont set it here for Intel to make Linux guests happy.
1549 if (env
->nr_cores
* env
->nr_threads
> 1) {
1550 uint32_t tebx
, tecx
, tedx
;
1551 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
1552 if (tebx
!= CPUID_VENDOR_INTEL_1
||
1553 tedx
!= CPUID_VENDOR_INTEL_2
||
1554 tecx
!= CPUID_VENDOR_INTEL_3
) {
1555 *ecx
|= 1 << 1; /* CmpLegacy bit */
1562 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
1563 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
1564 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
1565 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
1568 /* cache info (L1 cache) */
1575 /* cache info (L2 cache) */
1582 /* virtual & phys address size in low 2 bytes. */
1583 /* XXX: This value must match the one used in the MMU code. */
1584 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
) {
1585 /* 64 bit processor */
1586 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1587 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
1589 if (env
->cpuid_features
& CPUID_PSE36
)
1590 *eax
= 0x00000024; /* 36 bits physical */
1592 *eax
= 0x00000020; /* 32 bits physical */
1597 if (env
->nr_cores
* env
->nr_threads
> 1) {
1598 *ecx
|= (env
->nr_cores
* env
->nr_threads
) - 1;
1602 if (env
->cpuid_ext3_features
& CPUID_EXT3_SVM
) {
1603 *eax
= 0x00000001; /* SVM Revision */
1604 *ebx
= 0x00000010; /* nr of ASIDs */
1606 *edx
= env
->cpuid_svm_features
; /* optional features */
1615 *eax
= env
->cpuid_xlevel2
;
1621 /* Support for VIA CPU's CPUID instruction */
1622 *eax
= env
->cpuid_version
;
1625 *edx
= env
->cpuid_ext4_features
;
1630 /* Reserved for the future, and now filled with zero */
1637 /* reserved values: zero */
1646 /* CPUClass::reset() */
1647 static void x86_cpu_reset(CPUState
*s
)
1649 X86CPU
*cpu
= X86_CPU(s
);
1650 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
1651 CPUX86State
*env
= &cpu
->env
;
1654 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1655 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1656 log_cpu_state(env
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
1659 xcc
->parent_reset(s
);
1662 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
1666 env
->old_exception
= -1;
1668 /* init to reset state */
1670 #ifdef CONFIG_SOFTMMU
1671 env
->hflags
|= HF_SOFTMMU_MASK
;
1673 env
->hflags2
|= HF2_GIF_MASK
;
1675 cpu_x86_update_cr0(env
, 0x60000010);
1676 env
->a20_mask
= ~0x0;
1677 env
->smbase
= 0x30000;
1679 env
->idt
.limit
= 0xffff;
1680 env
->gdt
.limit
= 0xffff;
1681 env
->ldt
.limit
= 0xffff;
1682 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
1683 env
->tr
.limit
= 0xffff;
1684 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
1686 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
1687 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
1688 DESC_R_MASK
| DESC_A_MASK
);
1689 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
1690 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1692 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
1693 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1695 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
1696 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1698 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
1699 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1701 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
1702 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1706 env
->regs
[R_EDX
] = env
->cpuid_version
;
1711 for (i
= 0; i
< 8; i
++) {
1716 env
->mxcsr
= 0x1f80;
1718 env
->pat
= 0x0007040600070406ULL
;
1719 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
1721 memset(env
->dr
, 0, sizeof(env
->dr
));
1722 env
->dr
[6] = DR6_FIXED_1
;
1723 env
->dr
[7] = DR7_FIXED_1
;
1724 cpu_breakpoint_remove_all(env
, BP_CPU
);
1725 cpu_watchpoint_remove_all(env
, BP_CPU
);
1727 #if !defined(CONFIG_USER_ONLY)
1728 /* We hard-wire the BSP to the first CPU. */
1729 if (env
->cpu_index
== 0) {
1730 apic_designate_bsp(env
->apic_state
);
1733 env
->halted
= !cpu_is_bsp(cpu
);
1737 #ifndef CONFIG_USER_ONLY
1738 bool cpu_is_bsp(X86CPU
*cpu
)
1740 return cpu_get_apic_base(cpu
->env
.apic_state
) & MSR_IA32_APICBASE_BSP
;
1743 /* TODO: remove me, when reset over QOM tree is implemented */
1744 static void x86_cpu_machine_reset_cb(void *opaque
)
1746 X86CPU
*cpu
= opaque
;
1747 cpu_reset(CPU(cpu
));
1751 static void mce_init(X86CPU
*cpu
)
1753 CPUX86State
*cenv
= &cpu
->env
;
1756 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
1757 && (cenv
->cpuid_features
& (CPUID_MCE
| CPUID_MCA
)) ==
1758 (CPUID_MCE
| CPUID_MCA
)) {
1759 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
1760 cenv
->mcg_ctl
= ~(uint64_t)0;
1761 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
1762 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
1767 void x86_cpu_realize(Object
*obj
, Error
**errp
)
1769 X86CPU
*cpu
= X86_CPU(obj
);
1771 #ifndef CONFIG_USER_ONLY
1772 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
1776 qemu_init_vcpu(&cpu
->env
);
1777 cpu_reset(CPU(cpu
));
1780 static void x86_cpu_initfn(Object
*obj
)
1782 X86CPU
*cpu
= X86_CPU(obj
);
1783 CPUX86State
*env
= &cpu
->env
;
1788 object_property_add(obj
, "family", "int",
1789 x86_cpuid_version_get_family
,
1790 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
1791 object_property_add(obj
, "model", "int",
1792 x86_cpuid_version_get_model
,
1793 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
1794 object_property_add(obj
, "stepping", "int",
1795 x86_cpuid_version_get_stepping
,
1796 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
1797 object_property_add(obj
, "level", "int",
1798 x86_cpuid_get_level
,
1799 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
1800 object_property_add(obj
, "xlevel", "int",
1801 x86_cpuid_get_xlevel
,
1802 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
1803 object_property_add_str(obj
, "vendor",
1804 x86_cpuid_get_vendor
,
1805 x86_cpuid_set_vendor
, NULL
);
1806 object_property_add_str(obj
, "model-id",
1807 x86_cpuid_get_model_id
,
1808 x86_cpuid_set_model_id
, NULL
);
1809 object_property_add(obj
, "tsc-frequency", "int",
1810 x86_cpuid_get_tsc_freq
,
1811 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
1813 env
->cpuid_apic_id
= env
->cpu_index
;
1815 /* init various static tables used in TCG mode */
1816 if (tcg_enabled() && !inited
) {
1818 optimize_flags_init();
1819 #ifndef CONFIG_USER_ONLY
1820 cpu_set_debug_excp_handler(breakpoint_handler
);
1825 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
1827 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1828 CPUClass
*cc
= CPU_CLASS(oc
);
1830 xcc
->parent_reset
= cc
->reset
;
1831 cc
->reset
= x86_cpu_reset
;
1834 static const TypeInfo x86_cpu_type_info
= {
1835 .name
= TYPE_X86_CPU
,
1837 .instance_size
= sizeof(X86CPU
),
1838 .instance_init
= x86_cpu_initfn
,
1840 .class_size
= sizeof(X86CPUClass
),
1841 .class_init
= x86_cpu_common_class_init
,
1844 static void x86_cpu_register_types(void)
1846 type_register_static(&x86_cpu_type_info
);
1849 type_init(x86_cpu_register_types
)