]> git.proxmox.com Git - mirror_qemu.git/blob - target-i386/cpu.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-i386/cpu: Add new Opteron CPU model
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "kvm.h"
26
27 #include "qemu-option.h"
28 #include "qemu-config.h"
29
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
32
33 #include "hyperv.h"
34
35 #include "hw/hw.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
38 #endif
39
40 #include "sysemu.h"
41 #ifndef CONFIG_USER_ONLY
42 #include "hw/xen.h"
43 #include "hw/sysbus.h"
44 #include "hw/apic_internal.h"
45 #endif
46
47 /* feature flags taken from "Intel Processor Identification and the CPUID
48 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
49 * between feature naming conventions, aliases may be added.
50 */
51 static const char *feature_name[] = {
52 "fpu", "vme", "de", "pse",
53 "tsc", "msr", "pae", "mce",
54 "cx8", "apic", NULL, "sep",
55 "mtrr", "pge", "mca", "cmov",
56 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
57 NULL, "ds" /* Intel dts */, "acpi", "mmx",
58 "fxsr", "sse", "sse2", "ss",
59 "ht" /* Intel htt */, "tm", "ia64", "pbe",
60 };
61 static const char *ext_feature_name[] = {
62 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
63 "ds_cpl", "vmx", "smx", "est",
64 "tm2", "ssse3", "cid", NULL,
65 "fma", "cx16", "xtpr", "pdcm",
66 NULL, "pcid", "dca", "sse4.1|sse4_1",
67 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
68 "tsc-deadline", "aes", "xsave", "osxsave",
69 "avx", "f16c", "rdrand", "hypervisor",
70 };
71 /* Feature names that are already defined on feature_name[] but are set on
72 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
73 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
74 * if and only if CPU vendor is AMD.
75 */
76 static const char *ext2_feature_name[] = {
77 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
78 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
79 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
80 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
81 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
82 "nx|xd", NULL, "mmxext", NULL /* mmx */,
83 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
84 NULL, "lm|i64", "3dnowext", "3dnow",
85 };
86 static const char *ext3_feature_name[] = {
87 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
88 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
89 "3dnowprefetch", "osvw", "ibs", "xop",
90 "skinit", "wdt", NULL, "lwp",
91 "fma4", "tce", NULL, "nodeid_msr",
92 NULL, "tbm", "topoext", "perfctr_core",
93 "perfctr_nb", NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95 };
96
97 static const char *kvm_feature_name[] = {
98 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
99 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
100 NULL, NULL, NULL, NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 };
107
108 static const char *svm_feature_name[] = {
109 "npt", "lbrv", "svm_lock", "nrip_save",
110 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
111 NULL, NULL, "pause_filter", NULL,
112 "pfthreshold", NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 };
118
119 static const char *cpuid_7_0_ebx_feature_name[] = {
120 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
121 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
122 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
123 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
124 };
125
126 /* collects per-function cpuid data
127 */
128 typedef struct model_features_t {
129 uint32_t *guest_feat;
130 uint32_t *host_feat;
131 uint32_t check_feat;
132 const char **flag_names;
133 uint32_t cpuid;
134 } model_features_t;
135
136 int check_cpuid = 0;
137 int enforce_cpuid = 0;
138
139 #if defined(CONFIG_KVM)
140 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
141 (1 << KVM_FEATURE_NOP_IO_DELAY) |
142 (1 << KVM_FEATURE_MMU_OP) |
143 (1 << KVM_FEATURE_CLOCKSOURCE2) |
144 (1 << KVM_FEATURE_ASYNC_PF) |
145 (1 << KVM_FEATURE_STEAL_TIME) |
146 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
147 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
148 #else
149 static uint32_t kvm_default_features = 0;
150 static const uint32_t kvm_pv_eoi_features = 0;
151 #endif
152
153 void enable_kvm_pv_eoi(void)
154 {
155 kvm_default_features |= kvm_pv_eoi_features;
156 }
157
158 void host_cpuid(uint32_t function, uint32_t count,
159 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
160 {
161 #if defined(CONFIG_KVM)
162 uint32_t vec[4];
163
164 #ifdef __x86_64__
165 asm volatile("cpuid"
166 : "=a"(vec[0]), "=b"(vec[1]),
167 "=c"(vec[2]), "=d"(vec[3])
168 : "0"(function), "c"(count) : "cc");
169 #else
170 asm volatile("pusha \n\t"
171 "cpuid \n\t"
172 "mov %%eax, 0(%2) \n\t"
173 "mov %%ebx, 4(%2) \n\t"
174 "mov %%ecx, 8(%2) \n\t"
175 "mov %%edx, 12(%2) \n\t"
176 "popa"
177 : : "a"(function), "c"(count), "S"(vec)
178 : "memory", "cc");
179 #endif
180
181 if (eax)
182 *eax = vec[0];
183 if (ebx)
184 *ebx = vec[1];
185 if (ecx)
186 *ecx = vec[2];
187 if (edx)
188 *edx = vec[3];
189 #endif
190 }
191
192 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
193
194 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
195 * a substring. ex if !NULL points to the first char after a substring,
196 * otherwise the string is assumed to sized by a terminating nul.
197 * Return lexical ordering of *s1:*s2.
198 */
199 static int sstrcmp(const char *s1, const char *e1, const char *s2,
200 const char *e2)
201 {
202 for (;;) {
203 if (!*s1 || !*s2 || *s1 != *s2)
204 return (*s1 - *s2);
205 ++s1, ++s2;
206 if (s1 == e1 && s2 == e2)
207 return (0);
208 else if (s1 == e1)
209 return (*s2);
210 else if (s2 == e2)
211 return (*s1);
212 }
213 }
214
215 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
216 * '|' delimited (possibly empty) strings in which case search for a match
217 * within the alternatives proceeds left to right. Return 0 for success,
218 * non-zero otherwise.
219 */
220 static int altcmp(const char *s, const char *e, const char *altstr)
221 {
222 const char *p, *q;
223
224 for (q = p = altstr; ; ) {
225 while (*p && *p != '|')
226 ++p;
227 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
228 return (0);
229 if (!*p)
230 return (1);
231 else
232 q = ++p;
233 }
234 }
235
236 /* search featureset for flag *[s..e), if found set corresponding bit in
237 * *pval and return true, otherwise return false
238 */
239 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
240 const char **featureset)
241 {
242 uint32_t mask;
243 const char **ppc;
244 bool found = false;
245
246 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
247 if (*ppc && !altcmp(s, e, *ppc)) {
248 *pval |= mask;
249 found = true;
250 }
251 }
252 return found;
253 }
254
255 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
256 uint32_t *ext_features,
257 uint32_t *ext2_features,
258 uint32_t *ext3_features,
259 uint32_t *kvm_features,
260 uint32_t *svm_features,
261 uint32_t *cpuid_7_0_ebx_features)
262 {
263 if (!lookup_feature(features, flagname, NULL, feature_name) &&
264 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
265 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
266 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
267 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
268 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
269 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
270 cpuid_7_0_ebx_feature_name))
271 fprintf(stderr, "CPU feature %s not found\n", flagname);
272 }
273
274 typedef struct x86_def_t {
275 struct x86_def_t *next;
276 const char *name;
277 uint32_t level;
278 uint32_t vendor1, vendor2, vendor3;
279 int family;
280 int model;
281 int stepping;
282 int tsc_khz;
283 uint32_t features, ext_features, ext2_features, ext3_features;
284 uint32_t kvm_features, svm_features;
285 uint32_t xlevel;
286 char model_id[48];
287 int vendor_override;
288 /* Store the results of Centaur's CPUID instructions */
289 uint32_t ext4_features;
290 uint32_t xlevel2;
291 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
292 uint32_t cpuid_7_0_ebx_features;
293 } x86_def_t;
294
295 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
296 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
297 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
298 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
299 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
300 CPUID_PSE36 | CPUID_FXSR)
301 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
302 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
303 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
304 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
305 CPUID_PAE | CPUID_SEP | CPUID_APIC)
306
307 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
308 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
309 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
310 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
311 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
312 /* partly implemented:
313 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
314 CPUID_PSE36 (needed for Solaris) */
315 /* missing:
316 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
317 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
318 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
319 CPUID_EXT_HYPERVISOR)
320 /* missing:
321 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
322 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
323 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
324 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
325 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
326 /* missing:
327 CPUID_EXT2_PDPE1GB */
328 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
329 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
330 #define TCG_SVM_FEATURES 0
331 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
332
333 /* maintains list of cpu model definitions
334 */
335 static x86_def_t *x86_defs = {NULL};
336
337 /* built-in cpu model definitions (deprecated)
338 */
339 static x86_def_t builtin_x86_defs[] = {
340 {
341 .name = "qemu64",
342 .level = 4,
343 .vendor1 = CPUID_VENDOR_AMD_1,
344 .vendor2 = CPUID_VENDOR_AMD_2,
345 .vendor3 = CPUID_VENDOR_AMD_3,
346 .family = 6,
347 .model = 2,
348 .stepping = 3,
349 .features = PPRO_FEATURES |
350 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
351 CPUID_PSE36,
352 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
353 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
354 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
355 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
356 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
357 .xlevel = 0x8000000A,
358 },
359 {
360 .name = "phenom",
361 .level = 5,
362 .vendor1 = CPUID_VENDOR_AMD_1,
363 .vendor2 = CPUID_VENDOR_AMD_2,
364 .vendor3 = CPUID_VENDOR_AMD_3,
365 .family = 16,
366 .model = 2,
367 .stepping = 3,
368 .features = PPRO_FEATURES |
369 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
370 CPUID_PSE36 | CPUID_VME | CPUID_HT,
371 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
372 CPUID_EXT_POPCNT,
373 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
374 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
375 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
376 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
377 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
378 CPUID_EXT3_CR8LEG,
379 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
380 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
381 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
382 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
383 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
384 .xlevel = 0x8000001A,
385 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
386 },
387 {
388 .name = "core2duo",
389 .level = 10,
390 .family = 6,
391 .model = 15,
392 .stepping = 11,
393 .features = PPRO_FEATURES |
394 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
395 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
396 CPUID_HT | CPUID_TM | CPUID_PBE,
397 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
398 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
399 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
400 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
401 .ext3_features = CPUID_EXT3_LAHF_LM,
402 .xlevel = 0x80000008,
403 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
404 },
405 {
406 .name = "kvm64",
407 .level = 5,
408 .vendor1 = CPUID_VENDOR_INTEL_1,
409 .vendor2 = CPUID_VENDOR_INTEL_2,
410 .vendor3 = CPUID_VENDOR_INTEL_3,
411 .family = 15,
412 .model = 6,
413 .stepping = 1,
414 /* Missing: CPUID_VME, CPUID_HT */
415 .features = PPRO_FEATURES |
416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
417 CPUID_PSE36,
418 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
420 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
421 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
422 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
423 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
424 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
425 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
426 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
427 .ext3_features = 0,
428 .xlevel = 0x80000008,
429 .model_id = "Common KVM processor"
430 },
431 {
432 .name = "qemu32",
433 .level = 4,
434 .family = 6,
435 .model = 3,
436 .stepping = 3,
437 .features = PPRO_FEATURES,
438 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
439 .xlevel = 0x80000004,
440 },
441 {
442 .name = "kvm32",
443 .level = 5,
444 .family = 15,
445 .model = 6,
446 .stepping = 1,
447 .features = PPRO_FEATURES |
448 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
449 .ext_features = CPUID_EXT_SSE3,
450 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
451 .ext3_features = 0,
452 .xlevel = 0x80000008,
453 .model_id = "Common 32-bit KVM processor"
454 },
455 {
456 .name = "coreduo",
457 .level = 10,
458 .family = 6,
459 .model = 14,
460 .stepping = 8,
461 .features = PPRO_FEATURES | CPUID_VME |
462 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
463 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
464 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
465 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
466 .ext2_features = CPUID_EXT2_NX,
467 .xlevel = 0x80000008,
468 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
469 },
470 {
471 .name = "486",
472 .level = 1,
473 .family = 4,
474 .model = 0,
475 .stepping = 0,
476 .features = I486_FEATURES,
477 .xlevel = 0,
478 },
479 {
480 .name = "pentium",
481 .level = 1,
482 .family = 5,
483 .model = 4,
484 .stepping = 3,
485 .features = PENTIUM_FEATURES,
486 .xlevel = 0,
487 },
488 {
489 .name = "pentium2",
490 .level = 2,
491 .family = 6,
492 .model = 5,
493 .stepping = 2,
494 .features = PENTIUM2_FEATURES,
495 .xlevel = 0,
496 },
497 {
498 .name = "pentium3",
499 .level = 2,
500 .family = 6,
501 .model = 7,
502 .stepping = 3,
503 .features = PENTIUM3_FEATURES,
504 .xlevel = 0,
505 },
506 {
507 .name = "athlon",
508 .level = 2,
509 .vendor1 = CPUID_VENDOR_AMD_1,
510 .vendor2 = CPUID_VENDOR_AMD_2,
511 .vendor3 = CPUID_VENDOR_AMD_3,
512 .family = 6,
513 .model = 2,
514 .stepping = 3,
515 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
516 CPUID_MCA,
517 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
518 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
519 .xlevel = 0x80000008,
520 },
521 {
522 .name = "n270",
523 /* original is on level 10 */
524 .level = 5,
525 .family = 6,
526 .model = 28,
527 .stepping = 2,
528 .features = PPRO_FEATURES |
529 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
530 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
531 /* Some CPUs got no CPUID_SEP */
532 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
533 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
534 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
535 CPUID_EXT2_NX,
536 .ext3_features = CPUID_EXT3_LAHF_LM,
537 .xlevel = 0x8000000A,
538 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
539 },
540 {
541 .name = "Conroe",
542 .level = 2,
543 .vendor1 = CPUID_VENDOR_INTEL_1,
544 .vendor2 = CPUID_VENDOR_INTEL_2,
545 .vendor3 = CPUID_VENDOR_INTEL_3,
546 .family = 6,
547 .model = 2,
548 .stepping = 3,
549 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
550 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
551 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
552 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
553 CPUID_DE | CPUID_FP87,
554 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
555 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
556 .ext3_features = CPUID_EXT3_LAHF_LM,
557 .xlevel = 0x8000000A,
558 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
559 },
560 {
561 .name = "Penryn",
562 .level = 2,
563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
566 .family = 6,
567 .model = 2,
568 .stepping = 3,
569 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
570 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
571 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
572 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
573 CPUID_DE | CPUID_FP87,
574 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
575 CPUID_EXT_SSE3,
576 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
577 .ext3_features = CPUID_EXT3_LAHF_LM,
578 .xlevel = 0x8000000A,
579 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
580 },
581 {
582 .name = "Nehalem",
583 .level = 2,
584 .vendor1 = CPUID_VENDOR_INTEL_1,
585 .vendor2 = CPUID_VENDOR_INTEL_2,
586 .vendor3 = CPUID_VENDOR_INTEL_3,
587 .family = 6,
588 .model = 2,
589 .stepping = 3,
590 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
591 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
592 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
593 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
594 CPUID_DE | CPUID_FP87,
595 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
596 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
597 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
598 .ext3_features = CPUID_EXT3_LAHF_LM,
599 .xlevel = 0x8000000A,
600 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
601 },
602 {
603 .name = "Westmere",
604 .level = 11,
605 .vendor1 = CPUID_VENDOR_INTEL_1,
606 .vendor2 = CPUID_VENDOR_INTEL_2,
607 .vendor3 = CPUID_VENDOR_INTEL_3,
608 .family = 6,
609 .model = 44,
610 .stepping = 1,
611 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
612 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
613 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
614 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
615 CPUID_DE | CPUID_FP87,
616 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
617 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
618 CPUID_EXT_SSE3,
619 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
620 .ext3_features = CPUID_EXT3_LAHF_LM,
621 .xlevel = 0x8000000A,
622 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
623 },
624 {
625 .name = "SandyBridge",
626 .level = 0xd,
627 .vendor1 = CPUID_VENDOR_INTEL_1,
628 .vendor2 = CPUID_VENDOR_INTEL_2,
629 .vendor3 = CPUID_VENDOR_INTEL_3,
630 .family = 6,
631 .model = 42,
632 .stepping = 1,
633 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
634 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
635 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
636 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
637 CPUID_DE | CPUID_FP87,
638 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
639 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
640 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
641 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
642 CPUID_EXT_SSE3,
643 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
644 CPUID_EXT2_SYSCALL,
645 .ext3_features = CPUID_EXT3_LAHF_LM,
646 .xlevel = 0x8000000A,
647 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
648 },
649 {
650 .name = "Opteron_G1",
651 .level = 5,
652 .vendor1 = CPUID_VENDOR_AMD_1,
653 .vendor2 = CPUID_VENDOR_AMD_2,
654 .vendor3 = CPUID_VENDOR_AMD_3,
655 .family = 15,
656 .model = 6,
657 .stepping = 1,
658 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
662 CPUID_DE | CPUID_FP87,
663 .ext_features = CPUID_EXT_SSE3,
664 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
665 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
666 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
667 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
668 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
669 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
670 .xlevel = 0x80000008,
671 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
672 },
673 {
674 .name = "Opteron_G2",
675 .level = 5,
676 .vendor1 = CPUID_VENDOR_AMD_1,
677 .vendor2 = CPUID_VENDOR_AMD_2,
678 .vendor3 = CPUID_VENDOR_AMD_3,
679 .family = 15,
680 .model = 6,
681 .stepping = 1,
682 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
683 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
684 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
685 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
686 CPUID_DE | CPUID_FP87,
687 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
688 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
689 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
690 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
691 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
692 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
693 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
694 CPUID_EXT2_DE | CPUID_EXT2_FPU,
695 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
696 .xlevel = 0x80000008,
697 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
698 },
699 {
700 .name = "Opteron_G3",
701 .level = 5,
702 .vendor1 = CPUID_VENDOR_AMD_1,
703 .vendor2 = CPUID_VENDOR_AMD_2,
704 .vendor3 = CPUID_VENDOR_AMD_3,
705 .family = 15,
706 .model = 6,
707 .stepping = 1,
708 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
709 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
710 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
711 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
712 CPUID_DE | CPUID_FP87,
713 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
714 CPUID_EXT_SSE3,
715 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
716 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
717 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
718 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
719 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
720 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
721 CPUID_EXT2_DE | CPUID_EXT2_FPU,
722 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
723 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
724 .xlevel = 0x80000008,
725 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
726 },
727 {
728 .name = "Opteron_G4",
729 .level = 0xd,
730 .vendor1 = CPUID_VENDOR_AMD_1,
731 .vendor2 = CPUID_VENDOR_AMD_2,
732 .vendor3 = CPUID_VENDOR_AMD_3,
733 .family = 21,
734 .model = 1,
735 .stepping = 2,
736 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
737 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
738 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
739 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
740 CPUID_DE | CPUID_FP87,
741 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
742 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
743 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
744 CPUID_EXT_SSE3,
745 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
746 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
747 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
748 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
749 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
750 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
751 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
752 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
753 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
754 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
755 CPUID_EXT3_LAHF_LM,
756 .xlevel = 0x8000001A,
757 .model_id = "AMD Opteron 62xx class CPU",
758 },
759 {
760 .name = "Opteron_G5",
761 .level = 0xd,
762 .vendor1 = CPUID_VENDOR_AMD_1,
763 .vendor2 = CPUID_VENDOR_AMD_2,
764 .vendor3 = CPUID_VENDOR_AMD_3,
765 .family = 21,
766 .model = 2,
767 .stepping = 0,
768 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
769 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
770 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
771 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
772 CPUID_DE | CPUID_FP87,
773 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
774 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
775 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
776 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
777 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
778 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
779 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
780 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
781 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
782 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
783 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
784 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
785 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
786 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
787 CPUID_EXT3_LAHF_LM,
788 .xlevel = 0x8000001A,
789 .model_id = "AMD Opteron 63xx class CPU",
790 },
791 };
792
793 #ifdef CONFIG_KVM
794 static int cpu_x86_fill_model_id(char *str)
795 {
796 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
797 int i;
798
799 for (i = 0; i < 3; i++) {
800 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
801 memcpy(str + i * 16 + 0, &eax, 4);
802 memcpy(str + i * 16 + 4, &ebx, 4);
803 memcpy(str + i * 16 + 8, &ecx, 4);
804 memcpy(str + i * 16 + 12, &edx, 4);
805 }
806 return 0;
807 }
808 #endif
809
810 /* Fill a x86_def_t struct with information about the host CPU, and
811 * the CPU features supported by the host hardware + host kernel
812 *
813 * This function may be called only if KVM is enabled.
814 */
815 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
816 {
817 #ifdef CONFIG_KVM
818 KVMState *s = kvm_state;
819 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
820
821 assert(kvm_enabled());
822
823 x86_cpu_def->name = "host";
824 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
825 x86_cpu_def->vendor1 = ebx;
826 x86_cpu_def->vendor2 = edx;
827 x86_cpu_def->vendor3 = ecx;
828
829 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
830 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
831 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
832 x86_cpu_def->stepping = eax & 0x0F;
833
834 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
835 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
836 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
837
838 if (x86_cpu_def->level >= 7) {
839 x86_cpu_def->cpuid_7_0_ebx_features =
840 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
841 } else {
842 x86_cpu_def->cpuid_7_0_ebx_features = 0;
843 }
844
845 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
846 x86_cpu_def->ext2_features =
847 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
848 x86_cpu_def->ext3_features =
849 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
850
851 cpu_x86_fill_model_id(x86_cpu_def->model_id);
852 x86_cpu_def->vendor_override = 0;
853
854 /* Call Centaur's CPUID instruction. */
855 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
856 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
857 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
858 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
859 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
860 if (eax >= 0xC0000001) {
861 /* Support VIA max extended level */
862 x86_cpu_def->xlevel2 = eax;
863 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
864 x86_cpu_def->ext4_features =
865 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
866 }
867 }
868
869 /*
870 * Every SVM feature requires emulation support in KVM - so we can't just
871 * read the host features here. KVM might even support SVM features not
872 * available on the host hardware. Just set all bits and mask out the
873 * unsupported ones later.
874 */
875 x86_cpu_def->svm_features = -1;
876 #endif /* CONFIG_KVM */
877 }
878
879 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
880 {
881 int i;
882
883 for (i = 0; i < 32; ++i)
884 if (1 << i & mask) {
885 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
886 " flag '%s' [0x%08x]\n",
887 f->cpuid >> 16, f->cpuid & 0xffff,
888 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
889 break;
890 }
891 return 0;
892 }
893
894 /* best effort attempt to inform user requested cpu flags aren't making
895 * their way to the guest. Note: ft[].check_feat ideally should be
896 * specified via a guest_def field to suppress report of extraneous flags.
897 *
898 * This function may be called only if KVM is enabled.
899 */
900 static int kvm_check_features_against_host(x86_def_t *guest_def)
901 {
902 x86_def_t host_def;
903 uint32_t mask;
904 int rv, i;
905 struct model_features_t ft[] = {
906 {&guest_def->features, &host_def.features,
907 ~0, feature_name, 0x00000000},
908 {&guest_def->ext_features, &host_def.ext_features,
909 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
910 {&guest_def->ext2_features, &host_def.ext2_features,
911 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
912 {&guest_def->ext3_features, &host_def.ext3_features,
913 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
914
915 assert(kvm_enabled());
916
917 kvm_cpu_fill_host(&host_def);
918 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
919 for (mask = 1; mask; mask <<= 1)
920 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
921 !(*ft[i].host_feat & mask)) {
922 unavailable_host_feature(&ft[i], mask);
923 rv = 1;
924 }
925 return rv;
926 }
927
928 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
929 const char *name, Error **errp)
930 {
931 X86CPU *cpu = X86_CPU(obj);
932 CPUX86State *env = &cpu->env;
933 int64_t value;
934
935 value = (env->cpuid_version >> 8) & 0xf;
936 if (value == 0xf) {
937 value += (env->cpuid_version >> 20) & 0xff;
938 }
939 visit_type_int(v, &value, name, errp);
940 }
941
942 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
943 const char *name, Error **errp)
944 {
945 X86CPU *cpu = X86_CPU(obj);
946 CPUX86State *env = &cpu->env;
947 const int64_t min = 0;
948 const int64_t max = 0xff + 0xf;
949 int64_t value;
950
951 visit_type_int(v, &value, name, errp);
952 if (error_is_set(errp)) {
953 return;
954 }
955 if (value < min || value > max) {
956 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
957 name ? name : "null", value, min, max);
958 return;
959 }
960
961 env->cpuid_version &= ~0xff00f00;
962 if (value > 0x0f) {
963 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
964 } else {
965 env->cpuid_version |= value << 8;
966 }
967 }
968
969 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
970 const char *name, Error **errp)
971 {
972 X86CPU *cpu = X86_CPU(obj);
973 CPUX86State *env = &cpu->env;
974 int64_t value;
975
976 value = (env->cpuid_version >> 4) & 0xf;
977 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
978 visit_type_int(v, &value, name, errp);
979 }
980
981 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
982 const char *name, Error **errp)
983 {
984 X86CPU *cpu = X86_CPU(obj);
985 CPUX86State *env = &cpu->env;
986 const int64_t min = 0;
987 const int64_t max = 0xff;
988 int64_t value;
989
990 visit_type_int(v, &value, name, errp);
991 if (error_is_set(errp)) {
992 return;
993 }
994 if (value < min || value > max) {
995 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
996 name ? name : "null", value, min, max);
997 return;
998 }
999
1000 env->cpuid_version &= ~0xf00f0;
1001 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1002 }
1003
1004 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1005 void *opaque, const char *name,
1006 Error **errp)
1007 {
1008 X86CPU *cpu = X86_CPU(obj);
1009 CPUX86State *env = &cpu->env;
1010 int64_t value;
1011
1012 value = env->cpuid_version & 0xf;
1013 visit_type_int(v, &value, name, errp);
1014 }
1015
1016 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1017 void *opaque, const char *name,
1018 Error **errp)
1019 {
1020 X86CPU *cpu = X86_CPU(obj);
1021 CPUX86State *env = &cpu->env;
1022 const int64_t min = 0;
1023 const int64_t max = 0xf;
1024 int64_t value;
1025
1026 visit_type_int(v, &value, name, errp);
1027 if (error_is_set(errp)) {
1028 return;
1029 }
1030 if (value < min || value > max) {
1031 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1032 name ? name : "null", value, min, max);
1033 return;
1034 }
1035
1036 env->cpuid_version &= ~0xf;
1037 env->cpuid_version |= value & 0xf;
1038 }
1039
1040 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1041 const char *name, Error **errp)
1042 {
1043 X86CPU *cpu = X86_CPU(obj);
1044
1045 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1046 }
1047
1048 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1049 const char *name, Error **errp)
1050 {
1051 X86CPU *cpu = X86_CPU(obj);
1052
1053 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1054 }
1055
1056 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1057 const char *name, Error **errp)
1058 {
1059 X86CPU *cpu = X86_CPU(obj);
1060
1061 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1062 }
1063
1064 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1065 const char *name, Error **errp)
1066 {
1067 X86CPU *cpu = X86_CPU(obj);
1068
1069 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1070 }
1071
1072 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1073 {
1074 X86CPU *cpu = X86_CPU(obj);
1075 CPUX86State *env = &cpu->env;
1076 char *value;
1077 int i;
1078
1079 value = (char *)g_malloc(12 + 1);
1080 for (i = 0; i < 4; i++) {
1081 value[i ] = env->cpuid_vendor1 >> (8 * i);
1082 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1083 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1084 }
1085 value[12] = '\0';
1086 return value;
1087 }
1088
1089 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1090 Error **errp)
1091 {
1092 X86CPU *cpu = X86_CPU(obj);
1093 CPUX86State *env = &cpu->env;
1094 int i;
1095
1096 if (strlen(value) != 12) {
1097 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1098 "vendor", value);
1099 return;
1100 }
1101
1102 env->cpuid_vendor1 = 0;
1103 env->cpuid_vendor2 = 0;
1104 env->cpuid_vendor3 = 0;
1105 for (i = 0; i < 4; i++) {
1106 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1107 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1108 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1109 }
1110 env->cpuid_vendor_override = 1;
1111 }
1112
1113 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1114 {
1115 X86CPU *cpu = X86_CPU(obj);
1116 CPUX86State *env = &cpu->env;
1117 char *value;
1118 int i;
1119
1120 value = g_malloc(48 + 1);
1121 for (i = 0; i < 48; i++) {
1122 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1123 }
1124 value[48] = '\0';
1125 return value;
1126 }
1127
1128 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1129 Error **errp)
1130 {
1131 X86CPU *cpu = X86_CPU(obj);
1132 CPUX86State *env = &cpu->env;
1133 int c, len, i;
1134
1135 if (model_id == NULL) {
1136 model_id = "";
1137 }
1138 len = strlen(model_id);
1139 memset(env->cpuid_model, 0, 48);
1140 for (i = 0; i < 48; i++) {
1141 if (i >= len) {
1142 c = '\0';
1143 } else {
1144 c = (uint8_t)model_id[i];
1145 }
1146 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1147 }
1148 }
1149
1150 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1151 const char *name, Error **errp)
1152 {
1153 X86CPU *cpu = X86_CPU(obj);
1154 int64_t value;
1155
1156 value = cpu->env.tsc_khz * 1000;
1157 visit_type_int(v, &value, name, errp);
1158 }
1159
1160 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1161 const char *name, Error **errp)
1162 {
1163 X86CPU *cpu = X86_CPU(obj);
1164 const int64_t min = 0;
1165 const int64_t max = INT64_MAX;
1166 int64_t value;
1167
1168 visit_type_int(v, &value, name, errp);
1169 if (error_is_set(errp)) {
1170 return;
1171 }
1172 if (value < min || value > max) {
1173 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1174 name ? name : "null", value, min, max);
1175 return;
1176 }
1177
1178 cpu->env.tsc_khz = value / 1000;
1179 }
1180
1181 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
1182 {
1183 unsigned int i;
1184 x86_def_t *def;
1185
1186 char *s = g_strdup(cpu_model);
1187 char *featurestr, *name = strtok(s, ",");
1188 /* Features to be added*/
1189 uint32_t plus_features = 0, plus_ext_features = 0;
1190 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1191 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1192 uint32_t plus_7_0_ebx_features = 0;
1193 /* Features to be removed */
1194 uint32_t minus_features = 0, minus_ext_features = 0;
1195 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1196 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1197 uint32_t minus_7_0_ebx_features = 0;
1198 uint32_t numvalue;
1199
1200 for (def = x86_defs; def; def = def->next)
1201 if (name && !strcmp(name, def->name))
1202 break;
1203 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1204 kvm_cpu_fill_host(x86_cpu_def);
1205 } else if (!def) {
1206 goto error;
1207 } else {
1208 memcpy(x86_cpu_def, def, sizeof(*def));
1209 }
1210
1211 add_flagname_to_bitmaps("hypervisor", &plus_features,
1212 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1213 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1214
1215 featurestr = strtok(NULL, ",");
1216
1217 while (featurestr) {
1218 char *val;
1219 if (featurestr[0] == '+') {
1220 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1221 &plus_ext_features, &plus_ext2_features,
1222 &plus_ext3_features, &plus_kvm_features,
1223 &plus_svm_features, &plus_7_0_ebx_features);
1224 } else if (featurestr[0] == '-') {
1225 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1226 &minus_ext_features, &minus_ext2_features,
1227 &minus_ext3_features, &minus_kvm_features,
1228 &minus_svm_features, &minus_7_0_ebx_features);
1229 } else if ((val = strchr(featurestr, '='))) {
1230 *val = 0; val++;
1231 if (!strcmp(featurestr, "family")) {
1232 char *err;
1233 numvalue = strtoul(val, &err, 0);
1234 if (!*val || *err || numvalue > 0xff + 0xf) {
1235 fprintf(stderr, "bad numerical value %s\n", val);
1236 goto error;
1237 }
1238 x86_cpu_def->family = numvalue;
1239 } else if (!strcmp(featurestr, "model")) {
1240 char *err;
1241 numvalue = strtoul(val, &err, 0);
1242 if (!*val || *err || numvalue > 0xff) {
1243 fprintf(stderr, "bad numerical value %s\n", val);
1244 goto error;
1245 }
1246 x86_cpu_def->model = numvalue;
1247 } else if (!strcmp(featurestr, "stepping")) {
1248 char *err;
1249 numvalue = strtoul(val, &err, 0);
1250 if (!*val || *err || numvalue > 0xf) {
1251 fprintf(stderr, "bad numerical value %s\n", val);
1252 goto error;
1253 }
1254 x86_cpu_def->stepping = numvalue ;
1255 } else if (!strcmp(featurestr, "level")) {
1256 char *err;
1257 numvalue = strtoul(val, &err, 0);
1258 if (!*val || *err) {
1259 fprintf(stderr, "bad numerical value %s\n", val);
1260 goto error;
1261 }
1262 x86_cpu_def->level = numvalue;
1263 } else if (!strcmp(featurestr, "xlevel")) {
1264 char *err;
1265 numvalue = strtoul(val, &err, 0);
1266 if (!*val || *err) {
1267 fprintf(stderr, "bad numerical value %s\n", val);
1268 goto error;
1269 }
1270 if (numvalue < 0x80000000) {
1271 numvalue += 0x80000000;
1272 }
1273 x86_cpu_def->xlevel = numvalue;
1274 } else if (!strcmp(featurestr, "vendor")) {
1275 if (strlen(val) != 12) {
1276 fprintf(stderr, "vendor string must be 12 chars long\n");
1277 goto error;
1278 }
1279 x86_cpu_def->vendor1 = 0;
1280 x86_cpu_def->vendor2 = 0;
1281 x86_cpu_def->vendor3 = 0;
1282 for(i = 0; i < 4; i++) {
1283 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1284 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1285 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1286 }
1287 x86_cpu_def->vendor_override = 1;
1288 } else if (!strcmp(featurestr, "model_id")) {
1289 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1290 val);
1291 } else if (!strcmp(featurestr, "tsc_freq")) {
1292 int64_t tsc_freq;
1293 char *err;
1294
1295 tsc_freq = strtosz_suffix_unit(val, &err,
1296 STRTOSZ_DEFSUFFIX_B, 1000);
1297 if (tsc_freq < 0 || *err) {
1298 fprintf(stderr, "bad numerical value %s\n", val);
1299 goto error;
1300 }
1301 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1302 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1303 char *err;
1304 numvalue = strtoul(val, &err, 0);
1305 if (!*val || *err) {
1306 fprintf(stderr, "bad numerical value %s\n", val);
1307 goto error;
1308 }
1309 hyperv_set_spinlock_retries(numvalue);
1310 } else {
1311 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1312 goto error;
1313 }
1314 } else if (!strcmp(featurestr, "check")) {
1315 check_cpuid = 1;
1316 } else if (!strcmp(featurestr, "enforce")) {
1317 check_cpuid = enforce_cpuid = 1;
1318 } else if (!strcmp(featurestr, "hv_relaxed")) {
1319 hyperv_enable_relaxed_timing(true);
1320 } else if (!strcmp(featurestr, "hv_vapic")) {
1321 hyperv_enable_vapic_recommended(true);
1322 } else {
1323 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1324 goto error;
1325 }
1326 featurestr = strtok(NULL, ",");
1327 }
1328 x86_cpu_def->features |= plus_features;
1329 x86_cpu_def->ext_features |= plus_ext_features;
1330 x86_cpu_def->ext2_features |= plus_ext2_features;
1331 x86_cpu_def->ext3_features |= plus_ext3_features;
1332 x86_cpu_def->kvm_features |= plus_kvm_features;
1333 x86_cpu_def->svm_features |= plus_svm_features;
1334 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1335 x86_cpu_def->features &= ~minus_features;
1336 x86_cpu_def->ext_features &= ~minus_ext_features;
1337 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1338 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1339 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1340 x86_cpu_def->svm_features &= ~minus_svm_features;
1341 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1342 if (check_cpuid && kvm_enabled()) {
1343 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1344 goto error;
1345 }
1346 if (x86_cpu_def->cpuid_7_0_ebx_features && x86_cpu_def->level < 7) {
1347 x86_cpu_def->level = 7;
1348 }
1349 g_free(s);
1350 return 0;
1351
1352 error:
1353 g_free(s);
1354 return -1;
1355 }
1356
1357 /* generate a composite string into buf of all cpuid names in featureset
1358 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1359 * if flags, suppress names undefined in featureset.
1360 */
1361 static void listflags(char *buf, int bufsize, uint32_t fbits,
1362 const char **featureset, uint32_t flags)
1363 {
1364 const char **p = &featureset[31];
1365 char *q, *b, bit;
1366 int nc;
1367
1368 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1369 *buf = '\0';
1370 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1371 if (fbits & 1 << bit && (*p || !flags)) {
1372 if (*p)
1373 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1374 else
1375 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1376 if (bufsize <= nc) {
1377 if (b) {
1378 memcpy(b, "...", sizeof("..."));
1379 }
1380 return;
1381 }
1382 q += nc;
1383 bufsize -= nc;
1384 }
1385 }
1386
1387 /* generate CPU information. */
1388 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1389 {
1390 x86_def_t *def;
1391 char buf[256];
1392
1393 for (def = x86_defs; def; def = def->next) {
1394 snprintf(buf, sizeof(buf), "%s", def->name);
1395 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1396 }
1397 if (kvm_enabled()) {
1398 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1399 }
1400 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1401 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1402 (*cpu_fprintf)(f, " %s\n", buf);
1403 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1404 (*cpu_fprintf)(f, " %s\n", buf);
1405 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1406 (*cpu_fprintf)(f, " %s\n", buf);
1407 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1408 (*cpu_fprintf)(f, " %s\n", buf);
1409 }
1410
1411 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1412 {
1413 CpuDefinitionInfoList *cpu_list = NULL;
1414 x86_def_t *def;
1415
1416 for (def = x86_defs; def; def = def->next) {
1417 CpuDefinitionInfoList *entry;
1418 CpuDefinitionInfo *info;
1419
1420 info = g_malloc0(sizeof(*info));
1421 info->name = g_strdup(def->name);
1422
1423 entry = g_malloc0(sizeof(*entry));
1424 entry->value = info;
1425 entry->next = cpu_list;
1426 cpu_list = entry;
1427 }
1428
1429 return cpu_list;
1430 }
1431
1432 #ifdef CONFIG_KVM
1433 static void filter_features_for_kvm(X86CPU *cpu)
1434 {
1435 CPUX86State *env = &cpu->env;
1436 KVMState *s = kvm_state;
1437
1438 env->cpuid_features &=
1439 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1440 env->cpuid_ext_features &=
1441 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1442 env->cpuid_ext2_features &=
1443 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1444 env->cpuid_ext3_features &=
1445 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1446 env->cpuid_svm_features &=
1447 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1448 env->cpuid_7_0_ebx_features &=
1449 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1450 env->cpuid_kvm_features &=
1451 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1452 env->cpuid_ext4_features &=
1453 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1454
1455 }
1456 #endif
1457
1458 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1459 {
1460 CPUX86State *env = &cpu->env;
1461 x86_def_t def1, *def = &def1;
1462 Error *error = NULL;
1463
1464 memset(def, 0, sizeof(*def));
1465
1466 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1467 return -1;
1468 if (def->vendor1) {
1469 env->cpuid_vendor1 = def->vendor1;
1470 env->cpuid_vendor2 = def->vendor2;
1471 env->cpuid_vendor3 = def->vendor3;
1472 } else {
1473 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1474 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1475 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1476 }
1477 env->cpuid_vendor_override = def->vendor_override;
1478 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1479 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1480 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1481 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1482 env->cpuid_features = def->features;
1483 env->cpuid_ext_features = def->ext_features;
1484 env->cpuid_ext2_features = def->ext2_features;
1485 env->cpuid_ext3_features = def->ext3_features;
1486 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1487 env->cpuid_kvm_features = def->kvm_features;
1488 env->cpuid_svm_features = def->svm_features;
1489 env->cpuid_ext4_features = def->ext4_features;
1490 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1491 env->cpuid_xlevel2 = def->xlevel2;
1492 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1493 "tsc-frequency", &error);
1494
1495 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1496 * CPUID[1].EDX.
1497 */
1498 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1499 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1500 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1501 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1502 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1503 }
1504
1505 if (!kvm_enabled()) {
1506 env->cpuid_features &= TCG_FEATURES;
1507 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1508 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1509 #ifdef TARGET_X86_64
1510 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1511 #endif
1512 );
1513 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1514 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1515 } else {
1516 #ifdef CONFIG_KVM
1517 filter_features_for_kvm(cpu);
1518 #endif
1519 }
1520 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1521 if (error) {
1522 fprintf(stderr, "%s\n", error_get_pretty(error));
1523 error_free(error);
1524 return -1;
1525 }
1526 return 0;
1527 }
1528
1529 #if !defined(CONFIG_USER_ONLY)
1530
1531 void cpu_clear_apic_feature(CPUX86State *env)
1532 {
1533 env->cpuid_features &= ~CPUID_APIC;
1534 }
1535
1536 #endif /* !CONFIG_USER_ONLY */
1537
1538 /* Initialize list of CPU models, filling some non-static fields if necessary
1539 */
1540 void x86_cpudef_setup(void)
1541 {
1542 int i, j;
1543 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1544
1545 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1546 x86_def_t *def = &builtin_x86_defs[i];
1547 def->next = x86_defs;
1548
1549 /* Look for specific "cpudef" models that */
1550 /* have the QEMU version in .model_id */
1551 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1552 if (strcmp(model_with_versions[j], def->name) == 0) {
1553 pstrcpy(def->model_id, sizeof(def->model_id),
1554 "QEMU Virtual CPU version ");
1555 pstrcat(def->model_id, sizeof(def->model_id),
1556 qemu_get_version());
1557 break;
1558 }
1559 }
1560
1561 x86_defs = def;
1562 }
1563 }
1564
1565 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1566 uint32_t *ecx, uint32_t *edx)
1567 {
1568 *ebx = env->cpuid_vendor1;
1569 *edx = env->cpuid_vendor2;
1570 *ecx = env->cpuid_vendor3;
1571
1572 /* sysenter isn't supported on compatibility mode on AMD, syscall
1573 * isn't supported in compatibility mode on Intel.
1574 * Normally we advertise the actual cpu vendor, but you can override
1575 * this if you want to use KVM's sysenter/syscall emulation
1576 * in compatibility mode and when doing cross vendor migration
1577 */
1578 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1579 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1580 }
1581 }
1582
1583 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1584 uint32_t *eax, uint32_t *ebx,
1585 uint32_t *ecx, uint32_t *edx)
1586 {
1587 /* test if maximum index reached */
1588 if (index & 0x80000000) {
1589 if (index > env->cpuid_xlevel) {
1590 if (env->cpuid_xlevel2 > 0) {
1591 /* Handle the Centaur's CPUID instruction. */
1592 if (index > env->cpuid_xlevel2) {
1593 index = env->cpuid_xlevel2;
1594 } else if (index < 0xC0000000) {
1595 index = env->cpuid_xlevel;
1596 }
1597 } else {
1598 index = env->cpuid_xlevel;
1599 }
1600 }
1601 } else {
1602 if (index > env->cpuid_level)
1603 index = env->cpuid_level;
1604 }
1605
1606 switch(index) {
1607 case 0:
1608 *eax = env->cpuid_level;
1609 get_cpuid_vendor(env, ebx, ecx, edx);
1610 break;
1611 case 1:
1612 *eax = env->cpuid_version;
1613 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1614 *ecx = env->cpuid_ext_features;
1615 *edx = env->cpuid_features;
1616 if (env->nr_cores * env->nr_threads > 1) {
1617 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1618 *edx |= 1 << 28; /* HTT bit */
1619 }
1620 break;
1621 case 2:
1622 /* cache info: needed for Pentium Pro compatibility */
1623 *eax = 1;
1624 *ebx = 0;
1625 *ecx = 0;
1626 *edx = 0x2c307d;
1627 break;
1628 case 4:
1629 /* cache info: needed for Core compatibility */
1630 if (env->nr_cores > 1) {
1631 *eax = (env->nr_cores - 1) << 26;
1632 } else {
1633 *eax = 0;
1634 }
1635 switch (count) {
1636 case 0: /* L1 dcache info */
1637 *eax |= 0x0000121;
1638 *ebx = 0x1c0003f;
1639 *ecx = 0x000003f;
1640 *edx = 0x0000001;
1641 break;
1642 case 1: /* L1 icache info */
1643 *eax |= 0x0000122;
1644 *ebx = 0x1c0003f;
1645 *ecx = 0x000003f;
1646 *edx = 0x0000001;
1647 break;
1648 case 2: /* L2 cache info */
1649 *eax |= 0x0000143;
1650 if (env->nr_threads > 1) {
1651 *eax |= (env->nr_threads - 1) << 14;
1652 }
1653 *ebx = 0x3c0003f;
1654 *ecx = 0x0000fff;
1655 *edx = 0x0000001;
1656 break;
1657 default: /* end of info */
1658 *eax = 0;
1659 *ebx = 0;
1660 *ecx = 0;
1661 *edx = 0;
1662 break;
1663 }
1664 break;
1665 case 5:
1666 /* mwait info: needed for Core compatibility */
1667 *eax = 0; /* Smallest monitor-line size in bytes */
1668 *ebx = 0; /* Largest monitor-line size in bytes */
1669 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1670 *edx = 0;
1671 break;
1672 case 6:
1673 /* Thermal and Power Leaf */
1674 *eax = 0;
1675 *ebx = 0;
1676 *ecx = 0;
1677 *edx = 0;
1678 break;
1679 case 7:
1680 /* Structured Extended Feature Flags Enumeration Leaf */
1681 if (count == 0) {
1682 *eax = 0; /* Maximum ECX value for sub-leaves */
1683 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1684 *ecx = 0; /* Reserved */
1685 *edx = 0; /* Reserved */
1686 } else {
1687 *eax = 0;
1688 *ebx = 0;
1689 *ecx = 0;
1690 *edx = 0;
1691 }
1692 break;
1693 case 9:
1694 /* Direct Cache Access Information Leaf */
1695 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1696 *ebx = 0;
1697 *ecx = 0;
1698 *edx = 0;
1699 break;
1700 case 0xA:
1701 /* Architectural Performance Monitoring Leaf */
1702 if (kvm_enabled()) {
1703 KVMState *s = env->kvm_state;
1704
1705 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1706 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1707 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1708 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1709 } else {
1710 *eax = 0;
1711 *ebx = 0;
1712 *ecx = 0;
1713 *edx = 0;
1714 }
1715 break;
1716 case 0xD:
1717 /* Processor Extended State */
1718 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1719 *eax = 0;
1720 *ebx = 0;
1721 *ecx = 0;
1722 *edx = 0;
1723 break;
1724 }
1725 if (kvm_enabled()) {
1726 KVMState *s = env->kvm_state;
1727
1728 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1729 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1730 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1731 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1732 } else {
1733 *eax = 0;
1734 *ebx = 0;
1735 *ecx = 0;
1736 *edx = 0;
1737 }
1738 break;
1739 case 0x80000000:
1740 *eax = env->cpuid_xlevel;
1741 *ebx = env->cpuid_vendor1;
1742 *edx = env->cpuid_vendor2;
1743 *ecx = env->cpuid_vendor3;
1744 break;
1745 case 0x80000001:
1746 *eax = env->cpuid_version;
1747 *ebx = 0;
1748 *ecx = env->cpuid_ext3_features;
1749 *edx = env->cpuid_ext2_features;
1750
1751 /* The Linux kernel checks for the CMPLegacy bit and
1752 * discards multiple thread information if it is set.
1753 * So dont set it here for Intel to make Linux guests happy.
1754 */
1755 if (env->nr_cores * env->nr_threads > 1) {
1756 uint32_t tebx, tecx, tedx;
1757 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1758 if (tebx != CPUID_VENDOR_INTEL_1 ||
1759 tedx != CPUID_VENDOR_INTEL_2 ||
1760 tecx != CPUID_VENDOR_INTEL_3) {
1761 *ecx |= 1 << 1; /* CmpLegacy bit */
1762 }
1763 }
1764 break;
1765 case 0x80000002:
1766 case 0x80000003:
1767 case 0x80000004:
1768 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1769 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1770 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1771 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1772 break;
1773 case 0x80000005:
1774 /* cache info (L1 cache) */
1775 *eax = 0x01ff01ff;
1776 *ebx = 0x01ff01ff;
1777 *ecx = 0x40020140;
1778 *edx = 0x40020140;
1779 break;
1780 case 0x80000006:
1781 /* cache info (L2 cache) */
1782 *eax = 0;
1783 *ebx = 0x42004200;
1784 *ecx = 0x02008140;
1785 *edx = 0;
1786 break;
1787 case 0x80000008:
1788 /* virtual & phys address size in low 2 bytes. */
1789 /* XXX: This value must match the one used in the MMU code. */
1790 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1791 /* 64 bit processor */
1792 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1793 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1794 } else {
1795 if (env->cpuid_features & CPUID_PSE36)
1796 *eax = 0x00000024; /* 36 bits physical */
1797 else
1798 *eax = 0x00000020; /* 32 bits physical */
1799 }
1800 *ebx = 0;
1801 *ecx = 0;
1802 *edx = 0;
1803 if (env->nr_cores * env->nr_threads > 1) {
1804 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1805 }
1806 break;
1807 case 0x8000000A:
1808 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1809 *eax = 0x00000001; /* SVM Revision */
1810 *ebx = 0x00000010; /* nr of ASIDs */
1811 *ecx = 0;
1812 *edx = env->cpuid_svm_features; /* optional features */
1813 } else {
1814 *eax = 0;
1815 *ebx = 0;
1816 *ecx = 0;
1817 *edx = 0;
1818 }
1819 break;
1820 case 0xC0000000:
1821 *eax = env->cpuid_xlevel2;
1822 *ebx = 0;
1823 *ecx = 0;
1824 *edx = 0;
1825 break;
1826 case 0xC0000001:
1827 /* Support for VIA CPU's CPUID instruction */
1828 *eax = env->cpuid_version;
1829 *ebx = 0;
1830 *ecx = 0;
1831 *edx = env->cpuid_ext4_features;
1832 break;
1833 case 0xC0000002:
1834 case 0xC0000003:
1835 case 0xC0000004:
1836 /* Reserved for the future, and now filled with zero */
1837 *eax = 0;
1838 *ebx = 0;
1839 *ecx = 0;
1840 *edx = 0;
1841 break;
1842 default:
1843 /* reserved values: zero */
1844 *eax = 0;
1845 *ebx = 0;
1846 *ecx = 0;
1847 *edx = 0;
1848 break;
1849 }
1850 }
1851
1852 /* CPUClass::reset() */
1853 static void x86_cpu_reset(CPUState *s)
1854 {
1855 X86CPU *cpu = X86_CPU(s);
1856 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1857 CPUX86State *env = &cpu->env;
1858 int i;
1859
1860 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1861 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1862 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1863 }
1864
1865 xcc->parent_reset(s);
1866
1867
1868 memset(env, 0, offsetof(CPUX86State, breakpoints));
1869
1870 tlb_flush(env, 1);
1871
1872 env->old_exception = -1;
1873
1874 /* init to reset state */
1875
1876 #ifdef CONFIG_SOFTMMU
1877 env->hflags |= HF_SOFTMMU_MASK;
1878 #endif
1879 env->hflags2 |= HF2_GIF_MASK;
1880
1881 cpu_x86_update_cr0(env, 0x60000010);
1882 env->a20_mask = ~0x0;
1883 env->smbase = 0x30000;
1884
1885 env->idt.limit = 0xffff;
1886 env->gdt.limit = 0xffff;
1887 env->ldt.limit = 0xffff;
1888 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1889 env->tr.limit = 0xffff;
1890 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1891
1892 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1893 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1894 DESC_R_MASK | DESC_A_MASK);
1895 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1896 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1897 DESC_A_MASK);
1898 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1899 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1900 DESC_A_MASK);
1901 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1902 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1903 DESC_A_MASK);
1904 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1905 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1906 DESC_A_MASK);
1907 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1908 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1909 DESC_A_MASK);
1910
1911 env->eip = 0xfff0;
1912 env->regs[R_EDX] = env->cpuid_version;
1913
1914 env->eflags = 0x2;
1915
1916 /* FPU init */
1917 for (i = 0; i < 8; i++) {
1918 env->fptags[i] = 1;
1919 }
1920 env->fpuc = 0x37f;
1921
1922 env->mxcsr = 0x1f80;
1923
1924 env->pat = 0x0007040600070406ULL;
1925 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1926
1927 memset(env->dr, 0, sizeof(env->dr));
1928 env->dr[6] = DR6_FIXED_1;
1929 env->dr[7] = DR7_FIXED_1;
1930 cpu_breakpoint_remove_all(env, BP_CPU);
1931 cpu_watchpoint_remove_all(env, BP_CPU);
1932
1933 #if !defined(CONFIG_USER_ONLY)
1934 /* We hard-wire the BSP to the first CPU. */
1935 if (env->cpu_index == 0) {
1936 apic_designate_bsp(env->apic_state);
1937 }
1938
1939 env->halted = !cpu_is_bsp(cpu);
1940 #endif
1941 }
1942
1943 #ifndef CONFIG_USER_ONLY
1944 bool cpu_is_bsp(X86CPU *cpu)
1945 {
1946 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1947 }
1948
1949 /* TODO: remove me, when reset over QOM tree is implemented */
1950 static void x86_cpu_machine_reset_cb(void *opaque)
1951 {
1952 X86CPU *cpu = opaque;
1953 cpu_reset(CPU(cpu));
1954 }
1955 #endif
1956
1957 static void mce_init(X86CPU *cpu)
1958 {
1959 CPUX86State *cenv = &cpu->env;
1960 unsigned int bank;
1961
1962 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1963 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1964 (CPUID_MCE | CPUID_MCA)) {
1965 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1966 cenv->mcg_ctl = ~(uint64_t)0;
1967 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1968 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1969 }
1970 }
1971 }
1972
1973 #define MSI_ADDR_BASE 0xfee00000
1974
1975 #ifndef CONFIG_USER_ONLY
1976 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
1977 {
1978 static int apic_mapped;
1979 CPUX86State *env = &cpu->env;
1980 APICCommonState *apic;
1981 const char *apic_type = "apic";
1982
1983 if (kvm_irqchip_in_kernel()) {
1984 apic_type = "kvm-apic";
1985 } else if (xen_enabled()) {
1986 apic_type = "xen-apic";
1987 }
1988
1989 env->apic_state = qdev_try_create(NULL, apic_type);
1990 if (env->apic_state == NULL) {
1991 error_setg(errp, "APIC device '%s' could not be created", apic_type);
1992 return;
1993 }
1994
1995 object_property_add_child(OBJECT(cpu), "apic",
1996 OBJECT(env->apic_state), NULL);
1997 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
1998 /* TODO: convert to link<> */
1999 apic = APIC_COMMON(env->apic_state);
2000 apic->cpu = cpu;
2001
2002 if (qdev_init(env->apic_state)) {
2003 error_setg(errp, "APIC device '%s' could not be initialized",
2004 object_get_typename(OBJECT(env->apic_state)));
2005 return;
2006 }
2007
2008 /* XXX: mapping more APICs at the same memory location */
2009 if (apic_mapped == 0) {
2010 /* NOTE: the APIC is directly connected to the CPU - it is not
2011 on the global memory bus. */
2012 /* XXX: what if the base changes? */
2013 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2014 apic_mapped = 1;
2015 }
2016 }
2017 #endif
2018
2019 void x86_cpu_realize(Object *obj, Error **errp)
2020 {
2021 X86CPU *cpu = X86_CPU(obj);
2022
2023 #ifndef CONFIG_USER_ONLY
2024 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2025
2026 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2027 x86_cpu_apic_init(cpu, errp);
2028 if (error_is_set(errp)) {
2029 return;
2030 }
2031 }
2032 #endif
2033
2034 mce_init(cpu);
2035 qemu_init_vcpu(&cpu->env);
2036 cpu_reset(CPU(cpu));
2037 }
2038
2039 static void x86_cpu_initfn(Object *obj)
2040 {
2041 X86CPU *cpu = X86_CPU(obj);
2042 CPUX86State *env = &cpu->env;
2043 static int inited;
2044
2045 cpu_exec_init(env);
2046
2047 object_property_add(obj, "family", "int",
2048 x86_cpuid_version_get_family,
2049 x86_cpuid_version_set_family, NULL, NULL, NULL);
2050 object_property_add(obj, "model", "int",
2051 x86_cpuid_version_get_model,
2052 x86_cpuid_version_set_model, NULL, NULL, NULL);
2053 object_property_add(obj, "stepping", "int",
2054 x86_cpuid_version_get_stepping,
2055 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2056 object_property_add(obj, "level", "int",
2057 x86_cpuid_get_level,
2058 x86_cpuid_set_level, NULL, NULL, NULL);
2059 object_property_add(obj, "xlevel", "int",
2060 x86_cpuid_get_xlevel,
2061 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2062 object_property_add_str(obj, "vendor",
2063 x86_cpuid_get_vendor,
2064 x86_cpuid_set_vendor, NULL);
2065 object_property_add_str(obj, "model-id",
2066 x86_cpuid_get_model_id,
2067 x86_cpuid_set_model_id, NULL);
2068 object_property_add(obj, "tsc-frequency", "int",
2069 x86_cpuid_get_tsc_freq,
2070 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2071
2072 env->cpuid_apic_id = env->cpu_index;
2073
2074 /* init various static tables used in TCG mode */
2075 if (tcg_enabled() && !inited) {
2076 inited = 1;
2077 optimize_flags_init();
2078 #ifndef CONFIG_USER_ONLY
2079 cpu_set_debug_excp_handler(breakpoint_handler);
2080 #endif
2081 }
2082 }
2083
2084 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2085 {
2086 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2087 CPUClass *cc = CPU_CLASS(oc);
2088
2089 xcc->parent_reset = cc->reset;
2090 cc->reset = x86_cpu_reset;
2091 }
2092
2093 static const TypeInfo x86_cpu_type_info = {
2094 .name = TYPE_X86_CPU,
2095 .parent = TYPE_CPU,
2096 .instance_size = sizeof(X86CPU),
2097 .instance_init = x86_cpu_initfn,
2098 .abstract = false,
2099 .class_size = sizeof(X86CPUClass),
2100 .class_init = x86_cpu_common_class_init,
2101 };
2102
2103 static void x86_cpu_register_types(void)
2104 {
2105 type_register_static(&x86_cpu_type_info);
2106 }
2107
2108 type_init(x86_cpu_register_types)
QEMU mirror