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target-i386: Break CPUID feature definition lines
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
49 #endif
50
51 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
52 uint32_t vendor2, uint32_t vendor3)
53 {
54 int i;
55 for (i = 0; i < 4; i++) {
56 dst[i] = vendor1 >> (8 * i);
57 dst[i + 4] = vendor2 >> (8 * i);
58 dst[i + 8] = vendor3 >> (8 * i);
59 }
60 dst[CPUID_VENDOR_SZ] = '\0';
61 }
62
63 /* feature flags taken from "Intel Processor Identification and the CPUID
64 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
65 * between feature naming conventions, aliases may be added.
66 */
67 static const char *feature_name[] = {
68 "fpu", "vme", "de", "pse",
69 "tsc", "msr", "pae", "mce",
70 "cx8", "apic", NULL, "sep",
71 "mtrr", "pge", "mca", "cmov",
72 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
73 NULL, "ds" /* Intel dts */, "acpi", "mmx",
74 "fxsr", "sse", "sse2", "ss",
75 "ht" /* Intel htt */, "tm", "ia64", "pbe",
76 };
77 static const char *ext_feature_name[] = {
78 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
79 "ds_cpl", "vmx", "smx", "est",
80 "tm2", "ssse3", "cid", NULL,
81 "fma", "cx16", "xtpr", "pdcm",
82 NULL, "pcid", "dca", "sse4.1|sse4_1",
83 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
84 "tsc-deadline", "aes", "xsave", "osxsave",
85 "avx", "f16c", "rdrand", "hypervisor",
86 };
87 /* Feature names that are already defined on feature_name[] but are set on
88 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
89 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
90 * if and only if CPU vendor is AMD.
91 */
92 static const char *ext2_feature_name[] = {
93 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
94 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
95 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
96 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
97 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
98 "nx|xd", NULL, "mmxext", NULL /* mmx */,
99 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
100 NULL, "lm|i64", "3dnowext", "3dnow",
101 };
102 static const char *ext3_feature_name[] = {
103 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
104 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
105 "3dnowprefetch", "osvw", "ibs", "xop",
106 "skinit", "wdt", NULL, "lwp",
107 "fma4", "tce", NULL, "nodeid_msr",
108 NULL, "tbm", "topoext", "perfctr_core",
109 "perfctr_nb", NULL, NULL, NULL,
110 NULL, NULL, NULL, NULL,
111 };
112
113 static const char *ext4_feature_name[] = {
114 NULL, NULL, "xstore", "xstore-en",
115 NULL, NULL, "xcrypt", "xcrypt-en",
116 "ace2", "ace2-en", "phe", "phe-en",
117 "pmm", "pmm-en", NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 NULL, NULL, NULL, NULL,
122 };
123
124 static const char *kvm_feature_name[] = {
125 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
126 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 NULL, NULL, NULL, NULL,
133 };
134
135 static const char *svm_feature_name[] = {
136 "npt", "lbrv", "svm_lock", "nrip_save",
137 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
138 NULL, NULL, "pause_filter", NULL,
139 "pfthreshold", NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 NULL, NULL, NULL, NULL,
144 };
145
146 static const char *cpuid_7_0_ebx_feature_name[] = {
147 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
148 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
149 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
150 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
151 };
152
153 typedef struct FeatureWordInfo {
154 const char **feat_names;
155 uint32_t cpuid_eax; /* Input EAX for CPUID */
156 int cpuid_reg; /* R_* register constant */
157 } FeatureWordInfo;
158
159 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
160 [FEAT_1_EDX] = {
161 .feat_names = feature_name,
162 .cpuid_eax = 1, .cpuid_reg = R_EDX,
163 },
164 [FEAT_1_ECX] = {
165 .feat_names = ext_feature_name,
166 .cpuid_eax = 1, .cpuid_reg = R_ECX,
167 },
168 [FEAT_8000_0001_EDX] = {
169 .feat_names = ext2_feature_name,
170 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
171 },
172 [FEAT_8000_0001_ECX] = {
173 .feat_names = ext3_feature_name,
174 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
175 },
176 [FEAT_C000_0001_EDX] = {
177 .feat_names = ext4_feature_name,
178 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
179 },
180 [FEAT_KVM] = {
181 .feat_names = kvm_feature_name,
182 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
183 },
184 [FEAT_SVM] = {
185 .feat_names = svm_feature_name,
186 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
187 },
188 [FEAT_7_0_EBX] = {
189 .feat_names = cpuid_7_0_ebx_feature_name,
190 .cpuid_eax = 7, .cpuid_reg = R_EBX,
191 },
192 };
193
194 const char *get_register_name_32(unsigned int reg)
195 {
196 static const char *reg_names[CPU_NB_REGS32] = {
197 [R_EAX] = "EAX",
198 [R_ECX] = "ECX",
199 [R_EDX] = "EDX",
200 [R_EBX] = "EBX",
201 [R_ESP] = "ESP",
202 [R_EBP] = "EBP",
203 [R_ESI] = "ESI",
204 [R_EDI] = "EDI",
205 };
206
207 if (reg > CPU_NB_REGS32) {
208 return NULL;
209 }
210 return reg_names[reg];
211 }
212
213 /* collects per-function cpuid data
214 */
215 typedef struct model_features_t {
216 uint32_t *guest_feat;
217 uint32_t *host_feat;
218 FeatureWord feat_word;
219 } model_features_t;
220
221 int check_cpuid = 0;
222 int enforce_cpuid = 0;
223
224 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
225 (1 << KVM_FEATURE_NOP_IO_DELAY) |
226 (1 << KVM_FEATURE_CLOCKSOURCE2) |
227 (1 << KVM_FEATURE_ASYNC_PF) |
228 (1 << KVM_FEATURE_STEAL_TIME) |
229 (1 << KVM_FEATURE_PV_EOI) |
230 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
231
232 void disable_kvm_pv_eoi(void)
233 {
234 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
235 }
236
237 void host_cpuid(uint32_t function, uint32_t count,
238 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
239 {
240 #if defined(CONFIG_KVM)
241 uint32_t vec[4];
242
243 #ifdef __x86_64__
244 asm volatile("cpuid"
245 : "=a"(vec[0]), "=b"(vec[1]),
246 "=c"(vec[2]), "=d"(vec[3])
247 : "0"(function), "c"(count) : "cc");
248 #else
249 asm volatile("pusha \n\t"
250 "cpuid \n\t"
251 "mov %%eax, 0(%2) \n\t"
252 "mov %%ebx, 4(%2) \n\t"
253 "mov %%ecx, 8(%2) \n\t"
254 "mov %%edx, 12(%2) \n\t"
255 "popa"
256 : : "a"(function), "c"(count), "S"(vec)
257 : "memory", "cc");
258 #endif
259
260 if (eax)
261 *eax = vec[0];
262 if (ebx)
263 *ebx = vec[1];
264 if (ecx)
265 *ecx = vec[2];
266 if (edx)
267 *edx = vec[3];
268 #endif
269 }
270
271 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
272
273 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
274 * a substring. ex if !NULL points to the first char after a substring,
275 * otherwise the string is assumed to sized by a terminating nul.
276 * Return lexical ordering of *s1:*s2.
277 */
278 static int sstrcmp(const char *s1, const char *e1, const char *s2,
279 const char *e2)
280 {
281 for (;;) {
282 if (!*s1 || !*s2 || *s1 != *s2)
283 return (*s1 - *s2);
284 ++s1, ++s2;
285 if (s1 == e1 && s2 == e2)
286 return (0);
287 else if (s1 == e1)
288 return (*s2);
289 else if (s2 == e2)
290 return (*s1);
291 }
292 }
293
294 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
295 * '|' delimited (possibly empty) strings in which case search for a match
296 * within the alternatives proceeds left to right. Return 0 for success,
297 * non-zero otherwise.
298 */
299 static int altcmp(const char *s, const char *e, const char *altstr)
300 {
301 const char *p, *q;
302
303 for (q = p = altstr; ; ) {
304 while (*p && *p != '|')
305 ++p;
306 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
307 return (0);
308 if (!*p)
309 return (1);
310 else
311 q = ++p;
312 }
313 }
314
315 /* search featureset for flag *[s..e), if found set corresponding bit in
316 * *pval and return true, otherwise return false
317 */
318 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
319 const char **featureset)
320 {
321 uint32_t mask;
322 const char **ppc;
323 bool found = false;
324
325 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
326 if (*ppc && !altcmp(s, e, *ppc)) {
327 *pval |= mask;
328 found = true;
329 }
330 }
331 return found;
332 }
333
334 static void add_flagname_to_bitmaps(const char *flagname,
335 FeatureWordArray words)
336 {
337 FeatureWord w;
338 for (w = 0; w < FEATURE_WORDS; w++) {
339 FeatureWordInfo *wi = &feature_word_info[w];
340 if (wi->feat_names &&
341 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
342 break;
343 }
344 }
345 if (w == FEATURE_WORDS) {
346 fprintf(stderr, "CPU feature %s not found\n", flagname);
347 }
348 }
349
350 typedef struct x86_def_t {
351 const char *name;
352 uint32_t level;
353 uint32_t xlevel;
354 uint32_t xlevel2;
355 /* vendor is zero-terminated, 12 character ASCII string */
356 char vendor[CPUID_VENDOR_SZ + 1];
357 int family;
358 int model;
359 int stepping;
360 uint32_t features, ext_features, ext2_features, ext3_features;
361 uint32_t kvm_features, svm_features;
362 char model_id[48];
363 /* Store the results of Centaur's CPUID instructions */
364 uint32_t ext4_features;
365 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
366 uint32_t cpuid_7_0_ebx_features;
367 } x86_def_t;
368
369 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
370 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
371 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
372 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
373 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
374 CPUID_PSE36 | CPUID_FXSR)
375 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
376 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
377 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
378 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
379 CPUID_PAE | CPUID_SEP | CPUID_APIC)
380
381 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
382 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
383 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
384 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
385 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
386 /* partly implemented:
387 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
388 CPUID_PSE36 (needed for Solaris) */
389 /* missing:
390 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
391 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
392 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
393 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
394 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
395 /* missing:
396 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
397 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
398 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
399 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
400 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
401 CPUID_EXT_RDRAND */
402 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
403 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
404 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
405 /* missing:
406 CPUID_EXT2_PDPE1GB */
407 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
408 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
409 #define TCG_SVM_FEATURES 0
410 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
411 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
412 /* missing:
413 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
414 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
415 CPUID_7_0_EBX_RDSEED */
416
417 /* built-in CPU model definitions
418 */
419 static x86_def_t builtin_x86_defs[] = {
420 {
421 .name = "qemu64",
422 .level = 4,
423 .vendor = CPUID_VENDOR_AMD,
424 .family = 6,
425 .model = 2,
426 .stepping = 3,
427 .features =
428 PPRO_FEATURES |
429 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
430 CPUID_PSE36,
431 .ext_features =
432 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
433 .ext2_features =
434 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
435 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
436 .ext3_features =
437 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
438 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
439 .xlevel = 0x8000000A,
440 },
441 {
442 .name = "phenom",
443 .level = 5,
444 .vendor = CPUID_VENDOR_AMD,
445 .family = 16,
446 .model = 2,
447 .stepping = 3,
448 .features =
449 PPRO_FEATURES |
450 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
451 CPUID_PSE36 | CPUID_VME | CPUID_HT,
452 .ext_features =
453 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
454 CPUID_EXT_POPCNT,
455 .ext2_features =
456 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
457 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
458 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
459 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
460 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
461 CPUID_EXT3_CR8LEG,
462 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
463 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
464 .ext3_features =
465 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
466 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
467 .svm_features =
468 CPUID_SVM_NPT | CPUID_SVM_LBRV,
469 .xlevel = 0x8000001A,
470 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
471 },
472 {
473 .name = "core2duo",
474 .level = 10,
475 .vendor = CPUID_VENDOR_INTEL,
476 .family = 6,
477 .model = 15,
478 .stepping = 11,
479 .features =
480 PPRO_FEATURES |
481 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
482 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
483 CPUID_HT | CPUID_TM | CPUID_PBE,
484 .ext_features =
485 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
486 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
487 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
488 .ext2_features =
489 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
490 .ext3_features =
491 CPUID_EXT3_LAHF_LM,
492 .xlevel = 0x80000008,
493 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
494 },
495 {
496 .name = "kvm64",
497 .level = 5,
498 .vendor = CPUID_VENDOR_INTEL,
499 .family = 15,
500 .model = 6,
501 .stepping = 1,
502 /* Missing: CPUID_VME, CPUID_HT */
503 .features =
504 PPRO_FEATURES |
505 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
506 CPUID_PSE36,
507 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
508 .ext_features =
509 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
510 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
511 .ext2_features =
512 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
513 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
514 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
515 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
516 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
517 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
518 .ext3_features =
519 0,
520 .xlevel = 0x80000008,
521 .model_id = "Common KVM processor"
522 },
523 {
524 .name = "qemu32",
525 .level = 4,
526 .vendor = CPUID_VENDOR_INTEL,
527 .family = 6,
528 .model = 3,
529 .stepping = 3,
530 .features =
531 PPRO_FEATURES,
532 .ext_features =
533 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
534 .xlevel = 0x80000004,
535 },
536 {
537 .name = "kvm32",
538 .level = 5,
539 .vendor = CPUID_VENDOR_INTEL,
540 .family = 15,
541 .model = 6,
542 .stepping = 1,
543 .features =
544 PPRO_FEATURES |
545 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
546 .ext_features =
547 CPUID_EXT_SSE3,
548 .ext2_features =
549 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
550 .ext3_features =
551 0,
552 .xlevel = 0x80000008,
553 .model_id = "Common 32-bit KVM processor"
554 },
555 {
556 .name = "coreduo",
557 .level = 10,
558 .vendor = CPUID_VENDOR_INTEL,
559 .family = 6,
560 .model = 14,
561 .stepping = 8,
562 .features =
563 PPRO_FEATURES | CPUID_VME |
564 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
565 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
566 .ext_features =
567 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
568 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
569 .ext2_features =
570 CPUID_EXT2_NX,
571 .xlevel = 0x80000008,
572 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
573 },
574 {
575 .name = "486",
576 .level = 1,
577 .vendor = CPUID_VENDOR_INTEL,
578 .family = 4,
579 .model = 0,
580 .stepping = 0,
581 .features =
582 I486_FEATURES,
583 .xlevel = 0,
584 },
585 {
586 .name = "pentium",
587 .level = 1,
588 .vendor = CPUID_VENDOR_INTEL,
589 .family = 5,
590 .model = 4,
591 .stepping = 3,
592 .features =
593 PENTIUM_FEATURES,
594 .xlevel = 0,
595 },
596 {
597 .name = "pentium2",
598 .level = 2,
599 .vendor = CPUID_VENDOR_INTEL,
600 .family = 6,
601 .model = 5,
602 .stepping = 2,
603 .features =
604 PENTIUM2_FEATURES,
605 .xlevel = 0,
606 },
607 {
608 .name = "pentium3",
609 .level = 2,
610 .vendor = CPUID_VENDOR_INTEL,
611 .family = 6,
612 .model = 7,
613 .stepping = 3,
614 .features =
615 PENTIUM3_FEATURES,
616 .xlevel = 0,
617 },
618 {
619 .name = "athlon",
620 .level = 2,
621 .vendor = CPUID_VENDOR_AMD,
622 .family = 6,
623 .model = 2,
624 .stepping = 3,
625 .features =
626 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
627 CPUID_MCA,
628 .ext2_features =
629 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
630 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
631 .xlevel = 0x80000008,
632 },
633 {
634 .name = "n270",
635 /* original is on level 10 */
636 .level = 5,
637 .vendor = CPUID_VENDOR_INTEL,
638 .family = 6,
639 .model = 28,
640 .stepping = 2,
641 .features =
642 PPRO_FEATURES |
643 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
644 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
645 /* Some CPUs got no CPUID_SEP */
646 .ext_features =
647 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
648 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
649 .ext2_features =
650 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
651 CPUID_EXT2_NX,
652 .ext3_features =
653 CPUID_EXT3_LAHF_LM,
654 .xlevel = 0x8000000A,
655 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
656 },
657 {
658 .name = "Conroe",
659 .level = 2,
660 .vendor = CPUID_VENDOR_INTEL,
661 .family = 6,
662 .model = 2,
663 .stepping = 3,
664 .features =
665 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
666 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
667 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
668 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
669 CPUID_DE | CPUID_FP87,
670 .ext_features =
671 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
672 .ext2_features =
673 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
674 .ext3_features =
675 CPUID_EXT3_LAHF_LM,
676 .xlevel = 0x8000000A,
677 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
678 },
679 {
680 .name = "Penryn",
681 .level = 2,
682 .vendor = CPUID_VENDOR_INTEL,
683 .family = 6,
684 .model = 2,
685 .stepping = 3,
686 .features =
687 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
688 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
689 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
690 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
691 CPUID_DE | CPUID_FP87,
692 .ext_features =
693 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
694 CPUID_EXT_SSE3,
695 .ext2_features =
696 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
697 .ext3_features =
698 CPUID_EXT3_LAHF_LM,
699 .xlevel = 0x8000000A,
700 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
701 },
702 {
703 .name = "Nehalem",
704 .level = 2,
705 .vendor = CPUID_VENDOR_INTEL,
706 .family = 6,
707 .model = 2,
708 .stepping = 3,
709 .features =
710 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
711 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
712 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
713 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
714 CPUID_DE | CPUID_FP87,
715 .ext_features =
716 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
717 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
718 .ext2_features =
719 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
720 .ext3_features =
721 CPUID_EXT3_LAHF_LM,
722 .xlevel = 0x8000000A,
723 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
724 },
725 {
726 .name = "Westmere",
727 .level = 11,
728 .vendor = CPUID_VENDOR_INTEL,
729 .family = 6,
730 .model = 44,
731 .stepping = 1,
732 .features =
733 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
734 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
735 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
736 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
737 CPUID_DE | CPUID_FP87,
738 .ext_features =
739 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
740 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
741 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
742 .ext2_features =
743 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
744 .ext3_features =
745 CPUID_EXT3_LAHF_LM,
746 .xlevel = 0x8000000A,
747 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
748 },
749 {
750 .name = "SandyBridge",
751 .level = 0xd,
752 .vendor = CPUID_VENDOR_INTEL,
753 .family = 6,
754 .model = 42,
755 .stepping = 1,
756 .features =
757 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
758 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
759 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
760 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
761 CPUID_DE | CPUID_FP87,
762 .ext_features =
763 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
764 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
765 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
766 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
767 CPUID_EXT_SSE3,
768 .ext2_features =
769 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
770 CPUID_EXT2_SYSCALL,
771 .ext3_features =
772 CPUID_EXT3_LAHF_LM,
773 .xlevel = 0x8000000A,
774 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
775 },
776 {
777 .name = "Haswell",
778 .level = 0xd,
779 .vendor = CPUID_VENDOR_INTEL,
780 .family = 6,
781 .model = 60,
782 .stepping = 1,
783 .features =
784 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
785 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
786 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
787 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
788 CPUID_DE | CPUID_FP87,
789 .ext_features =
790 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
791 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
792 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
793 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
794 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
795 CPUID_EXT_PCID,
796 .ext2_features =
797 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
798 CPUID_EXT2_SYSCALL,
799 .ext3_features =
800 CPUID_EXT3_LAHF_LM,
801 .cpuid_7_0_ebx_features =
802 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
803 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
804 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
805 CPUID_7_0_EBX_RTM,
806 .xlevel = 0x8000000A,
807 .model_id = "Intel Core Processor (Haswell)",
808 },
809 {
810 .name = "Opteron_G1",
811 .level = 5,
812 .vendor = CPUID_VENDOR_AMD,
813 .family = 15,
814 .model = 6,
815 .stepping = 1,
816 .features =
817 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
818 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
819 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
820 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
821 CPUID_DE | CPUID_FP87,
822 .ext_features =
823 CPUID_EXT_SSE3,
824 .ext2_features =
825 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
826 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
827 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
828 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
829 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
830 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
831 .xlevel = 0x80000008,
832 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
833 },
834 {
835 .name = "Opteron_G2",
836 .level = 5,
837 .vendor = CPUID_VENDOR_AMD,
838 .family = 15,
839 .model = 6,
840 .stepping = 1,
841 .features =
842 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
843 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
844 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
845 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
846 CPUID_DE | CPUID_FP87,
847 .ext_features =
848 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
849 .ext2_features =
850 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
851 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
852 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
853 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
854 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
855 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
856 CPUID_EXT2_DE | CPUID_EXT2_FPU,
857 .ext3_features =
858 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
859 .xlevel = 0x80000008,
860 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
861 },
862 {
863 .name = "Opteron_G3",
864 .level = 5,
865 .vendor = CPUID_VENDOR_AMD,
866 .family = 15,
867 .model = 6,
868 .stepping = 1,
869 .features =
870 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
871 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
872 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
873 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
874 CPUID_DE | CPUID_FP87,
875 .ext_features =
876 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
877 CPUID_EXT_SSE3,
878 .ext2_features =
879 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
880 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
881 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
882 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
883 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
884 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
885 CPUID_EXT2_DE | CPUID_EXT2_FPU,
886 .ext3_features =
887 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
888 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
889 .xlevel = 0x80000008,
890 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
891 },
892 {
893 .name = "Opteron_G4",
894 .level = 0xd,
895 .vendor = CPUID_VENDOR_AMD,
896 .family = 21,
897 .model = 1,
898 .stepping = 2,
899 .features =
900 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
901 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
902 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
903 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
904 CPUID_DE | CPUID_FP87,
905 .ext_features =
906 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
907 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
908 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
909 CPUID_EXT_SSE3,
910 .ext2_features =
911 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
912 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
913 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
914 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
915 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
916 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
917 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
918 .ext3_features =
919 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
920 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
921 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
922 CPUID_EXT3_LAHF_LM,
923 .xlevel = 0x8000001A,
924 .model_id = "AMD Opteron 62xx class CPU",
925 },
926 {
927 .name = "Opteron_G5",
928 .level = 0xd,
929 .vendor = CPUID_VENDOR_AMD,
930 .family = 21,
931 .model = 2,
932 .stepping = 0,
933 .features =
934 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
935 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
936 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
937 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
938 CPUID_DE | CPUID_FP87,
939 .ext_features =
940 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
941 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
942 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
943 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
944 .ext2_features =
945 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
946 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
947 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
948 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
949 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
950 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
951 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
952 .ext3_features =
953 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
954 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
955 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
956 CPUID_EXT3_LAHF_LM,
957 .xlevel = 0x8000001A,
958 .model_id = "AMD Opteron 63xx class CPU",
959 },
960 };
961
962 #ifdef CONFIG_KVM
963 static int cpu_x86_fill_model_id(char *str)
964 {
965 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
966 int i;
967
968 for (i = 0; i < 3; i++) {
969 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
970 memcpy(str + i * 16 + 0, &eax, 4);
971 memcpy(str + i * 16 + 4, &ebx, 4);
972 memcpy(str + i * 16 + 8, &ecx, 4);
973 memcpy(str + i * 16 + 12, &edx, 4);
974 }
975 return 0;
976 }
977 #endif
978
979 /* Fill a x86_def_t struct with information about the host CPU, and
980 * the CPU features supported by the host hardware + host kernel
981 *
982 * This function may be called only if KVM is enabled.
983 */
984 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
985 {
986 #ifdef CONFIG_KVM
987 KVMState *s = kvm_state;
988 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
989
990 assert(kvm_enabled());
991
992 x86_cpu_def->name = "host";
993 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
994 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
995
996 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
997 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
998 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
999 x86_cpu_def->stepping = eax & 0x0F;
1000
1001 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1002 x86_cpu_def->features =
1003 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
1004 x86_cpu_def->ext_features =
1005 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
1006
1007 if (x86_cpu_def->level >= 7) {
1008 x86_cpu_def->cpuid_7_0_ebx_features =
1009 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
1010 } else {
1011 x86_cpu_def->cpuid_7_0_ebx_features = 0;
1012 }
1013
1014 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1015 x86_cpu_def->ext2_features =
1016 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1017 x86_cpu_def->ext3_features =
1018 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1019
1020 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1021
1022 /* Call Centaur's CPUID instruction. */
1023 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
1024 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
1025 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1026 if (eax >= 0xC0000001) {
1027 /* Support VIA max extended level */
1028 x86_cpu_def->xlevel2 = eax;
1029 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
1030 x86_cpu_def->ext4_features =
1031 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1032 }
1033 }
1034
1035 /* Other KVM-specific feature fields: */
1036 x86_cpu_def->svm_features =
1037 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1038 x86_cpu_def->kvm_features =
1039 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1040
1041 #endif /* CONFIG_KVM */
1042 }
1043
1044 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1045 {
1046 int i;
1047
1048 for (i = 0; i < 32; ++i)
1049 if (1 << i & mask) {
1050 const char *reg = get_register_name_32(f->cpuid_reg);
1051 assert(reg);
1052 fprintf(stderr, "warning: host doesn't support requested feature: "
1053 "CPUID.%02XH:%s%s%s [bit %d]\n",
1054 f->cpuid_eax, reg,
1055 f->feat_names[i] ? "." : "",
1056 f->feat_names[i] ? f->feat_names[i] : "", i);
1057 break;
1058 }
1059 return 0;
1060 }
1061
1062 /* Check if all requested cpu flags are making their way to the guest
1063 *
1064 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1065 *
1066 * This function may be called only if KVM is enabled.
1067 */
1068 static int kvm_check_features_against_host(X86CPU *cpu)
1069 {
1070 CPUX86State *env = &cpu->env;
1071 x86_def_t host_def;
1072 uint32_t mask;
1073 int rv, i;
1074 struct model_features_t ft[] = {
1075 {&env->cpuid_features,
1076 &host_def.features,
1077 FEAT_1_EDX },
1078 {&env->cpuid_ext_features,
1079 &host_def.ext_features,
1080 FEAT_1_ECX },
1081 {&env->cpuid_ext2_features,
1082 &host_def.ext2_features,
1083 FEAT_8000_0001_EDX },
1084 {&env->cpuid_ext3_features,
1085 &host_def.ext3_features,
1086 FEAT_8000_0001_ECX },
1087 {&env->cpuid_ext4_features,
1088 &host_def.ext4_features,
1089 FEAT_C000_0001_EDX },
1090 {&env->cpuid_7_0_ebx_features,
1091 &host_def.cpuid_7_0_ebx_features,
1092 FEAT_7_0_EBX },
1093 {&env->cpuid_svm_features,
1094 &host_def.svm_features,
1095 FEAT_SVM },
1096 {&env->cpuid_kvm_features,
1097 &host_def.kvm_features,
1098 FEAT_KVM },
1099 };
1100
1101 assert(kvm_enabled());
1102
1103 kvm_cpu_fill_host(&host_def);
1104 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1105 FeatureWord w = ft[i].feat_word;
1106 FeatureWordInfo *wi = &feature_word_info[w];
1107 for (mask = 1; mask; mask <<= 1) {
1108 if (*ft[i].guest_feat & mask &&
1109 !(*ft[i].host_feat & mask)) {
1110 unavailable_host_feature(wi, mask);
1111 rv = 1;
1112 }
1113 }
1114 }
1115 return rv;
1116 }
1117
1118 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1119 const char *name, Error **errp)
1120 {
1121 X86CPU *cpu = X86_CPU(obj);
1122 CPUX86State *env = &cpu->env;
1123 int64_t value;
1124
1125 value = (env->cpuid_version >> 8) & 0xf;
1126 if (value == 0xf) {
1127 value += (env->cpuid_version >> 20) & 0xff;
1128 }
1129 visit_type_int(v, &value, name, errp);
1130 }
1131
1132 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1133 const char *name, Error **errp)
1134 {
1135 X86CPU *cpu = X86_CPU(obj);
1136 CPUX86State *env = &cpu->env;
1137 const int64_t min = 0;
1138 const int64_t max = 0xff + 0xf;
1139 int64_t value;
1140
1141 visit_type_int(v, &value, name, errp);
1142 if (error_is_set(errp)) {
1143 return;
1144 }
1145 if (value < min || value > max) {
1146 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1147 name ? name : "null", value, min, max);
1148 return;
1149 }
1150
1151 env->cpuid_version &= ~0xff00f00;
1152 if (value > 0x0f) {
1153 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1154 } else {
1155 env->cpuid_version |= value << 8;
1156 }
1157 }
1158
1159 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1160 const char *name, Error **errp)
1161 {
1162 X86CPU *cpu = X86_CPU(obj);
1163 CPUX86State *env = &cpu->env;
1164 int64_t value;
1165
1166 value = (env->cpuid_version >> 4) & 0xf;
1167 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1168 visit_type_int(v, &value, name, errp);
1169 }
1170
1171 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1172 const char *name, Error **errp)
1173 {
1174 X86CPU *cpu = X86_CPU(obj);
1175 CPUX86State *env = &cpu->env;
1176 const int64_t min = 0;
1177 const int64_t max = 0xff;
1178 int64_t value;
1179
1180 visit_type_int(v, &value, name, errp);
1181 if (error_is_set(errp)) {
1182 return;
1183 }
1184 if (value < min || value > max) {
1185 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1186 name ? name : "null", value, min, max);
1187 return;
1188 }
1189
1190 env->cpuid_version &= ~0xf00f0;
1191 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1192 }
1193
1194 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1195 void *opaque, const char *name,
1196 Error **errp)
1197 {
1198 X86CPU *cpu = X86_CPU(obj);
1199 CPUX86State *env = &cpu->env;
1200 int64_t value;
1201
1202 value = env->cpuid_version & 0xf;
1203 visit_type_int(v, &value, name, errp);
1204 }
1205
1206 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1207 void *opaque, const char *name,
1208 Error **errp)
1209 {
1210 X86CPU *cpu = X86_CPU(obj);
1211 CPUX86State *env = &cpu->env;
1212 const int64_t min = 0;
1213 const int64_t max = 0xf;
1214 int64_t value;
1215
1216 visit_type_int(v, &value, name, errp);
1217 if (error_is_set(errp)) {
1218 return;
1219 }
1220 if (value < min || value > max) {
1221 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1222 name ? name : "null", value, min, max);
1223 return;
1224 }
1225
1226 env->cpuid_version &= ~0xf;
1227 env->cpuid_version |= value & 0xf;
1228 }
1229
1230 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1231 const char *name, Error **errp)
1232 {
1233 X86CPU *cpu = X86_CPU(obj);
1234
1235 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1236 }
1237
1238 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1239 const char *name, Error **errp)
1240 {
1241 X86CPU *cpu = X86_CPU(obj);
1242
1243 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1244 }
1245
1246 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1247 const char *name, Error **errp)
1248 {
1249 X86CPU *cpu = X86_CPU(obj);
1250
1251 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1252 }
1253
1254 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1255 const char *name, Error **errp)
1256 {
1257 X86CPU *cpu = X86_CPU(obj);
1258
1259 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1260 }
1261
1262 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1263 {
1264 X86CPU *cpu = X86_CPU(obj);
1265 CPUX86State *env = &cpu->env;
1266 char *value;
1267
1268 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1269 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1270 env->cpuid_vendor3);
1271 return value;
1272 }
1273
1274 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1275 Error **errp)
1276 {
1277 X86CPU *cpu = X86_CPU(obj);
1278 CPUX86State *env = &cpu->env;
1279 int i;
1280
1281 if (strlen(value) != CPUID_VENDOR_SZ) {
1282 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1283 "vendor", value);
1284 return;
1285 }
1286
1287 env->cpuid_vendor1 = 0;
1288 env->cpuid_vendor2 = 0;
1289 env->cpuid_vendor3 = 0;
1290 for (i = 0; i < 4; i++) {
1291 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1292 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1293 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1294 }
1295 }
1296
1297 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1298 {
1299 X86CPU *cpu = X86_CPU(obj);
1300 CPUX86State *env = &cpu->env;
1301 char *value;
1302 int i;
1303
1304 value = g_malloc(48 + 1);
1305 for (i = 0; i < 48; i++) {
1306 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1307 }
1308 value[48] = '\0';
1309 return value;
1310 }
1311
1312 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1313 Error **errp)
1314 {
1315 X86CPU *cpu = X86_CPU(obj);
1316 CPUX86State *env = &cpu->env;
1317 int c, len, i;
1318
1319 if (model_id == NULL) {
1320 model_id = "";
1321 }
1322 len = strlen(model_id);
1323 memset(env->cpuid_model, 0, 48);
1324 for (i = 0; i < 48; i++) {
1325 if (i >= len) {
1326 c = '\0';
1327 } else {
1328 c = (uint8_t)model_id[i];
1329 }
1330 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1331 }
1332 }
1333
1334 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1335 const char *name, Error **errp)
1336 {
1337 X86CPU *cpu = X86_CPU(obj);
1338 int64_t value;
1339
1340 value = cpu->env.tsc_khz * 1000;
1341 visit_type_int(v, &value, name, errp);
1342 }
1343
1344 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1345 const char *name, Error **errp)
1346 {
1347 X86CPU *cpu = X86_CPU(obj);
1348 const int64_t min = 0;
1349 const int64_t max = INT64_MAX;
1350 int64_t value;
1351
1352 visit_type_int(v, &value, name, errp);
1353 if (error_is_set(errp)) {
1354 return;
1355 }
1356 if (value < min || value > max) {
1357 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1358 name ? name : "null", value, min, max);
1359 return;
1360 }
1361
1362 cpu->env.tsc_khz = value / 1000;
1363 }
1364
1365 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1366 const char *name, Error **errp)
1367 {
1368 X86CPU *cpu = X86_CPU(obj);
1369 int64_t value = cpu->env.cpuid_apic_id;
1370
1371 visit_type_int(v, &value, name, errp);
1372 }
1373
1374 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1375 const char *name, Error **errp)
1376 {
1377 X86CPU *cpu = X86_CPU(obj);
1378 DeviceState *dev = DEVICE(obj);
1379 const int64_t min = 0;
1380 const int64_t max = UINT32_MAX;
1381 Error *error = NULL;
1382 int64_t value;
1383
1384 if (dev->realized) {
1385 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1386 "it was realized", name, object_get_typename(obj));
1387 return;
1388 }
1389
1390 visit_type_int(v, &value, name, &error);
1391 if (error) {
1392 error_propagate(errp, error);
1393 return;
1394 }
1395 if (value < min || value > max) {
1396 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1397 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1398 object_get_typename(obj), name, value, min, max);
1399 return;
1400 }
1401
1402 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1403 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1404 return;
1405 }
1406 cpu->env.cpuid_apic_id = value;
1407 }
1408
1409 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1410 {
1411 x86_def_t *def;
1412 int i;
1413
1414 if (name == NULL) {
1415 return -1;
1416 }
1417 if (kvm_enabled() && strcmp(name, "host") == 0) {
1418 kvm_cpu_fill_host(x86_cpu_def);
1419 return 0;
1420 }
1421
1422 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1423 def = &builtin_x86_defs[i];
1424 if (strcmp(name, def->name) == 0) {
1425 memcpy(x86_cpu_def, def, sizeof(*def));
1426 /* sysenter isn't supported in compatibility mode on AMD,
1427 * syscall isn't supported in compatibility mode on Intel.
1428 * Normally we advertise the actual CPU vendor, but you can
1429 * override this using the 'vendor' property if you want to use
1430 * KVM's sysenter/syscall emulation in compatibility mode and
1431 * when doing cross vendor migration
1432 */
1433 if (kvm_enabled()) {
1434 uint32_t ebx = 0, ecx = 0, edx = 0;
1435 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1436 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1437 }
1438 return 0;
1439 }
1440 }
1441
1442 return -1;
1443 }
1444
1445 /* Convert all '_' in a feature string option name to '-', to make feature
1446 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1447 */
1448 static inline void feat2prop(char *s)
1449 {
1450 while ((s = strchr(s, '_'))) {
1451 *s = '-';
1452 }
1453 }
1454
1455 /* Parse "+feature,-feature,feature=foo" CPU feature string
1456 */
1457 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1458 {
1459 char *featurestr; /* Single 'key=value" string being parsed */
1460 /* Features to be added */
1461 FeatureWordArray plus_features = { 0 };
1462 /* Features to be removed */
1463 FeatureWordArray minus_features = { 0 };
1464 uint32_t numvalue;
1465 CPUX86State *env = &cpu->env;
1466
1467 featurestr = features ? strtok(features, ",") : NULL;
1468
1469 while (featurestr) {
1470 char *val;
1471 if (featurestr[0] == '+') {
1472 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1473 } else if (featurestr[0] == '-') {
1474 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1475 } else if ((val = strchr(featurestr, '='))) {
1476 *val = 0; val++;
1477 feat2prop(featurestr);
1478 if (!strcmp(featurestr, "family")) {
1479 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1480 } else if (!strcmp(featurestr, "model")) {
1481 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1482 } else if (!strcmp(featurestr, "stepping")) {
1483 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1484 } else if (!strcmp(featurestr, "level")) {
1485 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1486 } else if (!strcmp(featurestr, "xlevel")) {
1487 char *err;
1488 char num[32];
1489
1490 numvalue = strtoul(val, &err, 0);
1491 if (!*val || *err) {
1492 error_setg(errp, "bad numerical value %s", val);
1493 goto out;
1494 }
1495 if (numvalue < 0x80000000) {
1496 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1497 ", fixup will be removed in future versions\n");
1498 numvalue += 0x80000000;
1499 }
1500 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1501 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1502 } else if (!strcmp(featurestr, "vendor")) {
1503 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1504 } else if (!strcmp(featurestr, "model-id")) {
1505 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1506 } else if (!strcmp(featurestr, "tsc-freq")) {
1507 int64_t tsc_freq;
1508 char *err;
1509 char num[32];
1510
1511 tsc_freq = strtosz_suffix_unit(val, &err,
1512 STRTOSZ_DEFSUFFIX_B, 1000);
1513 if (tsc_freq < 0 || *err) {
1514 error_setg(errp, "bad numerical value %s", val);
1515 goto out;
1516 }
1517 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1518 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1519 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1520 char *err;
1521 numvalue = strtoul(val, &err, 0);
1522 if (!*val || *err) {
1523 error_setg(errp, "bad numerical value %s", val);
1524 goto out;
1525 }
1526 hyperv_set_spinlock_retries(numvalue);
1527 } else {
1528 error_setg(errp, "unrecognized feature %s", featurestr);
1529 goto out;
1530 }
1531 } else if (!strcmp(featurestr, "check")) {
1532 check_cpuid = 1;
1533 } else if (!strcmp(featurestr, "enforce")) {
1534 check_cpuid = enforce_cpuid = 1;
1535 } else if (!strcmp(featurestr, "hv_relaxed")) {
1536 hyperv_enable_relaxed_timing(true);
1537 } else if (!strcmp(featurestr, "hv_vapic")) {
1538 hyperv_enable_vapic_recommended(true);
1539 } else {
1540 error_setg(errp, "feature string `%s' not in format (+feature|"
1541 "-feature|feature=xyz)", featurestr);
1542 goto out;
1543 }
1544 if (error_is_set(errp)) {
1545 goto out;
1546 }
1547 featurestr = strtok(NULL, ",");
1548 }
1549 env->cpuid_features |= plus_features[FEAT_1_EDX];
1550 env->cpuid_ext_features |= plus_features[FEAT_1_ECX];
1551 env->cpuid_ext2_features |= plus_features[FEAT_8000_0001_EDX];
1552 env->cpuid_ext3_features |= plus_features[FEAT_8000_0001_ECX];
1553 env->cpuid_ext4_features |= plus_features[FEAT_C000_0001_EDX];
1554 env->cpuid_kvm_features |= plus_features[FEAT_KVM];
1555 env->cpuid_svm_features |= plus_features[FEAT_SVM];
1556 env->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1557 env->cpuid_features &= ~minus_features[FEAT_1_EDX];
1558 env->cpuid_ext_features &= ~minus_features[FEAT_1_ECX];
1559 env->cpuid_ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1560 env->cpuid_ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1561 env->cpuid_ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1562 env->cpuid_kvm_features &= ~minus_features[FEAT_KVM];
1563 env->cpuid_svm_features &= ~minus_features[FEAT_SVM];
1564 env->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1565
1566 out:
1567 return;
1568 }
1569
1570 /* generate a composite string into buf of all cpuid names in featureset
1571 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1572 * if flags, suppress names undefined in featureset.
1573 */
1574 static void listflags(char *buf, int bufsize, uint32_t fbits,
1575 const char **featureset, uint32_t flags)
1576 {
1577 const char **p = &featureset[31];
1578 char *q, *b, bit;
1579 int nc;
1580
1581 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1582 *buf = '\0';
1583 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1584 if (fbits & 1 << bit && (*p || !flags)) {
1585 if (*p)
1586 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1587 else
1588 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1589 if (bufsize <= nc) {
1590 if (b) {
1591 memcpy(b, "...", sizeof("..."));
1592 }
1593 return;
1594 }
1595 q += nc;
1596 bufsize -= nc;
1597 }
1598 }
1599
1600 /* generate CPU information. */
1601 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1602 {
1603 x86_def_t *def;
1604 char buf[256];
1605 int i;
1606
1607 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1608 def = &builtin_x86_defs[i];
1609 snprintf(buf, sizeof(buf), "%s", def->name);
1610 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1611 }
1612 #ifdef CONFIG_KVM
1613 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1614 "KVM processor with all supported host features "
1615 "(only available in KVM mode)");
1616 #endif
1617
1618 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1619 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1620 FeatureWordInfo *fw = &feature_word_info[i];
1621
1622 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1623 (*cpu_fprintf)(f, " %s\n", buf);
1624 }
1625 }
1626
1627 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1628 {
1629 CpuDefinitionInfoList *cpu_list = NULL;
1630 x86_def_t *def;
1631 int i;
1632
1633 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1634 CpuDefinitionInfoList *entry;
1635 CpuDefinitionInfo *info;
1636
1637 def = &builtin_x86_defs[i];
1638 info = g_malloc0(sizeof(*info));
1639 info->name = g_strdup(def->name);
1640
1641 entry = g_malloc0(sizeof(*entry));
1642 entry->value = info;
1643 entry->next = cpu_list;
1644 cpu_list = entry;
1645 }
1646
1647 return cpu_list;
1648 }
1649
1650 #ifdef CONFIG_KVM
1651 static void filter_features_for_kvm(X86CPU *cpu)
1652 {
1653 CPUX86State *env = &cpu->env;
1654 KVMState *s = kvm_state;
1655
1656 env->cpuid_features &=
1657 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1658 env->cpuid_ext_features &=
1659 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1660 env->cpuid_ext2_features &=
1661 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1662 env->cpuid_ext3_features &=
1663 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1664 env->cpuid_svm_features &=
1665 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1666 env->cpuid_7_0_ebx_features &=
1667 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1668 env->cpuid_kvm_features &=
1669 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1670 env->cpuid_ext4_features &=
1671 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1672
1673 }
1674 #endif
1675
1676 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1677 {
1678 CPUX86State *env = &cpu->env;
1679 x86_def_t def1, *def = &def1;
1680
1681 memset(def, 0, sizeof(*def));
1682
1683 if (cpu_x86_find_by_name(def, name) < 0) {
1684 error_setg(errp, "Unable to find CPU definition: %s", name);
1685 return;
1686 }
1687
1688 if (kvm_enabled()) {
1689 def->kvm_features |= kvm_default_features;
1690 }
1691 def->ext_features |= CPUID_EXT_HYPERVISOR;
1692
1693 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1694 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1695 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1696 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1697 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1698 env->cpuid_features = def->features;
1699 env->cpuid_ext_features = def->ext_features;
1700 env->cpuid_ext2_features = def->ext2_features;
1701 env->cpuid_ext3_features = def->ext3_features;
1702 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1703 env->cpuid_kvm_features = def->kvm_features;
1704 env->cpuid_svm_features = def->svm_features;
1705 env->cpuid_ext4_features = def->ext4_features;
1706 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1707 env->cpuid_xlevel2 = def->xlevel2;
1708
1709 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1710 }
1711
1712 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1713 Error **errp)
1714 {
1715 X86CPU *cpu = NULL;
1716 CPUX86State *env;
1717 gchar **model_pieces;
1718 char *name, *features;
1719 Error *error = NULL;
1720
1721 model_pieces = g_strsplit(cpu_model, ",", 2);
1722 if (!model_pieces[0]) {
1723 error_setg(&error, "Invalid/empty CPU model name");
1724 goto out;
1725 }
1726 name = model_pieces[0];
1727 features = model_pieces[1];
1728
1729 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1730 #ifndef CONFIG_USER_ONLY
1731 if (icc_bridge == NULL) {
1732 error_setg(&error, "Invalid icc-bridge value");
1733 goto out;
1734 }
1735 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1736 object_unref(OBJECT(cpu));
1737 #endif
1738 env = &cpu->env;
1739 env->cpu_model_str = cpu_model;
1740
1741 cpu_x86_register(cpu, name, &error);
1742 if (error) {
1743 goto out;
1744 }
1745
1746 cpu_x86_parse_featurestr(cpu, features, &error);
1747 if (error) {
1748 goto out;
1749 }
1750
1751 out:
1752 error_propagate(errp, error);
1753 g_strfreev(model_pieces);
1754 return cpu;
1755 }
1756
1757 X86CPU *cpu_x86_init(const char *cpu_model)
1758 {
1759 Error *error = NULL;
1760 X86CPU *cpu;
1761
1762 cpu = cpu_x86_create(cpu_model, NULL, &error);
1763 if (error) {
1764 goto out;
1765 }
1766
1767 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1768
1769 out:
1770 if (error) {
1771 fprintf(stderr, "%s\n", error_get_pretty(error));
1772 error_free(error);
1773 if (cpu != NULL) {
1774 object_unref(OBJECT(cpu));
1775 cpu = NULL;
1776 }
1777 }
1778 return cpu;
1779 }
1780
1781 #if !defined(CONFIG_USER_ONLY)
1782
1783 void cpu_clear_apic_feature(CPUX86State *env)
1784 {
1785 env->cpuid_features &= ~CPUID_APIC;
1786 }
1787
1788 #endif /* !CONFIG_USER_ONLY */
1789
1790 /* Initialize list of CPU models, filling some non-static fields if necessary
1791 */
1792 void x86_cpudef_setup(void)
1793 {
1794 int i, j;
1795 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1796
1797 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1798 x86_def_t *def = &builtin_x86_defs[i];
1799
1800 /* Look for specific "cpudef" models that */
1801 /* have the QEMU version in .model_id */
1802 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1803 if (strcmp(model_with_versions[j], def->name) == 0) {
1804 pstrcpy(def->model_id, sizeof(def->model_id),
1805 "QEMU Virtual CPU version ");
1806 pstrcat(def->model_id, sizeof(def->model_id),
1807 qemu_get_version());
1808 break;
1809 }
1810 }
1811 }
1812 }
1813
1814 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1815 uint32_t *ecx, uint32_t *edx)
1816 {
1817 *ebx = env->cpuid_vendor1;
1818 *edx = env->cpuid_vendor2;
1819 *ecx = env->cpuid_vendor3;
1820 }
1821
1822 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1823 uint32_t *eax, uint32_t *ebx,
1824 uint32_t *ecx, uint32_t *edx)
1825 {
1826 X86CPU *cpu = x86_env_get_cpu(env);
1827 CPUState *cs = CPU(cpu);
1828
1829 /* test if maximum index reached */
1830 if (index & 0x80000000) {
1831 if (index > env->cpuid_xlevel) {
1832 if (env->cpuid_xlevel2 > 0) {
1833 /* Handle the Centaur's CPUID instruction. */
1834 if (index > env->cpuid_xlevel2) {
1835 index = env->cpuid_xlevel2;
1836 } else if (index < 0xC0000000) {
1837 index = env->cpuid_xlevel;
1838 }
1839 } else {
1840 /* Intel documentation states that invalid EAX input will
1841 * return the same information as EAX=cpuid_level
1842 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1843 */
1844 index = env->cpuid_level;
1845 }
1846 }
1847 } else {
1848 if (index > env->cpuid_level)
1849 index = env->cpuid_level;
1850 }
1851
1852 switch(index) {
1853 case 0:
1854 *eax = env->cpuid_level;
1855 get_cpuid_vendor(env, ebx, ecx, edx);
1856 break;
1857 case 1:
1858 *eax = env->cpuid_version;
1859 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1860 *ecx = env->cpuid_ext_features;
1861 *edx = env->cpuid_features;
1862 if (cs->nr_cores * cs->nr_threads > 1) {
1863 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1864 *edx |= 1 << 28; /* HTT bit */
1865 }
1866 break;
1867 case 2:
1868 /* cache info: needed for Pentium Pro compatibility */
1869 *eax = 1;
1870 *ebx = 0;
1871 *ecx = 0;
1872 *edx = 0x2c307d;
1873 break;
1874 case 4:
1875 /* cache info: needed for Core compatibility */
1876 if (cs->nr_cores > 1) {
1877 *eax = (cs->nr_cores - 1) << 26;
1878 } else {
1879 *eax = 0;
1880 }
1881 switch (count) {
1882 case 0: /* L1 dcache info */
1883 *eax |= 0x0000121;
1884 *ebx = 0x1c0003f;
1885 *ecx = 0x000003f;
1886 *edx = 0x0000001;
1887 break;
1888 case 1: /* L1 icache info */
1889 *eax |= 0x0000122;
1890 *ebx = 0x1c0003f;
1891 *ecx = 0x000003f;
1892 *edx = 0x0000001;
1893 break;
1894 case 2: /* L2 cache info */
1895 *eax |= 0x0000143;
1896 if (cs->nr_threads > 1) {
1897 *eax |= (cs->nr_threads - 1) << 14;
1898 }
1899 *ebx = 0x3c0003f;
1900 *ecx = 0x0000fff;
1901 *edx = 0x0000001;
1902 break;
1903 default: /* end of info */
1904 *eax = 0;
1905 *ebx = 0;
1906 *ecx = 0;
1907 *edx = 0;
1908 break;
1909 }
1910 break;
1911 case 5:
1912 /* mwait info: needed for Core compatibility */
1913 *eax = 0; /* Smallest monitor-line size in bytes */
1914 *ebx = 0; /* Largest monitor-line size in bytes */
1915 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1916 *edx = 0;
1917 break;
1918 case 6:
1919 /* Thermal and Power Leaf */
1920 *eax = 0;
1921 *ebx = 0;
1922 *ecx = 0;
1923 *edx = 0;
1924 break;
1925 case 7:
1926 /* Structured Extended Feature Flags Enumeration Leaf */
1927 if (count == 0) {
1928 *eax = 0; /* Maximum ECX value for sub-leaves */
1929 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1930 *ecx = 0; /* Reserved */
1931 *edx = 0; /* Reserved */
1932 } else {
1933 *eax = 0;
1934 *ebx = 0;
1935 *ecx = 0;
1936 *edx = 0;
1937 }
1938 break;
1939 case 9:
1940 /* Direct Cache Access Information Leaf */
1941 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1942 *ebx = 0;
1943 *ecx = 0;
1944 *edx = 0;
1945 break;
1946 case 0xA:
1947 /* Architectural Performance Monitoring Leaf */
1948 if (kvm_enabled()) {
1949 KVMState *s = cs->kvm_state;
1950
1951 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1952 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1953 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1954 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1955 } else {
1956 *eax = 0;
1957 *ebx = 0;
1958 *ecx = 0;
1959 *edx = 0;
1960 }
1961 break;
1962 case 0xD:
1963 /* Processor Extended State */
1964 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1965 *eax = 0;
1966 *ebx = 0;
1967 *ecx = 0;
1968 *edx = 0;
1969 break;
1970 }
1971 if (kvm_enabled()) {
1972 KVMState *s = cs->kvm_state;
1973
1974 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1975 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1976 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1977 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1978 } else {
1979 *eax = 0;
1980 *ebx = 0;
1981 *ecx = 0;
1982 *edx = 0;
1983 }
1984 break;
1985 case 0x80000000:
1986 *eax = env->cpuid_xlevel;
1987 *ebx = env->cpuid_vendor1;
1988 *edx = env->cpuid_vendor2;
1989 *ecx = env->cpuid_vendor3;
1990 break;
1991 case 0x80000001:
1992 *eax = env->cpuid_version;
1993 *ebx = 0;
1994 *ecx = env->cpuid_ext3_features;
1995 *edx = env->cpuid_ext2_features;
1996
1997 /* The Linux kernel checks for the CMPLegacy bit and
1998 * discards multiple thread information if it is set.
1999 * So dont set it here for Intel to make Linux guests happy.
2000 */
2001 if (cs->nr_cores * cs->nr_threads > 1) {
2002 uint32_t tebx, tecx, tedx;
2003 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2004 if (tebx != CPUID_VENDOR_INTEL_1 ||
2005 tedx != CPUID_VENDOR_INTEL_2 ||
2006 tecx != CPUID_VENDOR_INTEL_3) {
2007 *ecx |= 1 << 1; /* CmpLegacy bit */
2008 }
2009 }
2010 break;
2011 case 0x80000002:
2012 case 0x80000003:
2013 case 0x80000004:
2014 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2015 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2016 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2017 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2018 break;
2019 case 0x80000005:
2020 /* cache info (L1 cache) */
2021 *eax = 0x01ff01ff;
2022 *ebx = 0x01ff01ff;
2023 *ecx = 0x40020140;
2024 *edx = 0x40020140;
2025 break;
2026 case 0x80000006:
2027 /* cache info (L2 cache) */
2028 *eax = 0;
2029 *ebx = 0x42004200;
2030 *ecx = 0x02008140;
2031 *edx = 0;
2032 break;
2033 case 0x80000008:
2034 /* virtual & phys address size in low 2 bytes. */
2035 /* XXX: This value must match the one used in the MMU code. */
2036 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
2037 /* 64 bit processor */
2038 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2039 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2040 } else {
2041 if (env->cpuid_features & CPUID_PSE36) {
2042 *eax = 0x00000024; /* 36 bits physical */
2043 } else {
2044 *eax = 0x00000020; /* 32 bits physical */
2045 }
2046 }
2047 *ebx = 0;
2048 *ecx = 0;
2049 *edx = 0;
2050 if (cs->nr_cores * cs->nr_threads > 1) {
2051 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2052 }
2053 break;
2054 case 0x8000000A:
2055 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
2056 *eax = 0x00000001; /* SVM Revision */
2057 *ebx = 0x00000010; /* nr of ASIDs */
2058 *ecx = 0;
2059 *edx = env->cpuid_svm_features; /* optional features */
2060 } else {
2061 *eax = 0;
2062 *ebx = 0;
2063 *ecx = 0;
2064 *edx = 0;
2065 }
2066 break;
2067 case 0xC0000000:
2068 *eax = env->cpuid_xlevel2;
2069 *ebx = 0;
2070 *ecx = 0;
2071 *edx = 0;
2072 break;
2073 case 0xC0000001:
2074 /* Support for VIA CPU's CPUID instruction */
2075 *eax = env->cpuid_version;
2076 *ebx = 0;
2077 *ecx = 0;
2078 *edx = env->cpuid_ext4_features;
2079 break;
2080 case 0xC0000002:
2081 case 0xC0000003:
2082 case 0xC0000004:
2083 /* Reserved for the future, and now filled with zero */
2084 *eax = 0;
2085 *ebx = 0;
2086 *ecx = 0;
2087 *edx = 0;
2088 break;
2089 default:
2090 /* reserved values: zero */
2091 *eax = 0;
2092 *ebx = 0;
2093 *ecx = 0;
2094 *edx = 0;
2095 break;
2096 }
2097 }
2098
2099 /* CPUClass::reset() */
2100 static void x86_cpu_reset(CPUState *s)
2101 {
2102 X86CPU *cpu = X86_CPU(s);
2103 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2104 CPUX86State *env = &cpu->env;
2105 int i;
2106
2107 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2108 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
2109 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
2110 }
2111
2112 xcc->parent_reset(s);
2113
2114
2115 memset(env, 0, offsetof(CPUX86State, breakpoints));
2116
2117 tlb_flush(env, 1);
2118
2119 env->old_exception = -1;
2120
2121 /* init to reset state */
2122
2123 #ifdef CONFIG_SOFTMMU
2124 env->hflags |= HF_SOFTMMU_MASK;
2125 #endif
2126 env->hflags2 |= HF2_GIF_MASK;
2127
2128 cpu_x86_update_cr0(env, 0x60000010);
2129 env->a20_mask = ~0x0;
2130 env->smbase = 0x30000;
2131
2132 env->idt.limit = 0xffff;
2133 env->gdt.limit = 0xffff;
2134 env->ldt.limit = 0xffff;
2135 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2136 env->tr.limit = 0xffff;
2137 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2138
2139 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2140 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2141 DESC_R_MASK | DESC_A_MASK);
2142 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2143 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2144 DESC_A_MASK);
2145 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2146 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2147 DESC_A_MASK);
2148 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2149 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2150 DESC_A_MASK);
2151 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2152 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2153 DESC_A_MASK);
2154 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2155 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2156 DESC_A_MASK);
2157
2158 env->eip = 0xfff0;
2159 env->regs[R_EDX] = env->cpuid_version;
2160
2161 env->eflags = 0x2;
2162
2163 /* FPU init */
2164 for (i = 0; i < 8; i++) {
2165 env->fptags[i] = 1;
2166 }
2167 env->fpuc = 0x37f;
2168
2169 env->mxcsr = 0x1f80;
2170
2171 env->pat = 0x0007040600070406ULL;
2172 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2173
2174 memset(env->dr, 0, sizeof(env->dr));
2175 env->dr[6] = DR6_FIXED_1;
2176 env->dr[7] = DR7_FIXED_1;
2177 cpu_breakpoint_remove_all(env, BP_CPU);
2178 cpu_watchpoint_remove_all(env, BP_CPU);
2179
2180 #if !defined(CONFIG_USER_ONLY)
2181 /* We hard-wire the BSP to the first CPU. */
2182 if (s->cpu_index == 0) {
2183 apic_designate_bsp(env->apic_state);
2184 }
2185
2186 s->halted = !cpu_is_bsp(cpu);
2187 #endif
2188 }
2189
2190 #ifndef CONFIG_USER_ONLY
2191 bool cpu_is_bsp(X86CPU *cpu)
2192 {
2193 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2194 }
2195
2196 /* TODO: remove me, when reset over QOM tree is implemented */
2197 static void x86_cpu_machine_reset_cb(void *opaque)
2198 {
2199 X86CPU *cpu = opaque;
2200 cpu_reset(CPU(cpu));
2201 }
2202 #endif
2203
2204 static void mce_init(X86CPU *cpu)
2205 {
2206 CPUX86State *cenv = &cpu->env;
2207 unsigned int bank;
2208
2209 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2210 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2211 (CPUID_MCE | CPUID_MCA)) {
2212 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2213 cenv->mcg_ctl = ~(uint64_t)0;
2214 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2215 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2216 }
2217 }
2218 }
2219
2220 #ifndef CONFIG_USER_ONLY
2221 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2222 {
2223 CPUX86State *env = &cpu->env;
2224 DeviceState *dev = DEVICE(cpu);
2225 APICCommonState *apic;
2226 const char *apic_type = "apic";
2227
2228 if (kvm_irqchip_in_kernel()) {
2229 apic_type = "kvm-apic";
2230 } else if (xen_enabled()) {
2231 apic_type = "xen-apic";
2232 }
2233
2234 env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2235 if (env->apic_state == NULL) {
2236 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2237 return;
2238 }
2239
2240 object_property_add_child(OBJECT(cpu), "apic",
2241 OBJECT(env->apic_state), NULL);
2242 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2243 /* TODO: convert to link<> */
2244 apic = APIC_COMMON(env->apic_state);
2245 apic->cpu = cpu;
2246 }
2247
2248 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2249 {
2250 CPUX86State *env = &cpu->env;
2251
2252 if (env->apic_state == NULL) {
2253 return;
2254 }
2255
2256 if (qdev_init(env->apic_state)) {
2257 error_setg(errp, "APIC device '%s' could not be initialized",
2258 object_get_typename(OBJECT(env->apic_state)));
2259 return;
2260 }
2261 }
2262 #else
2263 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2264 {
2265 }
2266 #endif
2267
2268 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2269 {
2270 X86CPU *cpu = X86_CPU(dev);
2271 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2272 CPUX86State *env = &cpu->env;
2273 Error *local_err = NULL;
2274
2275 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2276 env->cpuid_level = 7;
2277 }
2278
2279 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2280 * CPUID[1].EDX.
2281 */
2282 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2283 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2284 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2285 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2286 env->cpuid_ext2_features |= (env->cpuid_features
2287 & CPUID_EXT2_AMD_ALIASES);
2288 }
2289
2290 if (!kvm_enabled()) {
2291 env->cpuid_features &= TCG_FEATURES;
2292 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2293 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2294 #ifdef TARGET_X86_64
2295 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2296 #endif
2297 );
2298 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2299 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2300 } else {
2301 if (check_cpuid && kvm_check_features_against_host(cpu)
2302 && enforce_cpuid) {
2303 error_setg(&local_err,
2304 "Host's CPU doesn't support requested features");
2305 goto out;
2306 }
2307 #ifdef CONFIG_KVM
2308 filter_features_for_kvm(cpu);
2309 #endif
2310 }
2311
2312 #ifndef CONFIG_USER_ONLY
2313 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2314
2315 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2316 x86_cpu_apic_create(cpu, &local_err);
2317 if (local_err != NULL) {
2318 goto out;
2319 }
2320 }
2321 #endif
2322
2323 mce_init(cpu);
2324 qemu_init_vcpu(&cpu->env);
2325
2326 x86_cpu_apic_realize(cpu, &local_err);
2327 if (local_err != NULL) {
2328 goto out;
2329 }
2330 cpu_reset(CPU(cpu));
2331
2332 xcc->parent_realize(dev, &local_err);
2333 out:
2334 if (local_err != NULL) {
2335 error_propagate(errp, local_err);
2336 return;
2337 }
2338 }
2339
2340 /* Enables contiguous-apic-ID mode, for compatibility */
2341 static bool compat_apic_id_mode;
2342
2343 void enable_compat_apic_id_mode(void)
2344 {
2345 compat_apic_id_mode = true;
2346 }
2347
2348 /* Calculates initial APIC ID for a specific CPU index
2349 *
2350 * Currently we need to be able to calculate the APIC ID from the CPU index
2351 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2352 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2353 * all CPUs up to max_cpus.
2354 */
2355 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2356 {
2357 uint32_t correct_id;
2358 static bool warned;
2359
2360 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2361 if (compat_apic_id_mode) {
2362 if (cpu_index != correct_id && !warned) {
2363 error_report("APIC IDs set in compatibility mode, "
2364 "CPU topology won't match the configuration");
2365 warned = true;
2366 }
2367 return cpu_index;
2368 } else {
2369 return correct_id;
2370 }
2371 }
2372
2373 static void x86_cpu_initfn(Object *obj)
2374 {
2375 CPUState *cs = CPU(obj);
2376 X86CPU *cpu = X86_CPU(obj);
2377 CPUX86State *env = &cpu->env;
2378 static int inited;
2379
2380 cs->env_ptr = env;
2381 cpu_exec_init(env);
2382
2383 object_property_add(obj, "family", "int",
2384 x86_cpuid_version_get_family,
2385 x86_cpuid_version_set_family, NULL, NULL, NULL);
2386 object_property_add(obj, "model", "int",
2387 x86_cpuid_version_get_model,
2388 x86_cpuid_version_set_model, NULL, NULL, NULL);
2389 object_property_add(obj, "stepping", "int",
2390 x86_cpuid_version_get_stepping,
2391 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2392 object_property_add(obj, "level", "int",
2393 x86_cpuid_get_level,
2394 x86_cpuid_set_level, NULL, NULL, NULL);
2395 object_property_add(obj, "xlevel", "int",
2396 x86_cpuid_get_xlevel,
2397 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2398 object_property_add_str(obj, "vendor",
2399 x86_cpuid_get_vendor,
2400 x86_cpuid_set_vendor, NULL);
2401 object_property_add_str(obj, "model-id",
2402 x86_cpuid_get_model_id,
2403 x86_cpuid_set_model_id, NULL);
2404 object_property_add(obj, "tsc-frequency", "int",
2405 x86_cpuid_get_tsc_freq,
2406 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2407 object_property_add(obj, "apic-id", "int",
2408 x86_cpuid_get_apic_id,
2409 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2410
2411 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2412
2413 /* init various static tables used in TCG mode */
2414 if (tcg_enabled() && !inited) {
2415 inited = 1;
2416 optimize_flags_init();
2417 #ifndef CONFIG_USER_ONLY
2418 cpu_set_debug_excp_handler(breakpoint_handler);
2419 #endif
2420 }
2421 }
2422
2423 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2424 {
2425 X86CPU *cpu = X86_CPU(cs);
2426 CPUX86State *env = &cpu->env;
2427
2428 return env->cpuid_apic_id;
2429 }
2430
2431 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2432 {
2433 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2434 CPUClass *cc = CPU_CLASS(oc);
2435 DeviceClass *dc = DEVICE_CLASS(oc);
2436
2437 xcc->parent_realize = dc->realize;
2438 dc->realize = x86_cpu_realizefn;
2439 dc->bus_type = TYPE_ICC_BUS;
2440
2441 xcc->parent_reset = cc->reset;
2442 cc->reset = x86_cpu_reset;
2443
2444 cc->do_interrupt = x86_cpu_do_interrupt;
2445 #ifndef CONFIG_USER_ONLY
2446 cc->write_elf64_note = x86_cpu_write_elf64_note;
2447 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2448 cc->write_elf32_note = x86_cpu_write_elf32_note;
2449 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2450 #endif
2451 cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
2452
2453 cc->get_arch_id = x86_cpu_get_arch_id;
2454 }
2455
2456 static const TypeInfo x86_cpu_type_info = {
2457 .name = TYPE_X86_CPU,
2458 .parent = TYPE_CPU,
2459 .instance_size = sizeof(X86CPU),
2460 .instance_init = x86_cpu_initfn,
2461 .abstract = false,
2462 .class_size = sizeof(X86CPUClass),
2463 .class_init = x86_cpu_common_class_init,
2464 };
2465
2466 static void x86_cpu_register_types(void)
2467 {
2468 type_register_static(&x86_cpu_type_info);
2469 }
2470
2471 type_init(x86_cpu_register_types)
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