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Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
49 #endif
50
51
52 /* Cache topology CPUID constants: */
53
54 /* CPUID Leaf 2 Descriptors */
55
56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
58 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61 /* CPUID Leaf 4 constants: */
62
63 /* EAX: */
64 #define CPUID_4_TYPE_DCACHE 1
65 #define CPUID_4_TYPE_ICACHE 2
66 #define CPUID_4_TYPE_UNIFIED 3
67
68 #define CPUID_4_LEVEL(l) ((l) << 5)
69
70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71 #define CPUID_4_FULLY_ASSOC (1 << 9)
72
73 /* EDX: */
74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
75 #define CPUID_4_INCLUSIVE (1 << 1)
76 #define CPUID_4_COMPLEX_IDX (1 << 2)
77
78 #define ASSOC_FULL 0xFF
79
80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95 /* Definitions of the hardcoded cache entries we expose: */
96
97 /* L1 data cache: */
98 #define L1D_LINE_SIZE 64
99 #define L1D_ASSOCIATIVITY 8
100 #define L1D_SETS 64
101 #define L1D_PARTITIONS 1
102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105 #define L1D_LINES_PER_TAG 1
106 #define L1D_SIZE_KB_AMD 64
107 #define L1D_ASSOCIATIVITY_AMD 2
108
109 /* L1 instruction cache: */
110 #define L1I_LINE_SIZE 64
111 #define L1I_ASSOCIATIVITY 8
112 #define L1I_SETS 64
113 #define L1I_PARTITIONS 1
114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117 #define L1I_LINES_PER_TAG 1
118 #define L1I_SIZE_KB_AMD 64
119 #define L1I_ASSOCIATIVITY_AMD 2
120
121 /* Level 2 unified cache: */
122 #define L2_LINE_SIZE 64
123 #define L2_ASSOCIATIVITY 16
124 #define L2_SETS 4096
125 #define L2_PARTITIONS 1
126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130 #define L2_LINES_PER_TAG 1
131 #define L2_SIZE_KB_AMD 512
132
133 /* No L3 cache: */
134 #define L3_SIZE_KB 0 /* disabled */
135 #define L3_ASSOCIATIVITY 0 /* disabled */
136 #define L3_LINES_PER_TAG 0 /* disabled */
137 #define L3_LINE_SIZE 0 /* disabled */
138
139 /* TLB definitions: */
140
141 #define L1_DTLB_2M_ASSOC 1
142 #define L1_DTLB_2M_ENTRIES 255
143 #define L1_DTLB_4K_ASSOC 1
144 #define L1_DTLB_4K_ENTRIES 255
145
146 #define L1_ITLB_2M_ASSOC 1
147 #define L1_ITLB_2M_ENTRIES 255
148 #define L1_ITLB_4K_ASSOC 1
149 #define L1_ITLB_4K_ENTRIES 255
150
151 #define L2_DTLB_2M_ASSOC 0 /* disabled */
152 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
153 #define L2_DTLB_4K_ASSOC 4
154 #define L2_DTLB_4K_ENTRIES 512
155
156 #define L2_ITLB_2M_ASSOC 0 /* disabled */
157 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
158 #define L2_ITLB_4K_ASSOC 4
159 #define L2_ITLB_4K_ENTRIES 512
160
161
162
163 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165 {
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173 }
174
175 /* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179 static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188 };
189 static const char *ext_feature_name[] = {
190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
191 "ds_cpl", "vmx", "smx", "est",
192 "tm2", "ssse3", "cid", NULL,
193 "fma", "cx16", "xtpr", "pdcm",
194 NULL, "pcid", "dca", "sse4.1|sse4_1",
195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
196 "tsc-deadline", "aes", "xsave", "osxsave",
197 "avx", "f16c", "rdrand", "hypervisor",
198 };
199 /* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
204 static const char *ext2_feature_name[] = {
205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
212 NULL, "lm|i64", "3dnowext", "3dnow",
213 };
214 static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
217 "3dnowprefetch", "osvw", "ibs", "xop",
218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
222 NULL, NULL, NULL, NULL,
223 };
224
225 static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 };
235
236 static const char *kvm_feature_name[] = {
237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 };
246
247 static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 };
257
258 static const char *cpuid_7_0_ebx_feature_name[] = {
259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263 };
264
265 typedef struct FeatureWordInfo {
266 const char **feat_names;
267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
271 } FeatureWordInfo;
272
273 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
307 },
308 };
309
310 typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315 } X86RegisterInfo32;
316
317 #define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
319 X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328 };
329 #undef REGISTER
330
331 typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334 } ExtSaveArea;
335
336 static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
338 .offset = 0x240, .size = 0x100 },
339 };
340
341 const char *get_register_name_32(unsigned int reg)
342 {
343 if (reg >= CPU_NB_REGS32) {
344 return NULL;
345 }
346 return x86_reg_info_32[reg].name;
347 }
348
349 /* collects per-function cpuid data
350 */
351 typedef struct model_features_t {
352 uint32_t *guest_feat;
353 uint32_t *host_feat;
354 FeatureWord feat_word;
355 } model_features_t;
356
357 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
358 (1 << KVM_FEATURE_NOP_IO_DELAY) |
359 (1 << KVM_FEATURE_CLOCKSOURCE2) |
360 (1 << KVM_FEATURE_ASYNC_PF) |
361 (1 << KVM_FEATURE_STEAL_TIME) |
362 (1 << KVM_FEATURE_PV_EOI) |
363 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
364
365 void disable_kvm_pv_eoi(void)
366 {
367 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
368 }
369
370 void host_cpuid(uint32_t function, uint32_t count,
371 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
372 {
373 #if defined(CONFIG_KVM)
374 uint32_t vec[4];
375
376 #ifdef __x86_64__
377 asm volatile("cpuid"
378 : "=a"(vec[0]), "=b"(vec[1]),
379 "=c"(vec[2]), "=d"(vec[3])
380 : "0"(function), "c"(count) : "cc");
381 #else
382 asm volatile("pusha \n\t"
383 "cpuid \n\t"
384 "mov %%eax, 0(%2) \n\t"
385 "mov %%ebx, 4(%2) \n\t"
386 "mov %%ecx, 8(%2) \n\t"
387 "mov %%edx, 12(%2) \n\t"
388 "popa"
389 : : "a"(function), "c"(count), "S"(vec)
390 : "memory", "cc");
391 #endif
392
393 if (eax)
394 *eax = vec[0];
395 if (ebx)
396 *ebx = vec[1];
397 if (ecx)
398 *ecx = vec[2];
399 if (edx)
400 *edx = vec[3];
401 #endif
402 }
403
404 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
405
406 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
407 * a substring. ex if !NULL points to the first char after a substring,
408 * otherwise the string is assumed to sized by a terminating nul.
409 * Return lexical ordering of *s1:*s2.
410 */
411 static int sstrcmp(const char *s1, const char *e1, const char *s2,
412 const char *e2)
413 {
414 for (;;) {
415 if (!*s1 || !*s2 || *s1 != *s2)
416 return (*s1 - *s2);
417 ++s1, ++s2;
418 if (s1 == e1 && s2 == e2)
419 return (0);
420 else if (s1 == e1)
421 return (*s2);
422 else if (s2 == e2)
423 return (*s1);
424 }
425 }
426
427 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
428 * '|' delimited (possibly empty) strings in which case search for a match
429 * within the alternatives proceeds left to right. Return 0 for success,
430 * non-zero otherwise.
431 */
432 static int altcmp(const char *s, const char *e, const char *altstr)
433 {
434 const char *p, *q;
435
436 for (q = p = altstr; ; ) {
437 while (*p && *p != '|')
438 ++p;
439 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
440 return (0);
441 if (!*p)
442 return (1);
443 else
444 q = ++p;
445 }
446 }
447
448 /* search featureset for flag *[s..e), if found set corresponding bit in
449 * *pval and return true, otherwise return false
450 */
451 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
452 const char **featureset)
453 {
454 uint32_t mask;
455 const char **ppc;
456 bool found = false;
457
458 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
459 if (*ppc && !altcmp(s, e, *ppc)) {
460 *pval |= mask;
461 found = true;
462 }
463 }
464 return found;
465 }
466
467 static void add_flagname_to_bitmaps(const char *flagname,
468 FeatureWordArray words)
469 {
470 FeatureWord w;
471 for (w = 0; w < FEATURE_WORDS; w++) {
472 FeatureWordInfo *wi = &feature_word_info[w];
473 if (wi->feat_names &&
474 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
475 break;
476 }
477 }
478 if (w == FEATURE_WORDS) {
479 fprintf(stderr, "CPU feature %s not found\n", flagname);
480 }
481 }
482
483 typedef struct x86_def_t {
484 const char *name;
485 uint32_t level;
486 uint32_t xlevel;
487 uint32_t xlevel2;
488 /* vendor is zero-terminated, 12 character ASCII string */
489 char vendor[CPUID_VENDOR_SZ + 1];
490 int family;
491 int model;
492 int stepping;
493 FeatureWordArray features;
494 char model_id[48];
495 bool cache_info_passthrough;
496 } x86_def_t;
497
498 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
499 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
500 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
501 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
502 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
503 CPUID_PSE36 | CPUID_FXSR)
504 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
505 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
506 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
507 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
508 CPUID_PAE | CPUID_SEP | CPUID_APIC)
509
510 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
511 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
512 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
513 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
514 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
515 /* partly implemented:
516 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
517 CPUID_PSE36 (needed for Solaris) */
518 /* missing:
519 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
520 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
521 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
522 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
523 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
524 /* missing:
525 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
526 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
527 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
528 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
529 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
530 CPUID_EXT_RDRAND */
531 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
532 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
533 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
534 /* missing:
535 CPUID_EXT2_PDPE1GB */
536 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
537 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
538 #define TCG_SVM_FEATURES 0
539 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
540 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
541 /* missing:
542 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
543 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
544 CPUID_7_0_EBX_RDSEED */
545
546 /* built-in CPU model definitions
547 */
548 static x86_def_t builtin_x86_defs[] = {
549 {
550 .name = "qemu64",
551 .level = 4,
552 .vendor = CPUID_VENDOR_AMD,
553 .family = 6,
554 .model = 6,
555 .stepping = 3,
556 .features[FEAT_1_EDX] =
557 PPRO_FEATURES |
558 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
559 CPUID_PSE36,
560 .features[FEAT_1_ECX] =
561 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
562 .features[FEAT_8000_0001_EDX] =
563 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
564 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
565 .features[FEAT_8000_0001_ECX] =
566 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
567 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
568 .xlevel = 0x8000000A,
569 },
570 {
571 .name = "phenom",
572 .level = 5,
573 .vendor = CPUID_VENDOR_AMD,
574 .family = 16,
575 .model = 2,
576 .stepping = 3,
577 .features[FEAT_1_EDX] =
578 PPRO_FEATURES |
579 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
580 CPUID_PSE36 | CPUID_VME | CPUID_HT,
581 .features[FEAT_1_ECX] =
582 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
583 CPUID_EXT_POPCNT,
584 .features[FEAT_8000_0001_EDX] =
585 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
586 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
587 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
588 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
589 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
590 CPUID_EXT3_CR8LEG,
591 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
592 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
593 .features[FEAT_8000_0001_ECX] =
594 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
595 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
596 .features[FEAT_SVM] =
597 CPUID_SVM_NPT | CPUID_SVM_LBRV,
598 .xlevel = 0x8000001A,
599 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
600 },
601 {
602 .name = "core2duo",
603 .level = 10,
604 .vendor = CPUID_VENDOR_INTEL,
605 .family = 6,
606 .model = 15,
607 .stepping = 11,
608 .features[FEAT_1_EDX] =
609 PPRO_FEATURES |
610 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
611 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
612 CPUID_HT | CPUID_TM | CPUID_PBE,
613 .features[FEAT_1_ECX] =
614 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
615 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
616 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
617 .features[FEAT_8000_0001_EDX] =
618 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
619 .features[FEAT_8000_0001_ECX] =
620 CPUID_EXT3_LAHF_LM,
621 .xlevel = 0x80000008,
622 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
623 },
624 {
625 .name = "kvm64",
626 .level = 5,
627 .vendor = CPUID_VENDOR_INTEL,
628 .family = 15,
629 .model = 6,
630 .stepping = 1,
631 /* Missing: CPUID_VME, CPUID_HT */
632 .features[FEAT_1_EDX] =
633 PPRO_FEATURES |
634 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
635 CPUID_PSE36,
636 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
637 .features[FEAT_1_ECX] =
638 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
639 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
640 .features[FEAT_8000_0001_EDX] =
641 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
642 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
643 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
644 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
645 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
646 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
647 .features[FEAT_8000_0001_ECX] =
648 0,
649 .xlevel = 0x80000008,
650 .model_id = "Common KVM processor"
651 },
652 {
653 .name = "qemu32",
654 .level = 4,
655 .vendor = CPUID_VENDOR_INTEL,
656 .family = 6,
657 .model = 6,
658 .stepping = 3,
659 .features[FEAT_1_EDX] =
660 PPRO_FEATURES,
661 .features[FEAT_1_ECX] =
662 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
663 .xlevel = 0x80000004,
664 },
665 {
666 .name = "kvm32",
667 .level = 5,
668 .vendor = CPUID_VENDOR_INTEL,
669 .family = 15,
670 .model = 6,
671 .stepping = 1,
672 .features[FEAT_1_EDX] =
673 PPRO_FEATURES |
674 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
675 .features[FEAT_1_ECX] =
676 CPUID_EXT_SSE3,
677 .features[FEAT_8000_0001_EDX] =
678 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
679 .features[FEAT_8000_0001_ECX] =
680 0,
681 .xlevel = 0x80000008,
682 .model_id = "Common 32-bit KVM processor"
683 },
684 {
685 .name = "coreduo",
686 .level = 10,
687 .vendor = CPUID_VENDOR_INTEL,
688 .family = 6,
689 .model = 14,
690 .stepping = 8,
691 .features[FEAT_1_EDX] =
692 PPRO_FEATURES | CPUID_VME |
693 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
694 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
695 .features[FEAT_1_ECX] =
696 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
697 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
698 .features[FEAT_8000_0001_EDX] =
699 CPUID_EXT2_NX,
700 .xlevel = 0x80000008,
701 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
702 },
703 {
704 .name = "486",
705 .level = 1,
706 .vendor = CPUID_VENDOR_INTEL,
707 .family = 4,
708 .model = 8,
709 .stepping = 0,
710 .features[FEAT_1_EDX] =
711 I486_FEATURES,
712 .xlevel = 0,
713 },
714 {
715 .name = "pentium",
716 .level = 1,
717 .vendor = CPUID_VENDOR_INTEL,
718 .family = 5,
719 .model = 4,
720 .stepping = 3,
721 .features[FEAT_1_EDX] =
722 PENTIUM_FEATURES,
723 .xlevel = 0,
724 },
725 {
726 .name = "pentium2",
727 .level = 2,
728 .vendor = CPUID_VENDOR_INTEL,
729 .family = 6,
730 .model = 5,
731 .stepping = 2,
732 .features[FEAT_1_EDX] =
733 PENTIUM2_FEATURES,
734 .xlevel = 0,
735 },
736 {
737 .name = "pentium3",
738 .level = 2,
739 .vendor = CPUID_VENDOR_INTEL,
740 .family = 6,
741 .model = 7,
742 .stepping = 3,
743 .features[FEAT_1_EDX] =
744 PENTIUM3_FEATURES,
745 .xlevel = 0,
746 },
747 {
748 .name = "athlon",
749 .level = 2,
750 .vendor = CPUID_VENDOR_AMD,
751 .family = 6,
752 .model = 2,
753 .stepping = 3,
754 .features[FEAT_1_EDX] =
755 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
756 CPUID_MCA,
757 .features[FEAT_8000_0001_EDX] =
758 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
759 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
760 .xlevel = 0x80000008,
761 },
762 {
763 .name = "n270",
764 /* original is on level 10 */
765 .level = 5,
766 .vendor = CPUID_VENDOR_INTEL,
767 .family = 6,
768 .model = 28,
769 .stepping = 2,
770 .features[FEAT_1_EDX] =
771 PPRO_FEATURES |
772 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
773 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
774 /* Some CPUs got no CPUID_SEP */
775 .features[FEAT_1_ECX] =
776 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
777 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
778 CPUID_EXT_MOVBE,
779 .features[FEAT_8000_0001_EDX] =
780 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
781 CPUID_EXT2_NX,
782 .features[FEAT_8000_0001_ECX] =
783 CPUID_EXT3_LAHF_LM,
784 .xlevel = 0x8000000A,
785 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
786 },
787 {
788 .name = "Conroe",
789 .level = 4,
790 .vendor = CPUID_VENDOR_INTEL,
791 .family = 6,
792 .model = 15,
793 .stepping = 3,
794 .features[FEAT_1_EDX] =
795 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
796 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
797 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
798 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
799 CPUID_DE | CPUID_FP87,
800 .features[FEAT_1_ECX] =
801 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
802 .features[FEAT_8000_0001_EDX] =
803 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
804 .features[FEAT_8000_0001_ECX] =
805 CPUID_EXT3_LAHF_LM,
806 .xlevel = 0x8000000A,
807 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
808 },
809 {
810 .name = "Penryn",
811 .level = 4,
812 .vendor = CPUID_VENDOR_INTEL,
813 .family = 6,
814 .model = 23,
815 .stepping = 3,
816 .features[FEAT_1_EDX] =
817 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
818 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
819 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
820 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
821 CPUID_DE | CPUID_FP87,
822 .features[FEAT_1_ECX] =
823 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
824 CPUID_EXT_SSE3,
825 .features[FEAT_8000_0001_EDX] =
826 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
827 .features[FEAT_8000_0001_ECX] =
828 CPUID_EXT3_LAHF_LM,
829 .xlevel = 0x8000000A,
830 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
831 },
832 {
833 .name = "Nehalem",
834 .level = 4,
835 .vendor = CPUID_VENDOR_INTEL,
836 .family = 6,
837 .model = 26,
838 .stepping = 3,
839 .features[FEAT_1_EDX] =
840 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
841 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
842 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
843 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
844 CPUID_DE | CPUID_FP87,
845 .features[FEAT_1_ECX] =
846 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
847 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
848 .features[FEAT_8000_0001_EDX] =
849 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
850 .features[FEAT_8000_0001_ECX] =
851 CPUID_EXT3_LAHF_LM,
852 .xlevel = 0x8000000A,
853 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
854 },
855 {
856 .name = "Westmere",
857 .level = 11,
858 .vendor = CPUID_VENDOR_INTEL,
859 .family = 6,
860 .model = 44,
861 .stepping = 1,
862 .features[FEAT_1_EDX] =
863 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
864 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
865 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
866 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
867 CPUID_DE | CPUID_FP87,
868 .features[FEAT_1_ECX] =
869 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
870 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
871 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
872 .features[FEAT_8000_0001_EDX] =
873 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
874 .features[FEAT_8000_0001_ECX] =
875 CPUID_EXT3_LAHF_LM,
876 .xlevel = 0x8000000A,
877 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
878 },
879 {
880 .name = "SandyBridge",
881 .level = 0xd,
882 .vendor = CPUID_VENDOR_INTEL,
883 .family = 6,
884 .model = 42,
885 .stepping = 1,
886 .features[FEAT_1_EDX] =
887 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
888 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
889 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
890 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
891 CPUID_DE | CPUID_FP87,
892 .features[FEAT_1_ECX] =
893 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
894 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
895 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
896 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
897 CPUID_EXT_SSE3,
898 .features[FEAT_8000_0001_EDX] =
899 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
900 CPUID_EXT2_SYSCALL,
901 .features[FEAT_8000_0001_ECX] =
902 CPUID_EXT3_LAHF_LM,
903 .xlevel = 0x8000000A,
904 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
905 },
906 {
907 .name = "Haswell",
908 .level = 0xd,
909 .vendor = CPUID_VENDOR_INTEL,
910 .family = 6,
911 .model = 60,
912 .stepping = 1,
913 .features[FEAT_1_EDX] =
914 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
915 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
916 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
917 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
918 CPUID_DE | CPUID_FP87,
919 .features[FEAT_1_ECX] =
920 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
921 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
922 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
923 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
924 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
925 CPUID_EXT_PCID,
926 .features[FEAT_8000_0001_EDX] =
927 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
928 CPUID_EXT2_SYSCALL,
929 .features[FEAT_8000_0001_ECX] =
930 CPUID_EXT3_LAHF_LM,
931 .features[FEAT_7_0_EBX] =
932 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
933 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
934 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
935 CPUID_7_0_EBX_RTM,
936 .xlevel = 0x8000000A,
937 .model_id = "Intel Core Processor (Haswell)",
938 },
939 {
940 .name = "Opteron_G1",
941 .level = 5,
942 .vendor = CPUID_VENDOR_AMD,
943 .family = 15,
944 .model = 6,
945 .stepping = 1,
946 .features[FEAT_1_EDX] =
947 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
948 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
949 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
950 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
951 CPUID_DE | CPUID_FP87,
952 .features[FEAT_1_ECX] =
953 CPUID_EXT_SSE3,
954 .features[FEAT_8000_0001_EDX] =
955 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
956 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
957 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
958 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
959 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
960 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
961 .xlevel = 0x80000008,
962 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
963 },
964 {
965 .name = "Opteron_G2",
966 .level = 5,
967 .vendor = CPUID_VENDOR_AMD,
968 .family = 15,
969 .model = 6,
970 .stepping = 1,
971 .features[FEAT_1_EDX] =
972 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
973 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
974 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
975 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
976 CPUID_DE | CPUID_FP87,
977 .features[FEAT_1_ECX] =
978 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
979 .features[FEAT_8000_0001_EDX] =
980 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
981 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
982 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
983 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
984 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
985 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
986 CPUID_EXT2_DE | CPUID_EXT2_FPU,
987 .features[FEAT_8000_0001_ECX] =
988 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
989 .xlevel = 0x80000008,
990 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
991 },
992 {
993 .name = "Opteron_G3",
994 .level = 5,
995 .vendor = CPUID_VENDOR_AMD,
996 .family = 15,
997 .model = 6,
998 .stepping = 1,
999 .features[FEAT_1_EDX] =
1000 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1001 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1002 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1003 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1004 CPUID_DE | CPUID_FP87,
1005 .features[FEAT_1_ECX] =
1006 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1007 CPUID_EXT_SSE3,
1008 .features[FEAT_8000_0001_EDX] =
1009 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1010 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1011 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1012 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1013 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1014 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1015 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1016 .features[FEAT_8000_0001_ECX] =
1017 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1018 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1019 .xlevel = 0x80000008,
1020 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1021 },
1022 {
1023 .name = "Opteron_G4",
1024 .level = 0xd,
1025 .vendor = CPUID_VENDOR_AMD,
1026 .family = 21,
1027 .model = 1,
1028 .stepping = 2,
1029 .features[FEAT_1_EDX] =
1030 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1031 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1032 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1033 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1034 CPUID_DE | CPUID_FP87,
1035 .features[FEAT_1_ECX] =
1036 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1037 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1038 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1039 CPUID_EXT_SSE3,
1040 .features[FEAT_8000_0001_EDX] =
1041 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1042 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1043 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1044 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1045 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1046 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1047 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1048 .features[FEAT_8000_0001_ECX] =
1049 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1050 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1051 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1052 CPUID_EXT3_LAHF_LM,
1053 .xlevel = 0x8000001A,
1054 .model_id = "AMD Opteron 62xx class CPU",
1055 },
1056 {
1057 .name = "Opteron_G5",
1058 .level = 0xd,
1059 .vendor = CPUID_VENDOR_AMD,
1060 .family = 21,
1061 .model = 2,
1062 .stepping = 0,
1063 .features[FEAT_1_EDX] =
1064 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1065 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1066 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1067 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1068 CPUID_DE | CPUID_FP87,
1069 .features[FEAT_1_ECX] =
1070 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1071 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1072 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1073 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1074 .features[FEAT_8000_0001_EDX] =
1075 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1076 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1077 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1078 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1079 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1080 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1081 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1082 .features[FEAT_8000_0001_ECX] =
1083 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1084 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1085 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1086 CPUID_EXT3_LAHF_LM,
1087 .xlevel = 0x8000001A,
1088 .model_id = "AMD Opteron 63xx class CPU",
1089 },
1090 };
1091
1092 /**
1093 * x86_cpu_compat_set_features:
1094 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1095 * @w: Identifies the feature word to be changed.
1096 * @feat_add: Feature bits to be added to feature word
1097 * @feat_remove: Feature bits to be removed from feature word
1098 *
1099 * Change CPU model feature bits for compatibility.
1100 *
1101 * This function may be used by machine-type compatibility functions
1102 * to enable or disable feature bits on specific CPU models.
1103 */
1104 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1105 uint32_t feat_add, uint32_t feat_remove)
1106 {
1107 x86_def_t *def;
1108 int i;
1109 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1110 def = &builtin_x86_defs[i];
1111 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1112 def->features[w] |= feat_add;
1113 def->features[w] &= ~feat_remove;
1114 }
1115 }
1116 }
1117
1118 #ifdef CONFIG_KVM
1119 static int cpu_x86_fill_model_id(char *str)
1120 {
1121 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1122 int i;
1123
1124 for (i = 0; i < 3; i++) {
1125 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1126 memcpy(str + i * 16 + 0, &eax, 4);
1127 memcpy(str + i * 16 + 4, &ebx, 4);
1128 memcpy(str + i * 16 + 8, &ecx, 4);
1129 memcpy(str + i * 16 + 12, &edx, 4);
1130 }
1131 return 0;
1132 }
1133 #endif
1134
1135 /* Fill a x86_def_t struct with information about the host CPU, and
1136 * the CPU features supported by the host hardware + host kernel
1137 *
1138 * This function may be called only if KVM is enabled.
1139 */
1140 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
1141 {
1142 #ifdef CONFIG_KVM
1143 KVMState *s = kvm_state;
1144 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1145
1146 assert(kvm_enabled());
1147
1148 x86_cpu_def->name = "host";
1149 x86_cpu_def->cache_info_passthrough = true;
1150 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1151 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1152
1153 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1154 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1155 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1156 x86_cpu_def->stepping = eax & 0x0F;
1157
1158 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1159 x86_cpu_def->features[FEAT_1_EDX] =
1160 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
1161 x86_cpu_def->features[FEAT_1_ECX] =
1162 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
1163
1164 if (x86_cpu_def->level >= 7) {
1165 x86_cpu_def->features[FEAT_7_0_EBX] =
1166 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
1167 } else {
1168 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
1169 }
1170
1171 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1172 x86_cpu_def->features[FEAT_8000_0001_EDX] =
1173 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1174 x86_cpu_def->features[FEAT_8000_0001_ECX] =
1175 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1176
1177 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1178
1179 /* Call Centaur's CPUID instruction. */
1180 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
1181 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
1182 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1183 if (eax >= 0xC0000001) {
1184 /* Support VIA max extended level */
1185 x86_cpu_def->xlevel2 = eax;
1186 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
1187 x86_cpu_def->features[FEAT_C000_0001_EDX] =
1188 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1189 }
1190 }
1191
1192 /* Other KVM-specific feature fields: */
1193 x86_cpu_def->features[FEAT_SVM] =
1194 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1195 x86_cpu_def->features[FEAT_KVM] =
1196 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1197
1198 #endif /* CONFIG_KVM */
1199 }
1200
1201 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1202 {
1203 int i;
1204
1205 for (i = 0; i < 32; ++i)
1206 if (1 << i & mask) {
1207 const char *reg = get_register_name_32(f->cpuid_reg);
1208 assert(reg);
1209 fprintf(stderr, "warning: host doesn't support requested feature: "
1210 "CPUID.%02XH:%s%s%s [bit %d]\n",
1211 f->cpuid_eax, reg,
1212 f->feat_names[i] ? "." : "",
1213 f->feat_names[i] ? f->feat_names[i] : "", i);
1214 break;
1215 }
1216 return 0;
1217 }
1218
1219 /* Check if all requested cpu flags are making their way to the guest
1220 *
1221 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1222 *
1223 * This function may be called only if KVM is enabled.
1224 */
1225 static int kvm_check_features_against_host(X86CPU *cpu)
1226 {
1227 CPUX86State *env = &cpu->env;
1228 x86_def_t host_def;
1229 uint32_t mask;
1230 int rv, i;
1231 struct model_features_t ft[] = {
1232 {&env->features[FEAT_1_EDX],
1233 &host_def.features[FEAT_1_EDX],
1234 FEAT_1_EDX },
1235 {&env->features[FEAT_1_ECX],
1236 &host_def.features[FEAT_1_ECX],
1237 FEAT_1_ECX },
1238 {&env->features[FEAT_8000_0001_EDX],
1239 &host_def.features[FEAT_8000_0001_EDX],
1240 FEAT_8000_0001_EDX },
1241 {&env->features[FEAT_8000_0001_ECX],
1242 &host_def.features[FEAT_8000_0001_ECX],
1243 FEAT_8000_0001_ECX },
1244 {&env->features[FEAT_C000_0001_EDX],
1245 &host_def.features[FEAT_C000_0001_EDX],
1246 FEAT_C000_0001_EDX },
1247 {&env->features[FEAT_7_0_EBX],
1248 &host_def.features[FEAT_7_0_EBX],
1249 FEAT_7_0_EBX },
1250 {&env->features[FEAT_SVM],
1251 &host_def.features[FEAT_SVM],
1252 FEAT_SVM },
1253 {&env->features[FEAT_KVM],
1254 &host_def.features[FEAT_KVM],
1255 FEAT_KVM },
1256 };
1257
1258 assert(kvm_enabled());
1259
1260 kvm_cpu_fill_host(&host_def);
1261 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1262 FeatureWord w = ft[i].feat_word;
1263 FeatureWordInfo *wi = &feature_word_info[w];
1264 for (mask = 1; mask; mask <<= 1) {
1265 if (*ft[i].guest_feat & mask &&
1266 !(*ft[i].host_feat & mask)) {
1267 unavailable_host_feature(wi, mask);
1268 rv = 1;
1269 }
1270 }
1271 }
1272 return rv;
1273 }
1274
1275 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1276 const char *name, Error **errp)
1277 {
1278 X86CPU *cpu = X86_CPU(obj);
1279 CPUX86State *env = &cpu->env;
1280 int64_t value;
1281
1282 value = (env->cpuid_version >> 8) & 0xf;
1283 if (value == 0xf) {
1284 value += (env->cpuid_version >> 20) & 0xff;
1285 }
1286 visit_type_int(v, &value, name, errp);
1287 }
1288
1289 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1290 const char *name, Error **errp)
1291 {
1292 X86CPU *cpu = X86_CPU(obj);
1293 CPUX86State *env = &cpu->env;
1294 const int64_t min = 0;
1295 const int64_t max = 0xff + 0xf;
1296 int64_t value;
1297
1298 visit_type_int(v, &value, name, errp);
1299 if (error_is_set(errp)) {
1300 return;
1301 }
1302 if (value < min || value > max) {
1303 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1304 name ? name : "null", value, min, max);
1305 return;
1306 }
1307
1308 env->cpuid_version &= ~0xff00f00;
1309 if (value > 0x0f) {
1310 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1311 } else {
1312 env->cpuid_version |= value << 8;
1313 }
1314 }
1315
1316 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1317 const char *name, Error **errp)
1318 {
1319 X86CPU *cpu = X86_CPU(obj);
1320 CPUX86State *env = &cpu->env;
1321 int64_t value;
1322
1323 value = (env->cpuid_version >> 4) & 0xf;
1324 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1325 visit_type_int(v, &value, name, errp);
1326 }
1327
1328 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1329 const char *name, Error **errp)
1330 {
1331 X86CPU *cpu = X86_CPU(obj);
1332 CPUX86State *env = &cpu->env;
1333 const int64_t min = 0;
1334 const int64_t max = 0xff;
1335 int64_t value;
1336
1337 visit_type_int(v, &value, name, errp);
1338 if (error_is_set(errp)) {
1339 return;
1340 }
1341 if (value < min || value > max) {
1342 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1343 name ? name : "null", value, min, max);
1344 return;
1345 }
1346
1347 env->cpuid_version &= ~0xf00f0;
1348 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1349 }
1350
1351 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1352 void *opaque, const char *name,
1353 Error **errp)
1354 {
1355 X86CPU *cpu = X86_CPU(obj);
1356 CPUX86State *env = &cpu->env;
1357 int64_t value;
1358
1359 value = env->cpuid_version & 0xf;
1360 visit_type_int(v, &value, name, errp);
1361 }
1362
1363 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1364 void *opaque, const char *name,
1365 Error **errp)
1366 {
1367 X86CPU *cpu = X86_CPU(obj);
1368 CPUX86State *env = &cpu->env;
1369 const int64_t min = 0;
1370 const int64_t max = 0xf;
1371 int64_t value;
1372
1373 visit_type_int(v, &value, name, errp);
1374 if (error_is_set(errp)) {
1375 return;
1376 }
1377 if (value < min || value > max) {
1378 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1379 name ? name : "null", value, min, max);
1380 return;
1381 }
1382
1383 env->cpuid_version &= ~0xf;
1384 env->cpuid_version |= value & 0xf;
1385 }
1386
1387 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1388 const char *name, Error **errp)
1389 {
1390 X86CPU *cpu = X86_CPU(obj);
1391
1392 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1393 }
1394
1395 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1396 const char *name, Error **errp)
1397 {
1398 X86CPU *cpu = X86_CPU(obj);
1399
1400 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1401 }
1402
1403 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1404 const char *name, Error **errp)
1405 {
1406 X86CPU *cpu = X86_CPU(obj);
1407
1408 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1409 }
1410
1411 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1412 const char *name, Error **errp)
1413 {
1414 X86CPU *cpu = X86_CPU(obj);
1415
1416 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1417 }
1418
1419 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1420 {
1421 X86CPU *cpu = X86_CPU(obj);
1422 CPUX86State *env = &cpu->env;
1423 char *value;
1424
1425 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1426 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1427 env->cpuid_vendor3);
1428 return value;
1429 }
1430
1431 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1432 Error **errp)
1433 {
1434 X86CPU *cpu = X86_CPU(obj);
1435 CPUX86State *env = &cpu->env;
1436 int i;
1437
1438 if (strlen(value) != CPUID_VENDOR_SZ) {
1439 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1440 "vendor", value);
1441 return;
1442 }
1443
1444 env->cpuid_vendor1 = 0;
1445 env->cpuid_vendor2 = 0;
1446 env->cpuid_vendor3 = 0;
1447 for (i = 0; i < 4; i++) {
1448 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1449 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1450 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1451 }
1452 }
1453
1454 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1455 {
1456 X86CPU *cpu = X86_CPU(obj);
1457 CPUX86State *env = &cpu->env;
1458 char *value;
1459 int i;
1460
1461 value = g_malloc(48 + 1);
1462 for (i = 0; i < 48; i++) {
1463 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1464 }
1465 value[48] = '\0';
1466 return value;
1467 }
1468
1469 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1470 Error **errp)
1471 {
1472 X86CPU *cpu = X86_CPU(obj);
1473 CPUX86State *env = &cpu->env;
1474 int c, len, i;
1475
1476 if (model_id == NULL) {
1477 model_id = "";
1478 }
1479 len = strlen(model_id);
1480 memset(env->cpuid_model, 0, 48);
1481 for (i = 0; i < 48; i++) {
1482 if (i >= len) {
1483 c = '\0';
1484 } else {
1485 c = (uint8_t)model_id[i];
1486 }
1487 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1488 }
1489 }
1490
1491 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1492 const char *name, Error **errp)
1493 {
1494 X86CPU *cpu = X86_CPU(obj);
1495 int64_t value;
1496
1497 value = cpu->env.tsc_khz * 1000;
1498 visit_type_int(v, &value, name, errp);
1499 }
1500
1501 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1502 const char *name, Error **errp)
1503 {
1504 X86CPU *cpu = X86_CPU(obj);
1505 const int64_t min = 0;
1506 const int64_t max = INT64_MAX;
1507 int64_t value;
1508
1509 visit_type_int(v, &value, name, errp);
1510 if (error_is_set(errp)) {
1511 return;
1512 }
1513 if (value < min || value > max) {
1514 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1515 name ? name : "null", value, min, max);
1516 return;
1517 }
1518
1519 cpu->env.tsc_khz = value / 1000;
1520 }
1521
1522 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1523 const char *name, Error **errp)
1524 {
1525 X86CPU *cpu = X86_CPU(obj);
1526 int64_t value = cpu->env.cpuid_apic_id;
1527
1528 visit_type_int(v, &value, name, errp);
1529 }
1530
1531 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1532 const char *name, Error **errp)
1533 {
1534 X86CPU *cpu = X86_CPU(obj);
1535 DeviceState *dev = DEVICE(obj);
1536 const int64_t min = 0;
1537 const int64_t max = UINT32_MAX;
1538 Error *error = NULL;
1539 int64_t value;
1540
1541 if (dev->realized) {
1542 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1543 "it was realized", name, object_get_typename(obj));
1544 return;
1545 }
1546
1547 visit_type_int(v, &value, name, &error);
1548 if (error) {
1549 error_propagate(errp, error);
1550 return;
1551 }
1552 if (value < min || value > max) {
1553 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1554 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1555 object_get_typename(obj), name, value, min, max);
1556 return;
1557 }
1558
1559 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1560 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1561 return;
1562 }
1563 cpu->env.cpuid_apic_id = value;
1564 }
1565
1566 /* Generic getter for "feature-words" and "filtered-features" properties */
1567 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1568 const char *name, Error **errp)
1569 {
1570 uint32_t *array = (uint32_t *)opaque;
1571 FeatureWord w;
1572 Error *err = NULL;
1573 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1574 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1575 X86CPUFeatureWordInfoList *list = NULL;
1576
1577 for (w = 0; w < FEATURE_WORDS; w++) {
1578 FeatureWordInfo *wi = &feature_word_info[w];
1579 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1580 qwi->cpuid_input_eax = wi->cpuid_eax;
1581 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1582 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1583 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1584 qwi->features = array[w];
1585
1586 /* List will be in reverse order, but order shouldn't matter */
1587 list_entries[w].next = list;
1588 list_entries[w].value = &word_infos[w];
1589 list = &list_entries[w];
1590 }
1591
1592 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1593 error_propagate(errp, err);
1594 }
1595
1596 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1597 const char *name, Error **errp)
1598 {
1599 X86CPU *cpu = X86_CPU(obj);
1600 int64_t value = cpu->hyperv_spinlock_attempts;
1601
1602 visit_type_int(v, &value, name, errp);
1603 }
1604
1605 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1606 const char *name, Error **errp)
1607 {
1608 const int64_t min = 0xFFF;
1609 const int64_t max = UINT_MAX;
1610 X86CPU *cpu = X86_CPU(obj);
1611 Error *err = NULL;
1612 int64_t value;
1613
1614 visit_type_int(v, &value, name, &err);
1615 if (err) {
1616 error_propagate(errp, err);
1617 return;
1618 }
1619
1620 if (value < min || value > max) {
1621 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1622 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1623 object_get_typename(obj), name ? name : "null",
1624 value, min, max);
1625 return;
1626 }
1627 cpu->hyperv_spinlock_attempts = value;
1628 }
1629
1630 static PropertyInfo qdev_prop_spinlocks = {
1631 .name = "int",
1632 .get = x86_get_hv_spinlocks,
1633 .set = x86_set_hv_spinlocks,
1634 };
1635
1636 static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1637 const char *name)
1638 {
1639 x86_def_t *def;
1640 Error *err = NULL;
1641 int i;
1642
1643 if (name == NULL) {
1644 return -1;
1645 }
1646 if (kvm_enabled() && strcmp(name, "host") == 0) {
1647 kvm_cpu_fill_host(x86_cpu_def);
1648 object_property_set_bool(OBJECT(cpu), true, "pmu", &err);
1649 assert_no_error(err);
1650 return 0;
1651 }
1652
1653 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1654 def = &builtin_x86_defs[i];
1655 if (strcmp(name, def->name) == 0) {
1656 memcpy(x86_cpu_def, def, sizeof(*def));
1657 /* sysenter isn't supported in compatibility mode on AMD,
1658 * syscall isn't supported in compatibility mode on Intel.
1659 * Normally we advertise the actual CPU vendor, but you can
1660 * override this using the 'vendor' property if you want to use
1661 * KVM's sysenter/syscall emulation in compatibility mode and
1662 * when doing cross vendor migration
1663 */
1664 if (kvm_enabled()) {
1665 uint32_t ebx = 0, ecx = 0, edx = 0;
1666 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1667 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1668 }
1669 return 0;
1670 }
1671 }
1672
1673 return -1;
1674 }
1675
1676 /* Convert all '_' in a feature string option name to '-', to make feature
1677 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1678 */
1679 static inline void feat2prop(char *s)
1680 {
1681 while ((s = strchr(s, '_'))) {
1682 *s = '-';
1683 }
1684 }
1685
1686 /* Parse "+feature,-feature,feature=foo" CPU feature string
1687 */
1688 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1689 {
1690 char *featurestr; /* Single 'key=value" string being parsed */
1691 /* Features to be added */
1692 FeatureWordArray plus_features = { 0 };
1693 /* Features to be removed */
1694 FeatureWordArray minus_features = { 0 };
1695 uint32_t numvalue;
1696 CPUX86State *env = &cpu->env;
1697
1698 featurestr = features ? strtok(features, ",") : NULL;
1699
1700 while (featurestr) {
1701 char *val;
1702 if (featurestr[0] == '+') {
1703 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1704 } else if (featurestr[0] == '-') {
1705 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1706 } else if ((val = strchr(featurestr, '='))) {
1707 *val = 0; val++;
1708 feat2prop(featurestr);
1709 if (!strcmp(featurestr, "xlevel")) {
1710 char *err;
1711 char num[32];
1712
1713 numvalue = strtoul(val, &err, 0);
1714 if (!*val || *err) {
1715 error_setg(errp, "bad numerical value %s", val);
1716 goto out;
1717 }
1718 if (numvalue < 0x80000000) {
1719 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1720 ", fixup will be removed in future versions\n");
1721 numvalue += 0x80000000;
1722 }
1723 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1724 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1725 } else if (!strcmp(featurestr, "tsc-freq")) {
1726 int64_t tsc_freq;
1727 char *err;
1728 char num[32];
1729
1730 tsc_freq = strtosz_suffix_unit(val, &err,
1731 STRTOSZ_DEFSUFFIX_B, 1000);
1732 if (tsc_freq < 0 || *err) {
1733 error_setg(errp, "bad numerical value %s", val);
1734 goto out;
1735 }
1736 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1737 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1738 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1739 char *err;
1740 const int min = 0xFFF;
1741 char num[32];
1742 numvalue = strtoul(val, &err, 0);
1743 if (!*val || *err) {
1744 error_setg(errp, "bad numerical value %s", val);
1745 goto out;
1746 }
1747 if (numvalue < min) {
1748 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1749 ", fixup will be removed in future versions\n",
1750 min);
1751 numvalue = min;
1752 }
1753 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1754 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1755 } else {
1756 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1757 }
1758 } else {
1759 feat2prop(featurestr);
1760 object_property_parse(OBJECT(cpu), "on", featurestr, errp);
1761 }
1762 if (error_is_set(errp)) {
1763 goto out;
1764 }
1765 featurestr = strtok(NULL, ",");
1766 }
1767 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1768 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1769 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1770 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1771 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1772 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1773 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1774 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1775 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1776 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1777 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1778 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1779 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1780 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1781 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1782 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1783
1784 out:
1785 return;
1786 }
1787
1788 /* generate a composite string into buf of all cpuid names in featureset
1789 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1790 * if flags, suppress names undefined in featureset.
1791 */
1792 static void listflags(char *buf, int bufsize, uint32_t fbits,
1793 const char **featureset, uint32_t flags)
1794 {
1795 const char **p = &featureset[31];
1796 char *q, *b, bit;
1797 int nc;
1798
1799 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1800 *buf = '\0';
1801 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1802 if (fbits & 1 << bit && (*p || !flags)) {
1803 if (*p)
1804 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1805 else
1806 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1807 if (bufsize <= nc) {
1808 if (b) {
1809 memcpy(b, "...", sizeof("..."));
1810 }
1811 return;
1812 }
1813 q += nc;
1814 bufsize -= nc;
1815 }
1816 }
1817
1818 /* generate CPU information. */
1819 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1820 {
1821 x86_def_t *def;
1822 char buf[256];
1823 int i;
1824
1825 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1826 def = &builtin_x86_defs[i];
1827 snprintf(buf, sizeof(buf), "%s", def->name);
1828 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1829 }
1830 #ifdef CONFIG_KVM
1831 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1832 "KVM processor with all supported host features "
1833 "(only available in KVM mode)");
1834 #endif
1835
1836 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1837 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1838 FeatureWordInfo *fw = &feature_word_info[i];
1839
1840 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1841 (*cpu_fprintf)(f, " %s\n", buf);
1842 }
1843 }
1844
1845 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1846 {
1847 CpuDefinitionInfoList *cpu_list = NULL;
1848 x86_def_t *def;
1849 int i;
1850
1851 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1852 CpuDefinitionInfoList *entry;
1853 CpuDefinitionInfo *info;
1854
1855 def = &builtin_x86_defs[i];
1856 info = g_malloc0(sizeof(*info));
1857 info->name = g_strdup(def->name);
1858
1859 entry = g_malloc0(sizeof(*entry));
1860 entry->value = info;
1861 entry->next = cpu_list;
1862 cpu_list = entry;
1863 }
1864
1865 return cpu_list;
1866 }
1867
1868 #ifdef CONFIG_KVM
1869 static void filter_features_for_kvm(X86CPU *cpu)
1870 {
1871 CPUX86State *env = &cpu->env;
1872 KVMState *s = kvm_state;
1873 FeatureWord w;
1874
1875 for (w = 0; w < FEATURE_WORDS; w++) {
1876 FeatureWordInfo *wi = &feature_word_info[w];
1877 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1878 wi->cpuid_ecx,
1879 wi->cpuid_reg);
1880 uint32_t requested_features = env->features[w];
1881 env->features[w] &= host_feat;
1882 cpu->filtered_features[w] = requested_features & ~env->features[w];
1883 }
1884 }
1885 #endif
1886
1887 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1888 {
1889 CPUX86State *env = &cpu->env;
1890 x86_def_t def1, *def = &def1;
1891
1892 memset(def, 0, sizeof(*def));
1893
1894 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
1895 error_setg(errp, "Unable to find CPU definition: %s", name);
1896 return;
1897 }
1898
1899 if (kvm_enabled()) {
1900 def->features[FEAT_KVM] |= kvm_default_features;
1901 }
1902 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1903
1904 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1905 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1906 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1907 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1908 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1909 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1910 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1911 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1912 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1913 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1914 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1915 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1916 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1917 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1918 env->cpuid_xlevel2 = def->xlevel2;
1919 cpu->cache_info_passthrough = def->cache_info_passthrough;
1920
1921 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1922 }
1923
1924 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1925 Error **errp)
1926 {
1927 X86CPU *cpu = NULL;
1928 gchar **model_pieces;
1929 char *name, *features;
1930 char *typename;
1931 Error *error = NULL;
1932
1933 model_pieces = g_strsplit(cpu_model, ",", 2);
1934 if (!model_pieces[0]) {
1935 error_setg(&error, "Invalid/empty CPU model name");
1936 goto out;
1937 }
1938 name = model_pieces[0];
1939 features = model_pieces[1];
1940
1941 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1942 #ifndef CONFIG_USER_ONLY
1943 if (icc_bridge == NULL) {
1944 error_setg(&error, "Invalid icc-bridge value");
1945 goto out;
1946 }
1947 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1948 object_unref(OBJECT(cpu));
1949 #endif
1950
1951 cpu_x86_register(cpu, name, &error);
1952 if (error) {
1953 goto out;
1954 }
1955
1956 /* Emulate per-model subclasses for global properties */
1957 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1958 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1959 g_free(typename);
1960 if (error) {
1961 goto out;
1962 }
1963
1964 cpu_x86_parse_featurestr(cpu, features, &error);
1965 if (error) {
1966 goto out;
1967 }
1968
1969 out:
1970 if (error != NULL) {
1971 error_propagate(errp, error);
1972 object_unref(OBJECT(cpu));
1973 cpu = NULL;
1974 }
1975 g_strfreev(model_pieces);
1976 return cpu;
1977 }
1978
1979 X86CPU *cpu_x86_init(const char *cpu_model)
1980 {
1981 Error *error = NULL;
1982 X86CPU *cpu;
1983
1984 cpu = cpu_x86_create(cpu_model, NULL, &error);
1985 if (error) {
1986 goto out;
1987 }
1988
1989 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1990
1991 out:
1992 if (error) {
1993 error_report("%s", error_get_pretty(error));
1994 error_free(error);
1995 if (cpu != NULL) {
1996 object_unref(OBJECT(cpu));
1997 cpu = NULL;
1998 }
1999 }
2000 return cpu;
2001 }
2002
2003 #if !defined(CONFIG_USER_ONLY)
2004
2005 void cpu_clear_apic_feature(CPUX86State *env)
2006 {
2007 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2008 }
2009
2010 #endif /* !CONFIG_USER_ONLY */
2011
2012 /* Initialize list of CPU models, filling some non-static fields if necessary
2013 */
2014 void x86_cpudef_setup(void)
2015 {
2016 int i, j;
2017 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2018
2019 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2020 x86_def_t *def = &builtin_x86_defs[i];
2021
2022 /* Look for specific "cpudef" models that */
2023 /* have the QEMU version in .model_id */
2024 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2025 if (strcmp(model_with_versions[j], def->name) == 0) {
2026 pstrcpy(def->model_id, sizeof(def->model_id),
2027 "QEMU Virtual CPU version ");
2028 pstrcat(def->model_id, sizeof(def->model_id),
2029 qemu_get_version());
2030 break;
2031 }
2032 }
2033 }
2034 }
2035
2036 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2037 uint32_t *ecx, uint32_t *edx)
2038 {
2039 *ebx = env->cpuid_vendor1;
2040 *edx = env->cpuid_vendor2;
2041 *ecx = env->cpuid_vendor3;
2042 }
2043
2044 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2045 uint32_t *eax, uint32_t *ebx,
2046 uint32_t *ecx, uint32_t *edx)
2047 {
2048 X86CPU *cpu = x86_env_get_cpu(env);
2049 CPUState *cs = CPU(cpu);
2050
2051 /* test if maximum index reached */
2052 if (index & 0x80000000) {
2053 if (index > env->cpuid_xlevel) {
2054 if (env->cpuid_xlevel2 > 0) {
2055 /* Handle the Centaur's CPUID instruction. */
2056 if (index > env->cpuid_xlevel2) {
2057 index = env->cpuid_xlevel2;
2058 } else if (index < 0xC0000000) {
2059 index = env->cpuid_xlevel;
2060 }
2061 } else {
2062 /* Intel documentation states that invalid EAX input will
2063 * return the same information as EAX=cpuid_level
2064 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2065 */
2066 index = env->cpuid_level;
2067 }
2068 }
2069 } else {
2070 if (index > env->cpuid_level)
2071 index = env->cpuid_level;
2072 }
2073
2074 switch(index) {
2075 case 0:
2076 *eax = env->cpuid_level;
2077 get_cpuid_vendor(env, ebx, ecx, edx);
2078 break;
2079 case 1:
2080 *eax = env->cpuid_version;
2081 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2082 *ecx = env->features[FEAT_1_ECX];
2083 *edx = env->features[FEAT_1_EDX];
2084 if (cs->nr_cores * cs->nr_threads > 1) {
2085 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2086 *edx |= 1 << 28; /* HTT bit */
2087 }
2088 break;
2089 case 2:
2090 /* cache info: needed for Pentium Pro compatibility */
2091 if (cpu->cache_info_passthrough) {
2092 host_cpuid(index, 0, eax, ebx, ecx, edx);
2093 break;
2094 }
2095 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2096 *ebx = 0;
2097 *ecx = 0;
2098 *edx = (L1D_DESCRIPTOR << 16) | \
2099 (L1I_DESCRIPTOR << 8) | \
2100 (L2_DESCRIPTOR);
2101 break;
2102 case 4:
2103 /* cache info: needed for Core compatibility */
2104 if (cpu->cache_info_passthrough) {
2105 host_cpuid(index, count, eax, ebx, ecx, edx);
2106 *eax &= ~0xFC000000;
2107 } else {
2108 *eax = 0;
2109 switch (count) {
2110 case 0: /* L1 dcache info */
2111 *eax |= CPUID_4_TYPE_DCACHE | \
2112 CPUID_4_LEVEL(1) | \
2113 CPUID_4_SELF_INIT_LEVEL;
2114 *ebx = (L1D_LINE_SIZE - 1) | \
2115 ((L1D_PARTITIONS - 1) << 12) | \
2116 ((L1D_ASSOCIATIVITY - 1) << 22);
2117 *ecx = L1D_SETS - 1;
2118 *edx = CPUID_4_NO_INVD_SHARING;
2119 break;
2120 case 1: /* L1 icache info */
2121 *eax |= CPUID_4_TYPE_ICACHE | \
2122 CPUID_4_LEVEL(1) | \
2123 CPUID_4_SELF_INIT_LEVEL;
2124 *ebx = (L1I_LINE_SIZE - 1) | \
2125 ((L1I_PARTITIONS - 1) << 12) | \
2126 ((L1I_ASSOCIATIVITY - 1) << 22);
2127 *ecx = L1I_SETS - 1;
2128 *edx = CPUID_4_NO_INVD_SHARING;
2129 break;
2130 case 2: /* L2 cache info */
2131 *eax |= CPUID_4_TYPE_UNIFIED | \
2132 CPUID_4_LEVEL(2) | \
2133 CPUID_4_SELF_INIT_LEVEL;
2134 if (cs->nr_threads > 1) {
2135 *eax |= (cs->nr_threads - 1) << 14;
2136 }
2137 *ebx = (L2_LINE_SIZE - 1) | \
2138 ((L2_PARTITIONS - 1) << 12) | \
2139 ((L2_ASSOCIATIVITY - 1) << 22);
2140 *ecx = L2_SETS - 1;
2141 *edx = CPUID_4_NO_INVD_SHARING;
2142 break;
2143 default: /* end of info */
2144 *eax = 0;
2145 *ebx = 0;
2146 *ecx = 0;
2147 *edx = 0;
2148 break;
2149 }
2150 }
2151
2152 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2153 if ((*eax & 31) && cs->nr_cores > 1) {
2154 *eax |= (cs->nr_cores - 1) << 26;
2155 }
2156 break;
2157 case 5:
2158 /* mwait info: needed for Core compatibility */
2159 *eax = 0; /* Smallest monitor-line size in bytes */
2160 *ebx = 0; /* Largest monitor-line size in bytes */
2161 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2162 *edx = 0;
2163 break;
2164 case 6:
2165 /* Thermal and Power Leaf */
2166 *eax = 0;
2167 *ebx = 0;
2168 *ecx = 0;
2169 *edx = 0;
2170 break;
2171 case 7:
2172 /* Structured Extended Feature Flags Enumeration Leaf */
2173 if (count == 0) {
2174 *eax = 0; /* Maximum ECX value for sub-leaves */
2175 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2176 *ecx = 0; /* Reserved */
2177 *edx = 0; /* Reserved */
2178 } else {
2179 *eax = 0;
2180 *ebx = 0;
2181 *ecx = 0;
2182 *edx = 0;
2183 }
2184 break;
2185 case 9:
2186 /* Direct Cache Access Information Leaf */
2187 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2188 *ebx = 0;
2189 *ecx = 0;
2190 *edx = 0;
2191 break;
2192 case 0xA:
2193 /* Architectural Performance Monitoring Leaf */
2194 if (kvm_enabled() && cpu->enable_pmu) {
2195 KVMState *s = cs->kvm_state;
2196
2197 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2198 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2199 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2200 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2201 } else {
2202 *eax = 0;
2203 *ebx = 0;
2204 *ecx = 0;
2205 *edx = 0;
2206 }
2207 break;
2208 case 0xD: {
2209 KVMState *s = cs->kvm_state;
2210 uint64_t kvm_mask;
2211 int i;
2212
2213 /* Processor Extended State */
2214 *eax = 0;
2215 *ebx = 0;
2216 *ecx = 0;
2217 *edx = 0;
2218 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2219 break;
2220 }
2221 kvm_mask =
2222 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2223 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2224
2225 if (count == 0) {
2226 *ecx = 0x240;
2227 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2228 const ExtSaveArea *esa = &ext_save_areas[i];
2229 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2230 (kvm_mask & (1 << i)) != 0) {
2231 if (i < 32) {
2232 *eax |= 1 << i;
2233 } else {
2234 *edx |= 1 << (i - 32);
2235 }
2236 *ecx = MAX(*ecx, esa->offset + esa->size);
2237 }
2238 }
2239 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2240 *ebx = *ecx;
2241 } else if (count == 1) {
2242 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2243 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2244 const ExtSaveArea *esa = &ext_save_areas[count];
2245 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2246 (kvm_mask & (1 << count)) != 0) {
2247 *eax = esa->size;
2248 *ebx = esa->offset;
2249 }
2250 }
2251 break;
2252 }
2253 case 0x80000000:
2254 *eax = env->cpuid_xlevel;
2255 *ebx = env->cpuid_vendor1;
2256 *edx = env->cpuid_vendor2;
2257 *ecx = env->cpuid_vendor3;
2258 break;
2259 case 0x80000001:
2260 *eax = env->cpuid_version;
2261 *ebx = 0;
2262 *ecx = env->features[FEAT_8000_0001_ECX];
2263 *edx = env->features[FEAT_8000_0001_EDX];
2264
2265 /* The Linux kernel checks for the CMPLegacy bit and
2266 * discards multiple thread information if it is set.
2267 * So dont set it here for Intel to make Linux guests happy.
2268 */
2269 if (cs->nr_cores * cs->nr_threads > 1) {
2270 uint32_t tebx, tecx, tedx;
2271 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2272 if (tebx != CPUID_VENDOR_INTEL_1 ||
2273 tedx != CPUID_VENDOR_INTEL_2 ||
2274 tecx != CPUID_VENDOR_INTEL_3) {
2275 *ecx |= 1 << 1; /* CmpLegacy bit */
2276 }
2277 }
2278 break;
2279 case 0x80000002:
2280 case 0x80000003:
2281 case 0x80000004:
2282 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2283 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2284 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2285 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2286 break;
2287 case 0x80000005:
2288 /* cache info (L1 cache) */
2289 if (cpu->cache_info_passthrough) {
2290 host_cpuid(index, 0, eax, ebx, ecx, edx);
2291 break;
2292 }
2293 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2294 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2295 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2296 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2297 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2298 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2299 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2300 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2301 break;
2302 case 0x80000006:
2303 /* cache info (L2 cache) */
2304 if (cpu->cache_info_passthrough) {
2305 host_cpuid(index, 0, eax, ebx, ecx, edx);
2306 break;
2307 }
2308 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2309 (L2_DTLB_2M_ENTRIES << 16) | \
2310 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2311 (L2_ITLB_2M_ENTRIES);
2312 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2313 (L2_DTLB_4K_ENTRIES << 16) | \
2314 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2315 (L2_ITLB_4K_ENTRIES);
2316 *ecx = (L2_SIZE_KB_AMD << 16) | \
2317 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2318 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2319 *edx = ((L3_SIZE_KB/512) << 18) | \
2320 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2321 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2322 break;
2323 case 0x80000008:
2324 /* virtual & phys address size in low 2 bytes. */
2325 /* XXX: This value must match the one used in the MMU code. */
2326 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2327 /* 64 bit processor */
2328 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2329 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2330 } else {
2331 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2332 *eax = 0x00000024; /* 36 bits physical */
2333 } else {
2334 *eax = 0x00000020; /* 32 bits physical */
2335 }
2336 }
2337 *ebx = 0;
2338 *ecx = 0;
2339 *edx = 0;
2340 if (cs->nr_cores * cs->nr_threads > 1) {
2341 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2342 }
2343 break;
2344 case 0x8000000A:
2345 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2346 *eax = 0x00000001; /* SVM Revision */
2347 *ebx = 0x00000010; /* nr of ASIDs */
2348 *ecx = 0;
2349 *edx = env->features[FEAT_SVM]; /* optional features */
2350 } else {
2351 *eax = 0;
2352 *ebx = 0;
2353 *ecx = 0;
2354 *edx = 0;
2355 }
2356 break;
2357 case 0xC0000000:
2358 *eax = env->cpuid_xlevel2;
2359 *ebx = 0;
2360 *ecx = 0;
2361 *edx = 0;
2362 break;
2363 case 0xC0000001:
2364 /* Support for VIA CPU's CPUID instruction */
2365 *eax = env->cpuid_version;
2366 *ebx = 0;
2367 *ecx = 0;
2368 *edx = env->features[FEAT_C000_0001_EDX];
2369 break;
2370 case 0xC0000002:
2371 case 0xC0000003:
2372 case 0xC0000004:
2373 /* Reserved for the future, and now filled with zero */
2374 *eax = 0;
2375 *ebx = 0;
2376 *ecx = 0;
2377 *edx = 0;
2378 break;
2379 default:
2380 /* reserved values: zero */
2381 *eax = 0;
2382 *ebx = 0;
2383 *ecx = 0;
2384 *edx = 0;
2385 break;
2386 }
2387 }
2388
2389 /* CPUClass::reset() */
2390 static void x86_cpu_reset(CPUState *s)
2391 {
2392 X86CPU *cpu = X86_CPU(s);
2393 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2394 CPUX86State *env = &cpu->env;
2395 int i;
2396
2397 xcc->parent_reset(s);
2398
2399
2400 memset(env, 0, offsetof(CPUX86State, breakpoints));
2401
2402 tlb_flush(env, 1);
2403
2404 env->old_exception = -1;
2405
2406 /* init to reset state */
2407
2408 #ifdef CONFIG_SOFTMMU
2409 env->hflags |= HF_SOFTMMU_MASK;
2410 #endif
2411 env->hflags2 |= HF2_GIF_MASK;
2412
2413 cpu_x86_update_cr0(env, 0x60000010);
2414 env->a20_mask = ~0x0;
2415 env->smbase = 0x30000;
2416
2417 env->idt.limit = 0xffff;
2418 env->gdt.limit = 0xffff;
2419 env->ldt.limit = 0xffff;
2420 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2421 env->tr.limit = 0xffff;
2422 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2423
2424 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2425 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2426 DESC_R_MASK | DESC_A_MASK);
2427 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2428 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2429 DESC_A_MASK);
2430 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2431 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2432 DESC_A_MASK);
2433 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2434 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2435 DESC_A_MASK);
2436 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2437 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2438 DESC_A_MASK);
2439 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2440 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2441 DESC_A_MASK);
2442
2443 env->eip = 0xfff0;
2444 env->regs[R_EDX] = env->cpuid_version;
2445
2446 env->eflags = 0x2;
2447
2448 /* FPU init */
2449 for (i = 0; i < 8; i++) {
2450 env->fptags[i] = 1;
2451 }
2452 env->fpuc = 0x37f;
2453
2454 env->mxcsr = 0x1f80;
2455 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2456
2457 env->pat = 0x0007040600070406ULL;
2458 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2459
2460 memset(env->dr, 0, sizeof(env->dr));
2461 env->dr[6] = DR6_FIXED_1;
2462 env->dr[7] = DR7_FIXED_1;
2463 cpu_breakpoint_remove_all(env, BP_CPU);
2464 cpu_watchpoint_remove_all(env, BP_CPU);
2465
2466 #if !defined(CONFIG_USER_ONLY)
2467 /* We hard-wire the BSP to the first CPU. */
2468 if (s->cpu_index == 0) {
2469 apic_designate_bsp(cpu->apic_state);
2470 }
2471
2472 s->halted = !cpu_is_bsp(cpu);
2473 #endif
2474 }
2475
2476 #ifndef CONFIG_USER_ONLY
2477 bool cpu_is_bsp(X86CPU *cpu)
2478 {
2479 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2480 }
2481
2482 /* TODO: remove me, when reset over QOM tree is implemented */
2483 static void x86_cpu_machine_reset_cb(void *opaque)
2484 {
2485 X86CPU *cpu = opaque;
2486 cpu_reset(CPU(cpu));
2487 }
2488 #endif
2489
2490 static void mce_init(X86CPU *cpu)
2491 {
2492 CPUX86State *cenv = &cpu->env;
2493 unsigned int bank;
2494
2495 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2496 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2497 (CPUID_MCE | CPUID_MCA)) {
2498 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2499 cenv->mcg_ctl = ~(uint64_t)0;
2500 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2501 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2502 }
2503 }
2504 }
2505
2506 #ifndef CONFIG_USER_ONLY
2507 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2508 {
2509 CPUX86State *env = &cpu->env;
2510 DeviceState *dev = DEVICE(cpu);
2511 APICCommonState *apic;
2512 const char *apic_type = "apic";
2513
2514 if (kvm_irqchip_in_kernel()) {
2515 apic_type = "kvm-apic";
2516 } else if (xen_enabled()) {
2517 apic_type = "xen-apic";
2518 }
2519
2520 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2521 if (cpu->apic_state == NULL) {
2522 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2523 return;
2524 }
2525
2526 object_property_add_child(OBJECT(cpu), "apic",
2527 OBJECT(cpu->apic_state), NULL);
2528 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2529 /* TODO: convert to link<> */
2530 apic = APIC_COMMON(cpu->apic_state);
2531 apic->cpu = cpu;
2532 }
2533
2534 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2535 {
2536 if (cpu->apic_state == NULL) {
2537 return;
2538 }
2539
2540 if (qdev_init(cpu->apic_state)) {
2541 error_setg(errp, "APIC device '%s' could not be initialized",
2542 object_get_typename(OBJECT(cpu->apic_state)));
2543 return;
2544 }
2545 }
2546 #else
2547 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2548 {
2549 }
2550 #endif
2551
2552 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2553 {
2554 CPUState *cs = CPU(dev);
2555 X86CPU *cpu = X86_CPU(dev);
2556 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2557 CPUX86State *env = &cpu->env;
2558 Error *local_err = NULL;
2559
2560 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2561 env->cpuid_level = 7;
2562 }
2563
2564 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2565 * CPUID[1].EDX.
2566 */
2567 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2568 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2569 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2570 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2571 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2572 & CPUID_EXT2_AMD_ALIASES);
2573 }
2574
2575 if (!kvm_enabled()) {
2576 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2577 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2578 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2579 #ifdef TARGET_X86_64
2580 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2581 #endif
2582 );
2583 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2584 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2585 } else {
2586 if ((cpu->check_cpuid || cpu->enforce_cpuid)
2587 && kvm_check_features_against_host(cpu) && cpu->enforce_cpuid) {
2588 error_setg(&local_err,
2589 "Host's CPU doesn't support requested features");
2590 goto out;
2591 }
2592 #ifdef CONFIG_KVM
2593 filter_features_for_kvm(cpu);
2594 #endif
2595 }
2596
2597 #ifndef CONFIG_USER_ONLY
2598 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2599
2600 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2601 x86_cpu_apic_create(cpu, &local_err);
2602 if (local_err != NULL) {
2603 goto out;
2604 }
2605 }
2606 #endif
2607
2608 mce_init(cpu);
2609 qemu_init_vcpu(cs);
2610
2611 x86_cpu_apic_realize(cpu, &local_err);
2612 if (local_err != NULL) {
2613 goto out;
2614 }
2615 cpu_reset(cs);
2616
2617 xcc->parent_realize(dev, &local_err);
2618 out:
2619 if (local_err != NULL) {
2620 error_propagate(errp, local_err);
2621 return;
2622 }
2623 }
2624
2625 /* Enables contiguous-apic-ID mode, for compatibility */
2626 static bool compat_apic_id_mode;
2627
2628 void enable_compat_apic_id_mode(void)
2629 {
2630 compat_apic_id_mode = true;
2631 }
2632
2633 /* Calculates initial APIC ID for a specific CPU index
2634 *
2635 * Currently we need to be able to calculate the APIC ID from the CPU index
2636 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2637 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2638 * all CPUs up to max_cpus.
2639 */
2640 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2641 {
2642 uint32_t correct_id;
2643 static bool warned;
2644
2645 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2646 if (compat_apic_id_mode) {
2647 if (cpu_index != correct_id && !warned) {
2648 error_report("APIC IDs set in compatibility mode, "
2649 "CPU topology won't match the configuration");
2650 warned = true;
2651 }
2652 return cpu_index;
2653 } else {
2654 return correct_id;
2655 }
2656 }
2657
2658 static void x86_cpu_initfn(Object *obj)
2659 {
2660 CPUState *cs = CPU(obj);
2661 X86CPU *cpu = X86_CPU(obj);
2662 CPUX86State *env = &cpu->env;
2663 static int inited;
2664
2665 cs->env_ptr = env;
2666 cpu_exec_init(env);
2667
2668 object_property_add(obj, "family", "int",
2669 x86_cpuid_version_get_family,
2670 x86_cpuid_version_set_family, NULL, NULL, NULL);
2671 object_property_add(obj, "model", "int",
2672 x86_cpuid_version_get_model,
2673 x86_cpuid_version_set_model, NULL, NULL, NULL);
2674 object_property_add(obj, "stepping", "int",
2675 x86_cpuid_version_get_stepping,
2676 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2677 object_property_add(obj, "level", "int",
2678 x86_cpuid_get_level,
2679 x86_cpuid_set_level, NULL, NULL, NULL);
2680 object_property_add(obj, "xlevel", "int",
2681 x86_cpuid_get_xlevel,
2682 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2683 object_property_add_str(obj, "vendor",
2684 x86_cpuid_get_vendor,
2685 x86_cpuid_set_vendor, NULL);
2686 object_property_add_str(obj, "model-id",
2687 x86_cpuid_get_model_id,
2688 x86_cpuid_set_model_id, NULL);
2689 object_property_add(obj, "tsc-frequency", "int",
2690 x86_cpuid_get_tsc_freq,
2691 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2692 object_property_add(obj, "apic-id", "int",
2693 x86_cpuid_get_apic_id,
2694 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2695 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2696 x86_cpu_get_feature_words,
2697 NULL, NULL, (void *)env->features, NULL);
2698 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2699 x86_cpu_get_feature_words,
2700 NULL, NULL, (void *)cpu->filtered_features, NULL);
2701
2702 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2703 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2704
2705 /* init various static tables used in TCG mode */
2706 if (tcg_enabled() && !inited) {
2707 inited = 1;
2708 optimize_flags_init();
2709 #ifndef CONFIG_USER_ONLY
2710 cpu_set_debug_excp_handler(breakpoint_handler);
2711 #endif
2712 }
2713 }
2714
2715 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2716 {
2717 X86CPU *cpu = X86_CPU(cs);
2718 CPUX86State *env = &cpu->env;
2719
2720 return env->cpuid_apic_id;
2721 }
2722
2723 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2724 {
2725 X86CPU *cpu = X86_CPU(cs);
2726
2727 return cpu->env.cr[0] & CR0_PG_MASK;
2728 }
2729
2730 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2731 {
2732 X86CPU *cpu = X86_CPU(cs);
2733
2734 cpu->env.eip = value;
2735 }
2736
2737 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2738 {
2739 X86CPU *cpu = X86_CPU(cs);
2740
2741 cpu->env.eip = tb->pc - tb->cs_base;
2742 }
2743
2744 static Property x86_cpu_properties[] = {
2745 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2746 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2747 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2748 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2749 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2750 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2751 DEFINE_PROP_END_OF_LIST()
2752 };
2753
2754 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2755 {
2756 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2757 CPUClass *cc = CPU_CLASS(oc);
2758 DeviceClass *dc = DEVICE_CLASS(oc);
2759
2760 xcc->parent_realize = dc->realize;
2761 dc->realize = x86_cpu_realizefn;
2762 dc->bus_type = TYPE_ICC_BUS;
2763 dc->props = x86_cpu_properties;
2764
2765 xcc->parent_reset = cc->reset;
2766 cc->reset = x86_cpu_reset;
2767 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2768
2769 cc->do_interrupt = x86_cpu_do_interrupt;
2770 cc->dump_state = x86_cpu_dump_state;
2771 cc->set_pc = x86_cpu_set_pc;
2772 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2773 cc->gdb_read_register = x86_cpu_gdb_read_register;
2774 cc->gdb_write_register = x86_cpu_gdb_write_register;
2775 cc->get_arch_id = x86_cpu_get_arch_id;
2776 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2777 #ifndef CONFIG_USER_ONLY
2778 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2779 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2780 cc->write_elf64_note = x86_cpu_write_elf64_note;
2781 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2782 cc->write_elf32_note = x86_cpu_write_elf32_note;
2783 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2784 cc->vmsd = &vmstate_x86_cpu;
2785 #endif
2786 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2787 }
2788
2789 static const TypeInfo x86_cpu_type_info = {
2790 .name = TYPE_X86_CPU,
2791 .parent = TYPE_CPU,
2792 .instance_size = sizeof(X86CPU),
2793 .instance_init = x86_cpu_initfn,
2794 .abstract = false,
2795 .class_size = sizeof(X86CPUClass),
2796 .class_init = x86_cpu_common_class_init,
2797 };
2798
2799 static void x86_cpu_register_types(void)
2800 {
2801 type_register_static(&x86_cpu_type_info);
2802 }
2803
2804 type_init(x86_cpu_register_types)
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