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target-i386: Disable kvm_mmu by default
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26
27 #include "qemu/option.h"
28 #include "qemu/config-file.h"
29 #include "qapi/qmp/qerror.h"
30
31 #include "qapi/visitor.h"
32 #include "sysemu/arch_init.h"
33
34 #include "hyperv.h"
35
36 #include "hw/hw.h"
37 #if defined(CONFIG_KVM)
38 #include <linux/kvm_para.h>
39 #endif
40
41 #include "sysemu/sysemu.h"
42 #ifndef CONFIG_USER_ONLY
43 #include "hw/xen.h"
44 #include "hw/sysbus.h"
45 #include "hw/apic_internal.h"
46 #endif
47
48 /* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52 static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61 };
62 static const char *ext_feature_name[] = {
63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
64 "ds_cpl", "vmx", "smx", "est",
65 "tm2", "ssse3", "cid", NULL,
66 "fma", "cx16", "xtpr", "pdcm",
67 NULL, "pcid", "dca", "sse4.1|sse4_1",
68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
69 "tsc-deadline", "aes", "xsave", "osxsave",
70 "avx", "f16c", "rdrand", "hypervisor",
71 };
72 /* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
77 static const char *ext2_feature_name[] = {
78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
85 NULL, "lm|i64", "3dnowext", "3dnow",
86 };
87 static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
90 "3dnowprefetch", "osvw", "ibs", "xop",
91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
95 NULL, NULL, NULL, NULL,
96 };
97
98 static const char *kvm_feature_name[] = {
99 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
100 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107 };
108
109 static const char *svm_feature_name[] = {
110 "npt", "lbrv", "svm_lock", "nrip_save",
111 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
112 NULL, NULL, "pause_filter", NULL,
113 "pfthreshold", NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 };
119
120 static const char *cpuid_7_0_ebx_feature_name[] = {
121 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
122 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
123 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
125 };
126
127 const char *get_register_name_32(unsigned int reg)
128 {
129 static const char *reg_names[CPU_NB_REGS32] = {
130 [R_EAX] = "EAX",
131 [R_ECX] = "ECX",
132 [R_EDX] = "EDX",
133 [R_EBX] = "EBX",
134 [R_ESP] = "ESP",
135 [R_EBP] = "EBP",
136 [R_ESI] = "ESI",
137 [R_EDI] = "EDI",
138 };
139
140 if (reg > CPU_NB_REGS32) {
141 return NULL;
142 }
143 return reg_names[reg];
144 }
145
146 /* collects per-function cpuid data
147 */
148 typedef struct model_features_t {
149 uint32_t *guest_feat;
150 uint32_t *host_feat;
151 const char **flag_names;
152 uint32_t cpuid;
153 int reg;
154 } model_features_t;
155
156 int check_cpuid = 0;
157 int enforce_cpuid = 0;
158
159 #if defined(CONFIG_KVM)
160 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
161 (1 << KVM_FEATURE_NOP_IO_DELAY) |
162 (1 << KVM_FEATURE_CLOCKSOURCE2) |
163 (1 << KVM_FEATURE_ASYNC_PF) |
164 (1 << KVM_FEATURE_STEAL_TIME) |
165 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
166 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
167 #else
168 static uint32_t kvm_default_features = 0;
169 static const uint32_t kvm_pv_eoi_features = 0;
170 #endif
171
172 void enable_kvm_pv_eoi(void)
173 {
174 kvm_default_features |= kvm_pv_eoi_features;
175 }
176
177 void host_cpuid(uint32_t function, uint32_t count,
178 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
179 {
180 #if defined(CONFIG_KVM)
181 uint32_t vec[4];
182
183 #ifdef __x86_64__
184 asm volatile("cpuid"
185 : "=a"(vec[0]), "=b"(vec[1]),
186 "=c"(vec[2]), "=d"(vec[3])
187 : "0"(function), "c"(count) : "cc");
188 #else
189 asm volatile("pusha \n\t"
190 "cpuid \n\t"
191 "mov %%eax, 0(%2) \n\t"
192 "mov %%ebx, 4(%2) \n\t"
193 "mov %%ecx, 8(%2) \n\t"
194 "mov %%edx, 12(%2) \n\t"
195 "popa"
196 : : "a"(function), "c"(count), "S"(vec)
197 : "memory", "cc");
198 #endif
199
200 if (eax)
201 *eax = vec[0];
202 if (ebx)
203 *ebx = vec[1];
204 if (ecx)
205 *ecx = vec[2];
206 if (edx)
207 *edx = vec[3];
208 #endif
209 }
210
211 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
212
213 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
214 * a substring. ex if !NULL points to the first char after a substring,
215 * otherwise the string is assumed to sized by a terminating nul.
216 * Return lexical ordering of *s1:*s2.
217 */
218 static int sstrcmp(const char *s1, const char *e1, const char *s2,
219 const char *e2)
220 {
221 for (;;) {
222 if (!*s1 || !*s2 || *s1 != *s2)
223 return (*s1 - *s2);
224 ++s1, ++s2;
225 if (s1 == e1 && s2 == e2)
226 return (0);
227 else if (s1 == e1)
228 return (*s2);
229 else if (s2 == e2)
230 return (*s1);
231 }
232 }
233
234 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
235 * '|' delimited (possibly empty) strings in which case search for a match
236 * within the alternatives proceeds left to right. Return 0 for success,
237 * non-zero otherwise.
238 */
239 static int altcmp(const char *s, const char *e, const char *altstr)
240 {
241 const char *p, *q;
242
243 for (q = p = altstr; ; ) {
244 while (*p && *p != '|')
245 ++p;
246 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
247 return (0);
248 if (!*p)
249 return (1);
250 else
251 q = ++p;
252 }
253 }
254
255 /* search featureset for flag *[s..e), if found set corresponding bit in
256 * *pval and return true, otherwise return false
257 */
258 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
259 const char **featureset)
260 {
261 uint32_t mask;
262 const char **ppc;
263 bool found = false;
264
265 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
266 if (*ppc && !altcmp(s, e, *ppc)) {
267 *pval |= mask;
268 found = true;
269 }
270 }
271 return found;
272 }
273
274 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
275 uint32_t *ext_features,
276 uint32_t *ext2_features,
277 uint32_t *ext3_features,
278 uint32_t *kvm_features,
279 uint32_t *svm_features,
280 uint32_t *cpuid_7_0_ebx_features)
281 {
282 if (!lookup_feature(features, flagname, NULL, feature_name) &&
283 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
284 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
285 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
286 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
287 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
288 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
289 cpuid_7_0_ebx_feature_name))
290 fprintf(stderr, "CPU feature %s not found\n", flagname);
291 }
292
293 typedef struct x86_def_t {
294 struct x86_def_t *next;
295 const char *name;
296 uint32_t level;
297 uint32_t vendor1, vendor2, vendor3;
298 int family;
299 int model;
300 int stepping;
301 int tsc_khz;
302 uint32_t features, ext_features, ext2_features, ext3_features;
303 uint32_t kvm_features, svm_features;
304 uint32_t xlevel;
305 char model_id[48];
306 int vendor_override;
307 /* Store the results of Centaur's CPUID instructions */
308 uint32_t ext4_features;
309 uint32_t xlevel2;
310 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
311 uint32_t cpuid_7_0_ebx_features;
312 } x86_def_t;
313
314 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
315 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
316 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
317 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
318 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
319 CPUID_PSE36 | CPUID_FXSR)
320 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
321 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
322 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
323 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
324 CPUID_PAE | CPUID_SEP | CPUID_APIC)
325
326 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
327 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
328 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
329 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
330 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
331 /* partly implemented:
332 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
333 CPUID_PSE36 (needed for Solaris) */
334 /* missing:
335 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
336 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
337 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
338 CPUID_EXT_HYPERVISOR)
339 /* missing:
340 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
341 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
342 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
343 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
344 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
345 /* missing:
346 CPUID_EXT2_PDPE1GB */
347 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
348 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
349 #define TCG_SVM_FEATURES 0
350 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
351
352 /* maintains list of cpu model definitions
353 */
354 static x86_def_t *x86_defs = {NULL};
355
356 /* built-in cpu model definitions (deprecated)
357 */
358 static x86_def_t builtin_x86_defs[] = {
359 {
360 .name = "qemu64",
361 .level = 4,
362 .vendor1 = CPUID_VENDOR_AMD_1,
363 .vendor2 = CPUID_VENDOR_AMD_2,
364 .vendor3 = CPUID_VENDOR_AMD_3,
365 .family = 6,
366 .model = 2,
367 .stepping = 3,
368 .features = PPRO_FEATURES |
369 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
370 CPUID_PSE36,
371 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
372 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
373 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
374 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
375 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
376 .xlevel = 0x8000000A,
377 },
378 {
379 .name = "phenom",
380 .level = 5,
381 .vendor1 = CPUID_VENDOR_AMD_1,
382 .vendor2 = CPUID_VENDOR_AMD_2,
383 .vendor3 = CPUID_VENDOR_AMD_3,
384 .family = 16,
385 .model = 2,
386 .stepping = 3,
387 .features = PPRO_FEATURES |
388 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
389 CPUID_PSE36 | CPUID_VME | CPUID_HT,
390 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
391 CPUID_EXT_POPCNT,
392 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
393 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
394 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
395 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
396 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
397 CPUID_EXT3_CR8LEG,
398 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
399 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
400 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
401 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
402 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
403 .xlevel = 0x8000001A,
404 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
405 },
406 {
407 .name = "core2duo",
408 .level = 10,
409 .vendor1 = CPUID_VENDOR_INTEL_1,
410 .vendor2 = CPUID_VENDOR_INTEL_2,
411 .vendor3 = CPUID_VENDOR_INTEL_3,
412 .family = 6,
413 .model = 15,
414 .stepping = 11,
415 .features = PPRO_FEATURES |
416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
417 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
418 CPUID_HT | CPUID_TM | CPUID_PBE,
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
420 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
421 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
422 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
423 .ext3_features = CPUID_EXT3_LAHF_LM,
424 .xlevel = 0x80000008,
425 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
426 },
427 {
428 .name = "kvm64",
429 .level = 5,
430 .vendor1 = CPUID_VENDOR_INTEL_1,
431 .vendor2 = CPUID_VENDOR_INTEL_2,
432 .vendor3 = CPUID_VENDOR_INTEL_3,
433 .family = 15,
434 .model = 6,
435 .stepping = 1,
436 /* Missing: CPUID_VME, CPUID_HT */
437 .features = PPRO_FEATURES |
438 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
439 CPUID_PSE36,
440 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
441 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
442 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
443 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
444 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
445 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
446 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
447 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
448 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
449 .ext3_features = 0,
450 .xlevel = 0x80000008,
451 .model_id = "Common KVM processor"
452 },
453 {
454 .name = "qemu32",
455 .level = 4,
456 .vendor1 = CPUID_VENDOR_INTEL_1,
457 .vendor2 = CPUID_VENDOR_INTEL_2,
458 .vendor3 = CPUID_VENDOR_INTEL_3,
459 .family = 6,
460 .model = 3,
461 .stepping = 3,
462 .features = PPRO_FEATURES,
463 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
464 .xlevel = 0x80000004,
465 },
466 {
467 .name = "kvm32",
468 .level = 5,
469 .vendor1 = CPUID_VENDOR_INTEL_1,
470 .vendor2 = CPUID_VENDOR_INTEL_2,
471 .vendor3 = CPUID_VENDOR_INTEL_3,
472 .family = 15,
473 .model = 6,
474 .stepping = 1,
475 .features = PPRO_FEATURES |
476 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
477 .ext_features = CPUID_EXT_SSE3,
478 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
479 .ext3_features = 0,
480 .xlevel = 0x80000008,
481 .model_id = "Common 32-bit KVM processor"
482 },
483 {
484 .name = "coreduo",
485 .level = 10,
486 .vendor1 = CPUID_VENDOR_INTEL_1,
487 .vendor2 = CPUID_VENDOR_INTEL_2,
488 .vendor3 = CPUID_VENDOR_INTEL_3,
489 .family = 6,
490 .model = 14,
491 .stepping = 8,
492 .features = PPRO_FEATURES | CPUID_VME |
493 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
494 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
495 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
496 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
497 .ext2_features = CPUID_EXT2_NX,
498 .xlevel = 0x80000008,
499 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
500 },
501 {
502 .name = "486",
503 .level = 1,
504 .vendor1 = CPUID_VENDOR_INTEL_1,
505 .vendor2 = CPUID_VENDOR_INTEL_2,
506 .vendor3 = CPUID_VENDOR_INTEL_3,
507 .family = 4,
508 .model = 0,
509 .stepping = 0,
510 .features = I486_FEATURES,
511 .xlevel = 0,
512 },
513 {
514 .name = "pentium",
515 .level = 1,
516 .vendor1 = CPUID_VENDOR_INTEL_1,
517 .vendor2 = CPUID_VENDOR_INTEL_2,
518 .vendor3 = CPUID_VENDOR_INTEL_3,
519 .family = 5,
520 .model = 4,
521 .stepping = 3,
522 .features = PENTIUM_FEATURES,
523 .xlevel = 0,
524 },
525 {
526 .name = "pentium2",
527 .level = 2,
528 .vendor1 = CPUID_VENDOR_INTEL_1,
529 .vendor2 = CPUID_VENDOR_INTEL_2,
530 .vendor3 = CPUID_VENDOR_INTEL_3,
531 .family = 6,
532 .model = 5,
533 .stepping = 2,
534 .features = PENTIUM2_FEATURES,
535 .xlevel = 0,
536 },
537 {
538 .name = "pentium3",
539 .level = 2,
540 .vendor1 = CPUID_VENDOR_INTEL_1,
541 .vendor2 = CPUID_VENDOR_INTEL_2,
542 .vendor3 = CPUID_VENDOR_INTEL_3,
543 .family = 6,
544 .model = 7,
545 .stepping = 3,
546 .features = PENTIUM3_FEATURES,
547 .xlevel = 0,
548 },
549 {
550 .name = "athlon",
551 .level = 2,
552 .vendor1 = CPUID_VENDOR_AMD_1,
553 .vendor2 = CPUID_VENDOR_AMD_2,
554 .vendor3 = CPUID_VENDOR_AMD_3,
555 .family = 6,
556 .model = 2,
557 .stepping = 3,
558 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
559 CPUID_MCA,
560 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
561 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
562 .xlevel = 0x80000008,
563 },
564 {
565 .name = "n270",
566 /* original is on level 10 */
567 .level = 5,
568 .vendor1 = CPUID_VENDOR_INTEL_1,
569 .vendor2 = CPUID_VENDOR_INTEL_2,
570 .vendor3 = CPUID_VENDOR_INTEL_3,
571 .family = 6,
572 .model = 28,
573 .stepping = 2,
574 .features = PPRO_FEATURES |
575 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
576 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
577 /* Some CPUs got no CPUID_SEP */
578 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
579 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
580 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
581 CPUID_EXT2_NX,
582 .ext3_features = CPUID_EXT3_LAHF_LM,
583 .xlevel = 0x8000000A,
584 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
585 },
586 {
587 .name = "Conroe",
588 .level = 2,
589 .vendor1 = CPUID_VENDOR_INTEL_1,
590 .vendor2 = CPUID_VENDOR_INTEL_2,
591 .vendor3 = CPUID_VENDOR_INTEL_3,
592 .family = 6,
593 .model = 2,
594 .stepping = 3,
595 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
596 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
597 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
598 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
599 CPUID_DE | CPUID_FP87,
600 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
601 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
602 .ext3_features = CPUID_EXT3_LAHF_LM,
603 .xlevel = 0x8000000A,
604 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
605 },
606 {
607 .name = "Penryn",
608 .level = 2,
609 .vendor1 = CPUID_VENDOR_INTEL_1,
610 .vendor2 = CPUID_VENDOR_INTEL_2,
611 .vendor3 = CPUID_VENDOR_INTEL_3,
612 .family = 6,
613 .model = 2,
614 .stepping = 3,
615 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
616 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
617 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
618 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
619 CPUID_DE | CPUID_FP87,
620 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
621 CPUID_EXT_SSE3,
622 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
623 .ext3_features = CPUID_EXT3_LAHF_LM,
624 .xlevel = 0x8000000A,
625 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
626 },
627 {
628 .name = "Nehalem",
629 .level = 2,
630 .vendor1 = CPUID_VENDOR_INTEL_1,
631 .vendor2 = CPUID_VENDOR_INTEL_2,
632 .vendor3 = CPUID_VENDOR_INTEL_3,
633 .family = 6,
634 .model = 2,
635 .stepping = 3,
636 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
637 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
638 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
639 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
640 CPUID_DE | CPUID_FP87,
641 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
642 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
643 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
644 .ext3_features = CPUID_EXT3_LAHF_LM,
645 .xlevel = 0x8000000A,
646 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
647 },
648 {
649 .name = "Westmere",
650 .level = 11,
651 .vendor1 = CPUID_VENDOR_INTEL_1,
652 .vendor2 = CPUID_VENDOR_INTEL_2,
653 .vendor3 = CPUID_VENDOR_INTEL_3,
654 .family = 6,
655 .model = 44,
656 .stepping = 1,
657 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
658 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
659 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
660 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
661 CPUID_DE | CPUID_FP87,
662 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
663 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
664 CPUID_EXT_SSE3,
665 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
666 .ext3_features = CPUID_EXT3_LAHF_LM,
667 .xlevel = 0x8000000A,
668 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
669 },
670 {
671 .name = "SandyBridge",
672 .level = 0xd,
673 .vendor1 = CPUID_VENDOR_INTEL_1,
674 .vendor2 = CPUID_VENDOR_INTEL_2,
675 .vendor3 = CPUID_VENDOR_INTEL_3,
676 .family = 6,
677 .model = 42,
678 .stepping = 1,
679 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
683 CPUID_DE | CPUID_FP87,
684 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
685 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
686 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
687 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
688 CPUID_EXT_SSE3,
689 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
690 CPUID_EXT2_SYSCALL,
691 .ext3_features = CPUID_EXT3_LAHF_LM,
692 .xlevel = 0x8000000A,
693 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
694 },
695 {
696 .name = "Haswell",
697 .level = 0xd,
698 .vendor1 = CPUID_VENDOR_INTEL_1,
699 .vendor2 = CPUID_VENDOR_INTEL_2,
700 .vendor3 = CPUID_VENDOR_INTEL_3,
701 .family = 6,
702 .model = 60,
703 .stepping = 1,
704 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
705 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
706 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
707 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
708 CPUID_DE | CPUID_FP87,
709 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
710 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
711 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
712 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
713 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
714 CPUID_EXT_PCID,
715 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
716 CPUID_EXT2_SYSCALL,
717 .ext3_features = CPUID_EXT3_LAHF_LM,
718 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
719 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
720 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
721 CPUID_7_0_EBX_RTM,
722 .xlevel = 0x8000000A,
723 .model_id = "Intel Core Processor (Haswell)",
724 },
725 {
726 .name = "Opteron_G1",
727 .level = 5,
728 .vendor1 = CPUID_VENDOR_AMD_1,
729 .vendor2 = CPUID_VENDOR_AMD_2,
730 .vendor3 = CPUID_VENDOR_AMD_3,
731 .family = 15,
732 .model = 6,
733 .stepping = 1,
734 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
735 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
736 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
737 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
738 CPUID_DE | CPUID_FP87,
739 .ext_features = CPUID_EXT_SSE3,
740 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
741 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
742 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
743 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
744 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
745 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
746 .xlevel = 0x80000008,
747 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
748 },
749 {
750 .name = "Opteron_G2",
751 .level = 5,
752 .vendor1 = CPUID_VENDOR_AMD_1,
753 .vendor2 = CPUID_VENDOR_AMD_2,
754 .vendor3 = CPUID_VENDOR_AMD_3,
755 .family = 15,
756 .model = 6,
757 .stepping = 1,
758 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
759 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
760 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
761 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
762 CPUID_DE | CPUID_FP87,
763 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
764 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
765 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
766 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
767 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
768 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
769 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
770 CPUID_EXT2_DE | CPUID_EXT2_FPU,
771 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
772 .xlevel = 0x80000008,
773 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
774 },
775 {
776 .name = "Opteron_G3",
777 .level = 5,
778 .vendor1 = CPUID_VENDOR_AMD_1,
779 .vendor2 = CPUID_VENDOR_AMD_2,
780 .vendor3 = CPUID_VENDOR_AMD_3,
781 .family = 15,
782 .model = 6,
783 .stepping = 1,
784 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
785 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
786 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
787 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
788 CPUID_DE | CPUID_FP87,
789 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
790 CPUID_EXT_SSE3,
791 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
792 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
793 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
794 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
795 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
796 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
797 CPUID_EXT2_DE | CPUID_EXT2_FPU,
798 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
799 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
800 .xlevel = 0x80000008,
801 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
802 },
803 {
804 .name = "Opteron_G4",
805 .level = 0xd,
806 .vendor1 = CPUID_VENDOR_AMD_1,
807 .vendor2 = CPUID_VENDOR_AMD_2,
808 .vendor3 = CPUID_VENDOR_AMD_3,
809 .family = 21,
810 .model = 1,
811 .stepping = 2,
812 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
813 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
814 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
815 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
816 CPUID_DE | CPUID_FP87,
817 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
818 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
819 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
820 CPUID_EXT_SSE3,
821 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
822 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
823 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
824 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
825 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
826 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
827 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
828 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
829 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
830 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
831 CPUID_EXT3_LAHF_LM,
832 .xlevel = 0x8000001A,
833 .model_id = "AMD Opteron 62xx class CPU",
834 },
835 {
836 .name = "Opteron_G5",
837 .level = 0xd,
838 .vendor1 = CPUID_VENDOR_AMD_1,
839 .vendor2 = CPUID_VENDOR_AMD_2,
840 .vendor3 = CPUID_VENDOR_AMD_3,
841 .family = 21,
842 .model = 2,
843 .stepping = 0,
844 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
845 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
846 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
847 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
848 CPUID_DE | CPUID_FP87,
849 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
850 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
851 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
852 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
853 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
854 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
855 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
856 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
857 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
858 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
859 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
860 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
861 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
862 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
863 CPUID_EXT3_LAHF_LM,
864 .xlevel = 0x8000001A,
865 .model_id = "AMD Opteron 63xx class CPU",
866 },
867 };
868
869 #ifdef CONFIG_KVM
870 static int cpu_x86_fill_model_id(char *str)
871 {
872 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
873 int i;
874
875 for (i = 0; i < 3; i++) {
876 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
877 memcpy(str + i * 16 + 0, &eax, 4);
878 memcpy(str + i * 16 + 4, &ebx, 4);
879 memcpy(str + i * 16 + 8, &ecx, 4);
880 memcpy(str + i * 16 + 12, &edx, 4);
881 }
882 return 0;
883 }
884 #endif
885
886 /* Fill a x86_def_t struct with information about the host CPU, and
887 * the CPU features supported by the host hardware + host kernel
888 *
889 * This function may be called only if KVM is enabled.
890 */
891 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
892 {
893 #ifdef CONFIG_KVM
894 KVMState *s = kvm_state;
895 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
896
897 assert(kvm_enabled());
898
899 x86_cpu_def->name = "host";
900 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
901 x86_cpu_def->vendor1 = ebx;
902 x86_cpu_def->vendor2 = edx;
903 x86_cpu_def->vendor3 = ecx;
904
905 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
906 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
907 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
908 x86_cpu_def->stepping = eax & 0x0F;
909
910 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
911 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
912 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
913
914 if (x86_cpu_def->level >= 7) {
915 x86_cpu_def->cpuid_7_0_ebx_features =
916 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
917 } else {
918 x86_cpu_def->cpuid_7_0_ebx_features = 0;
919 }
920
921 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
922 x86_cpu_def->ext2_features =
923 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
924 x86_cpu_def->ext3_features =
925 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
926
927 cpu_x86_fill_model_id(x86_cpu_def->model_id);
928 x86_cpu_def->vendor_override = 0;
929
930 /* Call Centaur's CPUID instruction. */
931 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
932 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
933 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
934 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
935 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
936 if (eax >= 0xC0000001) {
937 /* Support VIA max extended level */
938 x86_cpu_def->xlevel2 = eax;
939 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
940 x86_cpu_def->ext4_features =
941 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
942 }
943 }
944
945 /* Other KVM-specific feature fields: */
946 x86_cpu_def->svm_features =
947 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
948 x86_cpu_def->kvm_features =
949 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
950
951 #endif /* CONFIG_KVM */
952 }
953
954 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
955 {
956 int i;
957
958 for (i = 0; i < 32; ++i)
959 if (1 << i & mask) {
960 const char *reg = get_register_name_32(f->reg);
961 assert(reg);
962 fprintf(stderr, "warning: host doesn't support requested feature: "
963 "CPUID.%02XH:%s%s%s [bit %d]\n",
964 f->cpuid, reg,
965 f->flag_names[i] ? "." : "",
966 f->flag_names[i] ? f->flag_names[i] : "", i);
967 break;
968 }
969 return 0;
970 }
971
972 /* best effort attempt to inform user requested cpu flags aren't making
973 * their way to the guest.
974 *
975 * This function may be called only if KVM is enabled.
976 */
977 static int kvm_check_features_against_host(x86_def_t *guest_def)
978 {
979 x86_def_t host_def;
980 uint32_t mask;
981 int rv, i;
982 struct model_features_t ft[] = {
983 {&guest_def->features, &host_def.features,
984 feature_name, 0x00000001, R_EDX},
985 {&guest_def->ext_features, &host_def.ext_features,
986 ext_feature_name, 0x00000001, R_ECX},
987 {&guest_def->ext2_features, &host_def.ext2_features,
988 ext2_feature_name, 0x80000001, R_EDX},
989 {&guest_def->ext3_features, &host_def.ext3_features,
990 ext3_feature_name, 0x80000001, R_ECX}
991 };
992
993 assert(kvm_enabled());
994
995 kvm_cpu_fill_host(&host_def);
996 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
997 for (mask = 1; mask; mask <<= 1)
998 if (*ft[i].guest_feat & mask &&
999 !(*ft[i].host_feat & mask)) {
1000 unavailable_host_feature(&ft[i], mask);
1001 rv = 1;
1002 }
1003 return rv;
1004 }
1005
1006 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1007 const char *name, Error **errp)
1008 {
1009 X86CPU *cpu = X86_CPU(obj);
1010 CPUX86State *env = &cpu->env;
1011 int64_t value;
1012
1013 value = (env->cpuid_version >> 8) & 0xf;
1014 if (value == 0xf) {
1015 value += (env->cpuid_version >> 20) & 0xff;
1016 }
1017 visit_type_int(v, &value, name, errp);
1018 }
1019
1020 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1021 const char *name, Error **errp)
1022 {
1023 X86CPU *cpu = X86_CPU(obj);
1024 CPUX86State *env = &cpu->env;
1025 const int64_t min = 0;
1026 const int64_t max = 0xff + 0xf;
1027 int64_t value;
1028
1029 visit_type_int(v, &value, name, errp);
1030 if (error_is_set(errp)) {
1031 return;
1032 }
1033 if (value < min || value > max) {
1034 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1035 name ? name : "null", value, min, max);
1036 return;
1037 }
1038
1039 env->cpuid_version &= ~0xff00f00;
1040 if (value > 0x0f) {
1041 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1042 } else {
1043 env->cpuid_version |= value << 8;
1044 }
1045 }
1046
1047 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1048 const char *name, Error **errp)
1049 {
1050 X86CPU *cpu = X86_CPU(obj);
1051 CPUX86State *env = &cpu->env;
1052 int64_t value;
1053
1054 value = (env->cpuid_version >> 4) & 0xf;
1055 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1056 visit_type_int(v, &value, name, errp);
1057 }
1058
1059 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1060 const char *name, Error **errp)
1061 {
1062 X86CPU *cpu = X86_CPU(obj);
1063 CPUX86State *env = &cpu->env;
1064 const int64_t min = 0;
1065 const int64_t max = 0xff;
1066 int64_t value;
1067
1068 visit_type_int(v, &value, name, errp);
1069 if (error_is_set(errp)) {
1070 return;
1071 }
1072 if (value < min || value > max) {
1073 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1074 name ? name : "null", value, min, max);
1075 return;
1076 }
1077
1078 env->cpuid_version &= ~0xf00f0;
1079 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1080 }
1081
1082 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1083 void *opaque, const char *name,
1084 Error **errp)
1085 {
1086 X86CPU *cpu = X86_CPU(obj);
1087 CPUX86State *env = &cpu->env;
1088 int64_t value;
1089
1090 value = env->cpuid_version & 0xf;
1091 visit_type_int(v, &value, name, errp);
1092 }
1093
1094 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1095 void *opaque, const char *name,
1096 Error **errp)
1097 {
1098 X86CPU *cpu = X86_CPU(obj);
1099 CPUX86State *env = &cpu->env;
1100 const int64_t min = 0;
1101 const int64_t max = 0xf;
1102 int64_t value;
1103
1104 visit_type_int(v, &value, name, errp);
1105 if (error_is_set(errp)) {
1106 return;
1107 }
1108 if (value < min || value > max) {
1109 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1110 name ? name : "null", value, min, max);
1111 return;
1112 }
1113
1114 env->cpuid_version &= ~0xf;
1115 env->cpuid_version |= value & 0xf;
1116 }
1117
1118 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1119 const char *name, Error **errp)
1120 {
1121 X86CPU *cpu = X86_CPU(obj);
1122
1123 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1124 }
1125
1126 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1127 const char *name, Error **errp)
1128 {
1129 X86CPU *cpu = X86_CPU(obj);
1130
1131 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1132 }
1133
1134 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1135 const char *name, Error **errp)
1136 {
1137 X86CPU *cpu = X86_CPU(obj);
1138
1139 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1140 }
1141
1142 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1143 const char *name, Error **errp)
1144 {
1145 X86CPU *cpu = X86_CPU(obj);
1146
1147 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1148 }
1149
1150 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1151 {
1152 X86CPU *cpu = X86_CPU(obj);
1153 CPUX86State *env = &cpu->env;
1154 char *value;
1155 int i;
1156
1157 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1158 for (i = 0; i < 4; i++) {
1159 value[i ] = env->cpuid_vendor1 >> (8 * i);
1160 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1161 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1162 }
1163 value[CPUID_VENDOR_SZ] = '\0';
1164 return value;
1165 }
1166
1167 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1168 Error **errp)
1169 {
1170 X86CPU *cpu = X86_CPU(obj);
1171 CPUX86State *env = &cpu->env;
1172 int i;
1173
1174 if (strlen(value) != CPUID_VENDOR_SZ) {
1175 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1176 "vendor", value);
1177 return;
1178 }
1179
1180 env->cpuid_vendor1 = 0;
1181 env->cpuid_vendor2 = 0;
1182 env->cpuid_vendor3 = 0;
1183 for (i = 0; i < 4; i++) {
1184 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1185 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1186 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1187 }
1188 env->cpuid_vendor_override = 1;
1189 }
1190
1191 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1192 {
1193 X86CPU *cpu = X86_CPU(obj);
1194 CPUX86State *env = &cpu->env;
1195 char *value;
1196 int i;
1197
1198 value = g_malloc(48 + 1);
1199 for (i = 0; i < 48; i++) {
1200 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1201 }
1202 value[48] = '\0';
1203 return value;
1204 }
1205
1206 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1207 Error **errp)
1208 {
1209 X86CPU *cpu = X86_CPU(obj);
1210 CPUX86State *env = &cpu->env;
1211 int c, len, i;
1212
1213 if (model_id == NULL) {
1214 model_id = "";
1215 }
1216 len = strlen(model_id);
1217 memset(env->cpuid_model, 0, 48);
1218 for (i = 0; i < 48; i++) {
1219 if (i >= len) {
1220 c = '\0';
1221 } else {
1222 c = (uint8_t)model_id[i];
1223 }
1224 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1225 }
1226 }
1227
1228 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1229 const char *name, Error **errp)
1230 {
1231 X86CPU *cpu = X86_CPU(obj);
1232 int64_t value;
1233
1234 value = cpu->env.tsc_khz * 1000;
1235 visit_type_int(v, &value, name, errp);
1236 }
1237
1238 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1239 const char *name, Error **errp)
1240 {
1241 X86CPU *cpu = X86_CPU(obj);
1242 const int64_t min = 0;
1243 const int64_t max = INT64_MAX;
1244 int64_t value;
1245
1246 visit_type_int(v, &value, name, errp);
1247 if (error_is_set(errp)) {
1248 return;
1249 }
1250 if (value < min || value > max) {
1251 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1252 name ? name : "null", value, min, max);
1253 return;
1254 }
1255
1256 cpu->env.tsc_khz = value / 1000;
1257 }
1258
1259 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1260 {
1261 x86_def_t *def;
1262
1263 for (def = x86_defs; def; def = def->next) {
1264 if (name && !strcmp(name, def->name)) {
1265 break;
1266 }
1267 }
1268 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1269 kvm_cpu_fill_host(x86_cpu_def);
1270 } else if (!def) {
1271 return -1;
1272 } else {
1273 memcpy(x86_cpu_def, def, sizeof(*def));
1274 }
1275
1276 return 0;
1277 }
1278
1279 /* Parse "+feature,-feature,feature=foo" CPU feature string
1280 */
1281 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1282 {
1283 unsigned int i;
1284 char *featurestr; /* Single 'key=value" string being parsed */
1285 /* Features to be added */
1286 uint32_t plus_features = 0, plus_ext_features = 0;
1287 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1288 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1289 uint32_t plus_7_0_ebx_features = 0;
1290 /* Features to be removed */
1291 uint32_t minus_features = 0, minus_ext_features = 0;
1292 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1293 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1294 uint32_t minus_7_0_ebx_features = 0;
1295 uint32_t numvalue;
1296
1297 add_flagname_to_bitmaps("hypervisor", &plus_features,
1298 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1299 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1300
1301 featurestr = features ? strtok(features, ",") : NULL;
1302
1303 while (featurestr) {
1304 char *val;
1305 if (featurestr[0] == '+') {
1306 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1307 &plus_ext_features, &plus_ext2_features,
1308 &plus_ext3_features, &plus_kvm_features,
1309 &plus_svm_features, &plus_7_0_ebx_features);
1310 } else if (featurestr[0] == '-') {
1311 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1312 &minus_ext_features, &minus_ext2_features,
1313 &minus_ext3_features, &minus_kvm_features,
1314 &minus_svm_features, &minus_7_0_ebx_features);
1315 } else if ((val = strchr(featurestr, '='))) {
1316 *val = 0; val++;
1317 if (!strcmp(featurestr, "family")) {
1318 char *err;
1319 numvalue = strtoul(val, &err, 0);
1320 if (!*val || *err || numvalue > 0xff + 0xf) {
1321 fprintf(stderr, "bad numerical value %s\n", val);
1322 goto error;
1323 }
1324 x86_cpu_def->family = numvalue;
1325 } else if (!strcmp(featurestr, "model")) {
1326 char *err;
1327 numvalue = strtoul(val, &err, 0);
1328 if (!*val || *err || numvalue > 0xff) {
1329 fprintf(stderr, "bad numerical value %s\n", val);
1330 goto error;
1331 }
1332 x86_cpu_def->model = numvalue;
1333 } else if (!strcmp(featurestr, "stepping")) {
1334 char *err;
1335 numvalue = strtoul(val, &err, 0);
1336 if (!*val || *err || numvalue > 0xf) {
1337 fprintf(stderr, "bad numerical value %s\n", val);
1338 goto error;
1339 }
1340 x86_cpu_def->stepping = numvalue ;
1341 } else if (!strcmp(featurestr, "level")) {
1342 char *err;
1343 numvalue = strtoul(val, &err, 0);
1344 if (!*val || *err) {
1345 fprintf(stderr, "bad numerical value %s\n", val);
1346 goto error;
1347 }
1348 x86_cpu_def->level = numvalue;
1349 } else if (!strcmp(featurestr, "xlevel")) {
1350 char *err;
1351 numvalue = strtoul(val, &err, 0);
1352 if (!*val || *err) {
1353 fprintf(stderr, "bad numerical value %s\n", val);
1354 goto error;
1355 }
1356 if (numvalue < 0x80000000) {
1357 numvalue += 0x80000000;
1358 }
1359 x86_cpu_def->xlevel = numvalue;
1360 } else if (!strcmp(featurestr, "vendor")) {
1361 if (strlen(val) != 12) {
1362 fprintf(stderr, "vendor string must be 12 chars long\n");
1363 goto error;
1364 }
1365 x86_cpu_def->vendor1 = 0;
1366 x86_cpu_def->vendor2 = 0;
1367 x86_cpu_def->vendor3 = 0;
1368 for(i = 0; i < 4; i++) {
1369 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1370 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1371 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1372 }
1373 x86_cpu_def->vendor_override = 1;
1374 } else if (!strcmp(featurestr, "model_id")) {
1375 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1376 val);
1377 } else if (!strcmp(featurestr, "tsc_freq")) {
1378 int64_t tsc_freq;
1379 char *err;
1380
1381 tsc_freq = strtosz_suffix_unit(val, &err,
1382 STRTOSZ_DEFSUFFIX_B, 1000);
1383 if (tsc_freq < 0 || *err) {
1384 fprintf(stderr, "bad numerical value %s\n", val);
1385 goto error;
1386 }
1387 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1388 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1389 char *err;
1390 numvalue = strtoul(val, &err, 0);
1391 if (!*val || *err) {
1392 fprintf(stderr, "bad numerical value %s\n", val);
1393 goto error;
1394 }
1395 hyperv_set_spinlock_retries(numvalue);
1396 } else {
1397 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1398 goto error;
1399 }
1400 } else if (!strcmp(featurestr, "check")) {
1401 check_cpuid = 1;
1402 } else if (!strcmp(featurestr, "enforce")) {
1403 check_cpuid = enforce_cpuid = 1;
1404 } else if (!strcmp(featurestr, "hv_relaxed")) {
1405 hyperv_enable_relaxed_timing(true);
1406 } else if (!strcmp(featurestr, "hv_vapic")) {
1407 hyperv_enable_vapic_recommended(true);
1408 } else {
1409 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1410 goto error;
1411 }
1412 featurestr = strtok(NULL, ",");
1413 }
1414 x86_cpu_def->features |= plus_features;
1415 x86_cpu_def->ext_features |= plus_ext_features;
1416 x86_cpu_def->ext2_features |= plus_ext2_features;
1417 x86_cpu_def->ext3_features |= plus_ext3_features;
1418 x86_cpu_def->kvm_features |= plus_kvm_features;
1419 x86_cpu_def->svm_features |= plus_svm_features;
1420 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1421 x86_cpu_def->features &= ~minus_features;
1422 x86_cpu_def->ext_features &= ~minus_ext_features;
1423 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1424 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1425 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1426 x86_cpu_def->svm_features &= ~minus_svm_features;
1427 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1428 if (check_cpuid && kvm_enabled()) {
1429 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1430 goto error;
1431 }
1432 return 0;
1433
1434 error:
1435 return -1;
1436 }
1437
1438 /* generate a composite string into buf of all cpuid names in featureset
1439 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1440 * if flags, suppress names undefined in featureset.
1441 */
1442 static void listflags(char *buf, int bufsize, uint32_t fbits,
1443 const char **featureset, uint32_t flags)
1444 {
1445 const char **p = &featureset[31];
1446 char *q, *b, bit;
1447 int nc;
1448
1449 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1450 *buf = '\0';
1451 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1452 if (fbits & 1 << bit && (*p || !flags)) {
1453 if (*p)
1454 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1455 else
1456 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1457 if (bufsize <= nc) {
1458 if (b) {
1459 memcpy(b, "...", sizeof("..."));
1460 }
1461 return;
1462 }
1463 q += nc;
1464 bufsize -= nc;
1465 }
1466 }
1467
1468 /* generate CPU information. */
1469 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1470 {
1471 x86_def_t *def;
1472 char buf[256];
1473
1474 for (def = x86_defs; def; def = def->next) {
1475 snprintf(buf, sizeof(buf), "%s", def->name);
1476 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1477 }
1478 if (kvm_enabled()) {
1479 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1480 }
1481 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1482 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1483 (*cpu_fprintf)(f, " %s\n", buf);
1484 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1485 (*cpu_fprintf)(f, " %s\n", buf);
1486 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1487 (*cpu_fprintf)(f, " %s\n", buf);
1488 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1489 (*cpu_fprintf)(f, " %s\n", buf);
1490 }
1491
1492 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1493 {
1494 CpuDefinitionInfoList *cpu_list = NULL;
1495 x86_def_t *def;
1496
1497 for (def = x86_defs; def; def = def->next) {
1498 CpuDefinitionInfoList *entry;
1499 CpuDefinitionInfo *info;
1500
1501 info = g_malloc0(sizeof(*info));
1502 info->name = g_strdup(def->name);
1503
1504 entry = g_malloc0(sizeof(*entry));
1505 entry->value = info;
1506 entry->next = cpu_list;
1507 cpu_list = entry;
1508 }
1509
1510 return cpu_list;
1511 }
1512
1513 #ifdef CONFIG_KVM
1514 static void filter_features_for_kvm(X86CPU *cpu)
1515 {
1516 CPUX86State *env = &cpu->env;
1517 KVMState *s = kvm_state;
1518
1519 env->cpuid_features &=
1520 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1521 env->cpuid_ext_features &=
1522 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1523 env->cpuid_ext2_features &=
1524 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1525 env->cpuid_ext3_features &=
1526 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1527 env->cpuid_svm_features &=
1528 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1529 env->cpuid_7_0_ebx_features &=
1530 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1531 env->cpuid_kvm_features &=
1532 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1533 env->cpuid_ext4_features &=
1534 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1535
1536 }
1537 #endif
1538
1539 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1540 {
1541 CPUX86State *env = &cpu->env;
1542 x86_def_t def1, *def = &def1;
1543 Error *error = NULL;
1544 char *name, *features;
1545 gchar **model_pieces;
1546
1547 memset(def, 0, sizeof(*def));
1548
1549 model_pieces = g_strsplit(cpu_model, ",", 2);
1550 if (!model_pieces[0]) {
1551 goto error;
1552 }
1553 name = model_pieces[0];
1554 features = model_pieces[1];
1555
1556 if (cpu_x86_find_by_name(def, name) < 0) {
1557 goto error;
1558 }
1559
1560 if (cpu_x86_parse_featurestr(def, features) < 0) {
1561 goto error;
1562 }
1563 assert(def->vendor1);
1564 env->cpuid_vendor1 = def->vendor1;
1565 env->cpuid_vendor2 = def->vendor2;
1566 env->cpuid_vendor3 = def->vendor3;
1567 env->cpuid_vendor_override = def->vendor_override;
1568 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1569 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1570 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1571 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1572 env->cpuid_features = def->features;
1573 env->cpuid_ext_features = def->ext_features;
1574 env->cpuid_ext2_features = def->ext2_features;
1575 env->cpuid_ext3_features = def->ext3_features;
1576 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1577 env->cpuid_kvm_features = def->kvm_features;
1578 env->cpuid_svm_features = def->svm_features;
1579 env->cpuid_ext4_features = def->ext4_features;
1580 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1581 env->cpuid_xlevel2 = def->xlevel2;
1582 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1583 "tsc-frequency", &error);
1584
1585 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1586 if (error) {
1587 fprintf(stderr, "%s\n", error_get_pretty(error));
1588 error_free(error);
1589 goto error;
1590 }
1591
1592 g_strfreev(model_pieces);
1593 return 0;
1594 error:
1595 g_strfreev(model_pieces);
1596 return -1;
1597 }
1598
1599 #if !defined(CONFIG_USER_ONLY)
1600
1601 void cpu_clear_apic_feature(CPUX86State *env)
1602 {
1603 env->cpuid_features &= ~CPUID_APIC;
1604 }
1605
1606 #endif /* !CONFIG_USER_ONLY */
1607
1608 /* Initialize list of CPU models, filling some non-static fields if necessary
1609 */
1610 void x86_cpudef_setup(void)
1611 {
1612 int i, j;
1613 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1614
1615 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1616 x86_def_t *def = &builtin_x86_defs[i];
1617 def->next = x86_defs;
1618
1619 /* Look for specific "cpudef" models that */
1620 /* have the QEMU version in .model_id */
1621 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1622 if (strcmp(model_with_versions[j], def->name) == 0) {
1623 pstrcpy(def->model_id, sizeof(def->model_id),
1624 "QEMU Virtual CPU version ");
1625 pstrcat(def->model_id, sizeof(def->model_id),
1626 qemu_get_version());
1627 break;
1628 }
1629 }
1630
1631 x86_defs = def;
1632 }
1633 }
1634
1635 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1636 uint32_t *ecx, uint32_t *edx)
1637 {
1638 *ebx = env->cpuid_vendor1;
1639 *edx = env->cpuid_vendor2;
1640 *ecx = env->cpuid_vendor3;
1641
1642 /* sysenter isn't supported on compatibility mode on AMD, syscall
1643 * isn't supported in compatibility mode on Intel.
1644 * Normally we advertise the actual cpu vendor, but you can override
1645 * this if you want to use KVM's sysenter/syscall emulation
1646 * in compatibility mode and when doing cross vendor migration
1647 */
1648 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1649 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1650 }
1651 }
1652
1653 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1654 uint32_t *eax, uint32_t *ebx,
1655 uint32_t *ecx, uint32_t *edx)
1656 {
1657 X86CPU *cpu = x86_env_get_cpu(env);
1658 CPUState *cs = CPU(cpu);
1659
1660 /* test if maximum index reached */
1661 if (index & 0x80000000) {
1662 if (index > env->cpuid_xlevel) {
1663 if (env->cpuid_xlevel2 > 0) {
1664 /* Handle the Centaur's CPUID instruction. */
1665 if (index > env->cpuid_xlevel2) {
1666 index = env->cpuid_xlevel2;
1667 } else if (index < 0xC0000000) {
1668 index = env->cpuid_xlevel;
1669 }
1670 } else {
1671 /* Intel documentation states that invalid EAX input will
1672 * return the same information as EAX=cpuid_level
1673 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1674 */
1675 index = env->cpuid_level;
1676 }
1677 }
1678 } else {
1679 if (index > env->cpuid_level)
1680 index = env->cpuid_level;
1681 }
1682
1683 switch(index) {
1684 case 0:
1685 *eax = env->cpuid_level;
1686 get_cpuid_vendor(env, ebx, ecx, edx);
1687 break;
1688 case 1:
1689 *eax = env->cpuid_version;
1690 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1691 *ecx = env->cpuid_ext_features;
1692 *edx = env->cpuid_features;
1693 if (cs->nr_cores * cs->nr_threads > 1) {
1694 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1695 *edx |= 1 << 28; /* HTT bit */
1696 }
1697 break;
1698 case 2:
1699 /* cache info: needed for Pentium Pro compatibility */
1700 *eax = 1;
1701 *ebx = 0;
1702 *ecx = 0;
1703 *edx = 0x2c307d;
1704 break;
1705 case 4:
1706 /* cache info: needed for Core compatibility */
1707 if (cs->nr_cores > 1) {
1708 *eax = (cs->nr_cores - 1) << 26;
1709 } else {
1710 *eax = 0;
1711 }
1712 switch (count) {
1713 case 0: /* L1 dcache info */
1714 *eax |= 0x0000121;
1715 *ebx = 0x1c0003f;
1716 *ecx = 0x000003f;
1717 *edx = 0x0000001;
1718 break;
1719 case 1: /* L1 icache info */
1720 *eax |= 0x0000122;
1721 *ebx = 0x1c0003f;
1722 *ecx = 0x000003f;
1723 *edx = 0x0000001;
1724 break;
1725 case 2: /* L2 cache info */
1726 *eax |= 0x0000143;
1727 if (cs->nr_threads > 1) {
1728 *eax |= (cs->nr_threads - 1) << 14;
1729 }
1730 *ebx = 0x3c0003f;
1731 *ecx = 0x0000fff;
1732 *edx = 0x0000001;
1733 break;
1734 default: /* end of info */
1735 *eax = 0;
1736 *ebx = 0;
1737 *ecx = 0;
1738 *edx = 0;
1739 break;
1740 }
1741 break;
1742 case 5:
1743 /* mwait info: needed for Core compatibility */
1744 *eax = 0; /* Smallest monitor-line size in bytes */
1745 *ebx = 0; /* Largest monitor-line size in bytes */
1746 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1747 *edx = 0;
1748 break;
1749 case 6:
1750 /* Thermal and Power Leaf */
1751 *eax = 0;
1752 *ebx = 0;
1753 *ecx = 0;
1754 *edx = 0;
1755 break;
1756 case 7:
1757 /* Structured Extended Feature Flags Enumeration Leaf */
1758 if (count == 0) {
1759 *eax = 0; /* Maximum ECX value for sub-leaves */
1760 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1761 *ecx = 0; /* Reserved */
1762 *edx = 0; /* Reserved */
1763 } else {
1764 *eax = 0;
1765 *ebx = 0;
1766 *ecx = 0;
1767 *edx = 0;
1768 }
1769 break;
1770 case 9:
1771 /* Direct Cache Access Information Leaf */
1772 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1773 *ebx = 0;
1774 *ecx = 0;
1775 *edx = 0;
1776 break;
1777 case 0xA:
1778 /* Architectural Performance Monitoring Leaf */
1779 if (kvm_enabled()) {
1780 KVMState *s = cs->kvm_state;
1781
1782 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1783 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1784 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1785 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1786 } else {
1787 *eax = 0;
1788 *ebx = 0;
1789 *ecx = 0;
1790 *edx = 0;
1791 }
1792 break;
1793 case 0xD:
1794 /* Processor Extended State */
1795 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1796 *eax = 0;
1797 *ebx = 0;
1798 *ecx = 0;
1799 *edx = 0;
1800 break;
1801 }
1802 if (kvm_enabled()) {
1803 KVMState *s = cs->kvm_state;
1804
1805 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1806 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1807 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1808 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1809 } else {
1810 *eax = 0;
1811 *ebx = 0;
1812 *ecx = 0;
1813 *edx = 0;
1814 }
1815 break;
1816 case 0x80000000:
1817 *eax = env->cpuid_xlevel;
1818 *ebx = env->cpuid_vendor1;
1819 *edx = env->cpuid_vendor2;
1820 *ecx = env->cpuid_vendor3;
1821 break;
1822 case 0x80000001:
1823 *eax = env->cpuid_version;
1824 *ebx = 0;
1825 *ecx = env->cpuid_ext3_features;
1826 *edx = env->cpuid_ext2_features;
1827
1828 /* The Linux kernel checks for the CMPLegacy bit and
1829 * discards multiple thread information if it is set.
1830 * So dont set it here for Intel to make Linux guests happy.
1831 */
1832 if (cs->nr_cores * cs->nr_threads > 1) {
1833 uint32_t tebx, tecx, tedx;
1834 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1835 if (tebx != CPUID_VENDOR_INTEL_1 ||
1836 tedx != CPUID_VENDOR_INTEL_2 ||
1837 tecx != CPUID_VENDOR_INTEL_3) {
1838 *ecx |= 1 << 1; /* CmpLegacy bit */
1839 }
1840 }
1841 break;
1842 case 0x80000002:
1843 case 0x80000003:
1844 case 0x80000004:
1845 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1846 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1847 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1848 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1849 break;
1850 case 0x80000005:
1851 /* cache info (L1 cache) */
1852 *eax = 0x01ff01ff;
1853 *ebx = 0x01ff01ff;
1854 *ecx = 0x40020140;
1855 *edx = 0x40020140;
1856 break;
1857 case 0x80000006:
1858 /* cache info (L2 cache) */
1859 *eax = 0;
1860 *ebx = 0x42004200;
1861 *ecx = 0x02008140;
1862 *edx = 0;
1863 break;
1864 case 0x80000008:
1865 /* virtual & phys address size in low 2 bytes. */
1866 /* XXX: This value must match the one used in the MMU code. */
1867 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1868 /* 64 bit processor */
1869 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1870 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1871 } else {
1872 if (env->cpuid_features & CPUID_PSE36)
1873 *eax = 0x00000024; /* 36 bits physical */
1874 else
1875 *eax = 0x00000020; /* 32 bits physical */
1876 }
1877 *ebx = 0;
1878 *ecx = 0;
1879 *edx = 0;
1880 if (cs->nr_cores * cs->nr_threads > 1) {
1881 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1882 }
1883 break;
1884 case 0x8000000A:
1885 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1886 *eax = 0x00000001; /* SVM Revision */
1887 *ebx = 0x00000010; /* nr of ASIDs */
1888 *ecx = 0;
1889 *edx = env->cpuid_svm_features; /* optional features */
1890 } else {
1891 *eax = 0;
1892 *ebx = 0;
1893 *ecx = 0;
1894 *edx = 0;
1895 }
1896 break;
1897 case 0xC0000000:
1898 *eax = env->cpuid_xlevel2;
1899 *ebx = 0;
1900 *ecx = 0;
1901 *edx = 0;
1902 break;
1903 case 0xC0000001:
1904 /* Support for VIA CPU's CPUID instruction */
1905 *eax = env->cpuid_version;
1906 *ebx = 0;
1907 *ecx = 0;
1908 *edx = env->cpuid_ext4_features;
1909 break;
1910 case 0xC0000002:
1911 case 0xC0000003:
1912 case 0xC0000004:
1913 /* Reserved for the future, and now filled with zero */
1914 *eax = 0;
1915 *ebx = 0;
1916 *ecx = 0;
1917 *edx = 0;
1918 break;
1919 default:
1920 /* reserved values: zero */
1921 *eax = 0;
1922 *ebx = 0;
1923 *ecx = 0;
1924 *edx = 0;
1925 break;
1926 }
1927 }
1928
1929 /* CPUClass::reset() */
1930 static void x86_cpu_reset(CPUState *s)
1931 {
1932 X86CPU *cpu = X86_CPU(s);
1933 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1934 CPUX86State *env = &cpu->env;
1935 int i;
1936
1937 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1938 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1939 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1940 }
1941
1942 xcc->parent_reset(s);
1943
1944
1945 memset(env, 0, offsetof(CPUX86State, breakpoints));
1946
1947 tlb_flush(env, 1);
1948
1949 env->old_exception = -1;
1950
1951 /* init to reset state */
1952
1953 #ifdef CONFIG_SOFTMMU
1954 env->hflags |= HF_SOFTMMU_MASK;
1955 #endif
1956 env->hflags2 |= HF2_GIF_MASK;
1957
1958 cpu_x86_update_cr0(env, 0x60000010);
1959 env->a20_mask = ~0x0;
1960 env->smbase = 0x30000;
1961
1962 env->idt.limit = 0xffff;
1963 env->gdt.limit = 0xffff;
1964 env->ldt.limit = 0xffff;
1965 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1966 env->tr.limit = 0xffff;
1967 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1968
1969 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1970 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1971 DESC_R_MASK | DESC_A_MASK);
1972 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1973 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1974 DESC_A_MASK);
1975 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1976 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1977 DESC_A_MASK);
1978 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1979 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1980 DESC_A_MASK);
1981 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1982 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1983 DESC_A_MASK);
1984 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1985 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1986 DESC_A_MASK);
1987
1988 env->eip = 0xfff0;
1989 env->regs[R_EDX] = env->cpuid_version;
1990
1991 env->eflags = 0x2;
1992
1993 /* FPU init */
1994 for (i = 0; i < 8; i++) {
1995 env->fptags[i] = 1;
1996 }
1997 env->fpuc = 0x37f;
1998
1999 env->mxcsr = 0x1f80;
2000
2001 env->pat = 0x0007040600070406ULL;
2002 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2003
2004 memset(env->dr, 0, sizeof(env->dr));
2005 env->dr[6] = DR6_FIXED_1;
2006 env->dr[7] = DR7_FIXED_1;
2007 cpu_breakpoint_remove_all(env, BP_CPU);
2008 cpu_watchpoint_remove_all(env, BP_CPU);
2009
2010 #if !defined(CONFIG_USER_ONLY)
2011 /* We hard-wire the BSP to the first CPU. */
2012 if (s->cpu_index == 0) {
2013 apic_designate_bsp(env->apic_state);
2014 }
2015
2016 env->halted = !cpu_is_bsp(cpu);
2017 #endif
2018 }
2019
2020 #ifndef CONFIG_USER_ONLY
2021 bool cpu_is_bsp(X86CPU *cpu)
2022 {
2023 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2024 }
2025
2026 /* TODO: remove me, when reset over QOM tree is implemented */
2027 static void x86_cpu_machine_reset_cb(void *opaque)
2028 {
2029 X86CPU *cpu = opaque;
2030 cpu_reset(CPU(cpu));
2031 }
2032 #endif
2033
2034 static void mce_init(X86CPU *cpu)
2035 {
2036 CPUX86State *cenv = &cpu->env;
2037 unsigned int bank;
2038
2039 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2040 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2041 (CPUID_MCE | CPUID_MCA)) {
2042 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2043 cenv->mcg_ctl = ~(uint64_t)0;
2044 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2045 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2046 }
2047 }
2048 }
2049
2050 #define MSI_ADDR_BASE 0xfee00000
2051
2052 #ifndef CONFIG_USER_ONLY
2053 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2054 {
2055 static int apic_mapped;
2056 CPUX86State *env = &cpu->env;
2057 APICCommonState *apic;
2058 const char *apic_type = "apic";
2059
2060 if (kvm_irqchip_in_kernel()) {
2061 apic_type = "kvm-apic";
2062 } else if (xen_enabled()) {
2063 apic_type = "xen-apic";
2064 }
2065
2066 env->apic_state = qdev_try_create(NULL, apic_type);
2067 if (env->apic_state == NULL) {
2068 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2069 return;
2070 }
2071
2072 object_property_add_child(OBJECT(cpu), "apic",
2073 OBJECT(env->apic_state), NULL);
2074 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2075 /* TODO: convert to link<> */
2076 apic = APIC_COMMON(env->apic_state);
2077 apic->cpu = cpu;
2078
2079 if (qdev_init(env->apic_state)) {
2080 error_setg(errp, "APIC device '%s' could not be initialized",
2081 object_get_typename(OBJECT(env->apic_state)));
2082 return;
2083 }
2084
2085 /* XXX: mapping more APICs at the same memory location */
2086 if (apic_mapped == 0) {
2087 /* NOTE: the APIC is directly connected to the CPU - it is not
2088 on the global memory bus. */
2089 /* XXX: what if the base changes? */
2090 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2091 apic_mapped = 1;
2092 }
2093 }
2094 #endif
2095
2096 void x86_cpu_realize(Object *obj, Error **errp)
2097 {
2098 X86CPU *cpu = X86_CPU(obj);
2099 CPUX86State *env = &cpu->env;
2100
2101 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2102 env->cpuid_level = 7;
2103 }
2104
2105 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2106 * CPUID[1].EDX.
2107 */
2108 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2109 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2110 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2111 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2112 env->cpuid_ext2_features |= (env->cpuid_features
2113 & CPUID_EXT2_AMD_ALIASES);
2114 }
2115
2116 if (!kvm_enabled()) {
2117 env->cpuid_features &= TCG_FEATURES;
2118 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2119 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2120 #ifdef TARGET_X86_64
2121 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2122 #endif
2123 );
2124 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2125 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2126 } else {
2127 #ifdef CONFIG_KVM
2128 filter_features_for_kvm(cpu);
2129 #endif
2130 }
2131
2132 #ifndef CONFIG_USER_ONLY
2133 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2134
2135 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2136 x86_cpu_apic_init(cpu, errp);
2137 if (error_is_set(errp)) {
2138 return;
2139 }
2140 }
2141 #endif
2142
2143 mce_init(cpu);
2144 qemu_init_vcpu(&cpu->env);
2145 cpu_reset(CPU(cpu));
2146 }
2147
2148 static void x86_cpu_initfn(Object *obj)
2149 {
2150 CPUState *cs = CPU(obj);
2151 X86CPU *cpu = X86_CPU(obj);
2152 CPUX86State *env = &cpu->env;
2153 static int inited;
2154
2155 cpu_exec_init(env);
2156
2157 object_property_add(obj, "family", "int",
2158 x86_cpuid_version_get_family,
2159 x86_cpuid_version_set_family, NULL, NULL, NULL);
2160 object_property_add(obj, "model", "int",
2161 x86_cpuid_version_get_model,
2162 x86_cpuid_version_set_model, NULL, NULL, NULL);
2163 object_property_add(obj, "stepping", "int",
2164 x86_cpuid_version_get_stepping,
2165 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2166 object_property_add(obj, "level", "int",
2167 x86_cpuid_get_level,
2168 x86_cpuid_set_level, NULL, NULL, NULL);
2169 object_property_add(obj, "xlevel", "int",
2170 x86_cpuid_get_xlevel,
2171 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2172 object_property_add_str(obj, "vendor",
2173 x86_cpuid_get_vendor,
2174 x86_cpuid_set_vendor, NULL);
2175 object_property_add_str(obj, "model-id",
2176 x86_cpuid_get_model_id,
2177 x86_cpuid_set_model_id, NULL);
2178 object_property_add(obj, "tsc-frequency", "int",
2179 x86_cpuid_get_tsc_freq,
2180 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2181
2182 env->cpuid_apic_id = cs->cpu_index;
2183
2184 /* init various static tables used in TCG mode */
2185 if (tcg_enabled() && !inited) {
2186 inited = 1;
2187 optimize_flags_init();
2188 #ifndef CONFIG_USER_ONLY
2189 cpu_set_debug_excp_handler(breakpoint_handler);
2190 #endif
2191 }
2192 }
2193
2194 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2195 {
2196 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2197 CPUClass *cc = CPU_CLASS(oc);
2198
2199 xcc->parent_reset = cc->reset;
2200 cc->reset = x86_cpu_reset;
2201 }
2202
2203 static const TypeInfo x86_cpu_type_info = {
2204 .name = TYPE_X86_CPU,
2205 .parent = TYPE_CPU,
2206 .instance_size = sizeof(X86CPU),
2207 .instance_init = x86_cpu_initfn,
2208 .abstract = false,
2209 .class_size = sizeof(X86CPUClass),
2210 .class_init = x86_cpu_common_class_init,
2211 };
2212
2213 static void x86_cpu_register_types(void)
2214 {
2215 type_register_static(&x86_cpu_type_info);
2216 }
2217
2218 type_init(x86_cpu_register_types)
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