2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
52 /* Cache topology CPUID constants: */
54 /* CPUID Leaf 2 Descriptors */
56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
58 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
61 /* CPUID Leaf 4 constants: */
64 #define CPUID_4_TYPE_DCACHE 1
65 #define CPUID_4_TYPE_ICACHE 2
66 #define CPUID_4_TYPE_UNIFIED 3
68 #define CPUID_4_LEVEL(l) ((l) << 5)
70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71 #define CPUID_4_FULLY_ASSOC (1 << 9)
74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
75 #define CPUID_4_INCLUSIVE (1 << 1)
76 #define CPUID_4_COMPLEX_IDX (1 << 2)
78 #define ASSOC_FULL 0xFF
80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
95 /* Definitions of the hardcoded cache entries we expose: */
98 #define L1D_LINE_SIZE 64
99 #define L1D_ASSOCIATIVITY 8
101 #define L1D_PARTITIONS 1
102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105 #define L1D_LINES_PER_TAG 1
106 #define L1D_SIZE_KB_AMD 64
107 #define L1D_ASSOCIATIVITY_AMD 2
109 /* L1 instruction cache: */
110 #define L1I_LINE_SIZE 64
111 #define L1I_ASSOCIATIVITY 8
113 #define L1I_PARTITIONS 1
114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117 #define L1I_LINES_PER_TAG 1
118 #define L1I_SIZE_KB_AMD 64
119 #define L1I_ASSOCIATIVITY_AMD 2
121 /* Level 2 unified cache: */
122 #define L2_LINE_SIZE 64
123 #define L2_ASSOCIATIVITY 16
125 #define L2_PARTITIONS 1
126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130 #define L2_LINES_PER_TAG 1
131 #define L2_SIZE_KB_AMD 512
134 #define L3_SIZE_KB 0 /* disabled */
135 #define L3_ASSOCIATIVITY 0 /* disabled */
136 #define L3_LINES_PER_TAG 0 /* disabled */
137 #define L3_LINE_SIZE 0 /* disabled */
139 /* TLB definitions: */
141 #define L1_DTLB_2M_ASSOC 1
142 #define L1_DTLB_2M_ENTRIES 255
143 #define L1_DTLB_4K_ASSOC 1
144 #define L1_DTLB_4K_ENTRIES 255
146 #define L1_ITLB_2M_ASSOC 1
147 #define L1_ITLB_2M_ENTRIES 255
148 #define L1_ITLB_4K_ASSOC 1
149 #define L1_ITLB_4K_ENTRIES 255
151 #define L2_DTLB_2M_ASSOC 0 /* disabled */
152 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
153 #define L2_DTLB_4K_ASSOC 4
154 #define L2_DTLB_4K_ENTRIES 512
156 #define L2_ITLB_2M_ASSOC 0 /* disabled */
157 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
158 #define L2_ITLB_4K_ASSOC 4
159 #define L2_ITLB_4K_ENTRIES 512
163 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
164 uint32_t vendor2
, uint32_t vendor3
)
167 for (i
= 0; i
< 4; i
++) {
168 dst
[i
] = vendor1
>> (8 * i
);
169 dst
[i
+ 4] = vendor2
>> (8 * i
);
170 dst
[i
+ 8] = vendor3
>> (8 * i
);
172 dst
[CPUID_VENDOR_SZ
] = '\0';
175 /* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
179 static const char *feature_name
[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL
, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189 static const char *ext_feature_name
[] = {
190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
191 "ds_cpl", "vmx", "smx", "est",
192 "tm2", "ssse3", "cid", NULL
,
193 "fma", "cx16", "xtpr", "pdcm",
194 NULL
, "pcid", "dca", "sse4.1|sse4_1",
195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
196 "tsc-deadline", "aes", "xsave", "osxsave",
197 "avx", "f16c", "rdrand", "hypervisor",
199 /* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
204 static const char *ext2_feature_name
[] = {
205 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
206 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
207 NULL
/* cx8 */ /* AMD CMPXCHG8B */, NULL
/* apic */, NULL
, "syscall",
208 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
209 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
210 "nx|xd", NULL
, "mmxext", NULL
/* mmx */,
211 NULL
/* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
212 NULL
, "lm|i64", "3dnowext", "3dnow",
214 static const char *ext3_feature_name
[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
217 "3dnowprefetch", "osvw", "ibs", "xop",
218 "skinit", "wdt", NULL
, "lwp",
219 "fma4", "tce", NULL
, "nodeid_msr",
220 NULL
, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL
, NULL
, NULL
,
222 NULL
, NULL
, NULL
, NULL
,
225 static const char *ext4_feature_name
[] = {
226 NULL
, NULL
, "xstore", "xstore-en",
227 NULL
, NULL
, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL
, NULL
,
230 NULL
, NULL
, NULL
, NULL
,
231 NULL
, NULL
, NULL
, NULL
,
232 NULL
, NULL
, NULL
, NULL
,
233 NULL
, NULL
, NULL
, NULL
,
236 static const char *kvm_feature_name
[] = {
237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
239 NULL
, NULL
, NULL
, NULL
,
240 NULL
, NULL
, NULL
, NULL
,
241 NULL
, NULL
, NULL
, NULL
,
242 NULL
, NULL
, NULL
, NULL
,
243 NULL
, NULL
, NULL
, NULL
,
244 NULL
, NULL
, NULL
, NULL
,
247 static const char *svm_feature_name
[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL
, NULL
, "pause_filter", NULL
,
251 "pfthreshold", NULL
, NULL
, NULL
,
252 NULL
, NULL
, NULL
, NULL
,
253 NULL
, NULL
, NULL
, NULL
,
254 NULL
, NULL
, NULL
, NULL
,
255 NULL
, NULL
, NULL
, NULL
,
258 static const char *cpuid_7_0_ebx_feature_name
[] = {
259 "fsgsbase", NULL
, NULL
, "bmi1", "hle", "avx2", NULL
, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL
, NULL
, NULL
, NULL
,
261 NULL
, NULL
, "rdseed", "adx", "smap", NULL
, NULL
, NULL
,
262 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
265 typedef struct FeatureWordInfo
{
266 const char **feat_names
;
267 uint32_t cpuid_eax
; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
270 int cpuid_reg
; /* output register (R_* constant) */
273 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
275 .feat_names
= feature_name
,
276 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
279 .feat_names
= ext_feature_name
,
280 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
282 [FEAT_8000_0001_EDX
] = {
283 .feat_names
= ext2_feature_name
,
284 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
286 [FEAT_8000_0001_ECX
] = {
287 .feat_names
= ext3_feature_name
,
288 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
290 [FEAT_C000_0001_EDX
] = {
291 .feat_names
= ext4_feature_name
,
292 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
295 .feat_names
= kvm_feature_name
,
296 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
299 .feat_names
= svm_feature_name
,
300 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
303 .feat_names
= cpuid_7_0_ebx_feature_name
,
305 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
310 typedef struct X86RegisterInfo32
{
311 /* Name of register */
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum
;
317 #define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
319 X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
331 typedef struct ExtSaveArea
{
332 uint32_t feature
, bits
;
333 uint32_t offset
, size
;
336 static const ExtSaveArea ext_save_areas
[] = {
337 [2] = { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
338 .offset
= 0x240, .size
= 0x100 },
339 [3] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
340 .offset
= 0x3c0, .size
= 0x40 },
341 [4] = { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
342 .offset
= 0x400, .size
= 0x40 },
345 const char *get_register_name_32(unsigned int reg
)
347 if (reg
>= CPU_NB_REGS32
) {
350 return x86_reg_info_32
[reg
].name
;
353 /* collects per-function cpuid data
355 typedef struct model_features_t
{
356 uint32_t *guest_feat
;
358 FeatureWord feat_word
;
361 /* KVM-specific features that are automatically added to all CPU models
362 * when KVM is enabled.
364 static uint32_t kvm_default_features
[FEATURE_WORDS
] = {
365 [FEAT_KVM
] = (1 << KVM_FEATURE_CLOCKSOURCE
) |
366 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
367 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
368 (1 << KVM_FEATURE_ASYNC_PF
) |
369 (1 << KVM_FEATURE_STEAL_TIME
) |
370 (1 << KVM_FEATURE_PV_EOI
) |
371 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
),
374 void x86_cpu_compat_disable_kvm_features(FeatureWord w
, uint32_t features
)
376 kvm_default_features
[w
] &= ~features
;
379 void host_cpuid(uint32_t function
, uint32_t count
,
380 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
386 : "=a"(vec
[0]), "=b"(vec
[1]),
387 "=c"(vec
[2]), "=d"(vec
[3])
388 : "0"(function
), "c"(count
) : "cc");
389 #elif defined(__i386__)
390 asm volatile("pusha \n\t"
392 "mov %%eax, 0(%2) \n\t"
393 "mov %%ebx, 4(%2) \n\t"
394 "mov %%ecx, 8(%2) \n\t"
395 "mov %%edx, 12(%2) \n\t"
397 : : "a"(function
), "c"(count
), "S"(vec
)
413 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
415 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
416 * a substring. ex if !NULL points to the first char after a substring,
417 * otherwise the string is assumed to sized by a terminating nul.
418 * Return lexical ordering of *s1:*s2.
420 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
424 if (!*s1
|| !*s2
|| *s1
!= *s2
)
427 if (s1
== e1
&& s2
== e2
)
436 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
437 * '|' delimited (possibly empty) strings in which case search for a match
438 * within the alternatives proceeds left to right. Return 0 for success,
439 * non-zero otherwise.
441 static int altcmp(const char *s
, const char *e
, const char *altstr
)
445 for (q
= p
= altstr
; ; ) {
446 while (*p
&& *p
!= '|')
448 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
457 /* search featureset for flag *[s..e), if found set corresponding bit in
458 * *pval and return true, otherwise return false
460 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
461 const char **featureset
)
467 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
468 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
476 static void add_flagname_to_bitmaps(const char *flagname
,
477 FeatureWordArray words
)
480 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
481 FeatureWordInfo
*wi
= &feature_word_info
[w
];
482 if (wi
->feat_names
&&
483 lookup_feature(&words
[w
], flagname
, NULL
, wi
->feat_names
)) {
487 if (w
== FEATURE_WORDS
) {
488 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
492 typedef struct X86CPUDefinition
{
497 /* vendor is zero-terminated, 12 character ASCII string */
498 char vendor
[CPUID_VENDOR_SZ
+ 1];
502 FeatureWordArray features
;
504 bool cache_info_passthrough
;
507 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
508 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
509 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
510 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
511 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
512 CPUID_PSE36 | CPUID_FXSR)
513 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
514 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
515 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
516 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
517 CPUID_PAE | CPUID_SEP | CPUID_APIC)
519 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
520 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
521 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
522 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
523 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
524 /* partly implemented:
525 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
526 CPUID_PSE36 (needed for Solaris) */
528 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
529 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
530 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
531 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
532 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
534 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
535 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
536 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
537 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
538 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
540 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
541 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
542 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
544 CPUID_EXT2_PDPE1GB */
545 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
546 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
547 #define TCG_SVM_FEATURES 0
548 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
549 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
551 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
552 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
553 CPUID_7_0_EBX_RDSEED */
555 /* built-in CPU model definitions
557 static X86CPUDefinition builtin_x86_defs
[] = {
561 .vendor
= CPUID_VENDOR_AMD
,
565 .features
[FEAT_1_EDX
] =
567 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
569 .features
[FEAT_1_ECX
] =
570 CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
571 .features
[FEAT_8000_0001_EDX
] =
572 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
573 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
574 .features
[FEAT_8000_0001_ECX
] =
575 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
576 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
577 .xlevel
= 0x8000000A,
582 .vendor
= CPUID_VENDOR_AMD
,
586 .features
[FEAT_1_EDX
] =
588 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
589 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
590 .features
[FEAT_1_ECX
] =
591 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
593 .features
[FEAT_8000_0001_EDX
] =
594 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
595 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
596 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
597 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
598 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
600 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
601 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
602 .features
[FEAT_8000_0001_ECX
] =
603 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
604 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
605 .features
[FEAT_SVM
] =
606 CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
607 .xlevel
= 0x8000001A,
608 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
613 .vendor
= CPUID_VENDOR_INTEL
,
617 .features
[FEAT_1_EDX
] =
619 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
620 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
621 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
622 .features
[FEAT_1_ECX
] =
623 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
624 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
625 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
626 .features
[FEAT_8000_0001_EDX
] =
627 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
628 .features
[FEAT_8000_0001_ECX
] =
630 .xlevel
= 0x80000008,
631 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
636 .vendor
= CPUID_VENDOR_INTEL
,
640 /* Missing: CPUID_VME, CPUID_HT */
641 .features
[FEAT_1_EDX
] =
643 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
645 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
646 .features
[FEAT_1_ECX
] =
647 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
648 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
649 .features
[FEAT_8000_0001_EDX
] =
650 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
651 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
652 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
653 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
654 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
655 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
656 .features
[FEAT_8000_0001_ECX
] =
658 .xlevel
= 0x80000008,
659 .model_id
= "Common KVM processor"
664 .vendor
= CPUID_VENDOR_INTEL
,
668 .features
[FEAT_1_EDX
] =
670 .features
[FEAT_1_ECX
] =
671 CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
672 .xlevel
= 0x80000004,
677 .vendor
= CPUID_VENDOR_INTEL
,
681 .features
[FEAT_1_EDX
] =
683 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
684 .features
[FEAT_1_ECX
] =
686 .features
[FEAT_8000_0001_EDX
] =
687 PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
,
688 .features
[FEAT_8000_0001_ECX
] =
690 .xlevel
= 0x80000008,
691 .model_id
= "Common 32-bit KVM processor"
696 .vendor
= CPUID_VENDOR_INTEL
,
700 .features
[FEAT_1_EDX
] =
701 PPRO_FEATURES
| CPUID_VME
|
702 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
703 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
704 .features
[FEAT_1_ECX
] =
705 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
706 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
707 .features
[FEAT_8000_0001_EDX
] =
709 .xlevel
= 0x80000008,
710 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
715 .vendor
= CPUID_VENDOR_INTEL
,
719 .features
[FEAT_1_EDX
] =
726 .vendor
= CPUID_VENDOR_INTEL
,
730 .features
[FEAT_1_EDX
] =
737 .vendor
= CPUID_VENDOR_INTEL
,
741 .features
[FEAT_1_EDX
] =
748 .vendor
= CPUID_VENDOR_INTEL
,
752 .features
[FEAT_1_EDX
] =
759 .vendor
= CPUID_VENDOR_AMD
,
763 .features
[FEAT_1_EDX
] =
764 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
766 .features
[FEAT_8000_0001_EDX
] =
767 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
768 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
769 .xlevel
= 0x80000008,
773 /* original is on level 10 */
775 .vendor
= CPUID_VENDOR_INTEL
,
779 .features
[FEAT_1_EDX
] =
781 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
782 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
783 /* Some CPUs got no CPUID_SEP */
784 .features
[FEAT_1_ECX
] =
785 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
786 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
|
788 .features
[FEAT_8000_0001_EDX
] =
789 (PPRO_FEATURES
& CPUID_EXT2_AMD_ALIASES
) |
791 .features
[FEAT_8000_0001_ECX
] =
793 .xlevel
= 0x8000000A,
794 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
799 .vendor
= CPUID_VENDOR_INTEL
,
803 .features
[FEAT_1_EDX
] =
804 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
805 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
806 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
807 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
808 CPUID_DE
| CPUID_FP87
,
809 .features
[FEAT_1_ECX
] =
810 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
811 .features
[FEAT_8000_0001_EDX
] =
812 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
813 .features
[FEAT_8000_0001_ECX
] =
815 .xlevel
= 0x8000000A,
816 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
821 .vendor
= CPUID_VENDOR_INTEL
,
825 .features
[FEAT_1_EDX
] =
826 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
827 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
828 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
829 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
830 CPUID_DE
| CPUID_FP87
,
831 .features
[FEAT_1_ECX
] =
832 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
834 .features
[FEAT_8000_0001_EDX
] =
835 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
836 .features
[FEAT_8000_0001_ECX
] =
838 .xlevel
= 0x8000000A,
839 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
844 .vendor
= CPUID_VENDOR_INTEL
,
848 .features
[FEAT_1_EDX
] =
849 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
850 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
851 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
852 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
853 CPUID_DE
| CPUID_FP87
,
854 .features
[FEAT_1_ECX
] =
855 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
856 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
857 .features
[FEAT_8000_0001_EDX
] =
858 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
859 .features
[FEAT_8000_0001_ECX
] =
861 .xlevel
= 0x8000000A,
862 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
867 .vendor
= CPUID_VENDOR_INTEL
,
871 .features
[FEAT_1_EDX
] =
872 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
873 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
874 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
875 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
876 CPUID_DE
| CPUID_FP87
,
877 .features
[FEAT_1_ECX
] =
878 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
879 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
880 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
881 .features
[FEAT_8000_0001_EDX
] =
882 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
883 .features
[FEAT_8000_0001_ECX
] =
885 .xlevel
= 0x8000000A,
886 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
889 .name
= "SandyBridge",
891 .vendor
= CPUID_VENDOR_INTEL
,
895 .features
[FEAT_1_EDX
] =
896 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
897 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
898 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
899 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
900 CPUID_DE
| CPUID_FP87
,
901 .features
[FEAT_1_ECX
] =
902 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
903 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
904 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
905 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
907 .features
[FEAT_8000_0001_EDX
] =
908 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
910 .features
[FEAT_8000_0001_ECX
] =
912 .xlevel
= 0x8000000A,
913 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
918 .vendor
= CPUID_VENDOR_INTEL
,
922 .features
[FEAT_1_EDX
] =
923 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
924 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
925 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
926 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
927 CPUID_DE
| CPUID_FP87
,
928 .features
[FEAT_1_ECX
] =
929 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
930 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
931 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
932 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
933 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
935 .features
[FEAT_8000_0001_EDX
] =
936 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
938 .features
[FEAT_8000_0001_ECX
] =
940 .features
[FEAT_7_0_EBX
] =
941 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
942 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
943 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
945 .xlevel
= 0x8000000A,
946 .model_id
= "Intel Core Processor (Haswell)",
949 .name
= "Opteron_G1",
951 .vendor
= CPUID_VENDOR_AMD
,
955 .features
[FEAT_1_EDX
] =
956 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
957 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
958 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
959 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
960 CPUID_DE
| CPUID_FP87
,
961 .features
[FEAT_1_ECX
] =
963 .features
[FEAT_8000_0001_EDX
] =
964 CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
965 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
966 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
967 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
968 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
969 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
970 .xlevel
= 0x80000008,
971 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
974 .name
= "Opteron_G2",
976 .vendor
= CPUID_VENDOR_AMD
,
980 .features
[FEAT_1_EDX
] =
981 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
982 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
983 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
984 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
985 CPUID_DE
| CPUID_FP87
,
986 .features
[FEAT_1_ECX
] =
987 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
988 .features
[FEAT_8000_0001_EDX
] =
989 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
990 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
991 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
992 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
993 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
994 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
995 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
996 .features
[FEAT_8000_0001_ECX
] =
997 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
998 .xlevel
= 0x80000008,
999 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1002 .name
= "Opteron_G3",
1004 .vendor
= CPUID_VENDOR_AMD
,
1008 .features
[FEAT_1_EDX
] =
1009 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1010 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1011 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1012 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1013 CPUID_DE
| CPUID_FP87
,
1014 .features
[FEAT_1_ECX
] =
1015 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1017 .features
[FEAT_8000_0001_EDX
] =
1018 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
1019 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
1020 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
1021 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
1022 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
1023 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
1024 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1025 .features
[FEAT_8000_0001_ECX
] =
1026 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1027 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1028 .xlevel
= 0x80000008,
1029 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1032 .name
= "Opteron_G4",
1034 .vendor
= CPUID_VENDOR_AMD
,
1038 .features
[FEAT_1_EDX
] =
1039 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1040 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1041 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1042 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1043 CPUID_DE
| CPUID_FP87
,
1044 .features
[FEAT_1_ECX
] =
1045 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1046 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1047 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1049 .features
[FEAT_8000_0001_EDX
] =
1050 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
1051 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1052 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1053 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1054 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1055 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1056 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1057 .features
[FEAT_8000_0001_ECX
] =
1058 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1059 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1060 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1062 .xlevel
= 0x8000001A,
1063 .model_id
= "AMD Opteron 62xx class CPU",
1066 .name
= "Opteron_G5",
1068 .vendor
= CPUID_VENDOR_AMD
,
1072 .features
[FEAT_1_EDX
] =
1073 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1074 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1075 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1076 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1077 CPUID_DE
| CPUID_FP87
,
1078 .features
[FEAT_1_ECX
] =
1079 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1080 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1081 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1082 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1083 .features
[FEAT_8000_0001_EDX
] =
1084 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
1085 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
1086 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
1087 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
1088 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
1089 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
1090 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
1091 .features
[FEAT_8000_0001_ECX
] =
1092 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1093 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1094 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1096 .xlevel
= 0x8000001A,
1097 .model_id
= "AMD Opteron 63xx class CPU",
1102 * x86_cpu_compat_set_features:
1103 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1104 * @w: Identifies the feature word to be changed.
1105 * @feat_add: Feature bits to be added to feature word
1106 * @feat_remove: Feature bits to be removed from feature word
1108 * Change CPU model feature bits for compatibility.
1110 * This function may be used by machine-type compatibility functions
1111 * to enable or disable feature bits on specific CPU models.
1113 void x86_cpu_compat_set_features(const char *cpu_model
, FeatureWord w
,
1114 uint32_t feat_add
, uint32_t feat_remove
)
1116 X86CPUDefinition
*def
;
1118 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1119 def
= &builtin_x86_defs
[i
];
1120 if (!cpu_model
|| !strcmp(cpu_model
, def
->name
)) {
1121 def
->features
[w
] |= feat_add
;
1122 def
->features
[w
] &= ~feat_remove
;
1127 static int cpu_x86_fill_model_id(char *str
)
1129 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1132 for (i
= 0; i
< 3; i
++) {
1133 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
1134 memcpy(str
+ i
* 16 + 0, &eax
, 4);
1135 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
1136 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
1137 memcpy(str
+ i
* 16 + 12, &edx
, 4);
1142 /* Fill a X86CPUDefinition struct with information about the host CPU, and
1143 * the CPU features supported by the host hardware + host kernel
1145 * This function may be called only if KVM is enabled.
1147 static void kvm_cpu_fill_host(X86CPUDefinition
*x86_cpu_def
)
1149 KVMState
*s
= kvm_state
;
1150 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1153 assert(kvm_enabled());
1155 x86_cpu_def
->name
= "host";
1156 x86_cpu_def
->cache_info_passthrough
= true;
1157 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1158 x86_cpu_vendor_words2str(x86_cpu_def
->vendor
, ebx
, edx
, ecx
);
1160 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1161 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1162 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1163 x86_cpu_def
->stepping
= eax
& 0x0F;
1165 x86_cpu_def
->level
= kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
1166 x86_cpu_def
->xlevel
= kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1167 x86_cpu_def
->xlevel2
=
1168 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1170 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
1172 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1173 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1174 x86_cpu_def
->features
[w
] =
1175 kvm_arch_get_supported_cpuid(s
, wi
->cpuid_eax
, wi
->cpuid_ecx
,
1180 static int unavailable_host_feature(FeatureWordInfo
*f
, uint32_t mask
)
1184 for (i
= 0; i
< 32; ++i
)
1185 if (1 << i
& mask
) {
1186 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1188 fprintf(stderr
, "warning: host doesn't support requested feature: "
1189 "CPUID.%02XH:%s%s%s [bit %d]\n",
1191 f
->feat_names
[i
] ? "." : "",
1192 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1198 /* Check if all requested cpu flags are making their way to the guest
1200 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1202 * This function may be called only if KVM is enabled.
1204 static int kvm_check_features_against_host(KVMState
*s
, X86CPU
*cpu
)
1206 CPUX86State
*env
= &cpu
->env
;
1210 assert(kvm_enabled());
1212 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1213 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1214 uint32_t guest_feat
= env
->features
[w
];
1215 uint32_t host_feat
= kvm_arch_get_supported_cpuid(s
, wi
->cpuid_eax
,
1219 for (mask
= 1; mask
; mask
<<= 1) {
1220 if (guest_feat
& mask
&& !(host_feat
& mask
)) {
1221 unavailable_host_feature(wi
, mask
);
1229 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
1230 const char *name
, Error
**errp
)
1232 X86CPU
*cpu
= X86_CPU(obj
);
1233 CPUX86State
*env
= &cpu
->env
;
1236 value
= (env
->cpuid_version
>> 8) & 0xf;
1238 value
+= (env
->cpuid_version
>> 20) & 0xff;
1240 visit_type_int(v
, &value
, name
, errp
);
1243 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
1244 const char *name
, Error
**errp
)
1246 X86CPU
*cpu
= X86_CPU(obj
);
1247 CPUX86State
*env
= &cpu
->env
;
1248 const int64_t min
= 0;
1249 const int64_t max
= 0xff + 0xf;
1252 visit_type_int(v
, &value
, name
, errp
);
1253 if (error_is_set(errp
)) {
1256 if (value
< min
|| value
> max
) {
1257 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1258 name
? name
: "null", value
, min
, max
);
1262 env
->cpuid_version
&= ~0xff00f00;
1264 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1266 env
->cpuid_version
|= value
<< 8;
1270 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
1271 const char *name
, Error
**errp
)
1273 X86CPU
*cpu
= X86_CPU(obj
);
1274 CPUX86State
*env
= &cpu
->env
;
1277 value
= (env
->cpuid_version
>> 4) & 0xf;
1278 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1279 visit_type_int(v
, &value
, name
, errp
);
1282 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
1283 const char *name
, Error
**errp
)
1285 X86CPU
*cpu
= X86_CPU(obj
);
1286 CPUX86State
*env
= &cpu
->env
;
1287 const int64_t min
= 0;
1288 const int64_t max
= 0xff;
1291 visit_type_int(v
, &value
, name
, errp
);
1292 if (error_is_set(errp
)) {
1295 if (value
< min
|| value
> max
) {
1296 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1297 name
? name
: "null", value
, min
, max
);
1301 env
->cpuid_version
&= ~0xf00f0;
1302 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1305 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1306 void *opaque
, const char *name
,
1309 X86CPU
*cpu
= X86_CPU(obj
);
1310 CPUX86State
*env
= &cpu
->env
;
1313 value
= env
->cpuid_version
& 0xf;
1314 visit_type_int(v
, &value
, name
, errp
);
1317 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1318 void *opaque
, const char *name
,
1321 X86CPU
*cpu
= X86_CPU(obj
);
1322 CPUX86State
*env
= &cpu
->env
;
1323 const int64_t min
= 0;
1324 const int64_t max
= 0xf;
1327 visit_type_int(v
, &value
, name
, errp
);
1328 if (error_is_set(errp
)) {
1331 if (value
< min
|| value
> max
) {
1332 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1333 name
? name
: "null", value
, min
, max
);
1337 env
->cpuid_version
&= ~0xf;
1338 env
->cpuid_version
|= value
& 0xf;
1341 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
1342 const char *name
, Error
**errp
)
1344 X86CPU
*cpu
= X86_CPU(obj
);
1346 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1349 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
1350 const char *name
, Error
**errp
)
1352 X86CPU
*cpu
= X86_CPU(obj
);
1354 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
1357 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1358 const char *name
, Error
**errp
)
1360 X86CPU
*cpu
= X86_CPU(obj
);
1362 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1365 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
1366 const char *name
, Error
**errp
)
1368 X86CPU
*cpu
= X86_CPU(obj
);
1370 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
1373 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1375 X86CPU
*cpu
= X86_CPU(obj
);
1376 CPUX86State
*env
= &cpu
->env
;
1379 value
= (char *)g_malloc(CPUID_VENDOR_SZ
+ 1);
1380 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1381 env
->cpuid_vendor3
);
1385 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1388 X86CPU
*cpu
= X86_CPU(obj
);
1389 CPUX86State
*env
= &cpu
->env
;
1392 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1393 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1398 env
->cpuid_vendor1
= 0;
1399 env
->cpuid_vendor2
= 0;
1400 env
->cpuid_vendor3
= 0;
1401 for (i
= 0; i
< 4; i
++) {
1402 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1403 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1404 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1408 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1410 X86CPU
*cpu
= X86_CPU(obj
);
1411 CPUX86State
*env
= &cpu
->env
;
1415 value
= g_malloc(48 + 1);
1416 for (i
= 0; i
< 48; i
++) {
1417 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1423 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1426 X86CPU
*cpu
= X86_CPU(obj
);
1427 CPUX86State
*env
= &cpu
->env
;
1430 if (model_id
== NULL
) {
1433 len
= strlen(model_id
);
1434 memset(env
->cpuid_model
, 0, 48);
1435 for (i
= 0; i
< 48; i
++) {
1439 c
= (uint8_t)model_id
[i
];
1441 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1445 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1446 const char *name
, Error
**errp
)
1448 X86CPU
*cpu
= X86_CPU(obj
);
1451 value
= cpu
->env
.tsc_khz
* 1000;
1452 visit_type_int(v
, &value
, name
, errp
);
1455 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1456 const char *name
, Error
**errp
)
1458 X86CPU
*cpu
= X86_CPU(obj
);
1459 const int64_t min
= 0;
1460 const int64_t max
= INT64_MAX
;
1463 visit_type_int(v
, &value
, name
, errp
);
1464 if (error_is_set(errp
)) {
1467 if (value
< min
|| value
> max
) {
1468 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1469 name
? name
: "null", value
, min
, max
);
1473 cpu
->env
.tsc_khz
= value
/ 1000;
1476 static void x86_cpuid_get_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1477 const char *name
, Error
**errp
)
1479 X86CPU
*cpu
= X86_CPU(obj
);
1480 int64_t value
= cpu
->env
.cpuid_apic_id
;
1482 visit_type_int(v
, &value
, name
, errp
);
1485 static void x86_cpuid_set_apic_id(Object
*obj
, Visitor
*v
, void *opaque
,
1486 const char *name
, Error
**errp
)
1488 X86CPU
*cpu
= X86_CPU(obj
);
1489 DeviceState
*dev
= DEVICE(obj
);
1490 const int64_t min
= 0;
1491 const int64_t max
= UINT32_MAX
;
1492 Error
*error
= NULL
;
1495 if (dev
->realized
) {
1496 error_setg(errp
, "Attempt to set property '%s' on '%s' after "
1497 "it was realized", name
, object_get_typename(obj
));
1501 visit_type_int(v
, &value
, name
, &error
);
1503 error_propagate(errp
, error
);
1506 if (value
< min
|| value
> max
) {
1507 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1508 " (minimum: %" PRId64
", maximum: %" PRId64
")" ,
1509 object_get_typename(obj
), name
, value
, min
, max
);
1513 if ((value
!= cpu
->env
.cpuid_apic_id
) && cpu_exists(value
)) {
1514 error_setg(errp
, "CPU with APIC ID %" PRIi64
" exists", value
);
1517 cpu
->env
.cpuid_apic_id
= value
;
1520 /* Generic getter for "feature-words" and "filtered-features" properties */
1521 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
, void *opaque
,
1522 const char *name
, Error
**errp
)
1524 uint32_t *array
= (uint32_t *)opaque
;
1527 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
1528 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
1529 X86CPUFeatureWordInfoList
*list
= NULL
;
1531 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1532 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1533 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
1534 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
1535 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
1536 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
1537 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
1538 qwi
->features
= array
[w
];
1540 /* List will be in reverse order, but order shouldn't matter */
1541 list_entries
[w
].next
= list
;
1542 list_entries
[w
].value
= &word_infos
[w
];
1543 list
= &list_entries
[w
];
1546 visit_type_X86CPUFeatureWordInfoList(v
, &list
, "feature-words", &err
);
1547 error_propagate(errp
, err
);
1550 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, void *opaque
,
1551 const char *name
, Error
**errp
)
1553 X86CPU
*cpu
= X86_CPU(obj
);
1554 int64_t value
= cpu
->hyperv_spinlock_attempts
;
1556 visit_type_int(v
, &value
, name
, errp
);
1559 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, void *opaque
,
1560 const char *name
, Error
**errp
)
1562 const int64_t min
= 0xFFF;
1563 const int64_t max
= UINT_MAX
;
1564 X86CPU
*cpu
= X86_CPU(obj
);
1568 visit_type_int(v
, &value
, name
, &err
);
1570 error_propagate(errp
, err
);
1574 if (value
< min
|| value
> max
) {
1575 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
1576 " (minimum: %" PRId64
", maximum: %" PRId64
")",
1577 object_get_typename(obj
), name
? name
: "null",
1581 cpu
->hyperv_spinlock_attempts
= value
;
1584 static PropertyInfo qdev_prop_spinlocks
= {
1586 .get
= x86_get_hv_spinlocks
,
1587 .set
= x86_set_hv_spinlocks
,
1590 static int cpu_x86_find_by_name(X86CPU
*cpu
, X86CPUDefinition
*x86_cpu_def
,
1593 X86CPUDefinition
*def
;
1599 if (kvm_enabled() && strcmp(name
, "host") == 0) {
1600 kvm_cpu_fill_host(x86_cpu_def
);
1601 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
1605 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1606 def
= &builtin_x86_defs
[i
];
1607 if (strcmp(name
, def
->name
) == 0) {
1608 memcpy(x86_cpu_def
, def
, sizeof(*def
));
1616 /* Convert all '_' in a feature string option name to '-', to make feature
1617 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1619 static inline void feat2prop(char *s
)
1621 while ((s
= strchr(s
, '_'))) {
1626 /* Parse "+feature,-feature,feature=foo" CPU feature string
1628 static void cpu_x86_parse_featurestr(X86CPU
*cpu
, char *features
, Error
**errp
)
1630 char *featurestr
; /* Single 'key=value" string being parsed */
1631 /* Features to be added */
1632 FeatureWordArray plus_features
= { 0 };
1633 /* Features to be removed */
1634 FeatureWordArray minus_features
= { 0 };
1636 CPUX86State
*env
= &cpu
->env
;
1638 featurestr
= features
? strtok(features
, ",") : NULL
;
1640 while (featurestr
) {
1642 if (featurestr
[0] == '+') {
1643 add_flagname_to_bitmaps(featurestr
+ 1, plus_features
);
1644 } else if (featurestr
[0] == '-') {
1645 add_flagname_to_bitmaps(featurestr
+ 1, minus_features
);
1646 } else if ((val
= strchr(featurestr
, '='))) {
1648 feat2prop(featurestr
);
1649 if (!strcmp(featurestr
, "xlevel")) {
1653 numvalue
= strtoul(val
, &err
, 0);
1654 if (!*val
|| *err
) {
1655 error_setg(errp
, "bad numerical value %s", val
);
1658 if (numvalue
< 0x80000000) {
1659 fprintf(stderr
, "xlevel value shall always be >= 0x80000000"
1660 ", fixup will be removed in future versions\n");
1661 numvalue
+= 0x80000000;
1663 snprintf(num
, sizeof(num
), "%" PRIu32
, numvalue
);
1664 object_property_parse(OBJECT(cpu
), num
, featurestr
, errp
);
1665 } else if (!strcmp(featurestr
, "tsc-freq")) {
1670 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1671 STRTOSZ_DEFSUFFIX_B
, 1000);
1672 if (tsc_freq
< 0 || *err
) {
1673 error_setg(errp
, "bad numerical value %s", val
);
1676 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
1677 object_property_parse(OBJECT(cpu
), num
, "tsc-frequency", errp
);
1678 } else if (!strcmp(featurestr
, "hv-spinlocks")) {
1680 const int min
= 0xFFF;
1682 numvalue
= strtoul(val
, &err
, 0);
1683 if (!*val
|| *err
) {
1684 error_setg(errp
, "bad numerical value %s", val
);
1687 if (numvalue
< min
) {
1688 fprintf(stderr
, "hv-spinlocks value shall always be >= 0x%x"
1689 ", fixup will be removed in future versions\n",
1693 snprintf(num
, sizeof(num
), "%" PRId32
, numvalue
);
1694 object_property_parse(OBJECT(cpu
), num
, featurestr
, errp
);
1696 object_property_parse(OBJECT(cpu
), val
, featurestr
, errp
);
1699 feat2prop(featurestr
);
1700 object_property_parse(OBJECT(cpu
), "on", featurestr
, errp
);
1702 if (error_is_set(errp
)) {
1705 featurestr
= strtok(NULL
, ",");
1707 env
->features
[FEAT_1_EDX
] |= plus_features
[FEAT_1_EDX
];
1708 env
->features
[FEAT_1_ECX
] |= plus_features
[FEAT_1_ECX
];
1709 env
->features
[FEAT_8000_0001_EDX
] |= plus_features
[FEAT_8000_0001_EDX
];
1710 env
->features
[FEAT_8000_0001_ECX
] |= plus_features
[FEAT_8000_0001_ECX
];
1711 env
->features
[FEAT_C000_0001_EDX
] |= plus_features
[FEAT_C000_0001_EDX
];
1712 env
->features
[FEAT_KVM
] |= plus_features
[FEAT_KVM
];
1713 env
->features
[FEAT_SVM
] |= plus_features
[FEAT_SVM
];
1714 env
->features
[FEAT_7_0_EBX
] |= plus_features
[FEAT_7_0_EBX
];
1715 env
->features
[FEAT_1_EDX
] &= ~minus_features
[FEAT_1_EDX
];
1716 env
->features
[FEAT_1_ECX
] &= ~minus_features
[FEAT_1_ECX
];
1717 env
->features
[FEAT_8000_0001_EDX
] &= ~minus_features
[FEAT_8000_0001_EDX
];
1718 env
->features
[FEAT_8000_0001_ECX
] &= ~minus_features
[FEAT_8000_0001_ECX
];
1719 env
->features
[FEAT_C000_0001_EDX
] &= ~minus_features
[FEAT_C000_0001_EDX
];
1720 env
->features
[FEAT_KVM
] &= ~minus_features
[FEAT_KVM
];
1721 env
->features
[FEAT_SVM
] &= ~minus_features
[FEAT_SVM
];
1722 env
->features
[FEAT_7_0_EBX
] &= ~minus_features
[FEAT_7_0_EBX
];
1728 /* generate a composite string into buf of all cpuid names in featureset
1729 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1730 * if flags, suppress names undefined in featureset.
1732 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1733 const char **featureset
, uint32_t flags
)
1735 const char **p
= &featureset
[31];
1739 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1741 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1742 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1744 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1746 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1747 if (bufsize
<= nc
) {
1749 memcpy(b
, "...", sizeof("..."));
1758 /* generate CPU information. */
1759 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1761 X86CPUDefinition
*def
;
1765 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1766 def
= &builtin_x86_defs
[i
];
1767 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
1768 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1771 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", "host",
1772 "KVM processor with all supported host features "
1773 "(only available in KVM mode)");
1776 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1777 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
1778 FeatureWordInfo
*fw
= &feature_word_info
[i
];
1780 listflags(buf
, sizeof(buf
), (uint32_t)~0, fw
->feat_names
, 1);
1781 (*cpu_fprintf
)(f
, " %s\n", buf
);
1785 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1787 CpuDefinitionInfoList
*cpu_list
= NULL
;
1788 X86CPUDefinition
*def
;
1791 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
1792 CpuDefinitionInfoList
*entry
;
1793 CpuDefinitionInfo
*info
;
1795 def
= &builtin_x86_defs
[i
];
1796 info
= g_malloc0(sizeof(*info
));
1797 info
->name
= g_strdup(def
->name
);
1799 entry
= g_malloc0(sizeof(*entry
));
1800 entry
->value
= info
;
1801 entry
->next
= cpu_list
;
1808 static void filter_features_for_kvm(X86CPU
*cpu
)
1810 CPUX86State
*env
= &cpu
->env
;
1811 KVMState
*s
= kvm_state
;
1814 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1815 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1816 uint32_t host_feat
= kvm_arch_get_supported_cpuid(s
, wi
->cpuid_eax
,
1819 uint32_t requested_features
= env
->features
[w
];
1820 env
->features
[w
] &= host_feat
;
1821 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
1825 /* Load CPU definition for a given CPU model name
1827 static void x86_cpu_load_def(X86CPU
*cpu
, const char *name
, Error
**errp
)
1829 CPUX86State
*env
= &cpu
->env
;
1830 X86CPUDefinition def1
, *def
= &def1
;
1832 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
1834 memset(def
, 0, sizeof(*def
));
1836 if (cpu_x86_find_by_name(cpu
, def
, name
) < 0) {
1837 error_setg(errp
, "Unable to find CPU definition: %s", name
);
1841 object_property_set_int(OBJECT(cpu
), def
->level
, "level", errp
);
1842 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
1843 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
1844 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
1845 env
->features
[FEAT_1_EDX
] = def
->features
[FEAT_1_EDX
];
1846 env
->features
[FEAT_1_ECX
] = def
->features
[FEAT_1_ECX
];
1847 env
->features
[FEAT_8000_0001_EDX
] = def
->features
[FEAT_8000_0001_EDX
];
1848 env
->features
[FEAT_8000_0001_ECX
] = def
->features
[FEAT_8000_0001_ECX
];
1849 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", errp
);
1850 env
->features
[FEAT_KVM
] = def
->features
[FEAT_KVM
];
1851 env
->features
[FEAT_SVM
] = def
->features
[FEAT_SVM
];
1852 env
->features
[FEAT_C000_0001_EDX
] = def
->features
[FEAT_C000_0001_EDX
];
1853 env
->features
[FEAT_7_0_EBX
] = def
->features
[FEAT_7_0_EBX
];
1854 env
->cpuid_xlevel2
= def
->xlevel2
;
1855 cpu
->cache_info_passthrough
= def
->cache_info_passthrough
;
1857 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
1859 /* Special cases not set in the X86CPUDefinition structs: */
1860 if (kvm_enabled()) {
1862 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
1863 env
->features
[w
] |= kvm_default_features
[w
];
1867 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
1869 /* sysenter isn't supported in compatibility mode on AMD,
1870 * syscall isn't supported in compatibility mode on Intel.
1871 * Normally we advertise the actual CPU vendor, but you can
1872 * override this using the 'vendor' property if you want to use
1873 * KVM's sysenter/syscall emulation in compatibility mode and
1874 * when doing cross vendor migration
1876 vendor
= def
->vendor
;
1877 if (kvm_enabled()) {
1878 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
1879 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
1880 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
1881 vendor
= host_vendor
;
1884 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
1888 X86CPU
*cpu_x86_create(const char *cpu_model
, DeviceState
*icc_bridge
,
1892 gchar
**model_pieces
;
1893 char *name
, *features
;
1895 Error
*error
= NULL
;
1897 model_pieces
= g_strsplit(cpu_model
, ",", 2);
1898 if (!model_pieces
[0]) {
1899 error_setg(&error
, "Invalid/empty CPU model name");
1902 name
= model_pieces
[0];
1903 features
= model_pieces
[1];
1905 cpu
= X86_CPU(object_new(TYPE_X86_CPU
));
1906 x86_cpu_load_def(cpu
, name
, &error
);
1911 #ifndef CONFIG_USER_ONLY
1912 if (icc_bridge
== NULL
) {
1913 error_setg(&error
, "Invalid icc-bridge value");
1916 qdev_set_parent_bus(DEVICE(cpu
), qdev_get_child_bus(icc_bridge
, "icc"));
1917 object_unref(OBJECT(cpu
));
1920 /* Emulate per-model subclasses for global properties */
1921 typename
= g_strdup_printf("%s-" TYPE_X86_CPU
, name
);
1922 qdev_prop_set_globals_for_type(DEVICE(cpu
), typename
, &error
);
1928 cpu_x86_parse_featurestr(cpu
, features
, &error
);
1934 if (error
!= NULL
) {
1935 error_propagate(errp
, error
);
1936 object_unref(OBJECT(cpu
));
1939 g_strfreev(model_pieces
);
1943 X86CPU
*cpu_x86_init(const char *cpu_model
)
1945 Error
*error
= NULL
;
1948 cpu
= cpu_x86_create(cpu_model
, NULL
, &error
);
1953 object_property_set_bool(OBJECT(cpu
), true, "realized", &error
);
1957 error_report("%s", error_get_pretty(error
));
1960 object_unref(OBJECT(cpu
));
1967 #if !defined(CONFIG_USER_ONLY)
1969 void cpu_clear_apic_feature(CPUX86State
*env
)
1971 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
1974 #endif /* !CONFIG_USER_ONLY */
1976 /* Initialize list of CPU models, filling some non-static fields if necessary
1978 void x86_cpudef_setup(void)
1981 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
1983 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
1984 X86CPUDefinition
*def
= &builtin_x86_defs
[i
];
1986 /* Look for specific "cpudef" models that */
1987 /* have the QEMU version in .model_id */
1988 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
1989 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
1990 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
1991 "QEMU Virtual CPU version ");
1992 pstrcat(def
->model_id
, sizeof(def
->model_id
),
1993 qemu_get_version());
2000 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
2001 uint32_t *ecx
, uint32_t *edx
)
2003 *ebx
= env
->cpuid_vendor1
;
2004 *edx
= env
->cpuid_vendor2
;
2005 *ecx
= env
->cpuid_vendor3
;
2008 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2009 uint32_t *eax
, uint32_t *ebx
,
2010 uint32_t *ecx
, uint32_t *edx
)
2012 X86CPU
*cpu
= x86_env_get_cpu(env
);
2013 CPUState
*cs
= CPU(cpu
);
2015 /* test if maximum index reached */
2016 if (index
& 0x80000000) {
2017 if (index
> env
->cpuid_xlevel
) {
2018 if (env
->cpuid_xlevel2
> 0) {
2019 /* Handle the Centaur's CPUID instruction. */
2020 if (index
> env
->cpuid_xlevel2
) {
2021 index
= env
->cpuid_xlevel2
;
2022 } else if (index
< 0xC0000000) {
2023 index
= env
->cpuid_xlevel
;
2026 /* Intel documentation states that invalid EAX input will
2027 * return the same information as EAX=cpuid_level
2028 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2030 index
= env
->cpuid_level
;
2034 if (index
> env
->cpuid_level
)
2035 index
= env
->cpuid_level
;
2040 *eax
= env
->cpuid_level
;
2041 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
2044 *eax
= env
->cpuid_version
;
2045 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2046 *ecx
= env
->features
[FEAT_1_ECX
];
2047 *edx
= env
->features
[FEAT_1_EDX
];
2048 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2049 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
2050 *edx
|= 1 << 28; /* HTT bit */
2054 /* cache info: needed for Pentium Pro compatibility */
2055 if (cpu
->cache_info_passthrough
) {
2056 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2059 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
2062 *edx
= (L1D_DESCRIPTOR
<< 16) | \
2063 (L1I_DESCRIPTOR
<< 8) | \
2067 /* cache info: needed for Core compatibility */
2068 if (cpu
->cache_info_passthrough
) {
2069 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
2070 *eax
&= ~0xFC000000;
2074 case 0: /* L1 dcache info */
2075 *eax
|= CPUID_4_TYPE_DCACHE
| \
2076 CPUID_4_LEVEL(1) | \
2077 CPUID_4_SELF_INIT_LEVEL
;
2078 *ebx
= (L1D_LINE_SIZE
- 1) | \
2079 ((L1D_PARTITIONS
- 1) << 12) | \
2080 ((L1D_ASSOCIATIVITY
- 1) << 22);
2081 *ecx
= L1D_SETS
- 1;
2082 *edx
= CPUID_4_NO_INVD_SHARING
;
2084 case 1: /* L1 icache info */
2085 *eax
|= CPUID_4_TYPE_ICACHE
| \
2086 CPUID_4_LEVEL(1) | \
2087 CPUID_4_SELF_INIT_LEVEL
;
2088 *ebx
= (L1I_LINE_SIZE
- 1) | \
2089 ((L1I_PARTITIONS
- 1) << 12) | \
2090 ((L1I_ASSOCIATIVITY
- 1) << 22);
2091 *ecx
= L1I_SETS
- 1;
2092 *edx
= CPUID_4_NO_INVD_SHARING
;
2094 case 2: /* L2 cache info */
2095 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2096 CPUID_4_LEVEL(2) | \
2097 CPUID_4_SELF_INIT_LEVEL
;
2098 if (cs
->nr_threads
> 1) {
2099 *eax
|= (cs
->nr_threads
- 1) << 14;
2101 *ebx
= (L2_LINE_SIZE
- 1) | \
2102 ((L2_PARTITIONS
- 1) << 12) | \
2103 ((L2_ASSOCIATIVITY
- 1) << 22);
2105 *edx
= CPUID_4_NO_INVD_SHARING
;
2107 default: /* end of info */
2116 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2117 if ((*eax
& 31) && cs
->nr_cores
> 1) {
2118 *eax
|= (cs
->nr_cores
- 1) << 26;
2122 /* mwait info: needed for Core compatibility */
2123 *eax
= 0; /* Smallest monitor-line size in bytes */
2124 *ebx
= 0; /* Largest monitor-line size in bytes */
2125 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2129 /* Thermal and Power Leaf */
2136 /* Structured Extended Feature Flags Enumeration Leaf */
2138 *eax
= 0; /* Maximum ECX value for sub-leaves */
2139 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
2140 *ecx
= 0; /* Reserved */
2141 *edx
= 0; /* Reserved */
2150 /* Direct Cache Access Information Leaf */
2151 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2157 /* Architectural Performance Monitoring Leaf */
2158 if (kvm_enabled() && cpu
->enable_pmu
) {
2159 KVMState
*s
= cs
->kvm_state
;
2161 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
2162 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
2163 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
2164 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
2173 KVMState
*s
= cs
->kvm_state
;
2177 /* Processor Extended State */
2182 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) || !kvm_enabled()) {
2186 kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EAX
) |
2187 ((uint64_t)kvm_arch_get_supported_cpuid(s
, 0xd, 0, R_EDX
) << 32);
2191 for (i
= 2; i
< ARRAY_SIZE(ext_save_areas
); i
++) {
2192 const ExtSaveArea
*esa
= &ext_save_areas
[i
];
2193 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
&&
2194 (kvm_mask
& (1 << i
)) != 0) {
2198 *edx
|= 1 << (i
- 32);
2200 *ecx
= MAX(*ecx
, esa
->offset
+ esa
->size
);
2203 *eax
|= kvm_mask
& (XSTATE_FP
| XSTATE_SSE
);
2205 } else if (count
== 1) {
2206 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, 1, R_EAX
);
2207 } else if (count
< ARRAY_SIZE(ext_save_areas
)) {
2208 const ExtSaveArea
*esa
= &ext_save_areas
[count
];
2209 if ((env
->features
[esa
->feature
] & esa
->bits
) == esa
->bits
&&
2210 (kvm_mask
& (1 << count
)) != 0) {
2218 *eax
= env
->cpuid_xlevel
;
2219 *ebx
= env
->cpuid_vendor1
;
2220 *edx
= env
->cpuid_vendor2
;
2221 *ecx
= env
->cpuid_vendor3
;
2224 *eax
= env
->cpuid_version
;
2226 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
2227 *edx
= env
->features
[FEAT_8000_0001_EDX
];
2229 /* The Linux kernel checks for the CMPLegacy bit and
2230 * discards multiple thread information if it is set.
2231 * So dont set it here for Intel to make Linux guests happy.
2233 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2234 uint32_t tebx
, tecx
, tedx
;
2235 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
2236 if (tebx
!= CPUID_VENDOR_INTEL_1
||
2237 tedx
!= CPUID_VENDOR_INTEL_2
||
2238 tecx
!= CPUID_VENDOR_INTEL_3
) {
2239 *ecx
|= 1 << 1; /* CmpLegacy bit */
2246 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
2247 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
2248 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
2249 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
2252 /* cache info (L1 cache) */
2253 if (cpu
->cache_info_passthrough
) {
2254 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2257 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
2258 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
2259 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
2260 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
2261 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
2262 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
2263 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
2264 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
2267 /* cache info (L2 cache) */
2268 if (cpu
->cache_info_passthrough
) {
2269 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2272 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
2273 (L2_DTLB_2M_ENTRIES
<< 16) | \
2274 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
2275 (L2_ITLB_2M_ENTRIES
);
2276 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
2277 (L2_DTLB_4K_ENTRIES
<< 16) | \
2278 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
2279 (L2_ITLB_4K_ENTRIES
);
2280 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
2281 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
2282 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
2283 *edx
= ((L3_SIZE_KB
/512) << 18) | \
2284 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
2285 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
2288 /* virtual & phys address size in low 2 bytes. */
2289 /* XXX: This value must match the one used in the MMU code. */
2290 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
2291 /* 64 bit processor */
2292 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2293 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
2295 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
2296 *eax
= 0x00000024; /* 36 bits physical */
2298 *eax
= 0x00000020; /* 32 bits physical */
2304 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2305 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
2309 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
2310 *eax
= 0x00000001; /* SVM Revision */
2311 *ebx
= 0x00000010; /* nr of ASIDs */
2313 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
2322 *eax
= env
->cpuid_xlevel2
;
2328 /* Support for VIA CPU's CPUID instruction */
2329 *eax
= env
->cpuid_version
;
2332 *edx
= env
->features
[FEAT_C000_0001_EDX
];
2337 /* Reserved for the future, and now filled with zero */
2344 /* reserved values: zero */
2353 /* CPUClass::reset() */
2354 static void x86_cpu_reset(CPUState
*s
)
2356 X86CPU
*cpu
= X86_CPU(s
);
2357 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
2358 CPUX86State
*env
= &cpu
->env
;
2361 xcc
->parent_reset(s
);
2364 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
2368 env
->old_exception
= -1;
2370 /* init to reset state */
2372 #ifdef CONFIG_SOFTMMU
2373 env
->hflags
|= HF_SOFTMMU_MASK
;
2375 env
->hflags2
|= HF2_GIF_MASK
;
2377 cpu_x86_update_cr0(env
, 0x60000010);
2378 env
->a20_mask
= ~0x0;
2379 env
->smbase
= 0x30000;
2381 env
->idt
.limit
= 0xffff;
2382 env
->gdt
.limit
= 0xffff;
2383 env
->ldt
.limit
= 0xffff;
2384 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
2385 env
->tr
.limit
= 0xffff;
2386 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
2388 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
2389 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
2390 DESC_R_MASK
| DESC_A_MASK
);
2391 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
2392 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2394 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
2395 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2397 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
2398 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2400 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
2401 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2403 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
2404 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
2408 env
->regs
[R_EDX
] = env
->cpuid_version
;
2413 for (i
= 0; i
< 8; i
++) {
2418 env
->mxcsr
= 0x1f80;
2419 env
->xstate_bv
= XSTATE_FP
| XSTATE_SSE
;
2421 env
->pat
= 0x0007040600070406ULL
;
2422 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
2424 memset(env
->dr
, 0, sizeof(env
->dr
));
2425 env
->dr
[6] = DR6_FIXED_1
;
2426 env
->dr
[7] = DR7_FIXED_1
;
2427 cpu_breakpoint_remove_all(env
, BP_CPU
);
2428 cpu_watchpoint_remove_all(env
, BP_CPU
);
2430 env
->tsc_adjust
= 0;
2433 #if !defined(CONFIG_USER_ONLY)
2434 /* We hard-wire the BSP to the first CPU. */
2435 if (s
->cpu_index
== 0) {
2436 apic_designate_bsp(cpu
->apic_state
);
2439 s
->halted
= !cpu_is_bsp(cpu
);
2443 #ifndef CONFIG_USER_ONLY
2444 bool cpu_is_bsp(X86CPU
*cpu
)
2446 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
2449 /* TODO: remove me, when reset over QOM tree is implemented */
2450 static void x86_cpu_machine_reset_cb(void *opaque
)
2452 X86CPU
*cpu
= opaque
;
2453 cpu_reset(CPU(cpu
));
2457 static void mce_init(X86CPU
*cpu
)
2459 CPUX86State
*cenv
= &cpu
->env
;
2462 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
2463 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
2464 (CPUID_MCE
| CPUID_MCA
)) {
2465 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
2466 cenv
->mcg_ctl
= ~(uint64_t)0;
2467 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
2468 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
2473 #ifndef CONFIG_USER_ONLY
2474 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
2476 CPUX86State
*env
= &cpu
->env
;
2477 DeviceState
*dev
= DEVICE(cpu
);
2478 APICCommonState
*apic
;
2479 const char *apic_type
= "apic";
2481 if (kvm_irqchip_in_kernel()) {
2482 apic_type
= "kvm-apic";
2483 } else if (xen_enabled()) {
2484 apic_type
= "xen-apic";
2487 cpu
->apic_state
= qdev_try_create(qdev_get_parent_bus(dev
), apic_type
);
2488 if (cpu
->apic_state
== NULL
) {
2489 error_setg(errp
, "APIC device '%s' could not be created", apic_type
);
2493 object_property_add_child(OBJECT(cpu
), "apic",
2494 OBJECT(cpu
->apic_state
), NULL
);
2495 qdev_prop_set_uint8(cpu
->apic_state
, "id", env
->cpuid_apic_id
);
2496 /* TODO: convert to link<> */
2497 apic
= APIC_COMMON(cpu
->apic_state
);
2501 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2503 if (cpu
->apic_state
== NULL
) {
2507 if (qdev_init(cpu
->apic_state
)) {
2508 error_setg(errp
, "APIC device '%s' could not be initialized",
2509 object_get_typename(OBJECT(cpu
->apic_state
)));
2514 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
2519 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
2521 CPUState
*cs
= CPU(dev
);
2522 X86CPU
*cpu
= X86_CPU(dev
);
2523 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
2524 CPUX86State
*env
= &cpu
->env
;
2525 Error
*local_err
= NULL
;
2527 if (env
->features
[FEAT_7_0_EBX
] && env
->cpuid_level
< 7) {
2528 env
->cpuid_level
= 7;
2531 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2534 if (env
->cpuid_vendor1
== CPUID_VENDOR_AMD_1
&&
2535 env
->cpuid_vendor2
== CPUID_VENDOR_AMD_2
&&
2536 env
->cpuid_vendor3
== CPUID_VENDOR_AMD_3
) {
2537 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
2538 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
2539 & CPUID_EXT2_AMD_ALIASES
);
2542 if (!kvm_enabled()) {
2543 env
->features
[FEAT_1_EDX
] &= TCG_FEATURES
;
2544 env
->features
[FEAT_1_ECX
] &= TCG_EXT_FEATURES
;
2545 env
->features
[FEAT_8000_0001_EDX
] &= (TCG_EXT2_FEATURES
2546 #ifdef TARGET_X86_64
2547 | CPUID_EXT2_SYSCALL
| CPUID_EXT2_LM
2550 env
->features
[FEAT_8000_0001_ECX
] &= TCG_EXT3_FEATURES
;
2551 env
->features
[FEAT_SVM
] &= TCG_SVM_FEATURES
;
2553 KVMState
*s
= kvm_state
;
2554 if ((cpu
->check_cpuid
|| cpu
->enforce_cpuid
)
2555 && kvm_check_features_against_host(s
, cpu
) && cpu
->enforce_cpuid
) {
2556 error_setg(&local_err
,
2557 "Host's CPU doesn't support requested features");
2560 filter_features_for_kvm(cpu
);
2563 #ifndef CONFIG_USER_ONLY
2564 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
2566 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
2567 x86_cpu_apic_create(cpu
, &local_err
);
2568 if (local_err
!= NULL
) {
2577 x86_cpu_apic_realize(cpu
, &local_err
);
2578 if (local_err
!= NULL
) {
2583 xcc
->parent_realize(dev
, &local_err
);
2585 if (local_err
!= NULL
) {
2586 error_propagate(errp
, local_err
);
2591 /* Enables contiguous-apic-ID mode, for compatibility */
2592 static bool compat_apic_id_mode
;
2594 void enable_compat_apic_id_mode(void)
2596 compat_apic_id_mode
= true;
2599 /* Calculates initial APIC ID for a specific CPU index
2601 * Currently we need to be able to calculate the APIC ID from the CPU index
2602 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2603 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2604 * all CPUs up to max_cpus.
2606 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index
)
2608 uint32_t correct_id
;
2611 correct_id
= x86_apicid_from_cpu_idx(smp_cores
, smp_threads
, cpu_index
);
2612 if (compat_apic_id_mode
) {
2613 if (cpu_index
!= correct_id
&& !warned
) {
2614 error_report("APIC IDs set in compatibility mode, "
2615 "CPU topology won't match the configuration");
2624 static void x86_cpu_initfn(Object
*obj
)
2626 CPUState
*cs
= CPU(obj
);
2627 X86CPU
*cpu
= X86_CPU(obj
);
2628 CPUX86State
*env
= &cpu
->env
;
2634 object_property_add(obj
, "family", "int",
2635 x86_cpuid_version_get_family
,
2636 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
2637 object_property_add(obj
, "model", "int",
2638 x86_cpuid_version_get_model
,
2639 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
2640 object_property_add(obj
, "stepping", "int",
2641 x86_cpuid_version_get_stepping
,
2642 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
2643 object_property_add(obj
, "level", "int",
2644 x86_cpuid_get_level
,
2645 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
2646 object_property_add(obj
, "xlevel", "int",
2647 x86_cpuid_get_xlevel
,
2648 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
2649 object_property_add_str(obj
, "vendor",
2650 x86_cpuid_get_vendor
,
2651 x86_cpuid_set_vendor
, NULL
);
2652 object_property_add_str(obj
, "model-id",
2653 x86_cpuid_get_model_id
,
2654 x86_cpuid_set_model_id
, NULL
);
2655 object_property_add(obj
, "tsc-frequency", "int",
2656 x86_cpuid_get_tsc_freq
,
2657 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
2658 object_property_add(obj
, "apic-id", "int",
2659 x86_cpuid_get_apic_id
,
2660 x86_cpuid_set_apic_id
, NULL
, NULL
, NULL
);
2661 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
2662 x86_cpu_get_feature_words
,
2663 NULL
, NULL
, (void *)env
->features
, NULL
);
2664 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
2665 x86_cpu_get_feature_words
,
2666 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
2668 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
2669 env
->cpuid_apic_id
= x86_cpu_apic_id_from_index(cs
->cpu_index
);
2671 /* init various static tables used in TCG mode */
2672 if (tcg_enabled() && !inited
) {
2674 optimize_flags_init();
2675 #ifndef CONFIG_USER_ONLY
2676 cpu_set_debug_excp_handler(breakpoint_handler
);
2681 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
2683 X86CPU
*cpu
= X86_CPU(cs
);
2684 CPUX86State
*env
= &cpu
->env
;
2686 return env
->cpuid_apic_id
;
2689 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
2691 X86CPU
*cpu
= X86_CPU(cs
);
2693 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
2696 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
2698 X86CPU
*cpu
= X86_CPU(cs
);
2700 cpu
->env
.eip
= value
;
2703 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
2705 X86CPU
*cpu
= X86_CPU(cs
);
2707 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
2710 static bool x86_cpu_has_work(CPUState
*cs
)
2712 X86CPU
*cpu
= X86_CPU(cs
);
2713 CPUX86State
*env
= &cpu
->env
;
2715 return ((cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
2716 CPU_INTERRUPT_POLL
)) &&
2717 (env
->eflags
& IF_MASK
)) ||
2718 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
2719 CPU_INTERRUPT_INIT
|
2720 CPU_INTERRUPT_SIPI
|
2721 CPU_INTERRUPT_MCE
));
2724 static Property x86_cpu_properties
[] = {
2725 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
2726 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
2727 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
2728 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
2729 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
2730 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, false),
2731 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
2732 DEFINE_PROP_END_OF_LIST()
2735 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
2737 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2738 CPUClass
*cc
= CPU_CLASS(oc
);
2739 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2741 xcc
->parent_realize
= dc
->realize
;
2742 dc
->realize
= x86_cpu_realizefn
;
2743 dc
->bus_type
= TYPE_ICC_BUS
;
2744 dc
->props
= x86_cpu_properties
;
2746 xcc
->parent_reset
= cc
->reset
;
2747 cc
->reset
= x86_cpu_reset
;
2748 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
2750 cc
->has_work
= x86_cpu_has_work
;
2751 cc
->do_interrupt
= x86_cpu_do_interrupt
;
2752 cc
->dump_state
= x86_cpu_dump_state
;
2753 cc
->set_pc
= x86_cpu_set_pc
;
2754 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
2755 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
2756 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
2757 cc
->get_arch_id
= x86_cpu_get_arch_id
;
2758 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
2759 #ifndef CONFIG_USER_ONLY
2760 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
2761 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
2762 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
2763 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
2764 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
2765 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
2766 cc
->vmsd
= &vmstate_x86_cpu
;
2768 cc
->gdb_num_core_regs
= CPU_NB_REGS
* 2 + 25;
2771 static const TypeInfo x86_cpu_type_info
= {
2772 .name
= TYPE_X86_CPU
,
2774 .instance_size
= sizeof(X86CPU
),
2775 .instance_init
= x86_cpu_initfn
,
2777 .class_size
= sizeof(X86CPUClass
),
2778 .class_init
= x86_cpu_common_class_init
,
2781 static void x86_cpu_register_types(void)
2783 type_register_static(&x86_cpu_type_info
);
2786 type_init(x86_cpu_register_types
)