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target-i386: Make TCG feature filtering more readable
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "kvm_i386.h"
28 #include "topology.h"
29
30 #include "qemu/option.h"
31 #include "qemu/config-file.h"
32 #include "qapi/qmp/qerror.h"
33
34 #include "qapi-types.h"
35 #include "qapi-visit.h"
36 #include "qapi/visitor.h"
37 #include "sysemu/arch_init.h"
38
39 #include "hw/hw.h"
40 #if defined(CONFIG_KVM)
41 #include <linux/kvm_para.h>
42 #endif
43
44 #include "sysemu/sysemu.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/cpu/icc_bus.h"
47 #ifndef CONFIG_USER_ONLY
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
50 #endif
51
52
53 /* Cache topology CPUID constants: */
54
55 /* CPUID Leaf 2 Descriptors */
56
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62 /* CPUID Leaf 4 constants: */
63
64 /* EAX: */
65 #define CPUID_4_TYPE_DCACHE 1
66 #define CPUID_4_TYPE_ICACHE 2
67 #define CPUID_4_TYPE_UNIFIED 3
68
69 #define CPUID_4_LEVEL(l) ((l) << 5)
70
71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72 #define CPUID_4_FULLY_ASSOC (1 << 9)
73
74 /* EDX: */
75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
76 #define CPUID_4_INCLUSIVE (1 << 1)
77 #define CPUID_4_COMPLEX_IDX (1 << 2)
78
79 #define ASSOC_FULL 0xFF
80
81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96 /* Definitions of the hardcoded cache entries we expose: */
97
98 /* L1 data cache: */
99 #define L1D_LINE_SIZE 64
100 #define L1D_ASSOCIATIVITY 8
101 #define L1D_SETS 64
102 #define L1D_PARTITIONS 1
103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106 #define L1D_LINES_PER_TAG 1
107 #define L1D_SIZE_KB_AMD 64
108 #define L1D_ASSOCIATIVITY_AMD 2
109
110 /* L1 instruction cache: */
111 #define L1I_LINE_SIZE 64
112 #define L1I_ASSOCIATIVITY 8
113 #define L1I_SETS 64
114 #define L1I_PARTITIONS 1
115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118 #define L1I_LINES_PER_TAG 1
119 #define L1I_SIZE_KB_AMD 64
120 #define L1I_ASSOCIATIVITY_AMD 2
121
122 /* Level 2 unified cache: */
123 #define L2_LINE_SIZE 64
124 #define L2_ASSOCIATIVITY 16
125 #define L2_SETS 4096
126 #define L2_PARTITIONS 1
127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131 #define L2_LINES_PER_TAG 1
132 #define L2_SIZE_KB_AMD 512
133
134 /* No L3 cache: */
135 #define L3_SIZE_KB 0 /* disabled */
136 #define L3_ASSOCIATIVITY 0 /* disabled */
137 #define L3_LINES_PER_TAG 0 /* disabled */
138 #define L3_LINE_SIZE 0 /* disabled */
139
140 /* TLB definitions: */
141
142 #define L1_DTLB_2M_ASSOC 1
143 #define L1_DTLB_2M_ENTRIES 255
144 #define L1_DTLB_4K_ASSOC 1
145 #define L1_DTLB_4K_ENTRIES 255
146
147 #define L1_ITLB_2M_ASSOC 1
148 #define L1_ITLB_2M_ENTRIES 255
149 #define L1_ITLB_4K_ASSOC 1
150 #define L1_ITLB_4K_ENTRIES 255
151
152 #define L2_DTLB_2M_ASSOC 0 /* disabled */
153 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
154 #define L2_DTLB_4K_ASSOC 4
155 #define L2_DTLB_4K_ENTRIES 512
156
157 #define L2_ITLB_2M_ASSOC 0 /* disabled */
158 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
159 #define L2_ITLB_4K_ASSOC 4
160 #define L2_ITLB_4K_ENTRIES 512
161
162
163
164 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166 {
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174 }
175
176 /* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180 static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189 };
190 static const char *ext_feature_name[] = {
191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
192 "ds_cpl", "vmx", "smx", "est",
193 "tm2", "ssse3", "cid", NULL,
194 "fma", "cx16", "xtpr", "pdcm",
195 NULL, "pcid", "dca", "sse4.1|sse4_1",
196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
197 "tsc-deadline", "aes", "xsave", "osxsave",
198 "avx", "f16c", "rdrand", "hypervisor",
199 };
200 /* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
205 static const char *ext2_feature_name[] = {
206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
213 NULL, "lm|i64", "3dnowext", "3dnow",
214 };
215 static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
218 "3dnowprefetch", "osvw", "ibs", "xop",
219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
223 NULL, NULL, NULL, NULL,
224 };
225
226 static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235 };
236
237 static const char *kvm_feature_name[] = {
238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
246 };
247
248 static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257 };
258
259 static const char *cpuid_7_0_ebx_feature_name[] = {
260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264 };
265
266 typedef struct FeatureWordInfo {
267 const char **feat_names;
268 uint32_t cpuid_eax; /* Input EAX for CPUID */
269 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
270 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
271 int cpuid_reg; /* output register (R_* constant) */
272 } FeatureWordInfo;
273
274 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
275 [FEAT_1_EDX] = {
276 .feat_names = feature_name,
277 .cpuid_eax = 1, .cpuid_reg = R_EDX,
278 },
279 [FEAT_1_ECX] = {
280 .feat_names = ext_feature_name,
281 .cpuid_eax = 1, .cpuid_reg = R_ECX,
282 },
283 [FEAT_8000_0001_EDX] = {
284 .feat_names = ext2_feature_name,
285 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
286 },
287 [FEAT_8000_0001_ECX] = {
288 .feat_names = ext3_feature_name,
289 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
290 },
291 [FEAT_C000_0001_EDX] = {
292 .feat_names = ext4_feature_name,
293 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
294 },
295 [FEAT_KVM] = {
296 .feat_names = kvm_feature_name,
297 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
298 },
299 [FEAT_SVM] = {
300 .feat_names = svm_feature_name,
301 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
302 },
303 [FEAT_7_0_EBX] = {
304 .feat_names = cpuid_7_0_ebx_feature_name,
305 .cpuid_eax = 7,
306 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
307 .cpuid_reg = R_EBX,
308 },
309 };
310
311 typedef struct X86RegisterInfo32 {
312 /* Name of register */
313 const char *name;
314 /* QAPI enum value register */
315 X86CPURegister32 qapi_enum;
316 } X86RegisterInfo32;
317
318 #define REGISTER(reg) \
319 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
320 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
321 REGISTER(EAX),
322 REGISTER(ECX),
323 REGISTER(EDX),
324 REGISTER(EBX),
325 REGISTER(ESP),
326 REGISTER(EBP),
327 REGISTER(ESI),
328 REGISTER(EDI),
329 };
330 #undef REGISTER
331
332 typedef struct ExtSaveArea {
333 uint32_t feature, bits;
334 uint32_t offset, size;
335 } ExtSaveArea;
336
337 static const ExtSaveArea ext_save_areas[] = {
338 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
339 .offset = 0x240, .size = 0x100 },
340 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
341 .offset = 0x3c0, .size = 0x40 },
342 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
343 .offset = 0x400, .size = 0x40 },
344 };
345
346 const char *get_register_name_32(unsigned int reg)
347 {
348 if (reg >= CPU_NB_REGS32) {
349 return NULL;
350 }
351 return x86_reg_info_32[reg].name;
352 }
353
354 /* collects per-function cpuid data
355 */
356 typedef struct model_features_t {
357 uint32_t *guest_feat;
358 uint32_t *host_feat;
359 FeatureWord feat_word;
360 } model_features_t;
361
362 /* KVM-specific features that are automatically added to all CPU models
363 * when KVM is enabled.
364 */
365 static uint32_t kvm_default_features[FEATURE_WORDS] = {
366 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
367 (1 << KVM_FEATURE_NOP_IO_DELAY) |
368 (1 << KVM_FEATURE_CLOCKSOURCE2) |
369 (1 << KVM_FEATURE_ASYNC_PF) |
370 (1 << KVM_FEATURE_STEAL_TIME) |
371 (1 << KVM_FEATURE_PV_EOI) |
372 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
373 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
374 };
375
376 /* Features that are not added by default to any CPU model when KVM is enabled.
377 */
378 static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
379 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
380 };
381
382 void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
383 {
384 kvm_default_features[w] &= ~features;
385 }
386
387 void host_cpuid(uint32_t function, uint32_t count,
388 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
389 {
390 uint32_t vec[4];
391
392 #ifdef __x86_64__
393 asm volatile("cpuid"
394 : "=a"(vec[0]), "=b"(vec[1]),
395 "=c"(vec[2]), "=d"(vec[3])
396 : "0"(function), "c"(count) : "cc");
397 #elif defined(__i386__)
398 asm volatile("pusha \n\t"
399 "cpuid \n\t"
400 "mov %%eax, 0(%2) \n\t"
401 "mov %%ebx, 4(%2) \n\t"
402 "mov %%ecx, 8(%2) \n\t"
403 "mov %%edx, 12(%2) \n\t"
404 "popa"
405 : : "a"(function), "c"(count), "S"(vec)
406 : "memory", "cc");
407 #else
408 abort();
409 #endif
410
411 if (eax)
412 *eax = vec[0];
413 if (ebx)
414 *ebx = vec[1];
415 if (ecx)
416 *ecx = vec[2];
417 if (edx)
418 *edx = vec[3];
419 }
420
421 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
422
423 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
424 * a substring. ex if !NULL points to the first char after a substring,
425 * otherwise the string is assumed to sized by a terminating nul.
426 * Return lexical ordering of *s1:*s2.
427 */
428 static int sstrcmp(const char *s1, const char *e1, const char *s2,
429 const char *e2)
430 {
431 for (;;) {
432 if (!*s1 || !*s2 || *s1 != *s2)
433 return (*s1 - *s2);
434 ++s1, ++s2;
435 if (s1 == e1 && s2 == e2)
436 return (0);
437 else if (s1 == e1)
438 return (*s2);
439 else if (s2 == e2)
440 return (*s1);
441 }
442 }
443
444 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
445 * '|' delimited (possibly empty) strings in which case search for a match
446 * within the alternatives proceeds left to right. Return 0 for success,
447 * non-zero otherwise.
448 */
449 static int altcmp(const char *s, const char *e, const char *altstr)
450 {
451 const char *p, *q;
452
453 for (q = p = altstr; ; ) {
454 while (*p && *p != '|')
455 ++p;
456 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
457 return (0);
458 if (!*p)
459 return (1);
460 else
461 q = ++p;
462 }
463 }
464
465 /* search featureset for flag *[s..e), if found set corresponding bit in
466 * *pval and return true, otherwise return false
467 */
468 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
469 const char **featureset)
470 {
471 uint32_t mask;
472 const char **ppc;
473 bool found = false;
474
475 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
476 if (*ppc && !altcmp(s, e, *ppc)) {
477 *pval |= mask;
478 found = true;
479 }
480 }
481 return found;
482 }
483
484 static void add_flagname_to_bitmaps(const char *flagname,
485 FeatureWordArray words)
486 {
487 FeatureWord w;
488 for (w = 0; w < FEATURE_WORDS; w++) {
489 FeatureWordInfo *wi = &feature_word_info[w];
490 if (wi->feat_names &&
491 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
492 break;
493 }
494 }
495 if (w == FEATURE_WORDS) {
496 fprintf(stderr, "CPU feature %s not found\n", flagname);
497 }
498 }
499
500 /* CPU class name definitions: */
501
502 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
503 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
504
505 /* Return type name for a given CPU model name
506 * Caller is responsible for freeing the returned string.
507 */
508 static char *x86_cpu_type_name(const char *model_name)
509 {
510 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
511 }
512
513 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
514 {
515 ObjectClass *oc;
516 char *typename;
517
518 if (cpu_model == NULL) {
519 return NULL;
520 }
521
522 typename = x86_cpu_type_name(cpu_model);
523 oc = object_class_by_name(typename);
524 g_free(typename);
525 return oc;
526 }
527
528 struct X86CPUDefinition {
529 const char *name;
530 uint32_t level;
531 uint32_t xlevel;
532 uint32_t xlevel2;
533 /* vendor is zero-terminated, 12 character ASCII string */
534 char vendor[CPUID_VENDOR_SZ + 1];
535 int family;
536 int model;
537 int stepping;
538 FeatureWordArray features;
539 char model_id[48];
540 bool cache_info_passthrough;
541 };
542
543 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
544 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
545 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
546 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
547 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
548 CPUID_PSE36 | CPUID_FXSR)
549 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
550 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
551 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
552 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
553 CPUID_PAE | CPUID_SEP | CPUID_APIC)
554
555 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
556 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
557 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
558 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
559 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
560 /* partly implemented:
561 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
562 /* missing:
563 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
564 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
565 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
566 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
567 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
568 /* missing:
569 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
570 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
571 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
572 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
573 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
574 CPUID_EXT_RDRAND */
575
576 #ifdef TARGET_X86_64
577 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
578 #else
579 #define TCG_EXT2_X86_64_FEATURES 0
580 #endif
581
582 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
583 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
584 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
585 TCG_EXT2_X86_64_FEATURES)
586 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
587 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
588 #define TCG_SVM_FEATURES 0
589 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
590 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
591 /* missing:
592 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
593 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
594 CPUID_7_0_EBX_RDSEED */
595
596 static X86CPUDefinition builtin_x86_defs[] = {
597 {
598 .name = "qemu64",
599 .level = 4,
600 .vendor = CPUID_VENDOR_AMD,
601 .family = 6,
602 .model = 6,
603 .stepping = 3,
604 .features[FEAT_1_EDX] =
605 PPRO_FEATURES |
606 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
607 CPUID_PSE36,
608 .features[FEAT_1_ECX] =
609 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
610 .features[FEAT_8000_0001_EDX] =
611 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
612 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
613 .features[FEAT_8000_0001_ECX] =
614 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
615 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
616 .xlevel = 0x8000000A,
617 },
618 {
619 .name = "phenom",
620 .level = 5,
621 .vendor = CPUID_VENDOR_AMD,
622 .family = 16,
623 .model = 2,
624 .stepping = 3,
625 .features[FEAT_1_EDX] =
626 PPRO_FEATURES |
627 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
628 CPUID_PSE36 | CPUID_VME | CPUID_HT,
629 .features[FEAT_1_ECX] =
630 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
631 CPUID_EXT_POPCNT,
632 .features[FEAT_8000_0001_EDX] =
633 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
634 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
635 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
636 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
637 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
638 CPUID_EXT3_CR8LEG,
639 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
640 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
641 .features[FEAT_8000_0001_ECX] =
642 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
643 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
644 .features[FEAT_SVM] =
645 CPUID_SVM_NPT | CPUID_SVM_LBRV,
646 .xlevel = 0x8000001A,
647 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
648 },
649 {
650 .name = "core2duo",
651 .level = 10,
652 .vendor = CPUID_VENDOR_INTEL,
653 .family = 6,
654 .model = 15,
655 .stepping = 11,
656 .features[FEAT_1_EDX] =
657 PPRO_FEATURES |
658 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
659 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
660 CPUID_HT | CPUID_TM | CPUID_PBE,
661 .features[FEAT_1_ECX] =
662 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
663 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
664 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
665 .features[FEAT_8000_0001_EDX] =
666 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
667 .features[FEAT_8000_0001_ECX] =
668 CPUID_EXT3_LAHF_LM,
669 .xlevel = 0x80000008,
670 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
671 },
672 {
673 .name = "kvm64",
674 .level = 5,
675 .vendor = CPUID_VENDOR_INTEL,
676 .family = 15,
677 .model = 6,
678 .stepping = 1,
679 /* Missing: CPUID_VME, CPUID_HT */
680 .features[FEAT_1_EDX] =
681 PPRO_FEATURES |
682 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
683 CPUID_PSE36,
684 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
685 .features[FEAT_1_ECX] =
686 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
687 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
688 .features[FEAT_8000_0001_EDX] =
689 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
690 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
691 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
692 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
693 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
694 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
695 .features[FEAT_8000_0001_ECX] =
696 0,
697 .xlevel = 0x80000008,
698 .model_id = "Common KVM processor"
699 },
700 {
701 .name = "qemu32",
702 .level = 4,
703 .vendor = CPUID_VENDOR_INTEL,
704 .family = 6,
705 .model = 6,
706 .stepping = 3,
707 .features[FEAT_1_EDX] =
708 PPRO_FEATURES,
709 .features[FEAT_1_ECX] =
710 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
711 .xlevel = 0x80000004,
712 },
713 {
714 .name = "kvm32",
715 .level = 5,
716 .vendor = CPUID_VENDOR_INTEL,
717 .family = 15,
718 .model = 6,
719 .stepping = 1,
720 .features[FEAT_1_EDX] =
721 PPRO_FEATURES |
722 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
723 .features[FEAT_1_ECX] =
724 CPUID_EXT_SSE3,
725 .features[FEAT_8000_0001_EDX] =
726 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
727 .features[FEAT_8000_0001_ECX] =
728 0,
729 .xlevel = 0x80000008,
730 .model_id = "Common 32-bit KVM processor"
731 },
732 {
733 .name = "coreduo",
734 .level = 10,
735 .vendor = CPUID_VENDOR_INTEL,
736 .family = 6,
737 .model = 14,
738 .stepping = 8,
739 .features[FEAT_1_EDX] =
740 PPRO_FEATURES | CPUID_VME |
741 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
742 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
743 .features[FEAT_1_ECX] =
744 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
745 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
746 .features[FEAT_8000_0001_EDX] =
747 CPUID_EXT2_NX,
748 .xlevel = 0x80000008,
749 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
750 },
751 {
752 .name = "486",
753 .level = 1,
754 .vendor = CPUID_VENDOR_INTEL,
755 .family = 4,
756 .model = 8,
757 .stepping = 0,
758 .features[FEAT_1_EDX] =
759 I486_FEATURES,
760 .xlevel = 0,
761 },
762 {
763 .name = "pentium",
764 .level = 1,
765 .vendor = CPUID_VENDOR_INTEL,
766 .family = 5,
767 .model = 4,
768 .stepping = 3,
769 .features[FEAT_1_EDX] =
770 PENTIUM_FEATURES,
771 .xlevel = 0,
772 },
773 {
774 .name = "pentium2",
775 .level = 2,
776 .vendor = CPUID_VENDOR_INTEL,
777 .family = 6,
778 .model = 5,
779 .stepping = 2,
780 .features[FEAT_1_EDX] =
781 PENTIUM2_FEATURES,
782 .xlevel = 0,
783 },
784 {
785 .name = "pentium3",
786 .level = 2,
787 .vendor = CPUID_VENDOR_INTEL,
788 .family = 6,
789 .model = 7,
790 .stepping = 3,
791 .features[FEAT_1_EDX] =
792 PENTIUM3_FEATURES,
793 .xlevel = 0,
794 },
795 {
796 .name = "athlon",
797 .level = 2,
798 .vendor = CPUID_VENDOR_AMD,
799 .family = 6,
800 .model = 2,
801 .stepping = 3,
802 .features[FEAT_1_EDX] =
803 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
804 CPUID_MCA,
805 .features[FEAT_8000_0001_EDX] =
806 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
807 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
808 .xlevel = 0x80000008,
809 },
810 {
811 .name = "n270",
812 /* original is on level 10 */
813 .level = 5,
814 .vendor = CPUID_VENDOR_INTEL,
815 .family = 6,
816 .model = 28,
817 .stepping = 2,
818 .features[FEAT_1_EDX] =
819 PPRO_FEATURES |
820 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
821 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
822 /* Some CPUs got no CPUID_SEP */
823 .features[FEAT_1_ECX] =
824 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
825 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
826 CPUID_EXT_MOVBE,
827 .features[FEAT_8000_0001_EDX] =
828 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
829 CPUID_EXT2_NX,
830 .features[FEAT_8000_0001_ECX] =
831 CPUID_EXT3_LAHF_LM,
832 .xlevel = 0x8000000A,
833 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
834 },
835 {
836 .name = "Conroe",
837 .level = 4,
838 .vendor = CPUID_VENDOR_INTEL,
839 .family = 6,
840 .model = 15,
841 .stepping = 3,
842 .features[FEAT_1_EDX] =
843 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
844 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
845 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
846 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
847 CPUID_DE | CPUID_FP87,
848 .features[FEAT_1_ECX] =
849 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
850 .features[FEAT_8000_0001_EDX] =
851 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
852 .features[FEAT_8000_0001_ECX] =
853 CPUID_EXT3_LAHF_LM,
854 .xlevel = 0x8000000A,
855 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
856 },
857 {
858 .name = "Penryn",
859 .level = 4,
860 .vendor = CPUID_VENDOR_INTEL,
861 .family = 6,
862 .model = 23,
863 .stepping = 3,
864 .features[FEAT_1_EDX] =
865 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
866 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
867 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
868 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
869 CPUID_DE | CPUID_FP87,
870 .features[FEAT_1_ECX] =
871 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
872 CPUID_EXT_SSE3,
873 .features[FEAT_8000_0001_EDX] =
874 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
875 .features[FEAT_8000_0001_ECX] =
876 CPUID_EXT3_LAHF_LM,
877 .xlevel = 0x8000000A,
878 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
879 },
880 {
881 .name = "Nehalem",
882 .level = 4,
883 .vendor = CPUID_VENDOR_INTEL,
884 .family = 6,
885 .model = 26,
886 .stepping = 3,
887 .features[FEAT_1_EDX] =
888 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
889 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
890 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
891 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
892 CPUID_DE | CPUID_FP87,
893 .features[FEAT_1_ECX] =
894 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
895 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
896 .features[FEAT_8000_0001_EDX] =
897 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
898 .features[FEAT_8000_0001_ECX] =
899 CPUID_EXT3_LAHF_LM,
900 .xlevel = 0x8000000A,
901 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
902 },
903 {
904 .name = "Westmere",
905 .level = 11,
906 .vendor = CPUID_VENDOR_INTEL,
907 .family = 6,
908 .model = 44,
909 .stepping = 1,
910 .features[FEAT_1_EDX] =
911 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
912 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
913 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
914 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
915 CPUID_DE | CPUID_FP87,
916 .features[FEAT_1_ECX] =
917 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
918 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
919 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
920 .features[FEAT_8000_0001_EDX] =
921 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
922 .features[FEAT_8000_0001_ECX] =
923 CPUID_EXT3_LAHF_LM,
924 .xlevel = 0x8000000A,
925 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
926 },
927 {
928 .name = "SandyBridge",
929 .level = 0xd,
930 .vendor = CPUID_VENDOR_INTEL,
931 .family = 6,
932 .model = 42,
933 .stepping = 1,
934 .features[FEAT_1_EDX] =
935 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
936 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
937 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
938 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
939 CPUID_DE | CPUID_FP87,
940 .features[FEAT_1_ECX] =
941 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
942 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
943 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
944 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
945 CPUID_EXT_SSE3,
946 .features[FEAT_8000_0001_EDX] =
947 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
948 CPUID_EXT2_SYSCALL,
949 .features[FEAT_8000_0001_ECX] =
950 CPUID_EXT3_LAHF_LM,
951 .xlevel = 0x8000000A,
952 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
953 },
954 {
955 .name = "Haswell",
956 .level = 0xd,
957 .vendor = CPUID_VENDOR_INTEL,
958 .family = 6,
959 .model = 60,
960 .stepping = 1,
961 .features[FEAT_1_EDX] =
962 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
963 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
964 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
965 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
966 CPUID_DE | CPUID_FP87,
967 .features[FEAT_1_ECX] =
968 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
969 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
970 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
971 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
972 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
973 CPUID_EXT_PCID,
974 .features[FEAT_8000_0001_EDX] =
975 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
976 CPUID_EXT2_SYSCALL,
977 .features[FEAT_8000_0001_ECX] =
978 CPUID_EXT3_LAHF_LM,
979 .features[FEAT_7_0_EBX] =
980 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
981 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
982 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
983 CPUID_7_0_EBX_RTM,
984 .xlevel = 0x8000000A,
985 .model_id = "Intel Core Processor (Haswell)",
986 },
987 {
988 .name = "Opteron_G1",
989 .level = 5,
990 .vendor = CPUID_VENDOR_AMD,
991 .family = 15,
992 .model = 6,
993 .stepping = 1,
994 .features[FEAT_1_EDX] =
995 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
996 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
997 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
998 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
999 CPUID_DE | CPUID_FP87,
1000 .features[FEAT_1_ECX] =
1001 CPUID_EXT_SSE3,
1002 .features[FEAT_8000_0001_EDX] =
1003 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1004 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1005 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1006 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1007 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1008 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1009 .xlevel = 0x80000008,
1010 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1011 },
1012 {
1013 .name = "Opteron_G2",
1014 .level = 5,
1015 .vendor = CPUID_VENDOR_AMD,
1016 .family = 15,
1017 .model = 6,
1018 .stepping = 1,
1019 .features[FEAT_1_EDX] =
1020 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1021 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1022 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1023 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1024 CPUID_DE | CPUID_FP87,
1025 .features[FEAT_1_ECX] =
1026 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1027 .features[FEAT_8000_0001_EDX] =
1028 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1029 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1030 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1031 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1032 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1033 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1034 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1035 .features[FEAT_8000_0001_ECX] =
1036 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1037 .xlevel = 0x80000008,
1038 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1039 },
1040 {
1041 .name = "Opteron_G3",
1042 .level = 5,
1043 .vendor = CPUID_VENDOR_AMD,
1044 .family = 15,
1045 .model = 6,
1046 .stepping = 1,
1047 .features[FEAT_1_EDX] =
1048 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1049 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1050 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1051 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1052 CPUID_DE | CPUID_FP87,
1053 .features[FEAT_1_ECX] =
1054 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1055 CPUID_EXT_SSE3,
1056 .features[FEAT_8000_0001_EDX] =
1057 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1058 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1059 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1060 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1061 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1062 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1063 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1064 .features[FEAT_8000_0001_ECX] =
1065 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1066 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1067 .xlevel = 0x80000008,
1068 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1069 },
1070 {
1071 .name = "Opteron_G4",
1072 .level = 0xd,
1073 .vendor = CPUID_VENDOR_AMD,
1074 .family = 21,
1075 .model = 1,
1076 .stepping = 2,
1077 .features[FEAT_1_EDX] =
1078 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1079 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1080 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1081 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1082 CPUID_DE | CPUID_FP87,
1083 .features[FEAT_1_ECX] =
1084 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1085 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1086 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1087 CPUID_EXT_SSE3,
1088 .features[FEAT_8000_0001_EDX] =
1089 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1090 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1091 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1092 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1093 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1094 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1095 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1096 .features[FEAT_8000_0001_ECX] =
1097 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1098 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1099 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1100 CPUID_EXT3_LAHF_LM,
1101 .xlevel = 0x8000001A,
1102 .model_id = "AMD Opteron 62xx class CPU",
1103 },
1104 {
1105 .name = "Opteron_G5",
1106 .level = 0xd,
1107 .vendor = CPUID_VENDOR_AMD,
1108 .family = 21,
1109 .model = 2,
1110 .stepping = 0,
1111 .features[FEAT_1_EDX] =
1112 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1113 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1114 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1115 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1116 CPUID_DE | CPUID_FP87,
1117 .features[FEAT_1_ECX] =
1118 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1119 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1120 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1121 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1122 .features[FEAT_8000_0001_EDX] =
1123 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1124 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1125 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1126 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1127 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1128 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1129 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1130 .features[FEAT_8000_0001_ECX] =
1131 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1132 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1133 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1134 CPUID_EXT3_LAHF_LM,
1135 .xlevel = 0x8000001A,
1136 .model_id = "AMD Opteron 63xx class CPU",
1137 },
1138 };
1139
1140 /**
1141 * x86_cpu_compat_set_features:
1142 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1143 * @w: Identifies the feature word to be changed.
1144 * @feat_add: Feature bits to be added to feature word
1145 * @feat_remove: Feature bits to be removed from feature word
1146 *
1147 * Change CPU model feature bits for compatibility.
1148 *
1149 * This function may be used by machine-type compatibility functions
1150 * to enable or disable feature bits on specific CPU models.
1151 */
1152 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1153 uint32_t feat_add, uint32_t feat_remove)
1154 {
1155 X86CPUDefinition *def;
1156 int i;
1157 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1158 def = &builtin_x86_defs[i];
1159 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1160 def->features[w] |= feat_add;
1161 def->features[w] &= ~feat_remove;
1162 }
1163 }
1164 }
1165
1166 #ifdef CONFIG_KVM
1167
1168 static int cpu_x86_fill_model_id(char *str)
1169 {
1170 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1171 int i;
1172
1173 for (i = 0; i < 3; i++) {
1174 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1175 memcpy(str + i * 16 + 0, &eax, 4);
1176 memcpy(str + i * 16 + 4, &ebx, 4);
1177 memcpy(str + i * 16 + 8, &ecx, 4);
1178 memcpy(str + i * 16 + 12, &edx, 4);
1179 }
1180 return 0;
1181 }
1182
1183 static X86CPUDefinition host_cpudef;
1184
1185 /* class_init for the "host" CPU model
1186 *
1187 * This function may be called before KVM is initialized.
1188 */
1189 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1190 {
1191 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1192 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1193
1194 xcc->kvm_required = true;
1195
1196 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1197 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1198
1199 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1200 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1201 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1202 host_cpudef.stepping = eax & 0x0F;
1203
1204 cpu_x86_fill_model_id(host_cpudef.model_id);
1205
1206 xcc->cpu_def = &host_cpudef;
1207 host_cpudef.cache_info_passthrough = true;
1208
1209 /* level, xlevel, xlevel2, and the feature words are initialized on
1210 * instance_init, because they require KVM to be initialized.
1211 */
1212 }
1213
1214 static void host_x86_cpu_initfn(Object *obj)
1215 {
1216 X86CPU *cpu = X86_CPU(obj);
1217 CPUX86State *env = &cpu->env;
1218 KVMState *s = kvm_state;
1219 FeatureWord w;
1220
1221 assert(kvm_enabled());
1222
1223 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1224 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1225 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1226
1227 for (w = 0; w < FEATURE_WORDS; w++) {
1228 FeatureWordInfo *wi = &feature_word_info[w];
1229 env->features[w] =
1230 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1231 wi->cpuid_reg);
1232 }
1233 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1234 }
1235
1236 static const TypeInfo host_x86_cpu_type_info = {
1237 .name = X86_CPU_TYPE_NAME("host"),
1238 .parent = TYPE_X86_CPU,
1239 .instance_init = host_x86_cpu_initfn,
1240 .class_init = host_x86_cpu_class_init,
1241 };
1242
1243 #endif
1244
1245 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1246 {
1247 FeatureWordInfo *f = &feature_word_info[w];
1248 int i;
1249
1250 for (i = 0; i < 32; ++i) {
1251 if (1 << i & mask) {
1252 const char *reg = get_register_name_32(f->cpuid_reg);
1253 assert(reg);
1254 fprintf(stderr, "warning: host doesn't support requested feature: "
1255 "CPUID.%02XH:%s%s%s [bit %d]\n",
1256 f->cpuid_eax, reg,
1257 f->feat_names[i] ? "." : "",
1258 f->feat_names[i] ? f->feat_names[i] : "", i);
1259 }
1260 }
1261 }
1262
1263 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1264 const char *name, Error **errp)
1265 {
1266 X86CPU *cpu = X86_CPU(obj);
1267 CPUX86State *env = &cpu->env;
1268 int64_t value;
1269
1270 value = (env->cpuid_version >> 8) & 0xf;
1271 if (value == 0xf) {
1272 value += (env->cpuid_version >> 20) & 0xff;
1273 }
1274 visit_type_int(v, &value, name, errp);
1275 }
1276
1277 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1278 const char *name, Error **errp)
1279 {
1280 X86CPU *cpu = X86_CPU(obj);
1281 CPUX86State *env = &cpu->env;
1282 const int64_t min = 0;
1283 const int64_t max = 0xff + 0xf;
1284 Error *local_err = NULL;
1285 int64_t value;
1286
1287 visit_type_int(v, &value, name, &local_err);
1288 if (local_err) {
1289 error_propagate(errp, local_err);
1290 return;
1291 }
1292 if (value < min || value > max) {
1293 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1294 name ? name : "null", value, min, max);
1295 return;
1296 }
1297
1298 env->cpuid_version &= ~0xff00f00;
1299 if (value > 0x0f) {
1300 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1301 } else {
1302 env->cpuid_version |= value << 8;
1303 }
1304 }
1305
1306 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1307 const char *name, Error **errp)
1308 {
1309 X86CPU *cpu = X86_CPU(obj);
1310 CPUX86State *env = &cpu->env;
1311 int64_t value;
1312
1313 value = (env->cpuid_version >> 4) & 0xf;
1314 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1315 visit_type_int(v, &value, name, errp);
1316 }
1317
1318 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1319 const char *name, Error **errp)
1320 {
1321 X86CPU *cpu = X86_CPU(obj);
1322 CPUX86State *env = &cpu->env;
1323 const int64_t min = 0;
1324 const int64_t max = 0xff;
1325 Error *local_err = NULL;
1326 int64_t value;
1327
1328 visit_type_int(v, &value, name, &local_err);
1329 if (local_err) {
1330 error_propagate(errp, local_err);
1331 return;
1332 }
1333 if (value < min || value > max) {
1334 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1335 name ? name : "null", value, min, max);
1336 return;
1337 }
1338
1339 env->cpuid_version &= ~0xf00f0;
1340 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1341 }
1342
1343 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1344 void *opaque, const char *name,
1345 Error **errp)
1346 {
1347 X86CPU *cpu = X86_CPU(obj);
1348 CPUX86State *env = &cpu->env;
1349 int64_t value;
1350
1351 value = env->cpuid_version & 0xf;
1352 visit_type_int(v, &value, name, errp);
1353 }
1354
1355 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1356 void *opaque, const char *name,
1357 Error **errp)
1358 {
1359 X86CPU *cpu = X86_CPU(obj);
1360 CPUX86State *env = &cpu->env;
1361 const int64_t min = 0;
1362 const int64_t max = 0xf;
1363 Error *local_err = NULL;
1364 int64_t value;
1365
1366 visit_type_int(v, &value, name, &local_err);
1367 if (local_err) {
1368 error_propagate(errp, local_err);
1369 return;
1370 }
1371 if (value < min || value > max) {
1372 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1373 name ? name : "null", value, min, max);
1374 return;
1375 }
1376
1377 env->cpuid_version &= ~0xf;
1378 env->cpuid_version |= value & 0xf;
1379 }
1380
1381 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1382 const char *name, Error **errp)
1383 {
1384 X86CPU *cpu = X86_CPU(obj);
1385
1386 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1387 }
1388
1389 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1390 const char *name, Error **errp)
1391 {
1392 X86CPU *cpu = X86_CPU(obj);
1393
1394 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1395 }
1396
1397 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1398 const char *name, Error **errp)
1399 {
1400 X86CPU *cpu = X86_CPU(obj);
1401
1402 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1403 }
1404
1405 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1406 const char *name, Error **errp)
1407 {
1408 X86CPU *cpu = X86_CPU(obj);
1409
1410 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1411 }
1412
1413 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1414 {
1415 X86CPU *cpu = X86_CPU(obj);
1416 CPUX86State *env = &cpu->env;
1417 char *value;
1418
1419 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1420 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1421 env->cpuid_vendor3);
1422 return value;
1423 }
1424
1425 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1426 Error **errp)
1427 {
1428 X86CPU *cpu = X86_CPU(obj);
1429 CPUX86State *env = &cpu->env;
1430 int i;
1431
1432 if (strlen(value) != CPUID_VENDOR_SZ) {
1433 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1434 "vendor", value);
1435 return;
1436 }
1437
1438 env->cpuid_vendor1 = 0;
1439 env->cpuid_vendor2 = 0;
1440 env->cpuid_vendor3 = 0;
1441 for (i = 0; i < 4; i++) {
1442 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1443 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1444 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1445 }
1446 }
1447
1448 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1449 {
1450 X86CPU *cpu = X86_CPU(obj);
1451 CPUX86State *env = &cpu->env;
1452 char *value;
1453 int i;
1454
1455 value = g_malloc(48 + 1);
1456 for (i = 0; i < 48; i++) {
1457 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1458 }
1459 value[48] = '\0';
1460 return value;
1461 }
1462
1463 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1464 Error **errp)
1465 {
1466 X86CPU *cpu = X86_CPU(obj);
1467 CPUX86State *env = &cpu->env;
1468 int c, len, i;
1469
1470 if (model_id == NULL) {
1471 model_id = "";
1472 }
1473 len = strlen(model_id);
1474 memset(env->cpuid_model, 0, 48);
1475 for (i = 0; i < 48; i++) {
1476 if (i >= len) {
1477 c = '\0';
1478 } else {
1479 c = (uint8_t)model_id[i];
1480 }
1481 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1482 }
1483 }
1484
1485 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1486 const char *name, Error **errp)
1487 {
1488 X86CPU *cpu = X86_CPU(obj);
1489 int64_t value;
1490
1491 value = cpu->env.tsc_khz * 1000;
1492 visit_type_int(v, &value, name, errp);
1493 }
1494
1495 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1496 const char *name, Error **errp)
1497 {
1498 X86CPU *cpu = X86_CPU(obj);
1499 const int64_t min = 0;
1500 const int64_t max = INT64_MAX;
1501 Error *local_err = NULL;
1502 int64_t value;
1503
1504 visit_type_int(v, &value, name, &local_err);
1505 if (local_err) {
1506 error_propagate(errp, local_err);
1507 return;
1508 }
1509 if (value < min || value > max) {
1510 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1511 name ? name : "null", value, min, max);
1512 return;
1513 }
1514
1515 cpu->env.tsc_khz = value / 1000;
1516 }
1517
1518 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1519 const char *name, Error **errp)
1520 {
1521 X86CPU *cpu = X86_CPU(obj);
1522 int64_t value = cpu->env.cpuid_apic_id;
1523
1524 visit_type_int(v, &value, name, errp);
1525 }
1526
1527 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1528 const char *name, Error **errp)
1529 {
1530 X86CPU *cpu = X86_CPU(obj);
1531 DeviceState *dev = DEVICE(obj);
1532 const int64_t min = 0;
1533 const int64_t max = UINT32_MAX;
1534 Error *error = NULL;
1535 int64_t value;
1536
1537 if (dev->realized) {
1538 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1539 "it was realized", name, object_get_typename(obj));
1540 return;
1541 }
1542
1543 visit_type_int(v, &value, name, &error);
1544 if (error) {
1545 error_propagate(errp, error);
1546 return;
1547 }
1548 if (value < min || value > max) {
1549 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1550 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1551 object_get_typename(obj), name, value, min, max);
1552 return;
1553 }
1554
1555 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1556 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1557 return;
1558 }
1559 cpu->env.cpuid_apic_id = value;
1560 }
1561
1562 /* Generic getter for "feature-words" and "filtered-features" properties */
1563 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1564 const char *name, Error **errp)
1565 {
1566 uint32_t *array = (uint32_t *)opaque;
1567 FeatureWord w;
1568 Error *err = NULL;
1569 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1570 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1571 X86CPUFeatureWordInfoList *list = NULL;
1572
1573 for (w = 0; w < FEATURE_WORDS; w++) {
1574 FeatureWordInfo *wi = &feature_word_info[w];
1575 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1576 qwi->cpuid_input_eax = wi->cpuid_eax;
1577 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1578 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1579 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1580 qwi->features = array[w];
1581
1582 /* List will be in reverse order, but order shouldn't matter */
1583 list_entries[w].next = list;
1584 list_entries[w].value = &word_infos[w];
1585 list = &list_entries[w];
1586 }
1587
1588 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1589 error_propagate(errp, err);
1590 }
1591
1592 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1593 const char *name, Error **errp)
1594 {
1595 X86CPU *cpu = X86_CPU(obj);
1596 int64_t value = cpu->hyperv_spinlock_attempts;
1597
1598 visit_type_int(v, &value, name, errp);
1599 }
1600
1601 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1602 const char *name, Error **errp)
1603 {
1604 const int64_t min = 0xFFF;
1605 const int64_t max = UINT_MAX;
1606 X86CPU *cpu = X86_CPU(obj);
1607 Error *err = NULL;
1608 int64_t value;
1609
1610 visit_type_int(v, &value, name, &err);
1611 if (err) {
1612 error_propagate(errp, err);
1613 return;
1614 }
1615
1616 if (value < min || value > max) {
1617 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1618 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1619 object_get_typename(obj), name ? name : "null",
1620 value, min, max);
1621 return;
1622 }
1623 cpu->hyperv_spinlock_attempts = value;
1624 }
1625
1626 static PropertyInfo qdev_prop_spinlocks = {
1627 .name = "int",
1628 .get = x86_get_hv_spinlocks,
1629 .set = x86_set_hv_spinlocks,
1630 };
1631
1632 /* Convert all '_' in a feature string option name to '-', to make feature
1633 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1634 */
1635 static inline void feat2prop(char *s)
1636 {
1637 while ((s = strchr(s, '_'))) {
1638 *s = '-';
1639 }
1640 }
1641
1642 /* Parse "+feature,-feature,feature=foo" CPU feature string
1643 */
1644 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1645 Error **errp)
1646 {
1647 X86CPU *cpu = X86_CPU(cs);
1648 char *featurestr; /* Single 'key=value" string being parsed */
1649 /* Features to be added */
1650 FeatureWordArray plus_features = { 0 };
1651 /* Features to be removed */
1652 FeatureWordArray minus_features = { 0 };
1653 uint32_t numvalue;
1654 CPUX86State *env = &cpu->env;
1655 Error *local_err = NULL;
1656
1657 featurestr = features ? strtok(features, ",") : NULL;
1658
1659 while (featurestr) {
1660 char *val;
1661 if (featurestr[0] == '+') {
1662 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1663 } else if (featurestr[0] == '-') {
1664 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1665 } else if ((val = strchr(featurestr, '='))) {
1666 *val = 0; val++;
1667 feat2prop(featurestr);
1668 if (!strcmp(featurestr, "xlevel")) {
1669 char *err;
1670 char num[32];
1671
1672 numvalue = strtoul(val, &err, 0);
1673 if (!*val || *err) {
1674 error_setg(errp, "bad numerical value %s", val);
1675 return;
1676 }
1677 if (numvalue < 0x80000000) {
1678 error_report("xlevel value shall always be >= 0x80000000"
1679 ", fixup will be removed in future versions");
1680 numvalue += 0x80000000;
1681 }
1682 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1683 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1684 } else if (!strcmp(featurestr, "tsc-freq")) {
1685 int64_t tsc_freq;
1686 char *err;
1687 char num[32];
1688
1689 tsc_freq = strtosz_suffix_unit(val, &err,
1690 STRTOSZ_DEFSUFFIX_B, 1000);
1691 if (tsc_freq < 0 || *err) {
1692 error_setg(errp, "bad numerical value %s", val);
1693 return;
1694 }
1695 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1696 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1697 &local_err);
1698 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1699 char *err;
1700 const int min = 0xFFF;
1701 char num[32];
1702 numvalue = strtoul(val, &err, 0);
1703 if (!*val || *err) {
1704 error_setg(errp, "bad numerical value %s", val);
1705 return;
1706 }
1707 if (numvalue < min) {
1708 error_report("hv-spinlocks value shall always be >= 0x%x"
1709 ", fixup will be removed in future versions",
1710 min);
1711 numvalue = min;
1712 }
1713 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1714 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1715 } else {
1716 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1717 }
1718 } else {
1719 feat2prop(featurestr);
1720 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1721 }
1722 if (local_err) {
1723 error_propagate(errp, local_err);
1724 return;
1725 }
1726 featurestr = strtok(NULL, ",");
1727 }
1728 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1729 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1730 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1731 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1732 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1733 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1734 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1735 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1736 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1737 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1738 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1739 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1740 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1741 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1742 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1743 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1744 }
1745
1746 /* generate a composite string into buf of all cpuid names in featureset
1747 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1748 * if flags, suppress names undefined in featureset.
1749 */
1750 static void listflags(char *buf, int bufsize, uint32_t fbits,
1751 const char **featureset, uint32_t flags)
1752 {
1753 const char **p = &featureset[31];
1754 char *q, *b, bit;
1755 int nc;
1756
1757 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1758 *buf = '\0';
1759 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1760 if (fbits & 1 << bit && (*p || !flags)) {
1761 if (*p)
1762 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1763 else
1764 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1765 if (bufsize <= nc) {
1766 if (b) {
1767 memcpy(b, "...", sizeof("..."));
1768 }
1769 return;
1770 }
1771 q += nc;
1772 bufsize -= nc;
1773 }
1774 }
1775
1776 /* generate CPU information. */
1777 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1778 {
1779 X86CPUDefinition *def;
1780 char buf[256];
1781 int i;
1782
1783 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1784 def = &builtin_x86_defs[i];
1785 snprintf(buf, sizeof(buf), "%s", def->name);
1786 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1787 }
1788 #ifdef CONFIG_KVM
1789 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1790 "KVM processor with all supported host features "
1791 "(only available in KVM mode)");
1792 #endif
1793
1794 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1795 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1796 FeatureWordInfo *fw = &feature_word_info[i];
1797
1798 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1799 (*cpu_fprintf)(f, " %s\n", buf);
1800 }
1801 }
1802
1803 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1804 {
1805 CpuDefinitionInfoList *cpu_list = NULL;
1806 X86CPUDefinition *def;
1807 int i;
1808
1809 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1810 CpuDefinitionInfoList *entry;
1811 CpuDefinitionInfo *info;
1812
1813 def = &builtin_x86_defs[i];
1814 info = g_malloc0(sizeof(*info));
1815 info->name = g_strdup(def->name);
1816
1817 entry = g_malloc0(sizeof(*entry));
1818 entry->value = info;
1819 entry->next = cpu_list;
1820 cpu_list = entry;
1821 }
1822
1823 return cpu_list;
1824 }
1825
1826 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w)
1827 {
1828 FeatureWordInfo *wi = &feature_word_info[w];
1829
1830 assert(kvm_enabled());
1831 return kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1832 wi->cpuid_ecx,
1833 wi->cpuid_reg);
1834 }
1835
1836 /*
1837 * Filters CPU feature words based on host availability of each feature.
1838 *
1839 * This function may be called only if KVM is enabled.
1840 *
1841 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1842 */
1843 static int x86_cpu_filter_features(X86CPU *cpu)
1844 {
1845 CPUX86State *env = &cpu->env;
1846 FeatureWord w;
1847 int rv = 0;
1848
1849 for (w = 0; w < FEATURE_WORDS; w++) {
1850 uint32_t host_feat = x86_cpu_get_supported_feature_word(w);
1851 uint32_t requested_features = env->features[w];
1852 env->features[w] &= host_feat;
1853 cpu->filtered_features[w] = requested_features & ~env->features[w];
1854 if (cpu->filtered_features[w]) {
1855 if (cpu->check_cpuid || cpu->enforce_cpuid) {
1856 report_unavailable_features(w, cpu->filtered_features[w]);
1857 }
1858 rv = 1;
1859 }
1860 }
1861
1862 return rv;
1863 }
1864
1865 /* Load data from X86CPUDefinition
1866 */
1867 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1868 {
1869 CPUX86State *env = &cpu->env;
1870 const char *vendor;
1871 char host_vendor[CPUID_VENDOR_SZ + 1];
1872
1873 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1874 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1875 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1876 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1877 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1878 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1879 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1880 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1881 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1882 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1883 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1884 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1885 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1886 env->cpuid_xlevel2 = def->xlevel2;
1887 cpu->cache_info_passthrough = def->cache_info_passthrough;
1888
1889 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1890
1891 /* Special cases not set in the X86CPUDefinition structs: */
1892 if (kvm_enabled()) {
1893 FeatureWord w;
1894 for (w = 0; w < FEATURE_WORDS; w++) {
1895 env->features[w] |= kvm_default_features[w];
1896 env->features[w] &= ~kvm_default_unset_features[w];
1897 }
1898 }
1899
1900 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1901
1902 /* sysenter isn't supported in compatibility mode on AMD,
1903 * syscall isn't supported in compatibility mode on Intel.
1904 * Normally we advertise the actual CPU vendor, but you can
1905 * override this using the 'vendor' property if you want to use
1906 * KVM's sysenter/syscall emulation in compatibility mode and
1907 * when doing cross vendor migration
1908 */
1909 vendor = def->vendor;
1910 if (kvm_enabled()) {
1911 uint32_t ebx = 0, ecx = 0, edx = 0;
1912 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1913 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1914 vendor = host_vendor;
1915 }
1916
1917 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1918
1919 }
1920
1921 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1922 Error **errp)
1923 {
1924 X86CPU *cpu = NULL;
1925 X86CPUClass *xcc;
1926 ObjectClass *oc;
1927 gchar **model_pieces;
1928 char *name, *features;
1929 Error *error = NULL;
1930
1931 model_pieces = g_strsplit(cpu_model, ",", 2);
1932 if (!model_pieces[0]) {
1933 error_setg(&error, "Invalid/empty CPU model name");
1934 goto out;
1935 }
1936 name = model_pieces[0];
1937 features = model_pieces[1];
1938
1939 oc = x86_cpu_class_by_name(name);
1940 if (oc == NULL) {
1941 error_setg(&error, "Unable to find CPU definition: %s", name);
1942 goto out;
1943 }
1944 xcc = X86_CPU_CLASS(oc);
1945
1946 if (xcc->kvm_required && !kvm_enabled()) {
1947 error_setg(&error, "CPU model '%s' requires KVM", name);
1948 goto out;
1949 }
1950
1951 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1952
1953 #ifndef CONFIG_USER_ONLY
1954 if (icc_bridge == NULL) {
1955 error_setg(&error, "Invalid icc-bridge value");
1956 goto out;
1957 }
1958 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1959 object_unref(OBJECT(cpu));
1960 #endif
1961
1962 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
1963 if (error) {
1964 goto out;
1965 }
1966
1967 out:
1968 if (error != NULL) {
1969 error_propagate(errp, error);
1970 if (cpu) {
1971 object_unref(OBJECT(cpu));
1972 cpu = NULL;
1973 }
1974 }
1975 g_strfreev(model_pieces);
1976 return cpu;
1977 }
1978
1979 X86CPU *cpu_x86_init(const char *cpu_model)
1980 {
1981 Error *error = NULL;
1982 X86CPU *cpu;
1983
1984 cpu = cpu_x86_create(cpu_model, NULL, &error);
1985 if (error) {
1986 goto out;
1987 }
1988
1989 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1990
1991 out:
1992 if (error) {
1993 error_report("%s", error_get_pretty(error));
1994 error_free(error);
1995 if (cpu != NULL) {
1996 object_unref(OBJECT(cpu));
1997 cpu = NULL;
1998 }
1999 }
2000 return cpu;
2001 }
2002
2003 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2004 {
2005 X86CPUDefinition *cpudef = data;
2006 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2007
2008 xcc->cpu_def = cpudef;
2009 }
2010
2011 static void x86_register_cpudef_type(X86CPUDefinition *def)
2012 {
2013 char *typename = x86_cpu_type_name(def->name);
2014 TypeInfo ti = {
2015 .name = typename,
2016 .parent = TYPE_X86_CPU,
2017 .class_init = x86_cpu_cpudef_class_init,
2018 .class_data = def,
2019 };
2020
2021 type_register(&ti);
2022 g_free(typename);
2023 }
2024
2025 #if !defined(CONFIG_USER_ONLY)
2026
2027 void cpu_clear_apic_feature(CPUX86State *env)
2028 {
2029 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2030 }
2031
2032 #endif /* !CONFIG_USER_ONLY */
2033
2034 /* Initialize list of CPU models, filling some non-static fields if necessary
2035 */
2036 void x86_cpudef_setup(void)
2037 {
2038 int i, j;
2039 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2040
2041 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2042 X86CPUDefinition *def = &builtin_x86_defs[i];
2043
2044 /* Look for specific "cpudef" models that */
2045 /* have the QEMU version in .model_id */
2046 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2047 if (strcmp(model_with_versions[j], def->name) == 0) {
2048 pstrcpy(def->model_id, sizeof(def->model_id),
2049 "QEMU Virtual CPU version ");
2050 pstrcat(def->model_id, sizeof(def->model_id),
2051 qemu_get_version());
2052 break;
2053 }
2054 }
2055 }
2056 }
2057
2058 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2059 uint32_t *ecx, uint32_t *edx)
2060 {
2061 *ebx = env->cpuid_vendor1;
2062 *edx = env->cpuid_vendor2;
2063 *ecx = env->cpuid_vendor3;
2064 }
2065
2066 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2067 uint32_t *eax, uint32_t *ebx,
2068 uint32_t *ecx, uint32_t *edx)
2069 {
2070 X86CPU *cpu = x86_env_get_cpu(env);
2071 CPUState *cs = CPU(cpu);
2072
2073 /* test if maximum index reached */
2074 if (index & 0x80000000) {
2075 if (index > env->cpuid_xlevel) {
2076 if (env->cpuid_xlevel2 > 0) {
2077 /* Handle the Centaur's CPUID instruction. */
2078 if (index > env->cpuid_xlevel2) {
2079 index = env->cpuid_xlevel2;
2080 } else if (index < 0xC0000000) {
2081 index = env->cpuid_xlevel;
2082 }
2083 } else {
2084 /* Intel documentation states that invalid EAX input will
2085 * return the same information as EAX=cpuid_level
2086 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2087 */
2088 index = env->cpuid_level;
2089 }
2090 }
2091 } else {
2092 if (index > env->cpuid_level)
2093 index = env->cpuid_level;
2094 }
2095
2096 switch(index) {
2097 case 0:
2098 *eax = env->cpuid_level;
2099 get_cpuid_vendor(env, ebx, ecx, edx);
2100 break;
2101 case 1:
2102 *eax = env->cpuid_version;
2103 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2104 *ecx = env->features[FEAT_1_ECX];
2105 *edx = env->features[FEAT_1_EDX];
2106 if (cs->nr_cores * cs->nr_threads > 1) {
2107 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2108 *edx |= 1 << 28; /* HTT bit */
2109 }
2110 break;
2111 case 2:
2112 /* cache info: needed for Pentium Pro compatibility */
2113 if (cpu->cache_info_passthrough) {
2114 host_cpuid(index, 0, eax, ebx, ecx, edx);
2115 break;
2116 }
2117 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2118 *ebx = 0;
2119 *ecx = 0;
2120 *edx = (L1D_DESCRIPTOR << 16) | \
2121 (L1I_DESCRIPTOR << 8) | \
2122 (L2_DESCRIPTOR);
2123 break;
2124 case 4:
2125 /* cache info: needed for Core compatibility */
2126 if (cpu->cache_info_passthrough) {
2127 host_cpuid(index, count, eax, ebx, ecx, edx);
2128 *eax &= ~0xFC000000;
2129 } else {
2130 *eax = 0;
2131 switch (count) {
2132 case 0: /* L1 dcache info */
2133 *eax |= CPUID_4_TYPE_DCACHE | \
2134 CPUID_4_LEVEL(1) | \
2135 CPUID_4_SELF_INIT_LEVEL;
2136 *ebx = (L1D_LINE_SIZE - 1) | \
2137 ((L1D_PARTITIONS - 1) << 12) | \
2138 ((L1D_ASSOCIATIVITY - 1) << 22);
2139 *ecx = L1D_SETS - 1;
2140 *edx = CPUID_4_NO_INVD_SHARING;
2141 break;
2142 case 1: /* L1 icache info */
2143 *eax |= CPUID_4_TYPE_ICACHE | \
2144 CPUID_4_LEVEL(1) | \
2145 CPUID_4_SELF_INIT_LEVEL;
2146 *ebx = (L1I_LINE_SIZE - 1) | \
2147 ((L1I_PARTITIONS - 1) << 12) | \
2148 ((L1I_ASSOCIATIVITY - 1) << 22);
2149 *ecx = L1I_SETS - 1;
2150 *edx = CPUID_4_NO_INVD_SHARING;
2151 break;
2152 case 2: /* L2 cache info */
2153 *eax |= CPUID_4_TYPE_UNIFIED | \
2154 CPUID_4_LEVEL(2) | \
2155 CPUID_4_SELF_INIT_LEVEL;
2156 if (cs->nr_threads > 1) {
2157 *eax |= (cs->nr_threads - 1) << 14;
2158 }
2159 *ebx = (L2_LINE_SIZE - 1) | \
2160 ((L2_PARTITIONS - 1) << 12) | \
2161 ((L2_ASSOCIATIVITY - 1) << 22);
2162 *ecx = L2_SETS - 1;
2163 *edx = CPUID_4_NO_INVD_SHARING;
2164 break;
2165 default: /* end of info */
2166 *eax = 0;
2167 *ebx = 0;
2168 *ecx = 0;
2169 *edx = 0;
2170 break;
2171 }
2172 }
2173
2174 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2175 if ((*eax & 31) && cs->nr_cores > 1) {
2176 *eax |= (cs->nr_cores - 1) << 26;
2177 }
2178 break;
2179 case 5:
2180 /* mwait info: needed for Core compatibility */
2181 *eax = 0; /* Smallest monitor-line size in bytes */
2182 *ebx = 0; /* Largest monitor-line size in bytes */
2183 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2184 *edx = 0;
2185 break;
2186 case 6:
2187 /* Thermal and Power Leaf */
2188 *eax = 0;
2189 *ebx = 0;
2190 *ecx = 0;
2191 *edx = 0;
2192 break;
2193 case 7:
2194 /* Structured Extended Feature Flags Enumeration Leaf */
2195 if (count == 0) {
2196 *eax = 0; /* Maximum ECX value for sub-leaves */
2197 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2198 *ecx = 0; /* Reserved */
2199 *edx = 0; /* Reserved */
2200 } else {
2201 *eax = 0;
2202 *ebx = 0;
2203 *ecx = 0;
2204 *edx = 0;
2205 }
2206 break;
2207 case 9:
2208 /* Direct Cache Access Information Leaf */
2209 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2210 *ebx = 0;
2211 *ecx = 0;
2212 *edx = 0;
2213 break;
2214 case 0xA:
2215 /* Architectural Performance Monitoring Leaf */
2216 if (kvm_enabled() && cpu->enable_pmu) {
2217 KVMState *s = cs->kvm_state;
2218
2219 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2220 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2221 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2222 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2223 } else {
2224 *eax = 0;
2225 *ebx = 0;
2226 *ecx = 0;
2227 *edx = 0;
2228 }
2229 break;
2230 case 0xD: {
2231 KVMState *s = cs->kvm_state;
2232 uint64_t kvm_mask;
2233 int i;
2234
2235 /* Processor Extended State */
2236 *eax = 0;
2237 *ebx = 0;
2238 *ecx = 0;
2239 *edx = 0;
2240 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2241 break;
2242 }
2243 kvm_mask =
2244 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2245 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2246
2247 if (count == 0) {
2248 *ecx = 0x240;
2249 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2250 const ExtSaveArea *esa = &ext_save_areas[i];
2251 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2252 (kvm_mask & (1 << i)) != 0) {
2253 if (i < 32) {
2254 *eax |= 1 << i;
2255 } else {
2256 *edx |= 1 << (i - 32);
2257 }
2258 *ecx = MAX(*ecx, esa->offset + esa->size);
2259 }
2260 }
2261 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2262 *ebx = *ecx;
2263 } else if (count == 1) {
2264 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2265 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2266 const ExtSaveArea *esa = &ext_save_areas[count];
2267 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2268 (kvm_mask & (1 << count)) != 0) {
2269 *eax = esa->size;
2270 *ebx = esa->offset;
2271 }
2272 }
2273 break;
2274 }
2275 case 0x80000000:
2276 *eax = env->cpuid_xlevel;
2277 *ebx = env->cpuid_vendor1;
2278 *edx = env->cpuid_vendor2;
2279 *ecx = env->cpuid_vendor3;
2280 break;
2281 case 0x80000001:
2282 *eax = env->cpuid_version;
2283 *ebx = 0;
2284 *ecx = env->features[FEAT_8000_0001_ECX];
2285 *edx = env->features[FEAT_8000_0001_EDX];
2286
2287 /* The Linux kernel checks for the CMPLegacy bit and
2288 * discards multiple thread information if it is set.
2289 * So dont set it here for Intel to make Linux guests happy.
2290 */
2291 if (cs->nr_cores * cs->nr_threads > 1) {
2292 uint32_t tebx, tecx, tedx;
2293 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2294 if (tebx != CPUID_VENDOR_INTEL_1 ||
2295 tedx != CPUID_VENDOR_INTEL_2 ||
2296 tecx != CPUID_VENDOR_INTEL_3) {
2297 *ecx |= 1 << 1; /* CmpLegacy bit */
2298 }
2299 }
2300 break;
2301 case 0x80000002:
2302 case 0x80000003:
2303 case 0x80000004:
2304 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2305 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2306 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2307 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2308 break;
2309 case 0x80000005:
2310 /* cache info (L1 cache) */
2311 if (cpu->cache_info_passthrough) {
2312 host_cpuid(index, 0, eax, ebx, ecx, edx);
2313 break;
2314 }
2315 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2316 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2317 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2318 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2319 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2320 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2321 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2322 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2323 break;
2324 case 0x80000006:
2325 /* cache info (L2 cache) */
2326 if (cpu->cache_info_passthrough) {
2327 host_cpuid(index, 0, eax, ebx, ecx, edx);
2328 break;
2329 }
2330 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2331 (L2_DTLB_2M_ENTRIES << 16) | \
2332 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2333 (L2_ITLB_2M_ENTRIES);
2334 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2335 (L2_DTLB_4K_ENTRIES << 16) | \
2336 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2337 (L2_ITLB_4K_ENTRIES);
2338 *ecx = (L2_SIZE_KB_AMD << 16) | \
2339 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2340 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2341 *edx = ((L3_SIZE_KB/512) << 18) | \
2342 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2343 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2344 break;
2345 case 0x80000008:
2346 /* virtual & phys address size in low 2 bytes. */
2347 /* XXX: This value must match the one used in the MMU code. */
2348 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2349 /* 64 bit processor */
2350 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2351 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2352 } else {
2353 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2354 *eax = 0x00000024; /* 36 bits physical */
2355 } else {
2356 *eax = 0x00000020; /* 32 bits physical */
2357 }
2358 }
2359 *ebx = 0;
2360 *ecx = 0;
2361 *edx = 0;
2362 if (cs->nr_cores * cs->nr_threads > 1) {
2363 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2364 }
2365 break;
2366 case 0x8000000A:
2367 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2368 *eax = 0x00000001; /* SVM Revision */
2369 *ebx = 0x00000010; /* nr of ASIDs */
2370 *ecx = 0;
2371 *edx = env->features[FEAT_SVM]; /* optional features */
2372 } else {
2373 *eax = 0;
2374 *ebx = 0;
2375 *ecx = 0;
2376 *edx = 0;
2377 }
2378 break;
2379 case 0xC0000000:
2380 *eax = env->cpuid_xlevel2;
2381 *ebx = 0;
2382 *ecx = 0;
2383 *edx = 0;
2384 break;
2385 case 0xC0000001:
2386 /* Support for VIA CPU's CPUID instruction */
2387 *eax = env->cpuid_version;
2388 *ebx = 0;
2389 *ecx = 0;
2390 *edx = env->features[FEAT_C000_0001_EDX];
2391 break;
2392 case 0xC0000002:
2393 case 0xC0000003:
2394 case 0xC0000004:
2395 /* Reserved for the future, and now filled with zero */
2396 *eax = 0;
2397 *ebx = 0;
2398 *ecx = 0;
2399 *edx = 0;
2400 break;
2401 default:
2402 /* reserved values: zero */
2403 *eax = 0;
2404 *ebx = 0;
2405 *ecx = 0;
2406 *edx = 0;
2407 break;
2408 }
2409 }
2410
2411 /* CPUClass::reset() */
2412 static void x86_cpu_reset(CPUState *s)
2413 {
2414 X86CPU *cpu = X86_CPU(s);
2415 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2416 CPUX86State *env = &cpu->env;
2417 int i;
2418
2419 xcc->parent_reset(s);
2420
2421 memset(env, 0, offsetof(CPUX86State, cpuid_level));
2422
2423 tlb_flush(s, 1);
2424
2425 env->old_exception = -1;
2426
2427 /* init to reset state */
2428
2429 #ifdef CONFIG_SOFTMMU
2430 env->hflags |= HF_SOFTMMU_MASK;
2431 #endif
2432 env->hflags2 |= HF2_GIF_MASK;
2433
2434 cpu_x86_update_cr0(env, 0x60000010);
2435 env->a20_mask = ~0x0;
2436 env->smbase = 0x30000;
2437
2438 env->idt.limit = 0xffff;
2439 env->gdt.limit = 0xffff;
2440 env->ldt.limit = 0xffff;
2441 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2442 env->tr.limit = 0xffff;
2443 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2444
2445 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2446 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2447 DESC_R_MASK | DESC_A_MASK);
2448 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2449 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2450 DESC_A_MASK);
2451 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2452 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2453 DESC_A_MASK);
2454 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2455 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2456 DESC_A_MASK);
2457 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2458 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2459 DESC_A_MASK);
2460 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2461 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2462 DESC_A_MASK);
2463
2464 env->eip = 0xfff0;
2465 env->regs[R_EDX] = env->cpuid_version;
2466
2467 env->eflags = 0x2;
2468
2469 /* FPU init */
2470 for (i = 0; i < 8; i++) {
2471 env->fptags[i] = 1;
2472 }
2473 env->fpuc = 0x37f;
2474
2475 env->mxcsr = 0x1f80;
2476 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2477
2478 env->pat = 0x0007040600070406ULL;
2479 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2480
2481 memset(env->dr, 0, sizeof(env->dr));
2482 env->dr[6] = DR6_FIXED_1;
2483 env->dr[7] = DR7_FIXED_1;
2484 cpu_breakpoint_remove_all(s, BP_CPU);
2485 cpu_watchpoint_remove_all(s, BP_CPU);
2486
2487 env->xcr0 = 1;
2488
2489 #if !defined(CONFIG_USER_ONLY)
2490 /* We hard-wire the BSP to the first CPU. */
2491 if (s->cpu_index == 0) {
2492 apic_designate_bsp(cpu->apic_state);
2493 }
2494
2495 s->halted = !cpu_is_bsp(cpu);
2496
2497 if (kvm_enabled()) {
2498 kvm_arch_reset_vcpu(cpu);
2499 }
2500 #endif
2501 }
2502
2503 #ifndef CONFIG_USER_ONLY
2504 bool cpu_is_bsp(X86CPU *cpu)
2505 {
2506 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2507 }
2508
2509 /* TODO: remove me, when reset over QOM tree is implemented */
2510 static void x86_cpu_machine_reset_cb(void *opaque)
2511 {
2512 X86CPU *cpu = opaque;
2513 cpu_reset(CPU(cpu));
2514 }
2515 #endif
2516
2517 static void mce_init(X86CPU *cpu)
2518 {
2519 CPUX86State *cenv = &cpu->env;
2520 unsigned int bank;
2521
2522 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2523 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2524 (CPUID_MCE | CPUID_MCA)) {
2525 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2526 cenv->mcg_ctl = ~(uint64_t)0;
2527 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2528 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2529 }
2530 }
2531 }
2532
2533 #ifndef CONFIG_USER_ONLY
2534 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2535 {
2536 CPUX86State *env = &cpu->env;
2537 DeviceState *dev = DEVICE(cpu);
2538 APICCommonState *apic;
2539 const char *apic_type = "apic";
2540
2541 if (kvm_irqchip_in_kernel()) {
2542 apic_type = "kvm-apic";
2543 } else if (xen_enabled()) {
2544 apic_type = "xen-apic";
2545 }
2546
2547 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2548 if (cpu->apic_state == NULL) {
2549 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2550 return;
2551 }
2552
2553 object_property_add_child(OBJECT(cpu), "apic",
2554 OBJECT(cpu->apic_state), NULL);
2555 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2556 /* TODO: convert to link<> */
2557 apic = APIC_COMMON(cpu->apic_state);
2558 apic->cpu = cpu;
2559 }
2560
2561 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2562 {
2563 if (cpu->apic_state == NULL) {
2564 return;
2565 }
2566
2567 if (qdev_init(cpu->apic_state)) {
2568 error_setg(errp, "APIC device '%s' could not be initialized",
2569 object_get_typename(OBJECT(cpu->apic_state)));
2570 return;
2571 }
2572 }
2573 #else
2574 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2575 {
2576 }
2577 #endif
2578
2579 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2580 {
2581 CPUState *cs = CPU(dev);
2582 X86CPU *cpu = X86_CPU(dev);
2583 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2584 CPUX86State *env = &cpu->env;
2585 Error *local_err = NULL;
2586
2587 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2588 env->cpuid_level = 7;
2589 }
2590
2591 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2592 * CPUID[1].EDX.
2593 */
2594 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2595 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2596 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2597 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2598 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2599 & CPUID_EXT2_AMD_ALIASES);
2600 }
2601
2602 if (!kvm_enabled()) {
2603 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2604 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2605 env->features[FEAT_8000_0001_EDX] &= TCG_EXT2_FEATURES;
2606 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2607 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2608 } else {
2609 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2610 error_setg(&local_err,
2611 "Host's CPU doesn't support requested features");
2612 goto out;
2613 }
2614 }
2615
2616 #ifndef CONFIG_USER_ONLY
2617 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2618
2619 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2620 x86_cpu_apic_create(cpu, &local_err);
2621 if (local_err != NULL) {
2622 goto out;
2623 }
2624 }
2625 #endif
2626
2627 mce_init(cpu);
2628 qemu_init_vcpu(cs);
2629
2630 x86_cpu_apic_realize(cpu, &local_err);
2631 if (local_err != NULL) {
2632 goto out;
2633 }
2634 cpu_reset(cs);
2635
2636 xcc->parent_realize(dev, &local_err);
2637 out:
2638 if (local_err != NULL) {
2639 error_propagate(errp, local_err);
2640 return;
2641 }
2642 }
2643
2644 /* Enables contiguous-apic-ID mode, for compatibility */
2645 static bool compat_apic_id_mode;
2646
2647 void enable_compat_apic_id_mode(void)
2648 {
2649 compat_apic_id_mode = true;
2650 }
2651
2652 /* Calculates initial APIC ID for a specific CPU index
2653 *
2654 * Currently we need to be able to calculate the APIC ID from the CPU index
2655 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2656 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2657 * all CPUs up to max_cpus.
2658 */
2659 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2660 {
2661 uint32_t correct_id;
2662 static bool warned;
2663
2664 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2665 if (compat_apic_id_mode) {
2666 if (cpu_index != correct_id && !warned) {
2667 error_report("APIC IDs set in compatibility mode, "
2668 "CPU topology won't match the configuration");
2669 warned = true;
2670 }
2671 return cpu_index;
2672 } else {
2673 return correct_id;
2674 }
2675 }
2676
2677 static void x86_cpu_initfn(Object *obj)
2678 {
2679 CPUState *cs = CPU(obj);
2680 X86CPU *cpu = X86_CPU(obj);
2681 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2682 CPUX86State *env = &cpu->env;
2683 static int inited;
2684
2685 cs->env_ptr = env;
2686 cpu_exec_init(env);
2687
2688 object_property_add(obj, "family", "int",
2689 x86_cpuid_version_get_family,
2690 x86_cpuid_version_set_family, NULL, NULL, NULL);
2691 object_property_add(obj, "model", "int",
2692 x86_cpuid_version_get_model,
2693 x86_cpuid_version_set_model, NULL, NULL, NULL);
2694 object_property_add(obj, "stepping", "int",
2695 x86_cpuid_version_get_stepping,
2696 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2697 object_property_add(obj, "level", "int",
2698 x86_cpuid_get_level,
2699 x86_cpuid_set_level, NULL, NULL, NULL);
2700 object_property_add(obj, "xlevel", "int",
2701 x86_cpuid_get_xlevel,
2702 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2703 object_property_add_str(obj, "vendor",
2704 x86_cpuid_get_vendor,
2705 x86_cpuid_set_vendor, NULL);
2706 object_property_add_str(obj, "model-id",
2707 x86_cpuid_get_model_id,
2708 x86_cpuid_set_model_id, NULL);
2709 object_property_add(obj, "tsc-frequency", "int",
2710 x86_cpuid_get_tsc_freq,
2711 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2712 object_property_add(obj, "apic-id", "int",
2713 x86_cpuid_get_apic_id,
2714 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2715 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2716 x86_cpu_get_feature_words,
2717 NULL, NULL, (void *)env->features, NULL);
2718 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2719 x86_cpu_get_feature_words,
2720 NULL, NULL, (void *)cpu->filtered_features, NULL);
2721
2722 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2723 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2724
2725 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2726
2727 /* init various static tables used in TCG mode */
2728 if (tcg_enabled() && !inited) {
2729 inited = 1;
2730 optimize_flags_init();
2731 #ifndef CONFIG_USER_ONLY
2732 cpu_set_debug_excp_handler(breakpoint_handler);
2733 #endif
2734 }
2735 }
2736
2737 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2738 {
2739 X86CPU *cpu = X86_CPU(cs);
2740 CPUX86State *env = &cpu->env;
2741
2742 return env->cpuid_apic_id;
2743 }
2744
2745 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2746 {
2747 X86CPU *cpu = X86_CPU(cs);
2748
2749 return cpu->env.cr[0] & CR0_PG_MASK;
2750 }
2751
2752 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2753 {
2754 X86CPU *cpu = X86_CPU(cs);
2755
2756 cpu->env.eip = value;
2757 }
2758
2759 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2760 {
2761 X86CPU *cpu = X86_CPU(cs);
2762
2763 cpu->env.eip = tb->pc - tb->cs_base;
2764 }
2765
2766 static bool x86_cpu_has_work(CPUState *cs)
2767 {
2768 X86CPU *cpu = X86_CPU(cs);
2769 CPUX86State *env = &cpu->env;
2770
2771 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2772 CPU_INTERRUPT_POLL)) &&
2773 (env->eflags & IF_MASK)) ||
2774 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2775 CPU_INTERRUPT_INIT |
2776 CPU_INTERRUPT_SIPI |
2777 CPU_INTERRUPT_MCE));
2778 }
2779
2780 static Property x86_cpu_properties[] = {
2781 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2782 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2783 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2784 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2785 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2786 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2787 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2788 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
2789 DEFINE_PROP_END_OF_LIST()
2790 };
2791
2792 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2793 {
2794 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2795 CPUClass *cc = CPU_CLASS(oc);
2796 DeviceClass *dc = DEVICE_CLASS(oc);
2797
2798 xcc->parent_realize = dc->realize;
2799 dc->realize = x86_cpu_realizefn;
2800 dc->bus_type = TYPE_ICC_BUS;
2801 dc->props = x86_cpu_properties;
2802
2803 xcc->parent_reset = cc->reset;
2804 cc->reset = x86_cpu_reset;
2805 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2806
2807 cc->class_by_name = x86_cpu_class_by_name;
2808 cc->parse_features = x86_cpu_parse_featurestr;
2809 cc->has_work = x86_cpu_has_work;
2810 cc->do_interrupt = x86_cpu_do_interrupt;
2811 cc->dump_state = x86_cpu_dump_state;
2812 cc->set_pc = x86_cpu_set_pc;
2813 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2814 cc->gdb_read_register = x86_cpu_gdb_read_register;
2815 cc->gdb_write_register = x86_cpu_gdb_write_register;
2816 cc->get_arch_id = x86_cpu_get_arch_id;
2817 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2818 #ifdef CONFIG_USER_ONLY
2819 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2820 #else
2821 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2822 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2823 cc->write_elf64_note = x86_cpu_write_elf64_note;
2824 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2825 cc->write_elf32_note = x86_cpu_write_elf32_note;
2826 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2827 cc->vmsd = &vmstate_x86_cpu;
2828 #endif
2829 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2830 }
2831
2832 static const TypeInfo x86_cpu_type_info = {
2833 .name = TYPE_X86_CPU,
2834 .parent = TYPE_CPU,
2835 .instance_size = sizeof(X86CPU),
2836 .instance_init = x86_cpu_initfn,
2837 .abstract = true,
2838 .class_size = sizeof(X86CPUClass),
2839 .class_init = x86_cpu_common_class_init,
2840 };
2841
2842 static void x86_cpu_register_types(void)
2843 {
2844 int i;
2845
2846 type_register_static(&x86_cpu_type_info);
2847 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2848 x86_register_cpudef_type(&builtin_x86_defs[i]);
2849 }
2850 #ifdef CONFIG_KVM
2851 type_register_static(&host_x86_cpu_type_info);
2852 #endif
2853 }
2854
2855 type_init(x86_cpu_register_types)
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