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target-i386: kvm: Enable all supported KVM features for -cpu host
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26
27 #include "qemu/option.h"
28 #include "qemu/config-file.h"
29 #include "qapi/qmp/qerror.h"
30
31 #include "qapi/visitor.h"
32 #include "sysemu/arch_init.h"
33
34 #include "hyperv.h"
35
36 #include "hw/hw.h"
37 #if defined(CONFIG_KVM)
38 #include <linux/kvm_para.h>
39 #endif
40
41 #include "sysemu/sysemu.h"
42 #ifndef CONFIG_USER_ONLY
43 #include "hw/xen.h"
44 #include "hw/sysbus.h"
45 #include "hw/apic_internal.h"
46 #endif
47
48 /* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52 static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61 };
62 static const char *ext_feature_name[] = {
63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
64 "ds_cpl", "vmx", "smx", "est",
65 "tm2", "ssse3", "cid", NULL,
66 "fma", "cx16", "xtpr", "pdcm",
67 NULL, "pcid", "dca", "sse4.1|sse4_1",
68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
69 "tsc-deadline", "aes", "xsave", "osxsave",
70 "avx", "f16c", "rdrand", "hypervisor",
71 };
72 /* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
77 static const char *ext2_feature_name[] = {
78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
85 NULL, "lm|i64", "3dnowext", "3dnow",
86 };
87 static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
90 "3dnowprefetch", "osvw", "ibs", "xop",
91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
95 NULL, NULL, NULL, NULL,
96 };
97
98 static const char *kvm_feature_name[] = {
99 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
100 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107 };
108
109 static const char *svm_feature_name[] = {
110 "npt", "lbrv", "svm_lock", "nrip_save",
111 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
112 NULL, NULL, "pause_filter", NULL,
113 "pfthreshold", NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 };
119
120 static const char *cpuid_7_0_ebx_feature_name[] = {
121 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
122 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
123 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
125 };
126
127 /* collects per-function cpuid data
128 */
129 typedef struct model_features_t {
130 uint32_t *guest_feat;
131 uint32_t *host_feat;
132 uint32_t check_feat;
133 const char **flag_names;
134 uint32_t cpuid;
135 } model_features_t;
136
137 int check_cpuid = 0;
138 int enforce_cpuid = 0;
139
140 #if defined(CONFIG_KVM)
141 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
142 (1 << KVM_FEATURE_NOP_IO_DELAY) |
143 (1 << KVM_FEATURE_MMU_OP) |
144 (1 << KVM_FEATURE_CLOCKSOURCE2) |
145 (1 << KVM_FEATURE_ASYNC_PF) |
146 (1 << KVM_FEATURE_STEAL_TIME) |
147 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
148 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
149 #else
150 static uint32_t kvm_default_features = 0;
151 static const uint32_t kvm_pv_eoi_features = 0;
152 #endif
153
154 void enable_kvm_pv_eoi(void)
155 {
156 kvm_default_features |= kvm_pv_eoi_features;
157 }
158
159 void host_cpuid(uint32_t function, uint32_t count,
160 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
161 {
162 #if defined(CONFIG_KVM)
163 uint32_t vec[4];
164
165 #ifdef __x86_64__
166 asm volatile("cpuid"
167 : "=a"(vec[0]), "=b"(vec[1]),
168 "=c"(vec[2]), "=d"(vec[3])
169 : "0"(function), "c"(count) : "cc");
170 #else
171 asm volatile("pusha \n\t"
172 "cpuid \n\t"
173 "mov %%eax, 0(%2) \n\t"
174 "mov %%ebx, 4(%2) \n\t"
175 "mov %%ecx, 8(%2) \n\t"
176 "mov %%edx, 12(%2) \n\t"
177 "popa"
178 : : "a"(function), "c"(count), "S"(vec)
179 : "memory", "cc");
180 #endif
181
182 if (eax)
183 *eax = vec[0];
184 if (ebx)
185 *ebx = vec[1];
186 if (ecx)
187 *ecx = vec[2];
188 if (edx)
189 *edx = vec[3];
190 #endif
191 }
192
193 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
194
195 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
196 * a substring. ex if !NULL points to the first char after a substring,
197 * otherwise the string is assumed to sized by a terminating nul.
198 * Return lexical ordering of *s1:*s2.
199 */
200 static int sstrcmp(const char *s1, const char *e1, const char *s2,
201 const char *e2)
202 {
203 for (;;) {
204 if (!*s1 || !*s2 || *s1 != *s2)
205 return (*s1 - *s2);
206 ++s1, ++s2;
207 if (s1 == e1 && s2 == e2)
208 return (0);
209 else if (s1 == e1)
210 return (*s2);
211 else if (s2 == e2)
212 return (*s1);
213 }
214 }
215
216 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
217 * '|' delimited (possibly empty) strings in which case search for a match
218 * within the alternatives proceeds left to right. Return 0 for success,
219 * non-zero otherwise.
220 */
221 static int altcmp(const char *s, const char *e, const char *altstr)
222 {
223 const char *p, *q;
224
225 for (q = p = altstr; ; ) {
226 while (*p && *p != '|')
227 ++p;
228 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
229 return (0);
230 if (!*p)
231 return (1);
232 else
233 q = ++p;
234 }
235 }
236
237 /* search featureset for flag *[s..e), if found set corresponding bit in
238 * *pval and return true, otherwise return false
239 */
240 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
241 const char **featureset)
242 {
243 uint32_t mask;
244 const char **ppc;
245 bool found = false;
246
247 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
248 if (*ppc && !altcmp(s, e, *ppc)) {
249 *pval |= mask;
250 found = true;
251 }
252 }
253 return found;
254 }
255
256 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
257 uint32_t *ext_features,
258 uint32_t *ext2_features,
259 uint32_t *ext3_features,
260 uint32_t *kvm_features,
261 uint32_t *svm_features,
262 uint32_t *cpuid_7_0_ebx_features)
263 {
264 if (!lookup_feature(features, flagname, NULL, feature_name) &&
265 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
266 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
267 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
268 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
269 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
270 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
271 cpuid_7_0_ebx_feature_name))
272 fprintf(stderr, "CPU feature %s not found\n", flagname);
273 }
274
275 typedef struct x86_def_t {
276 struct x86_def_t *next;
277 const char *name;
278 uint32_t level;
279 uint32_t vendor1, vendor2, vendor3;
280 int family;
281 int model;
282 int stepping;
283 int tsc_khz;
284 uint32_t features, ext_features, ext2_features, ext3_features;
285 uint32_t kvm_features, svm_features;
286 uint32_t xlevel;
287 char model_id[48];
288 int vendor_override;
289 /* Store the results of Centaur's CPUID instructions */
290 uint32_t ext4_features;
291 uint32_t xlevel2;
292 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
293 uint32_t cpuid_7_0_ebx_features;
294 } x86_def_t;
295
296 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
297 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
298 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
299 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
300 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
301 CPUID_PSE36 | CPUID_FXSR)
302 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
303 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
304 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
305 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
306 CPUID_PAE | CPUID_SEP | CPUID_APIC)
307
308 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
309 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
310 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
311 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
312 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
313 /* partly implemented:
314 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
315 CPUID_PSE36 (needed for Solaris) */
316 /* missing:
317 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
318 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
319 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
320 CPUID_EXT_HYPERVISOR)
321 /* missing:
322 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
323 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
324 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
325 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
326 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
327 /* missing:
328 CPUID_EXT2_PDPE1GB */
329 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
330 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
331 #define TCG_SVM_FEATURES 0
332 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
333
334 /* maintains list of cpu model definitions
335 */
336 static x86_def_t *x86_defs = {NULL};
337
338 /* built-in cpu model definitions (deprecated)
339 */
340 static x86_def_t builtin_x86_defs[] = {
341 {
342 .name = "qemu64",
343 .level = 4,
344 .vendor1 = CPUID_VENDOR_AMD_1,
345 .vendor2 = CPUID_VENDOR_AMD_2,
346 .vendor3 = CPUID_VENDOR_AMD_3,
347 .family = 6,
348 .model = 2,
349 .stepping = 3,
350 .features = PPRO_FEATURES |
351 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
352 CPUID_PSE36,
353 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
354 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
355 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
356 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
357 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
358 .xlevel = 0x8000000A,
359 },
360 {
361 .name = "phenom",
362 .level = 5,
363 .vendor1 = CPUID_VENDOR_AMD_1,
364 .vendor2 = CPUID_VENDOR_AMD_2,
365 .vendor3 = CPUID_VENDOR_AMD_3,
366 .family = 16,
367 .model = 2,
368 .stepping = 3,
369 .features = PPRO_FEATURES |
370 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
371 CPUID_PSE36 | CPUID_VME | CPUID_HT,
372 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
373 CPUID_EXT_POPCNT,
374 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
375 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
376 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
377 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
378 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
379 CPUID_EXT3_CR8LEG,
380 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
381 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
382 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
383 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
384 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
385 .xlevel = 0x8000001A,
386 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
387 },
388 {
389 .name = "core2duo",
390 .level = 10,
391 .family = 6,
392 .model = 15,
393 .stepping = 11,
394 .features = PPRO_FEATURES |
395 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
396 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
397 CPUID_HT | CPUID_TM | CPUID_PBE,
398 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
399 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
400 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
401 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
402 .ext3_features = CPUID_EXT3_LAHF_LM,
403 .xlevel = 0x80000008,
404 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
405 },
406 {
407 .name = "kvm64",
408 .level = 5,
409 .vendor1 = CPUID_VENDOR_INTEL_1,
410 .vendor2 = CPUID_VENDOR_INTEL_2,
411 .vendor3 = CPUID_VENDOR_INTEL_3,
412 .family = 15,
413 .model = 6,
414 .stepping = 1,
415 /* Missing: CPUID_VME, CPUID_HT */
416 .features = PPRO_FEATURES |
417 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
418 CPUID_PSE36,
419 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
420 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
421 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
422 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
423 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
424 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
425 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
426 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
427 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
428 .ext3_features = 0,
429 .xlevel = 0x80000008,
430 .model_id = "Common KVM processor"
431 },
432 {
433 .name = "qemu32",
434 .level = 4,
435 .family = 6,
436 .model = 3,
437 .stepping = 3,
438 .features = PPRO_FEATURES,
439 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
440 .xlevel = 0x80000004,
441 },
442 {
443 .name = "kvm32",
444 .level = 5,
445 .family = 15,
446 .model = 6,
447 .stepping = 1,
448 .features = PPRO_FEATURES |
449 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
450 .ext_features = CPUID_EXT_SSE3,
451 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
452 .ext3_features = 0,
453 .xlevel = 0x80000008,
454 .model_id = "Common 32-bit KVM processor"
455 },
456 {
457 .name = "coreduo",
458 .level = 10,
459 .family = 6,
460 .model = 14,
461 .stepping = 8,
462 .features = PPRO_FEATURES | CPUID_VME |
463 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
464 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
465 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
466 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
467 .ext2_features = CPUID_EXT2_NX,
468 .xlevel = 0x80000008,
469 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
470 },
471 {
472 .name = "486",
473 .level = 1,
474 .family = 4,
475 .model = 0,
476 .stepping = 0,
477 .features = I486_FEATURES,
478 .xlevel = 0,
479 },
480 {
481 .name = "pentium",
482 .level = 1,
483 .family = 5,
484 .model = 4,
485 .stepping = 3,
486 .features = PENTIUM_FEATURES,
487 .xlevel = 0,
488 },
489 {
490 .name = "pentium2",
491 .level = 2,
492 .family = 6,
493 .model = 5,
494 .stepping = 2,
495 .features = PENTIUM2_FEATURES,
496 .xlevel = 0,
497 },
498 {
499 .name = "pentium3",
500 .level = 2,
501 .family = 6,
502 .model = 7,
503 .stepping = 3,
504 .features = PENTIUM3_FEATURES,
505 .xlevel = 0,
506 },
507 {
508 .name = "athlon",
509 .level = 2,
510 .vendor1 = CPUID_VENDOR_AMD_1,
511 .vendor2 = CPUID_VENDOR_AMD_2,
512 .vendor3 = CPUID_VENDOR_AMD_3,
513 .family = 6,
514 .model = 2,
515 .stepping = 3,
516 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
517 CPUID_MCA,
518 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
519 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
520 .xlevel = 0x80000008,
521 },
522 {
523 .name = "n270",
524 /* original is on level 10 */
525 .level = 5,
526 .family = 6,
527 .model = 28,
528 .stepping = 2,
529 .features = PPRO_FEATURES |
530 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
531 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
532 /* Some CPUs got no CPUID_SEP */
533 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
534 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
535 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
536 CPUID_EXT2_NX,
537 .ext3_features = CPUID_EXT3_LAHF_LM,
538 .xlevel = 0x8000000A,
539 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
540 },
541 {
542 .name = "Conroe",
543 .level = 2,
544 .vendor1 = CPUID_VENDOR_INTEL_1,
545 .vendor2 = CPUID_VENDOR_INTEL_2,
546 .vendor3 = CPUID_VENDOR_INTEL_3,
547 .family = 6,
548 .model = 2,
549 .stepping = 3,
550 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
551 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
552 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
553 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
554 CPUID_DE | CPUID_FP87,
555 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
556 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
557 .ext3_features = CPUID_EXT3_LAHF_LM,
558 .xlevel = 0x8000000A,
559 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
560 },
561 {
562 .name = "Penryn",
563 .level = 2,
564 .vendor1 = CPUID_VENDOR_INTEL_1,
565 .vendor2 = CPUID_VENDOR_INTEL_2,
566 .vendor3 = CPUID_VENDOR_INTEL_3,
567 .family = 6,
568 .model = 2,
569 .stepping = 3,
570 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
571 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
572 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
573 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
574 CPUID_DE | CPUID_FP87,
575 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
576 CPUID_EXT_SSE3,
577 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
578 .ext3_features = CPUID_EXT3_LAHF_LM,
579 .xlevel = 0x8000000A,
580 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
581 },
582 {
583 .name = "Nehalem",
584 .level = 2,
585 .vendor1 = CPUID_VENDOR_INTEL_1,
586 .vendor2 = CPUID_VENDOR_INTEL_2,
587 .vendor3 = CPUID_VENDOR_INTEL_3,
588 .family = 6,
589 .model = 2,
590 .stepping = 3,
591 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
592 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
593 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
594 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
595 CPUID_DE | CPUID_FP87,
596 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
597 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
598 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
599 .ext3_features = CPUID_EXT3_LAHF_LM,
600 .xlevel = 0x8000000A,
601 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
602 },
603 {
604 .name = "Westmere",
605 .level = 11,
606 .vendor1 = CPUID_VENDOR_INTEL_1,
607 .vendor2 = CPUID_VENDOR_INTEL_2,
608 .vendor3 = CPUID_VENDOR_INTEL_3,
609 .family = 6,
610 .model = 44,
611 .stepping = 1,
612 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
613 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
614 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
615 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
616 CPUID_DE | CPUID_FP87,
617 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
618 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
619 CPUID_EXT_SSE3,
620 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
621 .ext3_features = CPUID_EXT3_LAHF_LM,
622 .xlevel = 0x8000000A,
623 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
624 },
625 {
626 .name = "SandyBridge",
627 .level = 0xd,
628 .vendor1 = CPUID_VENDOR_INTEL_1,
629 .vendor2 = CPUID_VENDOR_INTEL_2,
630 .vendor3 = CPUID_VENDOR_INTEL_3,
631 .family = 6,
632 .model = 42,
633 .stepping = 1,
634 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
635 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
636 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
637 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
638 CPUID_DE | CPUID_FP87,
639 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
640 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
641 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
642 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
643 CPUID_EXT_SSE3,
644 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
645 CPUID_EXT2_SYSCALL,
646 .ext3_features = CPUID_EXT3_LAHF_LM,
647 .xlevel = 0x8000000A,
648 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
649 },
650 {
651 .name = "Haswell",
652 .level = 0xd,
653 .vendor1 = CPUID_VENDOR_INTEL_1,
654 .vendor2 = CPUID_VENDOR_INTEL_2,
655 .vendor3 = CPUID_VENDOR_INTEL_3,
656 .family = 6,
657 .model = 60,
658 .stepping = 1,
659 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
660 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
661 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
662 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
663 CPUID_DE | CPUID_FP87,
664 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
665 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
666 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
667 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
668 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
669 CPUID_EXT_PCID,
670 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
671 CPUID_EXT2_SYSCALL,
672 .ext3_features = CPUID_EXT3_LAHF_LM,
673 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
674 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
675 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
676 CPUID_7_0_EBX_RTM,
677 .xlevel = 0x8000000A,
678 .model_id = "Intel Core Processor (Haswell)",
679 },
680 {
681 .name = "Opteron_G1",
682 .level = 5,
683 .vendor1 = CPUID_VENDOR_AMD_1,
684 .vendor2 = CPUID_VENDOR_AMD_2,
685 .vendor3 = CPUID_VENDOR_AMD_3,
686 .family = 15,
687 .model = 6,
688 .stepping = 1,
689 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
690 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
691 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
692 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
693 CPUID_DE | CPUID_FP87,
694 .ext_features = CPUID_EXT_SSE3,
695 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
696 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
697 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
698 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
699 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
700 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
701 .xlevel = 0x80000008,
702 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
703 },
704 {
705 .name = "Opteron_G2",
706 .level = 5,
707 .vendor1 = CPUID_VENDOR_AMD_1,
708 .vendor2 = CPUID_VENDOR_AMD_2,
709 .vendor3 = CPUID_VENDOR_AMD_3,
710 .family = 15,
711 .model = 6,
712 .stepping = 1,
713 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
714 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
715 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
716 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
717 CPUID_DE | CPUID_FP87,
718 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
719 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
720 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
721 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
722 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
723 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
724 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
725 CPUID_EXT2_DE | CPUID_EXT2_FPU,
726 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
727 .xlevel = 0x80000008,
728 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
729 },
730 {
731 .name = "Opteron_G3",
732 .level = 5,
733 .vendor1 = CPUID_VENDOR_AMD_1,
734 .vendor2 = CPUID_VENDOR_AMD_2,
735 .vendor3 = CPUID_VENDOR_AMD_3,
736 .family = 15,
737 .model = 6,
738 .stepping = 1,
739 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
740 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
741 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
742 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
743 CPUID_DE | CPUID_FP87,
744 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
745 CPUID_EXT_SSE3,
746 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
747 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
748 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
749 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
750 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
751 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
752 CPUID_EXT2_DE | CPUID_EXT2_FPU,
753 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
754 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
755 .xlevel = 0x80000008,
756 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
757 },
758 {
759 .name = "Opteron_G4",
760 .level = 0xd,
761 .vendor1 = CPUID_VENDOR_AMD_1,
762 .vendor2 = CPUID_VENDOR_AMD_2,
763 .vendor3 = CPUID_VENDOR_AMD_3,
764 .family = 21,
765 .model = 1,
766 .stepping = 2,
767 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
768 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
769 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
770 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
771 CPUID_DE | CPUID_FP87,
772 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
773 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
774 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
775 CPUID_EXT_SSE3,
776 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
777 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
778 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
779 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
780 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
781 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
782 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
783 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
784 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
785 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
786 CPUID_EXT3_LAHF_LM,
787 .xlevel = 0x8000001A,
788 .model_id = "AMD Opteron 62xx class CPU",
789 },
790 {
791 .name = "Opteron_G5",
792 .level = 0xd,
793 .vendor1 = CPUID_VENDOR_AMD_1,
794 .vendor2 = CPUID_VENDOR_AMD_2,
795 .vendor3 = CPUID_VENDOR_AMD_3,
796 .family = 21,
797 .model = 2,
798 .stepping = 0,
799 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
800 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
801 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
802 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
803 CPUID_DE | CPUID_FP87,
804 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
805 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
806 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
807 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
808 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
809 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
810 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
811 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
812 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
813 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
814 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
815 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
816 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
817 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
818 CPUID_EXT3_LAHF_LM,
819 .xlevel = 0x8000001A,
820 .model_id = "AMD Opteron 63xx class CPU",
821 },
822 };
823
824 #ifdef CONFIG_KVM
825 static int cpu_x86_fill_model_id(char *str)
826 {
827 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
828 int i;
829
830 for (i = 0; i < 3; i++) {
831 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
832 memcpy(str + i * 16 + 0, &eax, 4);
833 memcpy(str + i * 16 + 4, &ebx, 4);
834 memcpy(str + i * 16 + 8, &ecx, 4);
835 memcpy(str + i * 16 + 12, &edx, 4);
836 }
837 return 0;
838 }
839 #endif
840
841 /* Fill a x86_def_t struct with information about the host CPU, and
842 * the CPU features supported by the host hardware + host kernel
843 *
844 * This function may be called only if KVM is enabled.
845 */
846 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
847 {
848 #ifdef CONFIG_KVM
849 KVMState *s = kvm_state;
850 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
851
852 assert(kvm_enabled());
853
854 x86_cpu_def->name = "host";
855 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
856 x86_cpu_def->vendor1 = ebx;
857 x86_cpu_def->vendor2 = edx;
858 x86_cpu_def->vendor3 = ecx;
859
860 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
861 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
862 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
863 x86_cpu_def->stepping = eax & 0x0F;
864
865 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
866 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
867 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
868
869 if (x86_cpu_def->level >= 7) {
870 x86_cpu_def->cpuid_7_0_ebx_features =
871 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
872 } else {
873 x86_cpu_def->cpuid_7_0_ebx_features = 0;
874 }
875
876 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
877 x86_cpu_def->ext2_features =
878 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
879 x86_cpu_def->ext3_features =
880 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
881
882 cpu_x86_fill_model_id(x86_cpu_def->model_id);
883 x86_cpu_def->vendor_override = 0;
884
885 /* Call Centaur's CPUID instruction. */
886 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
887 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
888 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
889 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
890 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
891 if (eax >= 0xC0000001) {
892 /* Support VIA max extended level */
893 x86_cpu_def->xlevel2 = eax;
894 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
895 x86_cpu_def->ext4_features =
896 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
897 }
898 }
899
900 /* Other KVM-specific feature fields: */
901 x86_cpu_def->svm_features =
902 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
903 x86_cpu_def->kvm_features =
904 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
905
906 #endif /* CONFIG_KVM */
907 }
908
909 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
910 {
911 int i;
912
913 for (i = 0; i < 32; ++i)
914 if (1 << i & mask) {
915 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
916 " flag '%s' [0x%08x]\n",
917 f->cpuid >> 16, f->cpuid & 0xffff,
918 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
919 break;
920 }
921 return 0;
922 }
923
924 /* best effort attempt to inform user requested cpu flags aren't making
925 * their way to the guest. Note: ft[].check_feat ideally should be
926 * specified via a guest_def field to suppress report of extraneous flags.
927 *
928 * This function may be called only if KVM is enabled.
929 */
930 static int kvm_check_features_against_host(x86_def_t *guest_def)
931 {
932 x86_def_t host_def;
933 uint32_t mask;
934 int rv, i;
935 struct model_features_t ft[] = {
936 {&guest_def->features, &host_def.features,
937 ~0, feature_name, 0x00000000},
938 {&guest_def->ext_features, &host_def.ext_features,
939 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
940 {&guest_def->ext2_features, &host_def.ext2_features,
941 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
942 {&guest_def->ext3_features, &host_def.ext3_features,
943 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
944
945 assert(kvm_enabled());
946
947 kvm_cpu_fill_host(&host_def);
948 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
949 for (mask = 1; mask; mask <<= 1)
950 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
951 !(*ft[i].host_feat & mask)) {
952 unavailable_host_feature(&ft[i], mask);
953 rv = 1;
954 }
955 return rv;
956 }
957
958 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
959 const char *name, Error **errp)
960 {
961 X86CPU *cpu = X86_CPU(obj);
962 CPUX86State *env = &cpu->env;
963 int64_t value;
964
965 value = (env->cpuid_version >> 8) & 0xf;
966 if (value == 0xf) {
967 value += (env->cpuid_version >> 20) & 0xff;
968 }
969 visit_type_int(v, &value, name, errp);
970 }
971
972 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
973 const char *name, Error **errp)
974 {
975 X86CPU *cpu = X86_CPU(obj);
976 CPUX86State *env = &cpu->env;
977 const int64_t min = 0;
978 const int64_t max = 0xff + 0xf;
979 int64_t value;
980
981 visit_type_int(v, &value, name, errp);
982 if (error_is_set(errp)) {
983 return;
984 }
985 if (value < min || value > max) {
986 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
987 name ? name : "null", value, min, max);
988 return;
989 }
990
991 env->cpuid_version &= ~0xff00f00;
992 if (value > 0x0f) {
993 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
994 } else {
995 env->cpuid_version |= value << 8;
996 }
997 }
998
999 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1000 const char *name, Error **errp)
1001 {
1002 X86CPU *cpu = X86_CPU(obj);
1003 CPUX86State *env = &cpu->env;
1004 int64_t value;
1005
1006 value = (env->cpuid_version >> 4) & 0xf;
1007 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1008 visit_type_int(v, &value, name, errp);
1009 }
1010
1011 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1012 const char *name, Error **errp)
1013 {
1014 X86CPU *cpu = X86_CPU(obj);
1015 CPUX86State *env = &cpu->env;
1016 const int64_t min = 0;
1017 const int64_t max = 0xff;
1018 int64_t value;
1019
1020 visit_type_int(v, &value, name, errp);
1021 if (error_is_set(errp)) {
1022 return;
1023 }
1024 if (value < min || value > max) {
1025 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1026 name ? name : "null", value, min, max);
1027 return;
1028 }
1029
1030 env->cpuid_version &= ~0xf00f0;
1031 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1032 }
1033
1034 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1035 void *opaque, const char *name,
1036 Error **errp)
1037 {
1038 X86CPU *cpu = X86_CPU(obj);
1039 CPUX86State *env = &cpu->env;
1040 int64_t value;
1041
1042 value = env->cpuid_version & 0xf;
1043 visit_type_int(v, &value, name, errp);
1044 }
1045
1046 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1047 void *opaque, const char *name,
1048 Error **errp)
1049 {
1050 X86CPU *cpu = X86_CPU(obj);
1051 CPUX86State *env = &cpu->env;
1052 const int64_t min = 0;
1053 const int64_t max = 0xf;
1054 int64_t value;
1055
1056 visit_type_int(v, &value, name, errp);
1057 if (error_is_set(errp)) {
1058 return;
1059 }
1060 if (value < min || value > max) {
1061 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1062 name ? name : "null", value, min, max);
1063 return;
1064 }
1065
1066 env->cpuid_version &= ~0xf;
1067 env->cpuid_version |= value & 0xf;
1068 }
1069
1070 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1071 const char *name, Error **errp)
1072 {
1073 X86CPU *cpu = X86_CPU(obj);
1074
1075 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1076 }
1077
1078 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1079 const char *name, Error **errp)
1080 {
1081 X86CPU *cpu = X86_CPU(obj);
1082
1083 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1084 }
1085
1086 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1087 const char *name, Error **errp)
1088 {
1089 X86CPU *cpu = X86_CPU(obj);
1090
1091 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1092 }
1093
1094 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1095 const char *name, Error **errp)
1096 {
1097 X86CPU *cpu = X86_CPU(obj);
1098
1099 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1100 }
1101
1102 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1103 {
1104 X86CPU *cpu = X86_CPU(obj);
1105 CPUX86State *env = &cpu->env;
1106 char *value;
1107 int i;
1108
1109 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1110 for (i = 0; i < 4; i++) {
1111 value[i ] = env->cpuid_vendor1 >> (8 * i);
1112 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1113 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1114 }
1115 value[CPUID_VENDOR_SZ] = '\0';
1116 return value;
1117 }
1118
1119 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1120 Error **errp)
1121 {
1122 X86CPU *cpu = X86_CPU(obj);
1123 CPUX86State *env = &cpu->env;
1124 int i;
1125
1126 if (strlen(value) != CPUID_VENDOR_SZ) {
1127 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1128 "vendor", value);
1129 return;
1130 }
1131
1132 env->cpuid_vendor1 = 0;
1133 env->cpuid_vendor2 = 0;
1134 env->cpuid_vendor3 = 0;
1135 for (i = 0; i < 4; i++) {
1136 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1137 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1138 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1139 }
1140 env->cpuid_vendor_override = 1;
1141 }
1142
1143 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1144 {
1145 X86CPU *cpu = X86_CPU(obj);
1146 CPUX86State *env = &cpu->env;
1147 char *value;
1148 int i;
1149
1150 value = g_malloc(48 + 1);
1151 for (i = 0; i < 48; i++) {
1152 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1153 }
1154 value[48] = '\0';
1155 return value;
1156 }
1157
1158 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1159 Error **errp)
1160 {
1161 X86CPU *cpu = X86_CPU(obj);
1162 CPUX86State *env = &cpu->env;
1163 int c, len, i;
1164
1165 if (model_id == NULL) {
1166 model_id = "";
1167 }
1168 len = strlen(model_id);
1169 memset(env->cpuid_model, 0, 48);
1170 for (i = 0; i < 48; i++) {
1171 if (i >= len) {
1172 c = '\0';
1173 } else {
1174 c = (uint8_t)model_id[i];
1175 }
1176 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1177 }
1178 }
1179
1180 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1181 const char *name, Error **errp)
1182 {
1183 X86CPU *cpu = X86_CPU(obj);
1184 int64_t value;
1185
1186 value = cpu->env.tsc_khz * 1000;
1187 visit_type_int(v, &value, name, errp);
1188 }
1189
1190 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1191 const char *name, Error **errp)
1192 {
1193 X86CPU *cpu = X86_CPU(obj);
1194 const int64_t min = 0;
1195 const int64_t max = INT64_MAX;
1196 int64_t value;
1197
1198 visit_type_int(v, &value, name, errp);
1199 if (error_is_set(errp)) {
1200 return;
1201 }
1202 if (value < min || value > max) {
1203 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1204 name ? name : "null", value, min, max);
1205 return;
1206 }
1207
1208 cpu->env.tsc_khz = value / 1000;
1209 }
1210
1211 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1212 {
1213 x86_def_t *def;
1214
1215 for (def = x86_defs; def; def = def->next) {
1216 if (name && !strcmp(name, def->name)) {
1217 break;
1218 }
1219 }
1220 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1221 kvm_cpu_fill_host(x86_cpu_def);
1222 } else if (!def) {
1223 return -1;
1224 } else {
1225 memcpy(x86_cpu_def, def, sizeof(*def));
1226 }
1227
1228 return 0;
1229 }
1230
1231 /* Parse "+feature,-feature,feature=foo" CPU feature string
1232 */
1233 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1234 {
1235 unsigned int i;
1236 char *featurestr; /* Single 'key=value" string being parsed */
1237 /* Features to be added */
1238 uint32_t plus_features = 0, plus_ext_features = 0;
1239 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1240 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1241 uint32_t plus_7_0_ebx_features = 0;
1242 /* Features to be removed */
1243 uint32_t minus_features = 0, minus_ext_features = 0;
1244 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1245 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1246 uint32_t minus_7_0_ebx_features = 0;
1247 uint32_t numvalue;
1248
1249 add_flagname_to_bitmaps("hypervisor", &plus_features,
1250 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1251 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1252
1253 featurestr = features ? strtok(features, ",") : NULL;
1254
1255 while (featurestr) {
1256 char *val;
1257 if (featurestr[0] == '+') {
1258 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1259 &plus_ext_features, &plus_ext2_features,
1260 &plus_ext3_features, &plus_kvm_features,
1261 &plus_svm_features, &plus_7_0_ebx_features);
1262 } else if (featurestr[0] == '-') {
1263 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1264 &minus_ext_features, &minus_ext2_features,
1265 &minus_ext3_features, &minus_kvm_features,
1266 &minus_svm_features, &minus_7_0_ebx_features);
1267 } else if ((val = strchr(featurestr, '='))) {
1268 *val = 0; val++;
1269 if (!strcmp(featurestr, "family")) {
1270 char *err;
1271 numvalue = strtoul(val, &err, 0);
1272 if (!*val || *err || numvalue > 0xff + 0xf) {
1273 fprintf(stderr, "bad numerical value %s\n", val);
1274 goto error;
1275 }
1276 x86_cpu_def->family = numvalue;
1277 } else if (!strcmp(featurestr, "model")) {
1278 char *err;
1279 numvalue = strtoul(val, &err, 0);
1280 if (!*val || *err || numvalue > 0xff) {
1281 fprintf(stderr, "bad numerical value %s\n", val);
1282 goto error;
1283 }
1284 x86_cpu_def->model = numvalue;
1285 } else if (!strcmp(featurestr, "stepping")) {
1286 char *err;
1287 numvalue = strtoul(val, &err, 0);
1288 if (!*val || *err || numvalue > 0xf) {
1289 fprintf(stderr, "bad numerical value %s\n", val);
1290 goto error;
1291 }
1292 x86_cpu_def->stepping = numvalue ;
1293 } else if (!strcmp(featurestr, "level")) {
1294 char *err;
1295 numvalue = strtoul(val, &err, 0);
1296 if (!*val || *err) {
1297 fprintf(stderr, "bad numerical value %s\n", val);
1298 goto error;
1299 }
1300 x86_cpu_def->level = numvalue;
1301 } else if (!strcmp(featurestr, "xlevel")) {
1302 char *err;
1303 numvalue = strtoul(val, &err, 0);
1304 if (!*val || *err) {
1305 fprintf(stderr, "bad numerical value %s\n", val);
1306 goto error;
1307 }
1308 if (numvalue < 0x80000000) {
1309 numvalue += 0x80000000;
1310 }
1311 x86_cpu_def->xlevel = numvalue;
1312 } else if (!strcmp(featurestr, "vendor")) {
1313 if (strlen(val) != 12) {
1314 fprintf(stderr, "vendor string must be 12 chars long\n");
1315 goto error;
1316 }
1317 x86_cpu_def->vendor1 = 0;
1318 x86_cpu_def->vendor2 = 0;
1319 x86_cpu_def->vendor3 = 0;
1320 for(i = 0; i < 4; i++) {
1321 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1322 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1323 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1324 }
1325 x86_cpu_def->vendor_override = 1;
1326 } else if (!strcmp(featurestr, "model_id")) {
1327 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1328 val);
1329 } else if (!strcmp(featurestr, "tsc_freq")) {
1330 int64_t tsc_freq;
1331 char *err;
1332
1333 tsc_freq = strtosz_suffix_unit(val, &err,
1334 STRTOSZ_DEFSUFFIX_B, 1000);
1335 if (tsc_freq < 0 || *err) {
1336 fprintf(stderr, "bad numerical value %s\n", val);
1337 goto error;
1338 }
1339 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1340 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1341 char *err;
1342 numvalue = strtoul(val, &err, 0);
1343 if (!*val || *err) {
1344 fprintf(stderr, "bad numerical value %s\n", val);
1345 goto error;
1346 }
1347 hyperv_set_spinlock_retries(numvalue);
1348 } else {
1349 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1350 goto error;
1351 }
1352 } else if (!strcmp(featurestr, "check")) {
1353 check_cpuid = 1;
1354 } else if (!strcmp(featurestr, "enforce")) {
1355 check_cpuid = enforce_cpuid = 1;
1356 } else if (!strcmp(featurestr, "hv_relaxed")) {
1357 hyperv_enable_relaxed_timing(true);
1358 } else if (!strcmp(featurestr, "hv_vapic")) {
1359 hyperv_enable_vapic_recommended(true);
1360 } else {
1361 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1362 goto error;
1363 }
1364 featurestr = strtok(NULL, ",");
1365 }
1366 x86_cpu_def->features |= plus_features;
1367 x86_cpu_def->ext_features |= plus_ext_features;
1368 x86_cpu_def->ext2_features |= plus_ext2_features;
1369 x86_cpu_def->ext3_features |= plus_ext3_features;
1370 x86_cpu_def->kvm_features |= plus_kvm_features;
1371 x86_cpu_def->svm_features |= plus_svm_features;
1372 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1373 x86_cpu_def->features &= ~minus_features;
1374 x86_cpu_def->ext_features &= ~minus_ext_features;
1375 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1376 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1377 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1378 x86_cpu_def->svm_features &= ~minus_svm_features;
1379 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1380 if (check_cpuid && kvm_enabled()) {
1381 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1382 goto error;
1383 }
1384 return 0;
1385
1386 error:
1387 return -1;
1388 }
1389
1390 /* generate a composite string into buf of all cpuid names in featureset
1391 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1392 * if flags, suppress names undefined in featureset.
1393 */
1394 static void listflags(char *buf, int bufsize, uint32_t fbits,
1395 const char **featureset, uint32_t flags)
1396 {
1397 const char **p = &featureset[31];
1398 char *q, *b, bit;
1399 int nc;
1400
1401 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1402 *buf = '\0';
1403 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1404 if (fbits & 1 << bit && (*p || !flags)) {
1405 if (*p)
1406 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1407 else
1408 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1409 if (bufsize <= nc) {
1410 if (b) {
1411 memcpy(b, "...", sizeof("..."));
1412 }
1413 return;
1414 }
1415 q += nc;
1416 bufsize -= nc;
1417 }
1418 }
1419
1420 /* generate CPU information. */
1421 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1422 {
1423 x86_def_t *def;
1424 char buf[256];
1425
1426 for (def = x86_defs; def; def = def->next) {
1427 snprintf(buf, sizeof(buf), "%s", def->name);
1428 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1429 }
1430 if (kvm_enabled()) {
1431 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1432 }
1433 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1434 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1435 (*cpu_fprintf)(f, " %s\n", buf);
1436 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1437 (*cpu_fprintf)(f, " %s\n", buf);
1438 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1439 (*cpu_fprintf)(f, " %s\n", buf);
1440 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1441 (*cpu_fprintf)(f, " %s\n", buf);
1442 }
1443
1444 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1445 {
1446 CpuDefinitionInfoList *cpu_list = NULL;
1447 x86_def_t *def;
1448
1449 for (def = x86_defs; def; def = def->next) {
1450 CpuDefinitionInfoList *entry;
1451 CpuDefinitionInfo *info;
1452
1453 info = g_malloc0(sizeof(*info));
1454 info->name = g_strdup(def->name);
1455
1456 entry = g_malloc0(sizeof(*entry));
1457 entry->value = info;
1458 entry->next = cpu_list;
1459 cpu_list = entry;
1460 }
1461
1462 return cpu_list;
1463 }
1464
1465 #ifdef CONFIG_KVM
1466 static void filter_features_for_kvm(X86CPU *cpu)
1467 {
1468 CPUX86State *env = &cpu->env;
1469 KVMState *s = kvm_state;
1470
1471 env->cpuid_features &=
1472 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1473 env->cpuid_ext_features &=
1474 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1475 env->cpuid_ext2_features &=
1476 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1477 env->cpuid_ext3_features &=
1478 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1479 env->cpuid_svm_features &=
1480 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1481 env->cpuid_7_0_ebx_features &=
1482 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1483 env->cpuid_kvm_features &=
1484 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1485 env->cpuid_ext4_features &=
1486 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1487
1488 }
1489 #endif
1490
1491 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1492 {
1493 CPUX86State *env = &cpu->env;
1494 x86_def_t def1, *def = &def1;
1495 Error *error = NULL;
1496 char *name, *features;
1497 gchar **model_pieces;
1498
1499 memset(def, 0, sizeof(*def));
1500
1501 model_pieces = g_strsplit(cpu_model, ",", 2);
1502 if (!model_pieces[0]) {
1503 goto error;
1504 }
1505 name = model_pieces[0];
1506 features = model_pieces[1];
1507
1508 if (cpu_x86_find_by_name(def, name) < 0) {
1509 goto error;
1510 }
1511
1512 if (cpu_x86_parse_featurestr(def, features) < 0) {
1513 goto error;
1514 }
1515 if (def->vendor1) {
1516 env->cpuid_vendor1 = def->vendor1;
1517 env->cpuid_vendor2 = def->vendor2;
1518 env->cpuid_vendor3 = def->vendor3;
1519 } else {
1520 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1521 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1522 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1523 }
1524 env->cpuid_vendor_override = def->vendor_override;
1525 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1526 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1527 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1528 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1529 env->cpuid_features = def->features;
1530 env->cpuid_ext_features = def->ext_features;
1531 env->cpuid_ext2_features = def->ext2_features;
1532 env->cpuid_ext3_features = def->ext3_features;
1533 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1534 env->cpuid_kvm_features = def->kvm_features;
1535 env->cpuid_svm_features = def->svm_features;
1536 env->cpuid_ext4_features = def->ext4_features;
1537 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1538 env->cpuid_xlevel2 = def->xlevel2;
1539 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1540 "tsc-frequency", &error);
1541
1542 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
1543 * CPUID[1].EDX.
1544 */
1545 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
1546 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
1547 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
1548 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
1549 env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES);
1550 }
1551
1552 if (!kvm_enabled()) {
1553 env->cpuid_features &= TCG_FEATURES;
1554 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1555 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1556 #ifdef TARGET_X86_64
1557 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1558 #endif
1559 );
1560 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
1561 env->cpuid_svm_features &= TCG_SVM_FEATURES;
1562 } else {
1563 #ifdef CONFIG_KVM
1564 filter_features_for_kvm(cpu);
1565 #endif
1566 }
1567 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1568 if (error) {
1569 fprintf(stderr, "%s\n", error_get_pretty(error));
1570 error_free(error);
1571 goto error;
1572 }
1573
1574 g_strfreev(model_pieces);
1575 return 0;
1576 error:
1577 g_strfreev(model_pieces);
1578 return -1;
1579 }
1580
1581 #if !defined(CONFIG_USER_ONLY)
1582
1583 void cpu_clear_apic_feature(CPUX86State *env)
1584 {
1585 env->cpuid_features &= ~CPUID_APIC;
1586 }
1587
1588 #endif /* !CONFIG_USER_ONLY */
1589
1590 /* Initialize list of CPU models, filling some non-static fields if necessary
1591 */
1592 void x86_cpudef_setup(void)
1593 {
1594 int i, j;
1595 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1596
1597 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1598 x86_def_t *def = &builtin_x86_defs[i];
1599 def->next = x86_defs;
1600
1601 /* Look for specific "cpudef" models that */
1602 /* have the QEMU version in .model_id */
1603 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1604 if (strcmp(model_with_versions[j], def->name) == 0) {
1605 pstrcpy(def->model_id, sizeof(def->model_id),
1606 "QEMU Virtual CPU version ");
1607 pstrcat(def->model_id, sizeof(def->model_id),
1608 qemu_get_version());
1609 break;
1610 }
1611 }
1612
1613 x86_defs = def;
1614 }
1615 }
1616
1617 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1618 uint32_t *ecx, uint32_t *edx)
1619 {
1620 *ebx = env->cpuid_vendor1;
1621 *edx = env->cpuid_vendor2;
1622 *ecx = env->cpuid_vendor3;
1623
1624 /* sysenter isn't supported on compatibility mode on AMD, syscall
1625 * isn't supported in compatibility mode on Intel.
1626 * Normally we advertise the actual cpu vendor, but you can override
1627 * this if you want to use KVM's sysenter/syscall emulation
1628 * in compatibility mode and when doing cross vendor migration
1629 */
1630 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1631 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1632 }
1633 }
1634
1635 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1636 uint32_t *eax, uint32_t *ebx,
1637 uint32_t *ecx, uint32_t *edx)
1638 {
1639 X86CPU *cpu = x86_env_get_cpu(env);
1640 CPUState *cs = CPU(cpu);
1641
1642 /* test if maximum index reached */
1643 if (index & 0x80000000) {
1644 if (index > env->cpuid_xlevel) {
1645 if (env->cpuid_xlevel2 > 0) {
1646 /* Handle the Centaur's CPUID instruction. */
1647 if (index > env->cpuid_xlevel2) {
1648 index = env->cpuid_xlevel2;
1649 } else if (index < 0xC0000000) {
1650 index = env->cpuid_xlevel;
1651 }
1652 } else {
1653 /* Intel documentation states that invalid EAX input will
1654 * return the same information as EAX=cpuid_level
1655 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1656 */
1657 index = env->cpuid_level;
1658 }
1659 }
1660 } else {
1661 if (index > env->cpuid_level)
1662 index = env->cpuid_level;
1663 }
1664
1665 switch(index) {
1666 case 0:
1667 *eax = env->cpuid_level;
1668 get_cpuid_vendor(env, ebx, ecx, edx);
1669 break;
1670 case 1:
1671 *eax = env->cpuid_version;
1672 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1673 *ecx = env->cpuid_ext_features;
1674 *edx = env->cpuid_features;
1675 if (env->nr_cores * env->nr_threads > 1) {
1676 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1677 *edx |= 1 << 28; /* HTT bit */
1678 }
1679 break;
1680 case 2:
1681 /* cache info: needed for Pentium Pro compatibility */
1682 *eax = 1;
1683 *ebx = 0;
1684 *ecx = 0;
1685 *edx = 0x2c307d;
1686 break;
1687 case 4:
1688 /* cache info: needed for Core compatibility */
1689 if (env->nr_cores > 1) {
1690 *eax = (env->nr_cores - 1) << 26;
1691 } else {
1692 *eax = 0;
1693 }
1694 switch (count) {
1695 case 0: /* L1 dcache info */
1696 *eax |= 0x0000121;
1697 *ebx = 0x1c0003f;
1698 *ecx = 0x000003f;
1699 *edx = 0x0000001;
1700 break;
1701 case 1: /* L1 icache info */
1702 *eax |= 0x0000122;
1703 *ebx = 0x1c0003f;
1704 *ecx = 0x000003f;
1705 *edx = 0x0000001;
1706 break;
1707 case 2: /* L2 cache info */
1708 *eax |= 0x0000143;
1709 if (env->nr_threads > 1) {
1710 *eax |= (env->nr_threads - 1) << 14;
1711 }
1712 *ebx = 0x3c0003f;
1713 *ecx = 0x0000fff;
1714 *edx = 0x0000001;
1715 break;
1716 default: /* end of info */
1717 *eax = 0;
1718 *ebx = 0;
1719 *ecx = 0;
1720 *edx = 0;
1721 break;
1722 }
1723 break;
1724 case 5:
1725 /* mwait info: needed for Core compatibility */
1726 *eax = 0; /* Smallest monitor-line size in bytes */
1727 *ebx = 0; /* Largest monitor-line size in bytes */
1728 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1729 *edx = 0;
1730 break;
1731 case 6:
1732 /* Thermal and Power Leaf */
1733 *eax = 0;
1734 *ebx = 0;
1735 *ecx = 0;
1736 *edx = 0;
1737 break;
1738 case 7:
1739 /* Structured Extended Feature Flags Enumeration Leaf */
1740 if (count == 0) {
1741 *eax = 0; /* Maximum ECX value for sub-leaves */
1742 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1743 *ecx = 0; /* Reserved */
1744 *edx = 0; /* Reserved */
1745 } else {
1746 *eax = 0;
1747 *ebx = 0;
1748 *ecx = 0;
1749 *edx = 0;
1750 }
1751 break;
1752 case 9:
1753 /* Direct Cache Access Information Leaf */
1754 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1755 *ebx = 0;
1756 *ecx = 0;
1757 *edx = 0;
1758 break;
1759 case 0xA:
1760 /* Architectural Performance Monitoring Leaf */
1761 if (kvm_enabled()) {
1762 KVMState *s = cs->kvm_state;
1763
1764 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1765 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1766 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1767 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1768 } else {
1769 *eax = 0;
1770 *ebx = 0;
1771 *ecx = 0;
1772 *edx = 0;
1773 }
1774 break;
1775 case 0xD:
1776 /* Processor Extended State */
1777 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1778 *eax = 0;
1779 *ebx = 0;
1780 *ecx = 0;
1781 *edx = 0;
1782 break;
1783 }
1784 if (kvm_enabled()) {
1785 KVMState *s = cs->kvm_state;
1786
1787 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1788 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1789 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1790 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1791 } else {
1792 *eax = 0;
1793 *ebx = 0;
1794 *ecx = 0;
1795 *edx = 0;
1796 }
1797 break;
1798 case 0x80000000:
1799 *eax = env->cpuid_xlevel;
1800 *ebx = env->cpuid_vendor1;
1801 *edx = env->cpuid_vendor2;
1802 *ecx = env->cpuid_vendor3;
1803 break;
1804 case 0x80000001:
1805 *eax = env->cpuid_version;
1806 *ebx = 0;
1807 *ecx = env->cpuid_ext3_features;
1808 *edx = env->cpuid_ext2_features;
1809
1810 /* The Linux kernel checks for the CMPLegacy bit and
1811 * discards multiple thread information if it is set.
1812 * So dont set it here for Intel to make Linux guests happy.
1813 */
1814 if (env->nr_cores * env->nr_threads > 1) {
1815 uint32_t tebx, tecx, tedx;
1816 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1817 if (tebx != CPUID_VENDOR_INTEL_1 ||
1818 tedx != CPUID_VENDOR_INTEL_2 ||
1819 tecx != CPUID_VENDOR_INTEL_3) {
1820 *ecx |= 1 << 1; /* CmpLegacy bit */
1821 }
1822 }
1823 break;
1824 case 0x80000002:
1825 case 0x80000003:
1826 case 0x80000004:
1827 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1828 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1829 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1830 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1831 break;
1832 case 0x80000005:
1833 /* cache info (L1 cache) */
1834 *eax = 0x01ff01ff;
1835 *ebx = 0x01ff01ff;
1836 *ecx = 0x40020140;
1837 *edx = 0x40020140;
1838 break;
1839 case 0x80000006:
1840 /* cache info (L2 cache) */
1841 *eax = 0;
1842 *ebx = 0x42004200;
1843 *ecx = 0x02008140;
1844 *edx = 0;
1845 break;
1846 case 0x80000008:
1847 /* virtual & phys address size in low 2 bytes. */
1848 /* XXX: This value must match the one used in the MMU code. */
1849 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1850 /* 64 bit processor */
1851 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1852 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1853 } else {
1854 if (env->cpuid_features & CPUID_PSE36)
1855 *eax = 0x00000024; /* 36 bits physical */
1856 else
1857 *eax = 0x00000020; /* 32 bits physical */
1858 }
1859 *ebx = 0;
1860 *ecx = 0;
1861 *edx = 0;
1862 if (env->nr_cores * env->nr_threads > 1) {
1863 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1864 }
1865 break;
1866 case 0x8000000A:
1867 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1868 *eax = 0x00000001; /* SVM Revision */
1869 *ebx = 0x00000010; /* nr of ASIDs */
1870 *ecx = 0;
1871 *edx = env->cpuid_svm_features; /* optional features */
1872 } else {
1873 *eax = 0;
1874 *ebx = 0;
1875 *ecx = 0;
1876 *edx = 0;
1877 }
1878 break;
1879 case 0xC0000000:
1880 *eax = env->cpuid_xlevel2;
1881 *ebx = 0;
1882 *ecx = 0;
1883 *edx = 0;
1884 break;
1885 case 0xC0000001:
1886 /* Support for VIA CPU's CPUID instruction */
1887 *eax = env->cpuid_version;
1888 *ebx = 0;
1889 *ecx = 0;
1890 *edx = env->cpuid_ext4_features;
1891 break;
1892 case 0xC0000002:
1893 case 0xC0000003:
1894 case 0xC0000004:
1895 /* Reserved for the future, and now filled with zero */
1896 *eax = 0;
1897 *ebx = 0;
1898 *ecx = 0;
1899 *edx = 0;
1900 break;
1901 default:
1902 /* reserved values: zero */
1903 *eax = 0;
1904 *ebx = 0;
1905 *ecx = 0;
1906 *edx = 0;
1907 break;
1908 }
1909 }
1910
1911 /* CPUClass::reset() */
1912 static void x86_cpu_reset(CPUState *s)
1913 {
1914 X86CPU *cpu = X86_CPU(s);
1915 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1916 CPUX86State *env = &cpu->env;
1917 int i;
1918
1919 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1920 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1921 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1922 }
1923
1924 xcc->parent_reset(s);
1925
1926
1927 memset(env, 0, offsetof(CPUX86State, breakpoints));
1928
1929 tlb_flush(env, 1);
1930
1931 env->old_exception = -1;
1932
1933 /* init to reset state */
1934
1935 #ifdef CONFIG_SOFTMMU
1936 env->hflags |= HF_SOFTMMU_MASK;
1937 #endif
1938 env->hflags2 |= HF2_GIF_MASK;
1939
1940 cpu_x86_update_cr0(env, 0x60000010);
1941 env->a20_mask = ~0x0;
1942 env->smbase = 0x30000;
1943
1944 env->idt.limit = 0xffff;
1945 env->gdt.limit = 0xffff;
1946 env->ldt.limit = 0xffff;
1947 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1948 env->tr.limit = 0xffff;
1949 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1950
1951 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1952 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1953 DESC_R_MASK | DESC_A_MASK);
1954 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1955 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1956 DESC_A_MASK);
1957 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1958 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1959 DESC_A_MASK);
1960 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1961 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1962 DESC_A_MASK);
1963 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1964 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1965 DESC_A_MASK);
1966 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1967 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1968 DESC_A_MASK);
1969
1970 env->eip = 0xfff0;
1971 env->regs[R_EDX] = env->cpuid_version;
1972
1973 env->eflags = 0x2;
1974
1975 /* FPU init */
1976 for (i = 0; i < 8; i++) {
1977 env->fptags[i] = 1;
1978 }
1979 env->fpuc = 0x37f;
1980
1981 env->mxcsr = 0x1f80;
1982
1983 env->pat = 0x0007040600070406ULL;
1984 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1985
1986 memset(env->dr, 0, sizeof(env->dr));
1987 env->dr[6] = DR6_FIXED_1;
1988 env->dr[7] = DR7_FIXED_1;
1989 cpu_breakpoint_remove_all(env, BP_CPU);
1990 cpu_watchpoint_remove_all(env, BP_CPU);
1991
1992 #if !defined(CONFIG_USER_ONLY)
1993 /* We hard-wire the BSP to the first CPU. */
1994 if (env->cpu_index == 0) {
1995 apic_designate_bsp(env->apic_state);
1996 }
1997
1998 env->halted = !cpu_is_bsp(cpu);
1999 #endif
2000 }
2001
2002 #ifndef CONFIG_USER_ONLY
2003 bool cpu_is_bsp(X86CPU *cpu)
2004 {
2005 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2006 }
2007
2008 /* TODO: remove me, when reset over QOM tree is implemented */
2009 static void x86_cpu_machine_reset_cb(void *opaque)
2010 {
2011 X86CPU *cpu = opaque;
2012 cpu_reset(CPU(cpu));
2013 }
2014 #endif
2015
2016 static void mce_init(X86CPU *cpu)
2017 {
2018 CPUX86State *cenv = &cpu->env;
2019 unsigned int bank;
2020
2021 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2022 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2023 (CPUID_MCE | CPUID_MCA)) {
2024 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2025 cenv->mcg_ctl = ~(uint64_t)0;
2026 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2027 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2028 }
2029 }
2030 }
2031
2032 #define MSI_ADDR_BASE 0xfee00000
2033
2034 #ifndef CONFIG_USER_ONLY
2035 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2036 {
2037 static int apic_mapped;
2038 CPUX86State *env = &cpu->env;
2039 APICCommonState *apic;
2040 const char *apic_type = "apic";
2041
2042 if (kvm_irqchip_in_kernel()) {
2043 apic_type = "kvm-apic";
2044 } else if (xen_enabled()) {
2045 apic_type = "xen-apic";
2046 }
2047
2048 env->apic_state = qdev_try_create(NULL, apic_type);
2049 if (env->apic_state == NULL) {
2050 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2051 return;
2052 }
2053
2054 object_property_add_child(OBJECT(cpu), "apic",
2055 OBJECT(env->apic_state), NULL);
2056 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2057 /* TODO: convert to link<> */
2058 apic = APIC_COMMON(env->apic_state);
2059 apic->cpu = cpu;
2060
2061 if (qdev_init(env->apic_state)) {
2062 error_setg(errp, "APIC device '%s' could not be initialized",
2063 object_get_typename(OBJECT(env->apic_state)));
2064 return;
2065 }
2066
2067 /* XXX: mapping more APICs at the same memory location */
2068 if (apic_mapped == 0) {
2069 /* NOTE: the APIC is directly connected to the CPU - it is not
2070 on the global memory bus. */
2071 /* XXX: what if the base changes? */
2072 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2073 apic_mapped = 1;
2074 }
2075 }
2076 #endif
2077
2078 void x86_cpu_realize(Object *obj, Error **errp)
2079 {
2080 X86CPU *cpu = X86_CPU(obj);
2081 CPUX86State *env = &cpu->env;
2082
2083 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2084 env->cpuid_level = 7;
2085 }
2086
2087 #ifndef CONFIG_USER_ONLY
2088 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2089
2090 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2091 x86_cpu_apic_init(cpu, errp);
2092 if (error_is_set(errp)) {
2093 return;
2094 }
2095 }
2096 #endif
2097
2098 mce_init(cpu);
2099 qemu_init_vcpu(&cpu->env);
2100 cpu_reset(CPU(cpu));
2101 }
2102
2103 static void x86_cpu_initfn(Object *obj)
2104 {
2105 X86CPU *cpu = X86_CPU(obj);
2106 CPUX86State *env = &cpu->env;
2107 static int inited;
2108
2109 cpu_exec_init(env);
2110
2111 object_property_add(obj, "family", "int",
2112 x86_cpuid_version_get_family,
2113 x86_cpuid_version_set_family, NULL, NULL, NULL);
2114 object_property_add(obj, "model", "int",
2115 x86_cpuid_version_get_model,
2116 x86_cpuid_version_set_model, NULL, NULL, NULL);
2117 object_property_add(obj, "stepping", "int",
2118 x86_cpuid_version_get_stepping,
2119 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2120 object_property_add(obj, "level", "int",
2121 x86_cpuid_get_level,
2122 x86_cpuid_set_level, NULL, NULL, NULL);
2123 object_property_add(obj, "xlevel", "int",
2124 x86_cpuid_get_xlevel,
2125 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2126 object_property_add_str(obj, "vendor",
2127 x86_cpuid_get_vendor,
2128 x86_cpuid_set_vendor, NULL);
2129 object_property_add_str(obj, "model-id",
2130 x86_cpuid_get_model_id,
2131 x86_cpuid_set_model_id, NULL);
2132 object_property_add(obj, "tsc-frequency", "int",
2133 x86_cpuid_get_tsc_freq,
2134 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2135
2136 env->cpuid_apic_id = env->cpu_index;
2137
2138 /* init various static tables used in TCG mode */
2139 if (tcg_enabled() && !inited) {
2140 inited = 1;
2141 optimize_flags_init();
2142 #ifndef CONFIG_USER_ONLY
2143 cpu_set_debug_excp_handler(breakpoint_handler);
2144 #endif
2145 }
2146 }
2147
2148 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2149 {
2150 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2151 CPUClass *cc = CPU_CLASS(oc);
2152
2153 xcc->parent_reset = cc->reset;
2154 cc->reset = x86_cpu_reset;
2155 }
2156
2157 static const TypeInfo x86_cpu_type_info = {
2158 .name = TYPE_X86_CPU,
2159 .parent = TYPE_CPU,
2160 .instance_size = sizeof(X86CPU),
2161 .instance_init = x86_cpu_initfn,
2162 .abstract = false,
2163 .class_size = sizeof(X86CPUClass),
2164 .class_init = x86_cpu_common_class_init,
2165 };
2166
2167 static void x86_cpu_register_types(void)
2168 {
2169 type_register_static(&x86_cpu_type_info);
2170 }
2171
2172 type_init(x86_cpu_register_types)
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