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target-i386: X86CPU model subclasses
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
49 #endif
50
51
52 /* Cache topology CPUID constants: */
53
54 /* CPUID Leaf 2 Descriptors */
55
56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
58 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61 /* CPUID Leaf 4 constants: */
62
63 /* EAX: */
64 #define CPUID_4_TYPE_DCACHE 1
65 #define CPUID_4_TYPE_ICACHE 2
66 #define CPUID_4_TYPE_UNIFIED 3
67
68 #define CPUID_4_LEVEL(l) ((l) << 5)
69
70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71 #define CPUID_4_FULLY_ASSOC (1 << 9)
72
73 /* EDX: */
74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
75 #define CPUID_4_INCLUSIVE (1 << 1)
76 #define CPUID_4_COMPLEX_IDX (1 << 2)
77
78 #define ASSOC_FULL 0xFF
79
80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95 /* Definitions of the hardcoded cache entries we expose: */
96
97 /* L1 data cache: */
98 #define L1D_LINE_SIZE 64
99 #define L1D_ASSOCIATIVITY 8
100 #define L1D_SETS 64
101 #define L1D_PARTITIONS 1
102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105 #define L1D_LINES_PER_TAG 1
106 #define L1D_SIZE_KB_AMD 64
107 #define L1D_ASSOCIATIVITY_AMD 2
108
109 /* L1 instruction cache: */
110 #define L1I_LINE_SIZE 64
111 #define L1I_ASSOCIATIVITY 8
112 #define L1I_SETS 64
113 #define L1I_PARTITIONS 1
114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117 #define L1I_LINES_PER_TAG 1
118 #define L1I_SIZE_KB_AMD 64
119 #define L1I_ASSOCIATIVITY_AMD 2
120
121 /* Level 2 unified cache: */
122 #define L2_LINE_SIZE 64
123 #define L2_ASSOCIATIVITY 16
124 #define L2_SETS 4096
125 #define L2_PARTITIONS 1
126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130 #define L2_LINES_PER_TAG 1
131 #define L2_SIZE_KB_AMD 512
132
133 /* No L3 cache: */
134 #define L3_SIZE_KB 0 /* disabled */
135 #define L3_ASSOCIATIVITY 0 /* disabled */
136 #define L3_LINES_PER_TAG 0 /* disabled */
137 #define L3_LINE_SIZE 0 /* disabled */
138
139 /* TLB definitions: */
140
141 #define L1_DTLB_2M_ASSOC 1
142 #define L1_DTLB_2M_ENTRIES 255
143 #define L1_DTLB_4K_ASSOC 1
144 #define L1_DTLB_4K_ENTRIES 255
145
146 #define L1_ITLB_2M_ASSOC 1
147 #define L1_ITLB_2M_ENTRIES 255
148 #define L1_ITLB_4K_ASSOC 1
149 #define L1_ITLB_4K_ENTRIES 255
150
151 #define L2_DTLB_2M_ASSOC 0 /* disabled */
152 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
153 #define L2_DTLB_4K_ASSOC 4
154 #define L2_DTLB_4K_ENTRIES 512
155
156 #define L2_ITLB_2M_ASSOC 0 /* disabled */
157 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
158 #define L2_ITLB_4K_ASSOC 4
159 #define L2_ITLB_4K_ENTRIES 512
160
161
162
163 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165 {
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173 }
174
175 /* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179 static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188 };
189 static const char *ext_feature_name[] = {
190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
191 "ds_cpl", "vmx", "smx", "est",
192 "tm2", "ssse3", "cid", NULL,
193 "fma", "cx16", "xtpr", "pdcm",
194 NULL, "pcid", "dca", "sse4.1|sse4_1",
195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
196 "tsc-deadline", "aes", "xsave", "osxsave",
197 "avx", "f16c", "rdrand", "hypervisor",
198 };
199 /* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
204 static const char *ext2_feature_name[] = {
205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
212 NULL, "lm|i64", "3dnowext", "3dnow",
213 };
214 static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
217 "3dnowprefetch", "osvw", "ibs", "xop",
218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
222 NULL, NULL, NULL, NULL,
223 };
224
225 static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 };
235
236 static const char *kvm_feature_name[] = {
237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 };
246
247 static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 };
257
258 static const char *cpuid_7_0_ebx_feature_name[] = {
259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263 };
264
265 typedef struct FeatureWordInfo {
266 const char **feat_names;
267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
271 } FeatureWordInfo;
272
273 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
307 },
308 };
309
310 typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315 } X86RegisterInfo32;
316
317 #define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
319 X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328 };
329 #undef REGISTER
330
331 typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334 } ExtSaveArea;
335
336 static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
338 .offset = 0x240, .size = 0x100 },
339 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
340 .offset = 0x3c0, .size = 0x40 },
341 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
342 .offset = 0x400, .size = 0x40 },
343 };
344
345 const char *get_register_name_32(unsigned int reg)
346 {
347 if (reg >= CPU_NB_REGS32) {
348 return NULL;
349 }
350 return x86_reg_info_32[reg].name;
351 }
352
353 /* collects per-function cpuid data
354 */
355 typedef struct model_features_t {
356 uint32_t *guest_feat;
357 uint32_t *host_feat;
358 FeatureWord feat_word;
359 } model_features_t;
360
361 /* KVM-specific features that are automatically added to all CPU models
362 * when KVM is enabled.
363 */
364 static uint32_t kvm_default_features[FEATURE_WORDS] = {
365 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
366 (1 << KVM_FEATURE_NOP_IO_DELAY) |
367 (1 << KVM_FEATURE_CLOCKSOURCE2) |
368 (1 << KVM_FEATURE_ASYNC_PF) |
369 (1 << KVM_FEATURE_STEAL_TIME) |
370 (1 << KVM_FEATURE_PV_EOI) |
371 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
372 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
373 };
374
375 void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
376 {
377 kvm_default_features[w] &= ~features;
378 }
379
380 void host_cpuid(uint32_t function, uint32_t count,
381 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
382 {
383 uint32_t vec[4];
384
385 #ifdef __x86_64__
386 asm volatile("cpuid"
387 : "=a"(vec[0]), "=b"(vec[1]),
388 "=c"(vec[2]), "=d"(vec[3])
389 : "0"(function), "c"(count) : "cc");
390 #elif defined(__i386__)
391 asm volatile("pusha \n\t"
392 "cpuid \n\t"
393 "mov %%eax, 0(%2) \n\t"
394 "mov %%ebx, 4(%2) \n\t"
395 "mov %%ecx, 8(%2) \n\t"
396 "mov %%edx, 12(%2) \n\t"
397 "popa"
398 : : "a"(function), "c"(count), "S"(vec)
399 : "memory", "cc");
400 #else
401 abort();
402 #endif
403
404 if (eax)
405 *eax = vec[0];
406 if (ebx)
407 *ebx = vec[1];
408 if (ecx)
409 *ecx = vec[2];
410 if (edx)
411 *edx = vec[3];
412 }
413
414 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
415
416 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
417 * a substring. ex if !NULL points to the first char after a substring,
418 * otherwise the string is assumed to sized by a terminating nul.
419 * Return lexical ordering of *s1:*s2.
420 */
421 static int sstrcmp(const char *s1, const char *e1, const char *s2,
422 const char *e2)
423 {
424 for (;;) {
425 if (!*s1 || !*s2 || *s1 != *s2)
426 return (*s1 - *s2);
427 ++s1, ++s2;
428 if (s1 == e1 && s2 == e2)
429 return (0);
430 else if (s1 == e1)
431 return (*s2);
432 else if (s2 == e2)
433 return (*s1);
434 }
435 }
436
437 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
438 * '|' delimited (possibly empty) strings in which case search for a match
439 * within the alternatives proceeds left to right. Return 0 for success,
440 * non-zero otherwise.
441 */
442 static int altcmp(const char *s, const char *e, const char *altstr)
443 {
444 const char *p, *q;
445
446 for (q = p = altstr; ; ) {
447 while (*p && *p != '|')
448 ++p;
449 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
450 return (0);
451 if (!*p)
452 return (1);
453 else
454 q = ++p;
455 }
456 }
457
458 /* search featureset for flag *[s..e), if found set corresponding bit in
459 * *pval and return true, otherwise return false
460 */
461 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
462 const char **featureset)
463 {
464 uint32_t mask;
465 const char **ppc;
466 bool found = false;
467
468 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
469 if (*ppc && !altcmp(s, e, *ppc)) {
470 *pval |= mask;
471 found = true;
472 }
473 }
474 return found;
475 }
476
477 static void add_flagname_to_bitmaps(const char *flagname,
478 FeatureWordArray words)
479 {
480 FeatureWord w;
481 for (w = 0; w < FEATURE_WORDS; w++) {
482 FeatureWordInfo *wi = &feature_word_info[w];
483 if (wi->feat_names &&
484 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
485 break;
486 }
487 }
488 if (w == FEATURE_WORDS) {
489 fprintf(stderr, "CPU feature %s not found\n", flagname);
490 }
491 }
492
493 /* CPU class name definitions: */
494
495 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
496 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
497
498 /* Return type name for a given CPU model name
499 * Caller is responsible for freeing the returned string.
500 */
501 static char *x86_cpu_type_name(const char *model_name)
502 {
503 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
504 }
505
506 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
507 {
508 ObjectClass *oc;
509 char *typename;
510
511 if (cpu_model == NULL) {
512 return NULL;
513 }
514
515 typename = x86_cpu_type_name(cpu_model);
516 oc = object_class_by_name(typename);
517 g_free(typename);
518 return oc;
519 }
520
521 struct X86CPUDefinition {
522 const char *name;
523 uint32_t level;
524 uint32_t xlevel;
525 uint32_t xlevel2;
526 /* vendor is zero-terminated, 12 character ASCII string */
527 char vendor[CPUID_VENDOR_SZ + 1];
528 int family;
529 int model;
530 int stepping;
531 FeatureWordArray features;
532 char model_id[48];
533 bool cache_info_passthrough;
534 };
535
536 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
537 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
538 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
539 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
540 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
541 CPUID_PSE36 | CPUID_FXSR)
542 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
543 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
544 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
545 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
546 CPUID_PAE | CPUID_SEP | CPUID_APIC)
547
548 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
549 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
550 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
551 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
552 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
553 /* partly implemented:
554 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
555 CPUID_PSE36 (needed for Solaris) */
556 /* missing:
557 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
558 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
559 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
560 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
561 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
562 /* missing:
563 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
564 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
565 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
566 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
567 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
568 CPUID_EXT_RDRAND */
569 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
570 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
571 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
572 /* missing:
573 CPUID_EXT2_PDPE1GB */
574 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
575 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
576 #define TCG_SVM_FEATURES 0
577 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
578 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
579 /* missing:
580 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
581 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
582 CPUID_7_0_EBX_RDSEED */
583
584 static X86CPUDefinition builtin_x86_defs[] = {
585 {
586 .name = "qemu64",
587 .level = 4,
588 .vendor = CPUID_VENDOR_AMD,
589 .family = 6,
590 .model = 6,
591 .stepping = 3,
592 .features[FEAT_1_EDX] =
593 PPRO_FEATURES |
594 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
595 CPUID_PSE36,
596 .features[FEAT_1_ECX] =
597 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
598 .features[FEAT_8000_0001_EDX] =
599 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
600 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
601 .features[FEAT_8000_0001_ECX] =
602 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
603 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
604 .xlevel = 0x8000000A,
605 },
606 {
607 .name = "phenom",
608 .level = 5,
609 .vendor = CPUID_VENDOR_AMD,
610 .family = 16,
611 .model = 2,
612 .stepping = 3,
613 .features[FEAT_1_EDX] =
614 PPRO_FEATURES |
615 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
616 CPUID_PSE36 | CPUID_VME | CPUID_HT,
617 .features[FEAT_1_ECX] =
618 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
619 CPUID_EXT_POPCNT,
620 .features[FEAT_8000_0001_EDX] =
621 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
622 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
623 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
624 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
625 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
626 CPUID_EXT3_CR8LEG,
627 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
628 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
629 .features[FEAT_8000_0001_ECX] =
630 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
631 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
632 .features[FEAT_SVM] =
633 CPUID_SVM_NPT | CPUID_SVM_LBRV,
634 .xlevel = 0x8000001A,
635 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
636 },
637 {
638 .name = "core2duo",
639 .level = 10,
640 .vendor = CPUID_VENDOR_INTEL,
641 .family = 6,
642 .model = 15,
643 .stepping = 11,
644 .features[FEAT_1_EDX] =
645 PPRO_FEATURES |
646 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
647 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
648 CPUID_HT | CPUID_TM | CPUID_PBE,
649 .features[FEAT_1_ECX] =
650 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
651 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
652 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
653 .features[FEAT_8000_0001_EDX] =
654 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
655 .features[FEAT_8000_0001_ECX] =
656 CPUID_EXT3_LAHF_LM,
657 .xlevel = 0x80000008,
658 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
659 },
660 {
661 .name = "kvm64",
662 .level = 5,
663 .vendor = CPUID_VENDOR_INTEL,
664 .family = 15,
665 .model = 6,
666 .stepping = 1,
667 /* Missing: CPUID_VME, CPUID_HT */
668 .features[FEAT_1_EDX] =
669 PPRO_FEATURES |
670 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
671 CPUID_PSE36,
672 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
673 .features[FEAT_1_ECX] =
674 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
675 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
676 .features[FEAT_8000_0001_EDX] =
677 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
678 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
679 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
680 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
681 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
682 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
683 .features[FEAT_8000_0001_ECX] =
684 0,
685 .xlevel = 0x80000008,
686 .model_id = "Common KVM processor"
687 },
688 {
689 .name = "qemu32",
690 .level = 4,
691 .vendor = CPUID_VENDOR_INTEL,
692 .family = 6,
693 .model = 6,
694 .stepping = 3,
695 .features[FEAT_1_EDX] =
696 PPRO_FEATURES,
697 .features[FEAT_1_ECX] =
698 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
699 .xlevel = 0x80000004,
700 },
701 {
702 .name = "kvm32",
703 .level = 5,
704 .vendor = CPUID_VENDOR_INTEL,
705 .family = 15,
706 .model = 6,
707 .stepping = 1,
708 .features[FEAT_1_EDX] =
709 PPRO_FEATURES |
710 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
711 .features[FEAT_1_ECX] =
712 CPUID_EXT_SSE3,
713 .features[FEAT_8000_0001_EDX] =
714 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
715 .features[FEAT_8000_0001_ECX] =
716 0,
717 .xlevel = 0x80000008,
718 .model_id = "Common 32-bit KVM processor"
719 },
720 {
721 .name = "coreduo",
722 .level = 10,
723 .vendor = CPUID_VENDOR_INTEL,
724 .family = 6,
725 .model = 14,
726 .stepping = 8,
727 .features[FEAT_1_EDX] =
728 PPRO_FEATURES | CPUID_VME |
729 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
730 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
731 .features[FEAT_1_ECX] =
732 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
733 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
734 .features[FEAT_8000_0001_EDX] =
735 CPUID_EXT2_NX,
736 .xlevel = 0x80000008,
737 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
738 },
739 {
740 .name = "486",
741 .level = 1,
742 .vendor = CPUID_VENDOR_INTEL,
743 .family = 4,
744 .model = 8,
745 .stepping = 0,
746 .features[FEAT_1_EDX] =
747 I486_FEATURES,
748 .xlevel = 0,
749 },
750 {
751 .name = "pentium",
752 .level = 1,
753 .vendor = CPUID_VENDOR_INTEL,
754 .family = 5,
755 .model = 4,
756 .stepping = 3,
757 .features[FEAT_1_EDX] =
758 PENTIUM_FEATURES,
759 .xlevel = 0,
760 },
761 {
762 .name = "pentium2",
763 .level = 2,
764 .vendor = CPUID_VENDOR_INTEL,
765 .family = 6,
766 .model = 5,
767 .stepping = 2,
768 .features[FEAT_1_EDX] =
769 PENTIUM2_FEATURES,
770 .xlevel = 0,
771 },
772 {
773 .name = "pentium3",
774 .level = 2,
775 .vendor = CPUID_VENDOR_INTEL,
776 .family = 6,
777 .model = 7,
778 .stepping = 3,
779 .features[FEAT_1_EDX] =
780 PENTIUM3_FEATURES,
781 .xlevel = 0,
782 },
783 {
784 .name = "athlon",
785 .level = 2,
786 .vendor = CPUID_VENDOR_AMD,
787 .family = 6,
788 .model = 2,
789 .stepping = 3,
790 .features[FEAT_1_EDX] =
791 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
792 CPUID_MCA,
793 .features[FEAT_8000_0001_EDX] =
794 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
795 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
796 .xlevel = 0x80000008,
797 },
798 {
799 .name = "n270",
800 /* original is on level 10 */
801 .level = 5,
802 .vendor = CPUID_VENDOR_INTEL,
803 .family = 6,
804 .model = 28,
805 .stepping = 2,
806 .features[FEAT_1_EDX] =
807 PPRO_FEATURES |
808 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
809 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
810 /* Some CPUs got no CPUID_SEP */
811 .features[FEAT_1_ECX] =
812 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
813 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
814 CPUID_EXT_MOVBE,
815 .features[FEAT_8000_0001_EDX] =
816 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
817 CPUID_EXT2_NX,
818 .features[FEAT_8000_0001_ECX] =
819 CPUID_EXT3_LAHF_LM,
820 .xlevel = 0x8000000A,
821 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
822 },
823 {
824 .name = "Conroe",
825 .level = 4,
826 .vendor = CPUID_VENDOR_INTEL,
827 .family = 6,
828 .model = 15,
829 .stepping = 3,
830 .features[FEAT_1_EDX] =
831 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
832 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
833 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
834 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
835 CPUID_DE | CPUID_FP87,
836 .features[FEAT_1_ECX] =
837 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
838 .features[FEAT_8000_0001_EDX] =
839 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
840 .features[FEAT_8000_0001_ECX] =
841 CPUID_EXT3_LAHF_LM,
842 .xlevel = 0x8000000A,
843 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
844 },
845 {
846 .name = "Penryn",
847 .level = 4,
848 .vendor = CPUID_VENDOR_INTEL,
849 .family = 6,
850 .model = 23,
851 .stepping = 3,
852 .features[FEAT_1_EDX] =
853 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
854 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
855 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
856 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
857 CPUID_DE | CPUID_FP87,
858 .features[FEAT_1_ECX] =
859 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
860 CPUID_EXT_SSE3,
861 .features[FEAT_8000_0001_EDX] =
862 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
863 .features[FEAT_8000_0001_ECX] =
864 CPUID_EXT3_LAHF_LM,
865 .xlevel = 0x8000000A,
866 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
867 },
868 {
869 .name = "Nehalem",
870 .level = 4,
871 .vendor = CPUID_VENDOR_INTEL,
872 .family = 6,
873 .model = 26,
874 .stepping = 3,
875 .features[FEAT_1_EDX] =
876 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
880 CPUID_DE | CPUID_FP87,
881 .features[FEAT_1_ECX] =
882 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
883 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
884 .features[FEAT_8000_0001_EDX] =
885 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
886 .features[FEAT_8000_0001_ECX] =
887 CPUID_EXT3_LAHF_LM,
888 .xlevel = 0x8000000A,
889 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
890 },
891 {
892 .name = "Westmere",
893 .level = 11,
894 .vendor = CPUID_VENDOR_INTEL,
895 .family = 6,
896 .model = 44,
897 .stepping = 1,
898 .features[FEAT_1_EDX] =
899 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
900 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
901 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
902 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
903 CPUID_DE | CPUID_FP87,
904 .features[FEAT_1_ECX] =
905 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
906 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
907 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
908 .features[FEAT_8000_0001_EDX] =
909 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
910 .features[FEAT_8000_0001_ECX] =
911 CPUID_EXT3_LAHF_LM,
912 .xlevel = 0x8000000A,
913 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
914 },
915 {
916 .name = "SandyBridge",
917 .level = 0xd,
918 .vendor = CPUID_VENDOR_INTEL,
919 .family = 6,
920 .model = 42,
921 .stepping = 1,
922 .features[FEAT_1_EDX] =
923 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
927 CPUID_DE | CPUID_FP87,
928 .features[FEAT_1_ECX] =
929 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
930 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
931 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
932 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
933 CPUID_EXT_SSE3,
934 .features[FEAT_8000_0001_EDX] =
935 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
936 CPUID_EXT2_SYSCALL,
937 .features[FEAT_8000_0001_ECX] =
938 CPUID_EXT3_LAHF_LM,
939 .xlevel = 0x8000000A,
940 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
941 },
942 {
943 .name = "Haswell",
944 .level = 0xd,
945 .vendor = CPUID_VENDOR_INTEL,
946 .family = 6,
947 .model = 60,
948 .stepping = 1,
949 .features[FEAT_1_EDX] =
950 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
954 CPUID_DE | CPUID_FP87,
955 .features[FEAT_1_ECX] =
956 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
957 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
958 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
959 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
960 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
961 CPUID_EXT_PCID,
962 .features[FEAT_8000_0001_EDX] =
963 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
964 CPUID_EXT2_SYSCALL,
965 .features[FEAT_8000_0001_ECX] =
966 CPUID_EXT3_LAHF_LM,
967 .features[FEAT_7_0_EBX] =
968 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
969 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
970 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
971 CPUID_7_0_EBX_RTM,
972 .xlevel = 0x8000000A,
973 .model_id = "Intel Core Processor (Haswell)",
974 },
975 {
976 .name = "Opteron_G1",
977 .level = 5,
978 .vendor = CPUID_VENDOR_AMD,
979 .family = 15,
980 .model = 6,
981 .stepping = 1,
982 .features[FEAT_1_EDX] =
983 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
984 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
985 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
986 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
987 CPUID_DE | CPUID_FP87,
988 .features[FEAT_1_ECX] =
989 CPUID_EXT_SSE3,
990 .features[FEAT_8000_0001_EDX] =
991 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
992 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
993 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
994 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
995 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
996 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
997 .xlevel = 0x80000008,
998 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
999 },
1000 {
1001 .name = "Opteron_G2",
1002 .level = 5,
1003 .vendor = CPUID_VENDOR_AMD,
1004 .family = 15,
1005 .model = 6,
1006 .stepping = 1,
1007 .features[FEAT_1_EDX] =
1008 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1009 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1010 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1011 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1012 CPUID_DE | CPUID_FP87,
1013 .features[FEAT_1_ECX] =
1014 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1015 .features[FEAT_8000_0001_EDX] =
1016 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1017 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1018 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1019 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1020 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1021 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1022 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1023 .features[FEAT_8000_0001_ECX] =
1024 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1025 .xlevel = 0x80000008,
1026 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1027 },
1028 {
1029 .name = "Opteron_G3",
1030 .level = 5,
1031 .vendor = CPUID_VENDOR_AMD,
1032 .family = 15,
1033 .model = 6,
1034 .stepping = 1,
1035 .features[FEAT_1_EDX] =
1036 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1037 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1038 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1039 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1040 CPUID_DE | CPUID_FP87,
1041 .features[FEAT_1_ECX] =
1042 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1043 CPUID_EXT_SSE3,
1044 .features[FEAT_8000_0001_EDX] =
1045 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1046 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1047 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1048 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1049 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1050 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1051 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1052 .features[FEAT_8000_0001_ECX] =
1053 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1054 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1055 .xlevel = 0x80000008,
1056 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1057 },
1058 {
1059 .name = "Opteron_G4",
1060 .level = 0xd,
1061 .vendor = CPUID_VENDOR_AMD,
1062 .family = 21,
1063 .model = 1,
1064 .stepping = 2,
1065 .features[FEAT_1_EDX] =
1066 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1067 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1068 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1069 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1070 CPUID_DE | CPUID_FP87,
1071 .features[FEAT_1_ECX] =
1072 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1073 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1074 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1075 CPUID_EXT_SSE3,
1076 .features[FEAT_8000_0001_EDX] =
1077 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1078 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1079 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1080 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1081 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1082 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1083 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1084 .features[FEAT_8000_0001_ECX] =
1085 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1086 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1087 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1088 CPUID_EXT3_LAHF_LM,
1089 .xlevel = 0x8000001A,
1090 .model_id = "AMD Opteron 62xx class CPU",
1091 },
1092 {
1093 .name = "Opteron_G5",
1094 .level = 0xd,
1095 .vendor = CPUID_VENDOR_AMD,
1096 .family = 21,
1097 .model = 2,
1098 .stepping = 0,
1099 .features[FEAT_1_EDX] =
1100 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1101 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1102 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1103 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1104 CPUID_DE | CPUID_FP87,
1105 .features[FEAT_1_ECX] =
1106 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1107 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1108 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1109 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1110 .features[FEAT_8000_0001_EDX] =
1111 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1112 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1113 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1114 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1115 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1116 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1117 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1118 .features[FEAT_8000_0001_ECX] =
1119 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1120 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1121 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1122 CPUID_EXT3_LAHF_LM,
1123 .xlevel = 0x8000001A,
1124 .model_id = "AMD Opteron 63xx class CPU",
1125 },
1126 };
1127
1128 /**
1129 * x86_cpu_compat_set_features:
1130 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1131 * @w: Identifies the feature word to be changed.
1132 * @feat_add: Feature bits to be added to feature word
1133 * @feat_remove: Feature bits to be removed from feature word
1134 *
1135 * Change CPU model feature bits for compatibility.
1136 *
1137 * This function may be used by machine-type compatibility functions
1138 * to enable or disable feature bits on specific CPU models.
1139 */
1140 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1141 uint32_t feat_add, uint32_t feat_remove)
1142 {
1143 X86CPUDefinition *def;
1144 int i;
1145 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1146 def = &builtin_x86_defs[i];
1147 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1148 def->features[w] |= feat_add;
1149 def->features[w] &= ~feat_remove;
1150 }
1151 }
1152 }
1153
1154 #ifdef CONFIG_KVM
1155
1156 static int cpu_x86_fill_model_id(char *str)
1157 {
1158 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1159 int i;
1160
1161 for (i = 0; i < 3; i++) {
1162 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1163 memcpy(str + i * 16 + 0, &eax, 4);
1164 memcpy(str + i * 16 + 4, &ebx, 4);
1165 memcpy(str + i * 16 + 8, &ecx, 4);
1166 memcpy(str + i * 16 + 12, &edx, 4);
1167 }
1168 return 0;
1169 }
1170
1171 static X86CPUDefinition host_cpudef;
1172
1173 /* class_init for the "host" CPU model
1174 *
1175 * This function may be called before KVM is initialized.
1176 */
1177 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1178 {
1179 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1180 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1181
1182 xcc->kvm_required = true;
1183
1184 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1185 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1186
1187 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1188 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1189 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1190 host_cpudef.stepping = eax & 0x0F;
1191
1192 cpu_x86_fill_model_id(host_cpudef.model_id);
1193
1194 xcc->cpu_def = &host_cpudef;
1195 host_cpudef.cache_info_passthrough = true;
1196
1197 /* level, xlevel, xlevel2, and the feature words are initialized on
1198 * instance_init, because they require KVM to be initialized.
1199 */
1200 }
1201
1202 static void host_x86_cpu_initfn(Object *obj)
1203 {
1204 X86CPU *cpu = X86_CPU(obj);
1205 CPUX86State *env = &cpu->env;
1206 KVMState *s = kvm_state;
1207 FeatureWord w;
1208
1209 assert(kvm_enabled());
1210
1211 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1212 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1213 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1214
1215 for (w = 0; w < FEATURE_WORDS; w++) {
1216 FeatureWordInfo *wi = &feature_word_info[w];
1217 env->features[w] =
1218 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1219 wi->cpuid_reg);
1220 }
1221 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1222 }
1223
1224 static const TypeInfo host_x86_cpu_type_info = {
1225 .name = X86_CPU_TYPE_NAME("host"),
1226 .parent = TYPE_X86_CPU,
1227 .instance_init = host_x86_cpu_initfn,
1228 .class_init = host_x86_cpu_class_init,
1229 };
1230
1231 #endif
1232
1233 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1234 {
1235 int i;
1236
1237 for (i = 0; i < 32; ++i)
1238 if (1 << i & mask) {
1239 const char *reg = get_register_name_32(f->cpuid_reg);
1240 assert(reg);
1241 fprintf(stderr, "warning: host doesn't support requested feature: "
1242 "CPUID.%02XH:%s%s%s [bit %d]\n",
1243 f->cpuid_eax, reg,
1244 f->feat_names[i] ? "." : "",
1245 f->feat_names[i] ? f->feat_names[i] : "", i);
1246 break;
1247 }
1248 return 0;
1249 }
1250
1251 /* Check if all requested cpu flags are making their way to the guest
1252 *
1253 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1254 *
1255 * This function may be called only if KVM is enabled.
1256 */
1257 static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
1258 {
1259 CPUX86State *env = &cpu->env;
1260 int rv = 0;
1261 FeatureWord w;
1262
1263 assert(kvm_enabled());
1264
1265 for (w = 0; w < FEATURE_WORDS; w++) {
1266 FeatureWordInfo *wi = &feature_word_info[w];
1267 uint32_t guest_feat = env->features[w];
1268 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1269 wi->cpuid_ecx,
1270 wi->cpuid_reg);
1271 uint32_t mask;
1272 for (mask = 1; mask; mask <<= 1) {
1273 if (guest_feat & mask && !(host_feat & mask)) {
1274 unavailable_host_feature(wi, mask);
1275 rv = 1;
1276 }
1277 }
1278 }
1279 return rv;
1280 }
1281
1282 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1283 const char *name, Error **errp)
1284 {
1285 X86CPU *cpu = X86_CPU(obj);
1286 CPUX86State *env = &cpu->env;
1287 int64_t value;
1288
1289 value = (env->cpuid_version >> 8) & 0xf;
1290 if (value == 0xf) {
1291 value += (env->cpuid_version >> 20) & 0xff;
1292 }
1293 visit_type_int(v, &value, name, errp);
1294 }
1295
1296 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1297 const char *name, Error **errp)
1298 {
1299 X86CPU *cpu = X86_CPU(obj);
1300 CPUX86State *env = &cpu->env;
1301 const int64_t min = 0;
1302 const int64_t max = 0xff + 0xf;
1303 int64_t value;
1304
1305 visit_type_int(v, &value, name, errp);
1306 if (error_is_set(errp)) {
1307 return;
1308 }
1309 if (value < min || value > max) {
1310 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1311 name ? name : "null", value, min, max);
1312 return;
1313 }
1314
1315 env->cpuid_version &= ~0xff00f00;
1316 if (value > 0x0f) {
1317 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1318 } else {
1319 env->cpuid_version |= value << 8;
1320 }
1321 }
1322
1323 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1324 const char *name, Error **errp)
1325 {
1326 X86CPU *cpu = X86_CPU(obj);
1327 CPUX86State *env = &cpu->env;
1328 int64_t value;
1329
1330 value = (env->cpuid_version >> 4) & 0xf;
1331 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1332 visit_type_int(v, &value, name, errp);
1333 }
1334
1335 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1336 const char *name, Error **errp)
1337 {
1338 X86CPU *cpu = X86_CPU(obj);
1339 CPUX86State *env = &cpu->env;
1340 const int64_t min = 0;
1341 const int64_t max = 0xff;
1342 int64_t value;
1343
1344 visit_type_int(v, &value, name, errp);
1345 if (error_is_set(errp)) {
1346 return;
1347 }
1348 if (value < min || value > max) {
1349 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1350 name ? name : "null", value, min, max);
1351 return;
1352 }
1353
1354 env->cpuid_version &= ~0xf00f0;
1355 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1356 }
1357
1358 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1359 void *opaque, const char *name,
1360 Error **errp)
1361 {
1362 X86CPU *cpu = X86_CPU(obj);
1363 CPUX86State *env = &cpu->env;
1364 int64_t value;
1365
1366 value = env->cpuid_version & 0xf;
1367 visit_type_int(v, &value, name, errp);
1368 }
1369
1370 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1371 void *opaque, const char *name,
1372 Error **errp)
1373 {
1374 X86CPU *cpu = X86_CPU(obj);
1375 CPUX86State *env = &cpu->env;
1376 const int64_t min = 0;
1377 const int64_t max = 0xf;
1378 int64_t value;
1379
1380 visit_type_int(v, &value, name, errp);
1381 if (error_is_set(errp)) {
1382 return;
1383 }
1384 if (value < min || value > max) {
1385 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1386 name ? name : "null", value, min, max);
1387 return;
1388 }
1389
1390 env->cpuid_version &= ~0xf;
1391 env->cpuid_version |= value & 0xf;
1392 }
1393
1394 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1395 const char *name, Error **errp)
1396 {
1397 X86CPU *cpu = X86_CPU(obj);
1398
1399 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1400 }
1401
1402 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1403 const char *name, Error **errp)
1404 {
1405 X86CPU *cpu = X86_CPU(obj);
1406
1407 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1408 }
1409
1410 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1411 const char *name, Error **errp)
1412 {
1413 X86CPU *cpu = X86_CPU(obj);
1414
1415 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1416 }
1417
1418 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1419 const char *name, Error **errp)
1420 {
1421 X86CPU *cpu = X86_CPU(obj);
1422
1423 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1424 }
1425
1426 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1427 {
1428 X86CPU *cpu = X86_CPU(obj);
1429 CPUX86State *env = &cpu->env;
1430 char *value;
1431
1432 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1433 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1434 env->cpuid_vendor3);
1435 return value;
1436 }
1437
1438 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1439 Error **errp)
1440 {
1441 X86CPU *cpu = X86_CPU(obj);
1442 CPUX86State *env = &cpu->env;
1443 int i;
1444
1445 if (strlen(value) != CPUID_VENDOR_SZ) {
1446 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1447 "vendor", value);
1448 return;
1449 }
1450
1451 env->cpuid_vendor1 = 0;
1452 env->cpuid_vendor2 = 0;
1453 env->cpuid_vendor3 = 0;
1454 for (i = 0; i < 4; i++) {
1455 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1456 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1457 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1458 }
1459 }
1460
1461 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1462 {
1463 X86CPU *cpu = X86_CPU(obj);
1464 CPUX86State *env = &cpu->env;
1465 char *value;
1466 int i;
1467
1468 value = g_malloc(48 + 1);
1469 for (i = 0; i < 48; i++) {
1470 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1471 }
1472 value[48] = '\0';
1473 return value;
1474 }
1475
1476 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1477 Error **errp)
1478 {
1479 X86CPU *cpu = X86_CPU(obj);
1480 CPUX86State *env = &cpu->env;
1481 int c, len, i;
1482
1483 if (model_id == NULL) {
1484 model_id = "";
1485 }
1486 len = strlen(model_id);
1487 memset(env->cpuid_model, 0, 48);
1488 for (i = 0; i < 48; i++) {
1489 if (i >= len) {
1490 c = '\0';
1491 } else {
1492 c = (uint8_t)model_id[i];
1493 }
1494 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1495 }
1496 }
1497
1498 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1499 const char *name, Error **errp)
1500 {
1501 X86CPU *cpu = X86_CPU(obj);
1502 int64_t value;
1503
1504 value = cpu->env.tsc_khz * 1000;
1505 visit_type_int(v, &value, name, errp);
1506 }
1507
1508 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1509 const char *name, Error **errp)
1510 {
1511 X86CPU *cpu = X86_CPU(obj);
1512 const int64_t min = 0;
1513 const int64_t max = INT64_MAX;
1514 int64_t value;
1515
1516 visit_type_int(v, &value, name, errp);
1517 if (error_is_set(errp)) {
1518 return;
1519 }
1520 if (value < min || value > max) {
1521 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1522 name ? name : "null", value, min, max);
1523 return;
1524 }
1525
1526 cpu->env.tsc_khz = value / 1000;
1527 }
1528
1529 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1530 const char *name, Error **errp)
1531 {
1532 X86CPU *cpu = X86_CPU(obj);
1533 int64_t value = cpu->env.cpuid_apic_id;
1534
1535 visit_type_int(v, &value, name, errp);
1536 }
1537
1538 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1539 const char *name, Error **errp)
1540 {
1541 X86CPU *cpu = X86_CPU(obj);
1542 DeviceState *dev = DEVICE(obj);
1543 const int64_t min = 0;
1544 const int64_t max = UINT32_MAX;
1545 Error *error = NULL;
1546 int64_t value;
1547
1548 if (dev->realized) {
1549 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1550 "it was realized", name, object_get_typename(obj));
1551 return;
1552 }
1553
1554 visit_type_int(v, &value, name, &error);
1555 if (error) {
1556 error_propagate(errp, error);
1557 return;
1558 }
1559 if (value < min || value > max) {
1560 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1561 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1562 object_get_typename(obj), name, value, min, max);
1563 return;
1564 }
1565
1566 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1567 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1568 return;
1569 }
1570 cpu->env.cpuid_apic_id = value;
1571 }
1572
1573 /* Generic getter for "feature-words" and "filtered-features" properties */
1574 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1575 const char *name, Error **errp)
1576 {
1577 uint32_t *array = (uint32_t *)opaque;
1578 FeatureWord w;
1579 Error *err = NULL;
1580 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1581 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1582 X86CPUFeatureWordInfoList *list = NULL;
1583
1584 for (w = 0; w < FEATURE_WORDS; w++) {
1585 FeatureWordInfo *wi = &feature_word_info[w];
1586 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1587 qwi->cpuid_input_eax = wi->cpuid_eax;
1588 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1589 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1590 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1591 qwi->features = array[w];
1592
1593 /* List will be in reverse order, but order shouldn't matter */
1594 list_entries[w].next = list;
1595 list_entries[w].value = &word_infos[w];
1596 list = &list_entries[w];
1597 }
1598
1599 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1600 error_propagate(errp, err);
1601 }
1602
1603 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1604 const char *name, Error **errp)
1605 {
1606 X86CPU *cpu = X86_CPU(obj);
1607 int64_t value = cpu->hyperv_spinlock_attempts;
1608
1609 visit_type_int(v, &value, name, errp);
1610 }
1611
1612 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1613 const char *name, Error **errp)
1614 {
1615 const int64_t min = 0xFFF;
1616 const int64_t max = UINT_MAX;
1617 X86CPU *cpu = X86_CPU(obj);
1618 Error *err = NULL;
1619 int64_t value;
1620
1621 visit_type_int(v, &value, name, &err);
1622 if (err) {
1623 error_propagate(errp, err);
1624 return;
1625 }
1626
1627 if (value < min || value > max) {
1628 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1629 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1630 object_get_typename(obj), name ? name : "null",
1631 value, min, max);
1632 return;
1633 }
1634 cpu->hyperv_spinlock_attempts = value;
1635 }
1636
1637 static PropertyInfo qdev_prop_spinlocks = {
1638 .name = "int",
1639 .get = x86_get_hv_spinlocks,
1640 .set = x86_set_hv_spinlocks,
1641 };
1642
1643 /* Convert all '_' in a feature string option name to '-', to make feature
1644 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1645 */
1646 static inline void feat2prop(char *s)
1647 {
1648 while ((s = strchr(s, '_'))) {
1649 *s = '-';
1650 }
1651 }
1652
1653 /* Parse "+feature,-feature,feature=foo" CPU feature string
1654 */
1655 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1656 {
1657 char *featurestr; /* Single 'key=value" string being parsed */
1658 /* Features to be added */
1659 FeatureWordArray plus_features = { 0 };
1660 /* Features to be removed */
1661 FeatureWordArray minus_features = { 0 };
1662 uint32_t numvalue;
1663 CPUX86State *env = &cpu->env;
1664
1665 featurestr = features ? strtok(features, ",") : NULL;
1666
1667 while (featurestr) {
1668 char *val;
1669 if (featurestr[0] == '+') {
1670 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1671 } else if (featurestr[0] == '-') {
1672 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1673 } else if ((val = strchr(featurestr, '='))) {
1674 *val = 0; val++;
1675 feat2prop(featurestr);
1676 if (!strcmp(featurestr, "xlevel")) {
1677 char *err;
1678 char num[32];
1679
1680 numvalue = strtoul(val, &err, 0);
1681 if (!*val || *err) {
1682 error_setg(errp, "bad numerical value %s", val);
1683 goto out;
1684 }
1685 if (numvalue < 0x80000000) {
1686 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1687 ", fixup will be removed in future versions\n");
1688 numvalue += 0x80000000;
1689 }
1690 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1691 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1692 } else if (!strcmp(featurestr, "tsc-freq")) {
1693 int64_t tsc_freq;
1694 char *err;
1695 char num[32];
1696
1697 tsc_freq = strtosz_suffix_unit(val, &err,
1698 STRTOSZ_DEFSUFFIX_B, 1000);
1699 if (tsc_freq < 0 || *err) {
1700 error_setg(errp, "bad numerical value %s", val);
1701 goto out;
1702 }
1703 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1704 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1705 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1706 char *err;
1707 const int min = 0xFFF;
1708 char num[32];
1709 numvalue = strtoul(val, &err, 0);
1710 if (!*val || *err) {
1711 error_setg(errp, "bad numerical value %s", val);
1712 goto out;
1713 }
1714 if (numvalue < min) {
1715 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1716 ", fixup will be removed in future versions\n",
1717 min);
1718 numvalue = min;
1719 }
1720 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1721 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1722 } else {
1723 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1724 }
1725 } else {
1726 feat2prop(featurestr);
1727 object_property_parse(OBJECT(cpu), "on", featurestr, errp);
1728 }
1729 if (error_is_set(errp)) {
1730 goto out;
1731 }
1732 featurestr = strtok(NULL, ",");
1733 }
1734 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1735 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1736 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1737 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1738 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1739 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1740 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1741 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1742 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1743 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1744 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1745 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1746 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1747 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1748 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1749 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1750
1751 out:
1752 return;
1753 }
1754
1755 /* generate a composite string into buf of all cpuid names in featureset
1756 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1757 * if flags, suppress names undefined in featureset.
1758 */
1759 static void listflags(char *buf, int bufsize, uint32_t fbits,
1760 const char **featureset, uint32_t flags)
1761 {
1762 const char **p = &featureset[31];
1763 char *q, *b, bit;
1764 int nc;
1765
1766 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1767 *buf = '\0';
1768 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1769 if (fbits & 1 << bit && (*p || !flags)) {
1770 if (*p)
1771 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1772 else
1773 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1774 if (bufsize <= nc) {
1775 if (b) {
1776 memcpy(b, "...", sizeof("..."));
1777 }
1778 return;
1779 }
1780 q += nc;
1781 bufsize -= nc;
1782 }
1783 }
1784
1785 /* generate CPU information. */
1786 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1787 {
1788 X86CPUDefinition *def;
1789 char buf[256];
1790 int i;
1791
1792 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1793 def = &builtin_x86_defs[i];
1794 snprintf(buf, sizeof(buf), "%s", def->name);
1795 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1796 }
1797 #ifdef CONFIG_KVM
1798 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1799 "KVM processor with all supported host features "
1800 "(only available in KVM mode)");
1801 #endif
1802
1803 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1804 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1805 FeatureWordInfo *fw = &feature_word_info[i];
1806
1807 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1808 (*cpu_fprintf)(f, " %s\n", buf);
1809 }
1810 }
1811
1812 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1813 {
1814 CpuDefinitionInfoList *cpu_list = NULL;
1815 X86CPUDefinition *def;
1816 int i;
1817
1818 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1819 CpuDefinitionInfoList *entry;
1820 CpuDefinitionInfo *info;
1821
1822 def = &builtin_x86_defs[i];
1823 info = g_malloc0(sizeof(*info));
1824 info->name = g_strdup(def->name);
1825
1826 entry = g_malloc0(sizeof(*entry));
1827 entry->value = info;
1828 entry->next = cpu_list;
1829 cpu_list = entry;
1830 }
1831
1832 return cpu_list;
1833 }
1834
1835 static void filter_features_for_kvm(X86CPU *cpu)
1836 {
1837 CPUX86State *env = &cpu->env;
1838 KVMState *s = kvm_state;
1839 FeatureWord w;
1840
1841 for (w = 0; w < FEATURE_WORDS; w++) {
1842 FeatureWordInfo *wi = &feature_word_info[w];
1843 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1844 wi->cpuid_ecx,
1845 wi->cpuid_reg);
1846 uint32_t requested_features = env->features[w];
1847 env->features[w] &= host_feat;
1848 cpu->filtered_features[w] = requested_features & ~env->features[w];
1849 }
1850 }
1851
1852 /* Load data from X86CPUDefinition
1853 */
1854 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1855 {
1856 CPUX86State *env = &cpu->env;
1857 const char *vendor;
1858 char host_vendor[CPUID_VENDOR_SZ + 1];
1859
1860 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1861 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1862 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1863 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1864 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1865 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1866 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1867 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1868 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1869 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1870 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1871 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1872 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1873 env->cpuid_xlevel2 = def->xlevel2;
1874 cpu->cache_info_passthrough = def->cache_info_passthrough;
1875
1876 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1877
1878 /* Special cases not set in the X86CPUDefinition structs: */
1879 if (kvm_enabled()) {
1880 FeatureWord w;
1881 for (w = 0; w < FEATURE_WORDS; w++) {
1882 env->features[w] |= kvm_default_features[w];
1883 }
1884 }
1885
1886 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1887
1888 /* sysenter isn't supported in compatibility mode on AMD,
1889 * syscall isn't supported in compatibility mode on Intel.
1890 * Normally we advertise the actual CPU vendor, but you can
1891 * override this using the 'vendor' property if you want to use
1892 * KVM's sysenter/syscall emulation in compatibility mode and
1893 * when doing cross vendor migration
1894 */
1895 vendor = def->vendor;
1896 if (kvm_enabled()) {
1897 uint32_t ebx = 0, ecx = 0, edx = 0;
1898 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1899 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1900 vendor = host_vendor;
1901 }
1902
1903 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1904
1905 }
1906
1907 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1908 Error **errp)
1909 {
1910 X86CPU *cpu = NULL;
1911 X86CPUClass *xcc;
1912 ObjectClass *oc;
1913 gchar **model_pieces;
1914 char *name, *features;
1915 Error *error = NULL;
1916
1917 model_pieces = g_strsplit(cpu_model, ",", 2);
1918 if (!model_pieces[0]) {
1919 error_setg(&error, "Invalid/empty CPU model name");
1920 goto out;
1921 }
1922 name = model_pieces[0];
1923 features = model_pieces[1];
1924
1925 oc = x86_cpu_class_by_name(name);
1926 if (oc == NULL) {
1927 error_setg(&error, "Unable to find CPU definition: %s", name);
1928 goto out;
1929 }
1930 xcc = X86_CPU_CLASS(oc);
1931
1932 if (xcc->kvm_required && !kvm_enabled()) {
1933 error_setg(&error, "CPU model '%s' requires KVM", name);
1934 goto out;
1935 }
1936
1937 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1938
1939 #ifndef CONFIG_USER_ONLY
1940 if (icc_bridge == NULL) {
1941 error_setg(&error, "Invalid icc-bridge value");
1942 goto out;
1943 }
1944 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1945 object_unref(OBJECT(cpu));
1946 #endif
1947
1948 cpu_x86_parse_featurestr(cpu, features, &error);
1949 if (error) {
1950 goto out;
1951 }
1952
1953 out:
1954 if (error != NULL) {
1955 error_propagate(errp, error);
1956 if (cpu) {
1957 object_unref(OBJECT(cpu));
1958 cpu = NULL;
1959 }
1960 }
1961 g_strfreev(model_pieces);
1962 return cpu;
1963 }
1964
1965 X86CPU *cpu_x86_init(const char *cpu_model)
1966 {
1967 Error *error = NULL;
1968 X86CPU *cpu;
1969
1970 cpu = cpu_x86_create(cpu_model, NULL, &error);
1971 if (error) {
1972 goto out;
1973 }
1974
1975 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1976
1977 out:
1978 if (error) {
1979 error_report("%s", error_get_pretty(error));
1980 error_free(error);
1981 if (cpu != NULL) {
1982 object_unref(OBJECT(cpu));
1983 cpu = NULL;
1984 }
1985 }
1986 return cpu;
1987 }
1988
1989 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
1990 {
1991 X86CPUDefinition *cpudef = data;
1992 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1993
1994 xcc->cpu_def = cpudef;
1995 }
1996
1997 static void x86_register_cpudef_type(X86CPUDefinition *def)
1998 {
1999 char *typename = x86_cpu_type_name(def->name);
2000 TypeInfo ti = {
2001 .name = typename,
2002 .parent = TYPE_X86_CPU,
2003 .class_init = x86_cpu_cpudef_class_init,
2004 .class_data = def,
2005 };
2006
2007 type_register(&ti);
2008 g_free(typename);
2009 }
2010
2011 #if !defined(CONFIG_USER_ONLY)
2012
2013 void cpu_clear_apic_feature(CPUX86State *env)
2014 {
2015 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2016 }
2017
2018 #endif /* !CONFIG_USER_ONLY */
2019
2020 /* Initialize list of CPU models, filling some non-static fields if necessary
2021 */
2022 void x86_cpudef_setup(void)
2023 {
2024 int i, j;
2025 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2026
2027 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2028 X86CPUDefinition *def = &builtin_x86_defs[i];
2029
2030 /* Look for specific "cpudef" models that */
2031 /* have the QEMU version in .model_id */
2032 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2033 if (strcmp(model_with_versions[j], def->name) == 0) {
2034 pstrcpy(def->model_id, sizeof(def->model_id),
2035 "QEMU Virtual CPU version ");
2036 pstrcat(def->model_id, sizeof(def->model_id),
2037 qemu_get_version());
2038 break;
2039 }
2040 }
2041 }
2042 }
2043
2044 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2045 uint32_t *ecx, uint32_t *edx)
2046 {
2047 *ebx = env->cpuid_vendor1;
2048 *edx = env->cpuid_vendor2;
2049 *ecx = env->cpuid_vendor3;
2050 }
2051
2052 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2053 uint32_t *eax, uint32_t *ebx,
2054 uint32_t *ecx, uint32_t *edx)
2055 {
2056 X86CPU *cpu = x86_env_get_cpu(env);
2057 CPUState *cs = CPU(cpu);
2058
2059 /* test if maximum index reached */
2060 if (index & 0x80000000) {
2061 if (index > env->cpuid_xlevel) {
2062 if (env->cpuid_xlevel2 > 0) {
2063 /* Handle the Centaur's CPUID instruction. */
2064 if (index > env->cpuid_xlevel2) {
2065 index = env->cpuid_xlevel2;
2066 } else if (index < 0xC0000000) {
2067 index = env->cpuid_xlevel;
2068 }
2069 } else {
2070 /* Intel documentation states that invalid EAX input will
2071 * return the same information as EAX=cpuid_level
2072 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2073 */
2074 index = env->cpuid_level;
2075 }
2076 }
2077 } else {
2078 if (index > env->cpuid_level)
2079 index = env->cpuid_level;
2080 }
2081
2082 switch(index) {
2083 case 0:
2084 *eax = env->cpuid_level;
2085 get_cpuid_vendor(env, ebx, ecx, edx);
2086 break;
2087 case 1:
2088 *eax = env->cpuid_version;
2089 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2090 *ecx = env->features[FEAT_1_ECX];
2091 *edx = env->features[FEAT_1_EDX];
2092 if (cs->nr_cores * cs->nr_threads > 1) {
2093 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2094 *edx |= 1 << 28; /* HTT bit */
2095 }
2096 break;
2097 case 2:
2098 /* cache info: needed for Pentium Pro compatibility */
2099 if (cpu->cache_info_passthrough) {
2100 host_cpuid(index, 0, eax, ebx, ecx, edx);
2101 break;
2102 }
2103 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2104 *ebx = 0;
2105 *ecx = 0;
2106 *edx = (L1D_DESCRIPTOR << 16) | \
2107 (L1I_DESCRIPTOR << 8) | \
2108 (L2_DESCRIPTOR);
2109 break;
2110 case 4:
2111 /* cache info: needed for Core compatibility */
2112 if (cpu->cache_info_passthrough) {
2113 host_cpuid(index, count, eax, ebx, ecx, edx);
2114 *eax &= ~0xFC000000;
2115 } else {
2116 *eax = 0;
2117 switch (count) {
2118 case 0: /* L1 dcache info */
2119 *eax |= CPUID_4_TYPE_DCACHE | \
2120 CPUID_4_LEVEL(1) | \
2121 CPUID_4_SELF_INIT_LEVEL;
2122 *ebx = (L1D_LINE_SIZE - 1) | \
2123 ((L1D_PARTITIONS - 1) << 12) | \
2124 ((L1D_ASSOCIATIVITY - 1) << 22);
2125 *ecx = L1D_SETS - 1;
2126 *edx = CPUID_4_NO_INVD_SHARING;
2127 break;
2128 case 1: /* L1 icache info */
2129 *eax |= CPUID_4_TYPE_ICACHE | \
2130 CPUID_4_LEVEL(1) | \
2131 CPUID_4_SELF_INIT_LEVEL;
2132 *ebx = (L1I_LINE_SIZE - 1) | \
2133 ((L1I_PARTITIONS - 1) << 12) | \
2134 ((L1I_ASSOCIATIVITY - 1) << 22);
2135 *ecx = L1I_SETS - 1;
2136 *edx = CPUID_4_NO_INVD_SHARING;
2137 break;
2138 case 2: /* L2 cache info */
2139 *eax |= CPUID_4_TYPE_UNIFIED | \
2140 CPUID_4_LEVEL(2) | \
2141 CPUID_4_SELF_INIT_LEVEL;
2142 if (cs->nr_threads > 1) {
2143 *eax |= (cs->nr_threads - 1) << 14;
2144 }
2145 *ebx = (L2_LINE_SIZE - 1) | \
2146 ((L2_PARTITIONS - 1) << 12) | \
2147 ((L2_ASSOCIATIVITY - 1) << 22);
2148 *ecx = L2_SETS - 1;
2149 *edx = CPUID_4_NO_INVD_SHARING;
2150 break;
2151 default: /* end of info */
2152 *eax = 0;
2153 *ebx = 0;
2154 *ecx = 0;
2155 *edx = 0;
2156 break;
2157 }
2158 }
2159
2160 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2161 if ((*eax & 31) && cs->nr_cores > 1) {
2162 *eax |= (cs->nr_cores - 1) << 26;
2163 }
2164 break;
2165 case 5:
2166 /* mwait info: needed for Core compatibility */
2167 *eax = 0; /* Smallest monitor-line size in bytes */
2168 *ebx = 0; /* Largest monitor-line size in bytes */
2169 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2170 *edx = 0;
2171 break;
2172 case 6:
2173 /* Thermal and Power Leaf */
2174 *eax = 0;
2175 *ebx = 0;
2176 *ecx = 0;
2177 *edx = 0;
2178 break;
2179 case 7:
2180 /* Structured Extended Feature Flags Enumeration Leaf */
2181 if (count == 0) {
2182 *eax = 0; /* Maximum ECX value for sub-leaves */
2183 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2184 *ecx = 0; /* Reserved */
2185 *edx = 0; /* Reserved */
2186 } else {
2187 *eax = 0;
2188 *ebx = 0;
2189 *ecx = 0;
2190 *edx = 0;
2191 }
2192 break;
2193 case 9:
2194 /* Direct Cache Access Information Leaf */
2195 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2196 *ebx = 0;
2197 *ecx = 0;
2198 *edx = 0;
2199 break;
2200 case 0xA:
2201 /* Architectural Performance Monitoring Leaf */
2202 if (kvm_enabled() && cpu->enable_pmu) {
2203 KVMState *s = cs->kvm_state;
2204
2205 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2206 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2207 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2208 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2209 } else {
2210 *eax = 0;
2211 *ebx = 0;
2212 *ecx = 0;
2213 *edx = 0;
2214 }
2215 break;
2216 case 0xD: {
2217 KVMState *s = cs->kvm_state;
2218 uint64_t kvm_mask;
2219 int i;
2220
2221 /* Processor Extended State */
2222 *eax = 0;
2223 *ebx = 0;
2224 *ecx = 0;
2225 *edx = 0;
2226 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2227 break;
2228 }
2229 kvm_mask =
2230 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2231 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2232
2233 if (count == 0) {
2234 *ecx = 0x240;
2235 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2236 const ExtSaveArea *esa = &ext_save_areas[i];
2237 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2238 (kvm_mask & (1 << i)) != 0) {
2239 if (i < 32) {
2240 *eax |= 1 << i;
2241 } else {
2242 *edx |= 1 << (i - 32);
2243 }
2244 *ecx = MAX(*ecx, esa->offset + esa->size);
2245 }
2246 }
2247 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2248 *ebx = *ecx;
2249 } else if (count == 1) {
2250 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2251 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2252 const ExtSaveArea *esa = &ext_save_areas[count];
2253 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2254 (kvm_mask & (1 << count)) != 0) {
2255 *eax = esa->size;
2256 *ebx = esa->offset;
2257 }
2258 }
2259 break;
2260 }
2261 case 0x80000000:
2262 *eax = env->cpuid_xlevel;
2263 *ebx = env->cpuid_vendor1;
2264 *edx = env->cpuid_vendor2;
2265 *ecx = env->cpuid_vendor3;
2266 break;
2267 case 0x80000001:
2268 *eax = env->cpuid_version;
2269 *ebx = 0;
2270 *ecx = env->features[FEAT_8000_0001_ECX];
2271 *edx = env->features[FEAT_8000_0001_EDX];
2272
2273 /* The Linux kernel checks for the CMPLegacy bit and
2274 * discards multiple thread information if it is set.
2275 * So dont set it here for Intel to make Linux guests happy.
2276 */
2277 if (cs->nr_cores * cs->nr_threads > 1) {
2278 uint32_t tebx, tecx, tedx;
2279 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2280 if (tebx != CPUID_VENDOR_INTEL_1 ||
2281 tedx != CPUID_VENDOR_INTEL_2 ||
2282 tecx != CPUID_VENDOR_INTEL_3) {
2283 *ecx |= 1 << 1; /* CmpLegacy bit */
2284 }
2285 }
2286 break;
2287 case 0x80000002:
2288 case 0x80000003:
2289 case 0x80000004:
2290 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2291 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2292 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2293 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2294 break;
2295 case 0x80000005:
2296 /* cache info (L1 cache) */
2297 if (cpu->cache_info_passthrough) {
2298 host_cpuid(index, 0, eax, ebx, ecx, edx);
2299 break;
2300 }
2301 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2302 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2303 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2304 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2305 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2306 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2307 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2308 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2309 break;
2310 case 0x80000006:
2311 /* cache info (L2 cache) */
2312 if (cpu->cache_info_passthrough) {
2313 host_cpuid(index, 0, eax, ebx, ecx, edx);
2314 break;
2315 }
2316 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2317 (L2_DTLB_2M_ENTRIES << 16) | \
2318 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2319 (L2_ITLB_2M_ENTRIES);
2320 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2321 (L2_DTLB_4K_ENTRIES << 16) | \
2322 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2323 (L2_ITLB_4K_ENTRIES);
2324 *ecx = (L2_SIZE_KB_AMD << 16) | \
2325 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2326 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2327 *edx = ((L3_SIZE_KB/512) << 18) | \
2328 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2329 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2330 break;
2331 case 0x80000008:
2332 /* virtual & phys address size in low 2 bytes. */
2333 /* XXX: This value must match the one used in the MMU code. */
2334 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2335 /* 64 bit processor */
2336 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2337 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2338 } else {
2339 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2340 *eax = 0x00000024; /* 36 bits physical */
2341 } else {
2342 *eax = 0x00000020; /* 32 bits physical */
2343 }
2344 }
2345 *ebx = 0;
2346 *ecx = 0;
2347 *edx = 0;
2348 if (cs->nr_cores * cs->nr_threads > 1) {
2349 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2350 }
2351 break;
2352 case 0x8000000A:
2353 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2354 *eax = 0x00000001; /* SVM Revision */
2355 *ebx = 0x00000010; /* nr of ASIDs */
2356 *ecx = 0;
2357 *edx = env->features[FEAT_SVM]; /* optional features */
2358 } else {
2359 *eax = 0;
2360 *ebx = 0;
2361 *ecx = 0;
2362 *edx = 0;
2363 }
2364 break;
2365 case 0xC0000000:
2366 *eax = env->cpuid_xlevel2;
2367 *ebx = 0;
2368 *ecx = 0;
2369 *edx = 0;
2370 break;
2371 case 0xC0000001:
2372 /* Support for VIA CPU's CPUID instruction */
2373 *eax = env->cpuid_version;
2374 *ebx = 0;
2375 *ecx = 0;
2376 *edx = env->features[FEAT_C000_0001_EDX];
2377 break;
2378 case 0xC0000002:
2379 case 0xC0000003:
2380 case 0xC0000004:
2381 /* Reserved for the future, and now filled with zero */
2382 *eax = 0;
2383 *ebx = 0;
2384 *ecx = 0;
2385 *edx = 0;
2386 break;
2387 default:
2388 /* reserved values: zero */
2389 *eax = 0;
2390 *ebx = 0;
2391 *ecx = 0;
2392 *edx = 0;
2393 break;
2394 }
2395 }
2396
2397 /* CPUClass::reset() */
2398 static void x86_cpu_reset(CPUState *s)
2399 {
2400 X86CPU *cpu = X86_CPU(s);
2401 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2402 CPUX86State *env = &cpu->env;
2403 int i;
2404
2405 xcc->parent_reset(s);
2406
2407
2408 memset(env, 0, offsetof(CPUX86State, breakpoints));
2409
2410 tlb_flush(env, 1);
2411
2412 env->old_exception = -1;
2413
2414 /* init to reset state */
2415
2416 #ifdef CONFIG_SOFTMMU
2417 env->hflags |= HF_SOFTMMU_MASK;
2418 #endif
2419 env->hflags2 |= HF2_GIF_MASK;
2420
2421 cpu_x86_update_cr0(env, 0x60000010);
2422 env->a20_mask = ~0x0;
2423 env->smbase = 0x30000;
2424
2425 env->idt.limit = 0xffff;
2426 env->gdt.limit = 0xffff;
2427 env->ldt.limit = 0xffff;
2428 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2429 env->tr.limit = 0xffff;
2430 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2431
2432 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2433 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2434 DESC_R_MASK | DESC_A_MASK);
2435 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2436 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2437 DESC_A_MASK);
2438 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2439 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2440 DESC_A_MASK);
2441 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2442 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2443 DESC_A_MASK);
2444 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2445 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2446 DESC_A_MASK);
2447 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2448 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2449 DESC_A_MASK);
2450
2451 env->eip = 0xfff0;
2452 env->regs[R_EDX] = env->cpuid_version;
2453
2454 env->eflags = 0x2;
2455
2456 /* FPU init */
2457 for (i = 0; i < 8; i++) {
2458 env->fptags[i] = 1;
2459 }
2460 env->fpuc = 0x37f;
2461
2462 env->mxcsr = 0x1f80;
2463 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2464
2465 env->pat = 0x0007040600070406ULL;
2466 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2467
2468 memset(env->dr, 0, sizeof(env->dr));
2469 env->dr[6] = DR6_FIXED_1;
2470 env->dr[7] = DR7_FIXED_1;
2471 cpu_breakpoint_remove_all(env, BP_CPU);
2472 cpu_watchpoint_remove_all(env, BP_CPU);
2473
2474 env->tsc_adjust = 0;
2475 env->tsc = 0;
2476
2477 #if !defined(CONFIG_USER_ONLY)
2478 /* We hard-wire the BSP to the first CPU. */
2479 if (s->cpu_index == 0) {
2480 apic_designate_bsp(cpu->apic_state);
2481 }
2482
2483 s->halted = !cpu_is_bsp(cpu);
2484 #endif
2485 }
2486
2487 #ifndef CONFIG_USER_ONLY
2488 bool cpu_is_bsp(X86CPU *cpu)
2489 {
2490 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2491 }
2492
2493 /* TODO: remove me, when reset over QOM tree is implemented */
2494 static void x86_cpu_machine_reset_cb(void *opaque)
2495 {
2496 X86CPU *cpu = opaque;
2497 cpu_reset(CPU(cpu));
2498 }
2499 #endif
2500
2501 static void mce_init(X86CPU *cpu)
2502 {
2503 CPUX86State *cenv = &cpu->env;
2504 unsigned int bank;
2505
2506 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2507 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2508 (CPUID_MCE | CPUID_MCA)) {
2509 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2510 cenv->mcg_ctl = ~(uint64_t)0;
2511 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2512 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2513 }
2514 }
2515 }
2516
2517 #ifndef CONFIG_USER_ONLY
2518 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2519 {
2520 CPUX86State *env = &cpu->env;
2521 DeviceState *dev = DEVICE(cpu);
2522 APICCommonState *apic;
2523 const char *apic_type = "apic";
2524
2525 if (kvm_irqchip_in_kernel()) {
2526 apic_type = "kvm-apic";
2527 } else if (xen_enabled()) {
2528 apic_type = "xen-apic";
2529 }
2530
2531 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2532 if (cpu->apic_state == NULL) {
2533 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2534 return;
2535 }
2536
2537 object_property_add_child(OBJECT(cpu), "apic",
2538 OBJECT(cpu->apic_state), NULL);
2539 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2540 /* TODO: convert to link<> */
2541 apic = APIC_COMMON(cpu->apic_state);
2542 apic->cpu = cpu;
2543 }
2544
2545 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2546 {
2547 if (cpu->apic_state == NULL) {
2548 return;
2549 }
2550
2551 if (qdev_init(cpu->apic_state)) {
2552 error_setg(errp, "APIC device '%s' could not be initialized",
2553 object_get_typename(OBJECT(cpu->apic_state)));
2554 return;
2555 }
2556 }
2557 #else
2558 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2559 {
2560 }
2561 #endif
2562
2563 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2564 {
2565 CPUState *cs = CPU(dev);
2566 X86CPU *cpu = X86_CPU(dev);
2567 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2568 CPUX86State *env = &cpu->env;
2569 Error *local_err = NULL;
2570
2571 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2572 env->cpuid_level = 7;
2573 }
2574
2575 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2576 * CPUID[1].EDX.
2577 */
2578 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2579 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2580 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2581 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2582 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2583 & CPUID_EXT2_AMD_ALIASES);
2584 }
2585
2586 if (!kvm_enabled()) {
2587 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2588 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2589 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2590 #ifdef TARGET_X86_64
2591 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2592 #endif
2593 );
2594 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2595 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2596 } else {
2597 KVMState *s = kvm_state;
2598 if ((cpu->check_cpuid || cpu->enforce_cpuid)
2599 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
2600 error_setg(&local_err,
2601 "Host's CPU doesn't support requested features");
2602 goto out;
2603 }
2604 filter_features_for_kvm(cpu);
2605 }
2606
2607 #ifndef CONFIG_USER_ONLY
2608 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2609
2610 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2611 x86_cpu_apic_create(cpu, &local_err);
2612 if (local_err != NULL) {
2613 goto out;
2614 }
2615 }
2616 #endif
2617
2618 mce_init(cpu);
2619 qemu_init_vcpu(cs);
2620
2621 x86_cpu_apic_realize(cpu, &local_err);
2622 if (local_err != NULL) {
2623 goto out;
2624 }
2625 cpu_reset(cs);
2626
2627 xcc->parent_realize(dev, &local_err);
2628 out:
2629 if (local_err != NULL) {
2630 error_propagate(errp, local_err);
2631 return;
2632 }
2633 }
2634
2635 /* Enables contiguous-apic-ID mode, for compatibility */
2636 static bool compat_apic_id_mode;
2637
2638 void enable_compat_apic_id_mode(void)
2639 {
2640 compat_apic_id_mode = true;
2641 }
2642
2643 /* Calculates initial APIC ID for a specific CPU index
2644 *
2645 * Currently we need to be able to calculate the APIC ID from the CPU index
2646 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2647 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2648 * all CPUs up to max_cpus.
2649 */
2650 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2651 {
2652 uint32_t correct_id;
2653 static bool warned;
2654
2655 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2656 if (compat_apic_id_mode) {
2657 if (cpu_index != correct_id && !warned) {
2658 error_report("APIC IDs set in compatibility mode, "
2659 "CPU topology won't match the configuration");
2660 warned = true;
2661 }
2662 return cpu_index;
2663 } else {
2664 return correct_id;
2665 }
2666 }
2667
2668 static void x86_cpu_initfn(Object *obj)
2669 {
2670 CPUState *cs = CPU(obj);
2671 X86CPU *cpu = X86_CPU(obj);
2672 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2673 CPUX86State *env = &cpu->env;
2674 static int inited;
2675
2676 cs->env_ptr = env;
2677 cpu_exec_init(env);
2678
2679 object_property_add(obj, "family", "int",
2680 x86_cpuid_version_get_family,
2681 x86_cpuid_version_set_family, NULL, NULL, NULL);
2682 object_property_add(obj, "model", "int",
2683 x86_cpuid_version_get_model,
2684 x86_cpuid_version_set_model, NULL, NULL, NULL);
2685 object_property_add(obj, "stepping", "int",
2686 x86_cpuid_version_get_stepping,
2687 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2688 object_property_add(obj, "level", "int",
2689 x86_cpuid_get_level,
2690 x86_cpuid_set_level, NULL, NULL, NULL);
2691 object_property_add(obj, "xlevel", "int",
2692 x86_cpuid_get_xlevel,
2693 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2694 object_property_add_str(obj, "vendor",
2695 x86_cpuid_get_vendor,
2696 x86_cpuid_set_vendor, NULL);
2697 object_property_add_str(obj, "model-id",
2698 x86_cpuid_get_model_id,
2699 x86_cpuid_set_model_id, NULL);
2700 object_property_add(obj, "tsc-frequency", "int",
2701 x86_cpuid_get_tsc_freq,
2702 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2703 object_property_add(obj, "apic-id", "int",
2704 x86_cpuid_get_apic_id,
2705 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2706 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2707 x86_cpu_get_feature_words,
2708 NULL, NULL, (void *)env->features, NULL);
2709 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2710 x86_cpu_get_feature_words,
2711 NULL, NULL, (void *)cpu->filtered_features, NULL);
2712
2713 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2714 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2715
2716 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2717
2718 /* init various static tables used in TCG mode */
2719 if (tcg_enabled() && !inited) {
2720 inited = 1;
2721 optimize_flags_init();
2722 #ifndef CONFIG_USER_ONLY
2723 cpu_set_debug_excp_handler(breakpoint_handler);
2724 #endif
2725 }
2726 }
2727
2728 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2729 {
2730 X86CPU *cpu = X86_CPU(cs);
2731 CPUX86State *env = &cpu->env;
2732
2733 return env->cpuid_apic_id;
2734 }
2735
2736 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2737 {
2738 X86CPU *cpu = X86_CPU(cs);
2739
2740 return cpu->env.cr[0] & CR0_PG_MASK;
2741 }
2742
2743 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2744 {
2745 X86CPU *cpu = X86_CPU(cs);
2746
2747 cpu->env.eip = value;
2748 }
2749
2750 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2751 {
2752 X86CPU *cpu = X86_CPU(cs);
2753
2754 cpu->env.eip = tb->pc - tb->cs_base;
2755 }
2756
2757 static bool x86_cpu_has_work(CPUState *cs)
2758 {
2759 X86CPU *cpu = X86_CPU(cs);
2760 CPUX86State *env = &cpu->env;
2761
2762 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2763 CPU_INTERRUPT_POLL)) &&
2764 (env->eflags & IF_MASK)) ||
2765 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2766 CPU_INTERRUPT_INIT |
2767 CPU_INTERRUPT_SIPI |
2768 CPU_INTERRUPT_MCE));
2769 }
2770
2771 static Property x86_cpu_properties[] = {
2772 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2773 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2774 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2775 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2776 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2777 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2778 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2779 DEFINE_PROP_END_OF_LIST()
2780 };
2781
2782 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2783 {
2784 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2785 CPUClass *cc = CPU_CLASS(oc);
2786 DeviceClass *dc = DEVICE_CLASS(oc);
2787
2788 xcc->parent_realize = dc->realize;
2789 dc->realize = x86_cpu_realizefn;
2790 dc->bus_type = TYPE_ICC_BUS;
2791 dc->props = x86_cpu_properties;
2792
2793 xcc->parent_reset = cc->reset;
2794 cc->reset = x86_cpu_reset;
2795 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2796
2797 cc->class_by_name = x86_cpu_class_by_name;
2798 cc->has_work = x86_cpu_has_work;
2799 cc->do_interrupt = x86_cpu_do_interrupt;
2800 cc->dump_state = x86_cpu_dump_state;
2801 cc->set_pc = x86_cpu_set_pc;
2802 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2803 cc->gdb_read_register = x86_cpu_gdb_read_register;
2804 cc->gdb_write_register = x86_cpu_gdb_write_register;
2805 cc->get_arch_id = x86_cpu_get_arch_id;
2806 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2807 #ifndef CONFIG_USER_ONLY
2808 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2809 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2810 cc->write_elf64_note = x86_cpu_write_elf64_note;
2811 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2812 cc->write_elf32_note = x86_cpu_write_elf32_note;
2813 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2814 cc->vmsd = &vmstate_x86_cpu;
2815 #endif
2816 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2817 }
2818
2819 static const TypeInfo x86_cpu_type_info = {
2820 .name = TYPE_X86_CPU,
2821 .parent = TYPE_CPU,
2822 .instance_size = sizeof(X86CPU),
2823 .instance_init = x86_cpu_initfn,
2824 .abstract = true,
2825 .class_size = sizeof(X86CPUClass),
2826 .class_init = x86_cpu_common_class_init,
2827 };
2828
2829 static void x86_cpu_register_types(void)
2830 {
2831 int i;
2832
2833 type_register_static(&x86_cpu_type_info);
2834 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2835 x86_register_cpudef_type(&builtin_x86_defs[i]);
2836 }
2837 #ifdef CONFIG_KVM
2838 type_register_static(&host_x86_cpu_type_info);
2839 #endif
2840 }
2841
2842 type_init(x86_cpu_register_types)
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