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target-i386: do not special case TSC writeback
[mirror_qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
49 #endif
50
51
52 /* Cache topology CPUID constants: */
53
54 /* CPUID Leaf 2 Descriptors */
55
56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
58 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61 /* CPUID Leaf 4 constants: */
62
63 /* EAX: */
64 #define CPUID_4_TYPE_DCACHE 1
65 #define CPUID_4_TYPE_ICACHE 2
66 #define CPUID_4_TYPE_UNIFIED 3
67
68 #define CPUID_4_LEVEL(l) ((l) << 5)
69
70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71 #define CPUID_4_FULLY_ASSOC (1 << 9)
72
73 /* EDX: */
74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
75 #define CPUID_4_INCLUSIVE (1 << 1)
76 #define CPUID_4_COMPLEX_IDX (1 << 2)
77
78 #define ASSOC_FULL 0xFF
79
80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95 /* Definitions of the hardcoded cache entries we expose: */
96
97 /* L1 data cache: */
98 #define L1D_LINE_SIZE 64
99 #define L1D_ASSOCIATIVITY 8
100 #define L1D_SETS 64
101 #define L1D_PARTITIONS 1
102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105 #define L1D_LINES_PER_TAG 1
106 #define L1D_SIZE_KB_AMD 64
107 #define L1D_ASSOCIATIVITY_AMD 2
108
109 /* L1 instruction cache: */
110 #define L1I_LINE_SIZE 64
111 #define L1I_ASSOCIATIVITY 8
112 #define L1I_SETS 64
113 #define L1I_PARTITIONS 1
114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117 #define L1I_LINES_PER_TAG 1
118 #define L1I_SIZE_KB_AMD 64
119 #define L1I_ASSOCIATIVITY_AMD 2
120
121 /* Level 2 unified cache: */
122 #define L2_LINE_SIZE 64
123 #define L2_ASSOCIATIVITY 16
124 #define L2_SETS 4096
125 #define L2_PARTITIONS 1
126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130 #define L2_LINES_PER_TAG 1
131 #define L2_SIZE_KB_AMD 512
132
133 /* No L3 cache: */
134 #define L3_SIZE_KB 0 /* disabled */
135 #define L3_ASSOCIATIVITY 0 /* disabled */
136 #define L3_LINES_PER_TAG 0 /* disabled */
137 #define L3_LINE_SIZE 0 /* disabled */
138
139 /* TLB definitions: */
140
141 #define L1_DTLB_2M_ASSOC 1
142 #define L1_DTLB_2M_ENTRIES 255
143 #define L1_DTLB_4K_ASSOC 1
144 #define L1_DTLB_4K_ENTRIES 255
145
146 #define L1_ITLB_2M_ASSOC 1
147 #define L1_ITLB_2M_ENTRIES 255
148 #define L1_ITLB_4K_ASSOC 1
149 #define L1_ITLB_4K_ENTRIES 255
150
151 #define L2_DTLB_2M_ASSOC 0 /* disabled */
152 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
153 #define L2_DTLB_4K_ASSOC 4
154 #define L2_DTLB_4K_ENTRIES 512
155
156 #define L2_ITLB_2M_ASSOC 0 /* disabled */
157 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
158 #define L2_ITLB_4K_ASSOC 4
159 #define L2_ITLB_4K_ENTRIES 512
160
161
162
163 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165 {
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173 }
174
175 /* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179 static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188 };
189 static const char *ext_feature_name[] = {
190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
191 "ds_cpl", "vmx", "smx", "est",
192 "tm2", "ssse3", "cid", NULL,
193 "fma", "cx16", "xtpr", "pdcm",
194 NULL, "pcid", "dca", "sse4.1|sse4_1",
195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
196 "tsc-deadline", "aes", "xsave", "osxsave",
197 "avx", "f16c", "rdrand", "hypervisor",
198 };
199 /* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
204 static const char *ext2_feature_name[] = {
205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
212 NULL, "lm|i64", "3dnowext", "3dnow",
213 };
214 static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
217 "3dnowprefetch", "osvw", "ibs", "xop",
218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
222 NULL, NULL, NULL, NULL,
223 };
224
225 static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 };
235
236 static const char *kvm_feature_name[] = {
237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 };
246
247 static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 };
257
258 static const char *cpuid_7_0_ebx_feature_name[] = {
259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263 };
264
265 typedef struct FeatureWordInfo {
266 const char **feat_names;
267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
271 } FeatureWordInfo;
272
273 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
307 },
308 };
309
310 typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315 } X86RegisterInfo32;
316
317 #define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg }
319 X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328 };
329 #undef REGISTER
330
331 typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334 } ExtSaveArea;
335
336 static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
338 .offset = 0x240, .size = 0x100 },
339 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
340 .offset = 0x3c0, .size = 0x40 },
341 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
342 .offset = 0x400, .size = 0x10 },
343 };
344
345 const char *get_register_name_32(unsigned int reg)
346 {
347 if (reg >= CPU_NB_REGS32) {
348 return NULL;
349 }
350 return x86_reg_info_32[reg].name;
351 }
352
353 /* collects per-function cpuid data
354 */
355 typedef struct model_features_t {
356 uint32_t *guest_feat;
357 uint32_t *host_feat;
358 FeatureWord feat_word;
359 } model_features_t;
360
361 int check_cpuid = 0;
362 int enforce_cpuid = 0;
363
364 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
365 (1 << KVM_FEATURE_NOP_IO_DELAY) |
366 (1 << KVM_FEATURE_CLOCKSOURCE2) |
367 (1 << KVM_FEATURE_ASYNC_PF) |
368 (1 << KVM_FEATURE_STEAL_TIME) |
369 (1 << KVM_FEATURE_PV_EOI) |
370 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
371
372 void disable_kvm_pv_eoi(void)
373 {
374 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
375 }
376
377 void host_cpuid(uint32_t function, uint32_t count,
378 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
379 {
380 #if defined(CONFIG_KVM)
381 uint32_t vec[4];
382
383 #ifdef __x86_64__
384 asm volatile("cpuid"
385 : "=a"(vec[0]), "=b"(vec[1]),
386 "=c"(vec[2]), "=d"(vec[3])
387 : "0"(function), "c"(count) : "cc");
388 #else
389 asm volatile("pusha \n\t"
390 "cpuid \n\t"
391 "mov %%eax, 0(%2) \n\t"
392 "mov %%ebx, 4(%2) \n\t"
393 "mov %%ecx, 8(%2) \n\t"
394 "mov %%edx, 12(%2) \n\t"
395 "popa"
396 : : "a"(function), "c"(count), "S"(vec)
397 : "memory", "cc");
398 #endif
399
400 if (eax)
401 *eax = vec[0];
402 if (ebx)
403 *ebx = vec[1];
404 if (ecx)
405 *ecx = vec[2];
406 if (edx)
407 *edx = vec[3];
408 #endif
409 }
410
411 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
412
413 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
414 * a substring. ex if !NULL points to the first char after a substring,
415 * otherwise the string is assumed to sized by a terminating nul.
416 * Return lexical ordering of *s1:*s2.
417 */
418 static int sstrcmp(const char *s1, const char *e1, const char *s2,
419 const char *e2)
420 {
421 for (;;) {
422 if (!*s1 || !*s2 || *s1 != *s2)
423 return (*s1 - *s2);
424 ++s1, ++s2;
425 if (s1 == e1 && s2 == e2)
426 return (0);
427 else if (s1 == e1)
428 return (*s2);
429 else if (s2 == e2)
430 return (*s1);
431 }
432 }
433
434 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
435 * '|' delimited (possibly empty) strings in which case search for a match
436 * within the alternatives proceeds left to right. Return 0 for success,
437 * non-zero otherwise.
438 */
439 static int altcmp(const char *s, const char *e, const char *altstr)
440 {
441 const char *p, *q;
442
443 for (q = p = altstr; ; ) {
444 while (*p && *p != '|')
445 ++p;
446 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
447 return (0);
448 if (!*p)
449 return (1);
450 else
451 q = ++p;
452 }
453 }
454
455 /* search featureset for flag *[s..e), if found set corresponding bit in
456 * *pval and return true, otherwise return false
457 */
458 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
459 const char **featureset)
460 {
461 uint32_t mask;
462 const char **ppc;
463 bool found = false;
464
465 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
466 if (*ppc && !altcmp(s, e, *ppc)) {
467 *pval |= mask;
468 found = true;
469 }
470 }
471 return found;
472 }
473
474 static void add_flagname_to_bitmaps(const char *flagname,
475 FeatureWordArray words)
476 {
477 FeatureWord w;
478 for (w = 0; w < FEATURE_WORDS; w++) {
479 FeatureWordInfo *wi = &feature_word_info[w];
480 if (wi->feat_names &&
481 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
482 break;
483 }
484 }
485 if (w == FEATURE_WORDS) {
486 fprintf(stderr, "CPU feature %s not found\n", flagname);
487 }
488 }
489
490 typedef struct x86_def_t {
491 const char *name;
492 uint32_t level;
493 uint32_t xlevel;
494 uint32_t xlevel2;
495 /* vendor is zero-terminated, 12 character ASCII string */
496 char vendor[CPUID_VENDOR_SZ + 1];
497 int family;
498 int model;
499 int stepping;
500 FeatureWordArray features;
501 char model_id[48];
502 bool cache_info_passthrough;
503 } x86_def_t;
504
505 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
506 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
507 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
508 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
509 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
510 CPUID_PSE36 | CPUID_FXSR)
511 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
512 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
513 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
514 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
515 CPUID_PAE | CPUID_SEP | CPUID_APIC)
516
517 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
518 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
519 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
520 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
521 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
522 /* partly implemented:
523 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
524 CPUID_PSE36 (needed for Solaris) */
525 /* missing:
526 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
527 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
528 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
529 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
530 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
531 /* missing:
532 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
533 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
534 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
535 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
536 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
537 CPUID_EXT_RDRAND */
538 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
539 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
540 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
541 /* missing:
542 CPUID_EXT2_PDPE1GB */
543 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
544 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
545 #define TCG_SVM_FEATURES 0
546 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
547 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
548 /* missing:
549 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
550 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
551 CPUID_7_0_EBX_RDSEED */
552
553 /* built-in CPU model definitions
554 */
555 static x86_def_t builtin_x86_defs[] = {
556 {
557 .name = "qemu64",
558 .level = 4,
559 .vendor = CPUID_VENDOR_AMD,
560 .family = 6,
561 .model = 6,
562 .stepping = 3,
563 .features[FEAT_1_EDX] =
564 PPRO_FEATURES |
565 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
566 CPUID_PSE36,
567 .features[FEAT_1_ECX] =
568 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
569 .features[FEAT_8000_0001_EDX] =
570 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
571 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
572 .features[FEAT_8000_0001_ECX] =
573 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
574 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
575 .xlevel = 0x8000000A,
576 },
577 {
578 .name = "phenom",
579 .level = 5,
580 .vendor = CPUID_VENDOR_AMD,
581 .family = 16,
582 .model = 2,
583 .stepping = 3,
584 .features[FEAT_1_EDX] =
585 PPRO_FEATURES |
586 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
587 CPUID_PSE36 | CPUID_VME | CPUID_HT,
588 .features[FEAT_1_ECX] =
589 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
590 CPUID_EXT_POPCNT,
591 .features[FEAT_8000_0001_EDX] =
592 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
593 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
594 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
595 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
596 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
597 CPUID_EXT3_CR8LEG,
598 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
599 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
600 .features[FEAT_8000_0001_ECX] =
601 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
602 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
603 .features[FEAT_SVM] =
604 CPUID_SVM_NPT | CPUID_SVM_LBRV,
605 .xlevel = 0x8000001A,
606 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
607 },
608 {
609 .name = "core2duo",
610 .level = 10,
611 .vendor = CPUID_VENDOR_INTEL,
612 .family = 6,
613 .model = 15,
614 .stepping = 11,
615 .features[FEAT_1_EDX] =
616 PPRO_FEATURES |
617 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
618 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
619 CPUID_HT | CPUID_TM | CPUID_PBE,
620 .features[FEAT_1_ECX] =
621 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
622 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
623 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
624 .features[FEAT_8000_0001_EDX] =
625 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
626 .features[FEAT_8000_0001_ECX] =
627 CPUID_EXT3_LAHF_LM,
628 .xlevel = 0x80000008,
629 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
630 },
631 {
632 .name = "kvm64",
633 .level = 5,
634 .vendor = CPUID_VENDOR_INTEL,
635 .family = 15,
636 .model = 6,
637 .stepping = 1,
638 /* Missing: CPUID_VME, CPUID_HT */
639 .features[FEAT_1_EDX] =
640 PPRO_FEATURES |
641 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
642 CPUID_PSE36,
643 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
644 .features[FEAT_1_ECX] =
645 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
646 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
647 .features[FEAT_8000_0001_EDX] =
648 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
649 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
650 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
651 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
652 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
653 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
654 .features[FEAT_8000_0001_ECX] =
655 0,
656 .xlevel = 0x80000008,
657 .model_id = "Common KVM processor"
658 },
659 {
660 .name = "qemu32",
661 .level = 4,
662 .vendor = CPUID_VENDOR_INTEL,
663 .family = 6,
664 .model = 6,
665 .stepping = 3,
666 .features[FEAT_1_EDX] =
667 PPRO_FEATURES,
668 .features[FEAT_1_ECX] =
669 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
670 .xlevel = 0x80000004,
671 },
672 {
673 .name = "kvm32",
674 .level = 5,
675 .vendor = CPUID_VENDOR_INTEL,
676 .family = 15,
677 .model = 6,
678 .stepping = 1,
679 .features[FEAT_1_EDX] =
680 PPRO_FEATURES |
681 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
682 .features[FEAT_1_ECX] =
683 CPUID_EXT_SSE3,
684 .features[FEAT_8000_0001_EDX] =
685 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
686 .features[FEAT_8000_0001_ECX] =
687 0,
688 .xlevel = 0x80000008,
689 .model_id = "Common 32-bit KVM processor"
690 },
691 {
692 .name = "coreduo",
693 .level = 10,
694 .vendor = CPUID_VENDOR_INTEL,
695 .family = 6,
696 .model = 14,
697 .stepping = 8,
698 .features[FEAT_1_EDX] =
699 PPRO_FEATURES | CPUID_VME |
700 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
701 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
702 .features[FEAT_1_ECX] =
703 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
704 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
705 .features[FEAT_8000_0001_EDX] =
706 CPUID_EXT2_NX,
707 .xlevel = 0x80000008,
708 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
709 },
710 {
711 .name = "486",
712 .level = 1,
713 .vendor = CPUID_VENDOR_INTEL,
714 .family = 4,
715 .model = 8,
716 .stepping = 0,
717 .features[FEAT_1_EDX] =
718 I486_FEATURES,
719 .xlevel = 0,
720 },
721 {
722 .name = "pentium",
723 .level = 1,
724 .vendor = CPUID_VENDOR_INTEL,
725 .family = 5,
726 .model = 4,
727 .stepping = 3,
728 .features[FEAT_1_EDX] =
729 PENTIUM_FEATURES,
730 .xlevel = 0,
731 },
732 {
733 .name = "pentium2",
734 .level = 2,
735 .vendor = CPUID_VENDOR_INTEL,
736 .family = 6,
737 .model = 5,
738 .stepping = 2,
739 .features[FEAT_1_EDX] =
740 PENTIUM2_FEATURES,
741 .xlevel = 0,
742 },
743 {
744 .name = "pentium3",
745 .level = 2,
746 .vendor = CPUID_VENDOR_INTEL,
747 .family = 6,
748 .model = 7,
749 .stepping = 3,
750 .features[FEAT_1_EDX] =
751 PENTIUM3_FEATURES,
752 .xlevel = 0,
753 },
754 {
755 .name = "athlon",
756 .level = 2,
757 .vendor = CPUID_VENDOR_AMD,
758 .family = 6,
759 .model = 2,
760 .stepping = 3,
761 .features[FEAT_1_EDX] =
762 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
763 CPUID_MCA,
764 .features[FEAT_8000_0001_EDX] =
765 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
766 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
767 .xlevel = 0x80000008,
768 },
769 {
770 .name = "n270",
771 /* original is on level 10 */
772 .level = 5,
773 .vendor = CPUID_VENDOR_INTEL,
774 .family = 6,
775 .model = 28,
776 .stepping = 2,
777 .features[FEAT_1_EDX] =
778 PPRO_FEATURES |
779 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
780 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
781 /* Some CPUs got no CPUID_SEP */
782 .features[FEAT_1_ECX] =
783 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
784 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
785 CPUID_EXT_MOVBE,
786 .features[FEAT_8000_0001_EDX] =
787 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
788 CPUID_EXT2_NX,
789 .features[FEAT_8000_0001_ECX] =
790 CPUID_EXT3_LAHF_LM,
791 .xlevel = 0x8000000A,
792 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
793 },
794 {
795 .name = "Conroe",
796 .level = 4,
797 .vendor = CPUID_VENDOR_INTEL,
798 .family = 6,
799 .model = 15,
800 .stepping = 3,
801 .features[FEAT_1_EDX] =
802 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
803 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
804 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
805 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
806 CPUID_DE | CPUID_FP87,
807 .features[FEAT_1_ECX] =
808 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
809 .features[FEAT_8000_0001_EDX] =
810 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
811 .features[FEAT_8000_0001_ECX] =
812 CPUID_EXT3_LAHF_LM,
813 .xlevel = 0x8000000A,
814 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
815 },
816 {
817 .name = "Penryn",
818 .level = 4,
819 .vendor = CPUID_VENDOR_INTEL,
820 .family = 6,
821 .model = 23,
822 .stepping = 3,
823 .features[FEAT_1_EDX] =
824 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
825 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
826 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
827 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
828 CPUID_DE | CPUID_FP87,
829 .features[FEAT_1_ECX] =
830 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
831 CPUID_EXT_SSE3,
832 .features[FEAT_8000_0001_EDX] =
833 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
834 .features[FEAT_8000_0001_ECX] =
835 CPUID_EXT3_LAHF_LM,
836 .xlevel = 0x8000000A,
837 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
838 },
839 {
840 .name = "Nehalem",
841 .level = 4,
842 .vendor = CPUID_VENDOR_INTEL,
843 .family = 6,
844 .model = 26,
845 .stepping = 3,
846 .features[FEAT_1_EDX] =
847 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
848 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
849 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
850 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
851 CPUID_DE | CPUID_FP87,
852 .features[FEAT_1_ECX] =
853 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
854 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
855 .features[FEAT_8000_0001_EDX] =
856 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
857 .features[FEAT_8000_0001_ECX] =
858 CPUID_EXT3_LAHF_LM,
859 .xlevel = 0x8000000A,
860 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
861 },
862 {
863 .name = "Westmere",
864 .level = 11,
865 .vendor = CPUID_VENDOR_INTEL,
866 .family = 6,
867 .model = 44,
868 .stepping = 1,
869 .features[FEAT_1_EDX] =
870 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
871 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
872 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
873 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
874 CPUID_DE | CPUID_FP87,
875 .features[FEAT_1_ECX] =
876 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
877 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
878 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
879 .features[FEAT_8000_0001_EDX] =
880 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
881 .features[FEAT_8000_0001_ECX] =
882 CPUID_EXT3_LAHF_LM,
883 .xlevel = 0x8000000A,
884 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
885 },
886 {
887 .name = "SandyBridge",
888 .level = 0xd,
889 .vendor = CPUID_VENDOR_INTEL,
890 .family = 6,
891 .model = 42,
892 .stepping = 1,
893 .features[FEAT_1_EDX] =
894 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
895 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
896 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
897 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
898 CPUID_DE | CPUID_FP87,
899 .features[FEAT_1_ECX] =
900 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
901 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
902 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
903 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
904 CPUID_EXT_SSE3,
905 .features[FEAT_8000_0001_EDX] =
906 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
907 CPUID_EXT2_SYSCALL,
908 .features[FEAT_8000_0001_ECX] =
909 CPUID_EXT3_LAHF_LM,
910 .xlevel = 0x8000000A,
911 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
912 },
913 {
914 .name = "Haswell",
915 .level = 0xd,
916 .vendor = CPUID_VENDOR_INTEL,
917 .family = 6,
918 .model = 60,
919 .stepping = 1,
920 .features[FEAT_1_EDX] =
921 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
922 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
923 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
924 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
925 CPUID_DE | CPUID_FP87,
926 .features[FEAT_1_ECX] =
927 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
928 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
929 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
930 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
931 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
932 CPUID_EXT_PCID,
933 .features[FEAT_8000_0001_EDX] =
934 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
935 CPUID_EXT2_SYSCALL,
936 .features[FEAT_8000_0001_ECX] =
937 CPUID_EXT3_LAHF_LM,
938 .features[FEAT_7_0_EBX] =
939 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
940 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
941 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
942 CPUID_7_0_EBX_RTM,
943 .xlevel = 0x8000000A,
944 .model_id = "Intel Core Processor (Haswell)",
945 },
946 {
947 .name = "Opteron_G1",
948 .level = 5,
949 .vendor = CPUID_VENDOR_AMD,
950 .family = 15,
951 .model = 6,
952 .stepping = 1,
953 .features[FEAT_1_EDX] =
954 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
955 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
956 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
957 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
958 CPUID_DE | CPUID_FP87,
959 .features[FEAT_1_ECX] =
960 CPUID_EXT_SSE3,
961 .features[FEAT_8000_0001_EDX] =
962 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
963 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
964 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
965 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
966 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
967 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
968 .xlevel = 0x80000008,
969 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
970 },
971 {
972 .name = "Opteron_G2",
973 .level = 5,
974 .vendor = CPUID_VENDOR_AMD,
975 .family = 15,
976 .model = 6,
977 .stepping = 1,
978 .features[FEAT_1_EDX] =
979 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
980 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
981 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
982 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
983 CPUID_DE | CPUID_FP87,
984 .features[FEAT_1_ECX] =
985 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
986 .features[FEAT_8000_0001_EDX] =
987 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
988 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
989 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
990 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
991 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
992 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
993 CPUID_EXT2_DE | CPUID_EXT2_FPU,
994 .features[FEAT_8000_0001_ECX] =
995 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
996 .xlevel = 0x80000008,
997 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
998 },
999 {
1000 .name = "Opteron_G3",
1001 .level = 5,
1002 .vendor = CPUID_VENDOR_AMD,
1003 .family = 15,
1004 .model = 6,
1005 .stepping = 1,
1006 .features[FEAT_1_EDX] =
1007 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1008 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1009 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1010 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1011 CPUID_DE | CPUID_FP87,
1012 .features[FEAT_1_ECX] =
1013 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1014 CPUID_EXT_SSE3,
1015 .features[FEAT_8000_0001_EDX] =
1016 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1017 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1018 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1019 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1020 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1021 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1022 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1023 .features[FEAT_8000_0001_ECX] =
1024 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1025 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1026 .xlevel = 0x80000008,
1027 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1028 },
1029 {
1030 .name = "Opteron_G4",
1031 .level = 0xd,
1032 .vendor = CPUID_VENDOR_AMD,
1033 .family = 21,
1034 .model = 1,
1035 .stepping = 2,
1036 .features[FEAT_1_EDX] =
1037 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1038 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1039 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1040 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1041 CPUID_DE | CPUID_FP87,
1042 .features[FEAT_1_ECX] =
1043 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1044 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1045 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1046 CPUID_EXT_SSE3,
1047 .features[FEAT_8000_0001_EDX] =
1048 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1049 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1050 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1051 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1052 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1053 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1054 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1055 .features[FEAT_8000_0001_ECX] =
1056 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1057 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1058 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1059 CPUID_EXT3_LAHF_LM,
1060 .xlevel = 0x8000001A,
1061 .model_id = "AMD Opteron 62xx class CPU",
1062 },
1063 {
1064 .name = "Opteron_G5",
1065 .level = 0xd,
1066 .vendor = CPUID_VENDOR_AMD,
1067 .family = 21,
1068 .model = 2,
1069 .stepping = 0,
1070 .features[FEAT_1_EDX] =
1071 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1072 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1073 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1074 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1075 CPUID_DE | CPUID_FP87,
1076 .features[FEAT_1_ECX] =
1077 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1078 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1079 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1080 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1081 .features[FEAT_8000_0001_EDX] =
1082 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1083 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1084 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1085 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1086 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1087 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1088 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1089 .features[FEAT_8000_0001_ECX] =
1090 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1091 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1092 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1093 CPUID_EXT3_LAHF_LM,
1094 .xlevel = 0x8000001A,
1095 .model_id = "AMD Opteron 63xx class CPU",
1096 },
1097 };
1098
1099 /**
1100 * x86_cpu_compat_set_features:
1101 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1102 * @w: Identifies the feature word to be changed.
1103 * @feat_add: Feature bits to be added to feature word
1104 * @feat_remove: Feature bits to be removed from feature word
1105 *
1106 * Change CPU model feature bits for compatibility.
1107 *
1108 * This function may be used by machine-type compatibility functions
1109 * to enable or disable feature bits on specific CPU models.
1110 */
1111 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1112 uint32_t feat_add, uint32_t feat_remove)
1113 {
1114 x86_def_t *def;
1115 int i;
1116 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1117 def = &builtin_x86_defs[i];
1118 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1119 def->features[w] |= feat_add;
1120 def->features[w] &= ~feat_remove;
1121 }
1122 }
1123 }
1124
1125 #ifdef CONFIG_KVM
1126 static int cpu_x86_fill_model_id(char *str)
1127 {
1128 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1129 int i;
1130
1131 for (i = 0; i < 3; i++) {
1132 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1133 memcpy(str + i * 16 + 0, &eax, 4);
1134 memcpy(str + i * 16 + 4, &ebx, 4);
1135 memcpy(str + i * 16 + 8, &ecx, 4);
1136 memcpy(str + i * 16 + 12, &edx, 4);
1137 }
1138 return 0;
1139 }
1140 #endif
1141
1142 /* Fill a x86_def_t struct with information about the host CPU, and
1143 * the CPU features supported by the host hardware + host kernel
1144 *
1145 * This function may be called only if KVM is enabled.
1146 */
1147 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
1148 {
1149 #ifdef CONFIG_KVM
1150 KVMState *s = kvm_state;
1151 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1152
1153 assert(kvm_enabled());
1154
1155 x86_cpu_def->name = "host";
1156 x86_cpu_def->cache_info_passthrough = true;
1157 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1158 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1159
1160 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1161 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1162 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1163 x86_cpu_def->stepping = eax & 0x0F;
1164
1165 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1166 x86_cpu_def->features[FEAT_1_EDX] =
1167 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
1168 x86_cpu_def->features[FEAT_1_ECX] =
1169 kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
1170
1171 if (x86_cpu_def->level >= 7) {
1172 x86_cpu_def->features[FEAT_7_0_EBX] =
1173 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
1174 } else {
1175 x86_cpu_def->features[FEAT_7_0_EBX] = 0;
1176 }
1177
1178 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1179 x86_cpu_def->features[FEAT_8000_0001_EDX] =
1180 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1181 x86_cpu_def->features[FEAT_8000_0001_ECX] =
1182 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1183
1184 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1185
1186 /* Call Centaur's CPUID instruction. */
1187 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
1188 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
1189 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1190 if (eax >= 0xC0000001) {
1191 /* Support VIA max extended level */
1192 x86_cpu_def->xlevel2 = eax;
1193 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
1194 x86_cpu_def->features[FEAT_C000_0001_EDX] =
1195 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1196 }
1197 }
1198
1199 /* Other KVM-specific feature fields: */
1200 x86_cpu_def->features[FEAT_SVM] =
1201 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1202 x86_cpu_def->features[FEAT_KVM] =
1203 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1204
1205 #endif /* CONFIG_KVM */
1206 }
1207
1208 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1209 {
1210 int i;
1211
1212 for (i = 0; i < 32; ++i)
1213 if (1 << i & mask) {
1214 const char *reg = get_register_name_32(f->cpuid_reg);
1215 assert(reg);
1216 fprintf(stderr, "warning: host doesn't support requested feature: "
1217 "CPUID.%02XH:%s%s%s [bit %d]\n",
1218 f->cpuid_eax, reg,
1219 f->feat_names[i] ? "." : "",
1220 f->feat_names[i] ? f->feat_names[i] : "", i);
1221 break;
1222 }
1223 return 0;
1224 }
1225
1226 /* Check if all requested cpu flags are making their way to the guest
1227 *
1228 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1229 *
1230 * This function may be called only if KVM is enabled.
1231 */
1232 static int kvm_check_features_against_host(X86CPU *cpu)
1233 {
1234 CPUX86State *env = &cpu->env;
1235 x86_def_t host_def;
1236 uint32_t mask;
1237 int rv, i;
1238 struct model_features_t ft[] = {
1239 {&env->features[FEAT_1_EDX],
1240 &host_def.features[FEAT_1_EDX],
1241 FEAT_1_EDX },
1242 {&env->features[FEAT_1_ECX],
1243 &host_def.features[FEAT_1_ECX],
1244 FEAT_1_ECX },
1245 {&env->features[FEAT_8000_0001_EDX],
1246 &host_def.features[FEAT_8000_0001_EDX],
1247 FEAT_8000_0001_EDX },
1248 {&env->features[FEAT_8000_0001_ECX],
1249 &host_def.features[FEAT_8000_0001_ECX],
1250 FEAT_8000_0001_ECX },
1251 {&env->features[FEAT_C000_0001_EDX],
1252 &host_def.features[FEAT_C000_0001_EDX],
1253 FEAT_C000_0001_EDX },
1254 {&env->features[FEAT_7_0_EBX],
1255 &host_def.features[FEAT_7_0_EBX],
1256 FEAT_7_0_EBX },
1257 {&env->features[FEAT_SVM],
1258 &host_def.features[FEAT_SVM],
1259 FEAT_SVM },
1260 {&env->features[FEAT_KVM],
1261 &host_def.features[FEAT_KVM],
1262 FEAT_KVM },
1263 };
1264
1265 assert(kvm_enabled());
1266
1267 kvm_cpu_fill_host(&host_def);
1268 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1269 FeatureWord w = ft[i].feat_word;
1270 FeatureWordInfo *wi = &feature_word_info[w];
1271 for (mask = 1; mask; mask <<= 1) {
1272 if (*ft[i].guest_feat & mask &&
1273 !(*ft[i].host_feat & mask)) {
1274 unavailable_host_feature(wi, mask);
1275 rv = 1;
1276 }
1277 }
1278 }
1279 return rv;
1280 }
1281
1282 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1283 const char *name, Error **errp)
1284 {
1285 X86CPU *cpu = X86_CPU(obj);
1286 CPUX86State *env = &cpu->env;
1287 int64_t value;
1288
1289 value = (env->cpuid_version >> 8) & 0xf;
1290 if (value == 0xf) {
1291 value += (env->cpuid_version >> 20) & 0xff;
1292 }
1293 visit_type_int(v, &value, name, errp);
1294 }
1295
1296 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1297 const char *name, Error **errp)
1298 {
1299 X86CPU *cpu = X86_CPU(obj);
1300 CPUX86State *env = &cpu->env;
1301 const int64_t min = 0;
1302 const int64_t max = 0xff + 0xf;
1303 int64_t value;
1304
1305 visit_type_int(v, &value, name, errp);
1306 if (error_is_set(errp)) {
1307 return;
1308 }
1309 if (value < min || value > max) {
1310 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1311 name ? name : "null", value, min, max);
1312 return;
1313 }
1314
1315 env->cpuid_version &= ~0xff00f00;
1316 if (value > 0x0f) {
1317 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1318 } else {
1319 env->cpuid_version |= value << 8;
1320 }
1321 }
1322
1323 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1324 const char *name, Error **errp)
1325 {
1326 X86CPU *cpu = X86_CPU(obj);
1327 CPUX86State *env = &cpu->env;
1328 int64_t value;
1329
1330 value = (env->cpuid_version >> 4) & 0xf;
1331 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1332 visit_type_int(v, &value, name, errp);
1333 }
1334
1335 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1336 const char *name, Error **errp)
1337 {
1338 X86CPU *cpu = X86_CPU(obj);
1339 CPUX86State *env = &cpu->env;
1340 const int64_t min = 0;
1341 const int64_t max = 0xff;
1342 int64_t value;
1343
1344 visit_type_int(v, &value, name, errp);
1345 if (error_is_set(errp)) {
1346 return;
1347 }
1348 if (value < min || value > max) {
1349 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1350 name ? name : "null", value, min, max);
1351 return;
1352 }
1353
1354 env->cpuid_version &= ~0xf00f0;
1355 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1356 }
1357
1358 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1359 void *opaque, const char *name,
1360 Error **errp)
1361 {
1362 X86CPU *cpu = X86_CPU(obj);
1363 CPUX86State *env = &cpu->env;
1364 int64_t value;
1365
1366 value = env->cpuid_version & 0xf;
1367 visit_type_int(v, &value, name, errp);
1368 }
1369
1370 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1371 void *opaque, const char *name,
1372 Error **errp)
1373 {
1374 X86CPU *cpu = X86_CPU(obj);
1375 CPUX86State *env = &cpu->env;
1376 const int64_t min = 0;
1377 const int64_t max = 0xf;
1378 int64_t value;
1379
1380 visit_type_int(v, &value, name, errp);
1381 if (error_is_set(errp)) {
1382 return;
1383 }
1384 if (value < min || value > max) {
1385 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1386 name ? name : "null", value, min, max);
1387 return;
1388 }
1389
1390 env->cpuid_version &= ~0xf;
1391 env->cpuid_version |= value & 0xf;
1392 }
1393
1394 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1395 const char *name, Error **errp)
1396 {
1397 X86CPU *cpu = X86_CPU(obj);
1398
1399 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1400 }
1401
1402 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1403 const char *name, Error **errp)
1404 {
1405 X86CPU *cpu = X86_CPU(obj);
1406
1407 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1408 }
1409
1410 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1411 const char *name, Error **errp)
1412 {
1413 X86CPU *cpu = X86_CPU(obj);
1414
1415 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1416 }
1417
1418 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1419 const char *name, Error **errp)
1420 {
1421 X86CPU *cpu = X86_CPU(obj);
1422
1423 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1424 }
1425
1426 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1427 {
1428 X86CPU *cpu = X86_CPU(obj);
1429 CPUX86State *env = &cpu->env;
1430 char *value;
1431
1432 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1433 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1434 env->cpuid_vendor3);
1435 return value;
1436 }
1437
1438 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1439 Error **errp)
1440 {
1441 X86CPU *cpu = X86_CPU(obj);
1442 CPUX86State *env = &cpu->env;
1443 int i;
1444
1445 if (strlen(value) != CPUID_VENDOR_SZ) {
1446 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1447 "vendor", value);
1448 return;
1449 }
1450
1451 env->cpuid_vendor1 = 0;
1452 env->cpuid_vendor2 = 0;
1453 env->cpuid_vendor3 = 0;
1454 for (i = 0; i < 4; i++) {
1455 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1456 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1457 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1458 }
1459 }
1460
1461 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1462 {
1463 X86CPU *cpu = X86_CPU(obj);
1464 CPUX86State *env = &cpu->env;
1465 char *value;
1466 int i;
1467
1468 value = g_malloc(48 + 1);
1469 for (i = 0; i < 48; i++) {
1470 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1471 }
1472 value[48] = '\0';
1473 return value;
1474 }
1475
1476 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1477 Error **errp)
1478 {
1479 X86CPU *cpu = X86_CPU(obj);
1480 CPUX86State *env = &cpu->env;
1481 int c, len, i;
1482
1483 if (model_id == NULL) {
1484 model_id = "";
1485 }
1486 len = strlen(model_id);
1487 memset(env->cpuid_model, 0, 48);
1488 for (i = 0; i < 48; i++) {
1489 if (i >= len) {
1490 c = '\0';
1491 } else {
1492 c = (uint8_t)model_id[i];
1493 }
1494 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1495 }
1496 }
1497
1498 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1499 const char *name, Error **errp)
1500 {
1501 X86CPU *cpu = X86_CPU(obj);
1502 int64_t value;
1503
1504 value = cpu->env.tsc_khz * 1000;
1505 visit_type_int(v, &value, name, errp);
1506 }
1507
1508 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1509 const char *name, Error **errp)
1510 {
1511 X86CPU *cpu = X86_CPU(obj);
1512 const int64_t min = 0;
1513 const int64_t max = INT64_MAX;
1514 int64_t value;
1515
1516 visit_type_int(v, &value, name, errp);
1517 if (error_is_set(errp)) {
1518 return;
1519 }
1520 if (value < min || value > max) {
1521 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1522 name ? name : "null", value, min, max);
1523 return;
1524 }
1525
1526 cpu->env.tsc_khz = value / 1000;
1527 }
1528
1529 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1530 const char *name, Error **errp)
1531 {
1532 X86CPU *cpu = X86_CPU(obj);
1533 int64_t value = cpu->env.cpuid_apic_id;
1534
1535 visit_type_int(v, &value, name, errp);
1536 }
1537
1538 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1539 const char *name, Error **errp)
1540 {
1541 X86CPU *cpu = X86_CPU(obj);
1542 DeviceState *dev = DEVICE(obj);
1543 const int64_t min = 0;
1544 const int64_t max = UINT32_MAX;
1545 Error *error = NULL;
1546 int64_t value;
1547
1548 if (dev->realized) {
1549 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1550 "it was realized", name, object_get_typename(obj));
1551 return;
1552 }
1553
1554 visit_type_int(v, &value, name, &error);
1555 if (error) {
1556 error_propagate(errp, error);
1557 return;
1558 }
1559 if (value < min || value > max) {
1560 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1561 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1562 object_get_typename(obj), name, value, min, max);
1563 return;
1564 }
1565
1566 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1567 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1568 return;
1569 }
1570 cpu->env.cpuid_apic_id = value;
1571 }
1572
1573 /* Generic getter for "feature-words" and "filtered-features" properties */
1574 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1575 const char *name, Error **errp)
1576 {
1577 uint32_t *array = (uint32_t *)opaque;
1578 FeatureWord w;
1579 Error *err = NULL;
1580 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1581 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1582 X86CPUFeatureWordInfoList *list = NULL;
1583
1584 for (w = 0; w < FEATURE_WORDS; w++) {
1585 FeatureWordInfo *wi = &feature_word_info[w];
1586 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1587 qwi->cpuid_input_eax = wi->cpuid_eax;
1588 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1589 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1590 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1591 qwi->features = array[w];
1592
1593 /* List will be in reverse order, but order shouldn't matter */
1594 list_entries[w].next = list;
1595 list_entries[w].value = &word_infos[w];
1596 list = &list_entries[w];
1597 }
1598
1599 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1600 error_propagate(errp, err);
1601 }
1602
1603 static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
1604 const char *name)
1605 {
1606 x86_def_t *def;
1607 Error *err = NULL;
1608 int i;
1609
1610 if (name == NULL) {
1611 return -1;
1612 }
1613 if (kvm_enabled() && strcmp(name, "host") == 0) {
1614 kvm_cpu_fill_host(x86_cpu_def);
1615 object_property_set_bool(OBJECT(cpu), true, "pmu", &err);
1616 assert_no_error(err);
1617 return 0;
1618 }
1619
1620 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1621 def = &builtin_x86_defs[i];
1622 if (strcmp(name, def->name) == 0) {
1623 memcpy(x86_cpu_def, def, sizeof(*def));
1624 /* sysenter isn't supported in compatibility mode on AMD,
1625 * syscall isn't supported in compatibility mode on Intel.
1626 * Normally we advertise the actual CPU vendor, but you can
1627 * override this using the 'vendor' property if you want to use
1628 * KVM's sysenter/syscall emulation in compatibility mode and
1629 * when doing cross vendor migration
1630 */
1631 if (kvm_enabled()) {
1632 uint32_t ebx = 0, ecx = 0, edx = 0;
1633 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1634 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1635 }
1636 return 0;
1637 }
1638 }
1639
1640 return -1;
1641 }
1642
1643 /* Convert all '_' in a feature string option name to '-', to make feature
1644 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1645 */
1646 static inline void feat2prop(char *s)
1647 {
1648 while ((s = strchr(s, '_'))) {
1649 *s = '-';
1650 }
1651 }
1652
1653 /* Parse "+feature,-feature,feature=foo" CPU feature string
1654 */
1655 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1656 {
1657 char *featurestr; /* Single 'key=value" string being parsed */
1658 /* Features to be added */
1659 FeatureWordArray plus_features = { 0 };
1660 /* Features to be removed */
1661 FeatureWordArray minus_features = { 0 };
1662 uint32_t numvalue;
1663 CPUX86State *env = &cpu->env;
1664
1665 featurestr = features ? strtok(features, ",") : NULL;
1666
1667 while (featurestr) {
1668 char *val;
1669 if (featurestr[0] == '+') {
1670 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1671 } else if (featurestr[0] == '-') {
1672 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1673 } else if ((val = strchr(featurestr, '='))) {
1674 *val = 0; val++;
1675 feat2prop(featurestr);
1676 if (!strcmp(featurestr, "family")) {
1677 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1678 } else if (!strcmp(featurestr, "model")) {
1679 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1680 } else if (!strcmp(featurestr, "stepping")) {
1681 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1682 } else if (!strcmp(featurestr, "level")) {
1683 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1684 } else if (!strcmp(featurestr, "xlevel")) {
1685 char *err;
1686 char num[32];
1687
1688 numvalue = strtoul(val, &err, 0);
1689 if (!*val || *err) {
1690 error_setg(errp, "bad numerical value %s", val);
1691 goto out;
1692 }
1693 if (numvalue < 0x80000000) {
1694 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1695 ", fixup will be removed in future versions\n");
1696 numvalue += 0x80000000;
1697 }
1698 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1699 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1700 } else if (!strcmp(featurestr, "vendor")) {
1701 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1702 } else if (!strcmp(featurestr, "model-id")) {
1703 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1704 } else if (!strcmp(featurestr, "tsc-freq")) {
1705 int64_t tsc_freq;
1706 char *err;
1707 char num[32];
1708
1709 tsc_freq = strtosz_suffix_unit(val, &err,
1710 STRTOSZ_DEFSUFFIX_B, 1000);
1711 if (tsc_freq < 0 || *err) {
1712 error_setg(errp, "bad numerical value %s", val);
1713 goto out;
1714 }
1715 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1716 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1717 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1718 char *err;
1719 const int min = 0xFFF;
1720 numvalue = strtoul(val, &err, 0);
1721 if (!*val || *err) {
1722 error_setg(errp, "bad numerical value %s", val);
1723 goto out;
1724 }
1725 if (numvalue < min) {
1726 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1727 ", fixup will be removed in future versions\n",
1728 min);
1729 numvalue = min;
1730 }
1731 cpu->hyperv_spinlock_attempts = numvalue;
1732 } else {
1733 error_setg(errp, "unrecognized feature %s", featurestr);
1734 goto out;
1735 }
1736 } else if (!strcmp(featurestr, "check")) {
1737 check_cpuid = 1;
1738 } else if (!strcmp(featurestr, "enforce")) {
1739 check_cpuid = enforce_cpuid = 1;
1740 } else if (!strcmp(featurestr, "hv_relaxed")) {
1741 cpu->hyperv_relaxed_timing = true;
1742 } else if (!strcmp(featurestr, "hv_vapic")) {
1743 cpu->hyperv_vapic = true;
1744 } else {
1745 error_setg(errp, "feature string `%s' not in format (+feature|"
1746 "-feature|feature=xyz)", featurestr);
1747 goto out;
1748 }
1749 if (error_is_set(errp)) {
1750 goto out;
1751 }
1752 featurestr = strtok(NULL, ",");
1753 }
1754 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1755 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1756 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1757 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1758 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1759 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1760 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1761 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1762 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1763 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1764 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1765 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1766 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1767 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1768 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1769 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1770
1771 out:
1772 return;
1773 }
1774
1775 /* generate a composite string into buf of all cpuid names in featureset
1776 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1777 * if flags, suppress names undefined in featureset.
1778 */
1779 static void listflags(char *buf, int bufsize, uint32_t fbits,
1780 const char **featureset, uint32_t flags)
1781 {
1782 const char **p = &featureset[31];
1783 char *q, *b, bit;
1784 int nc;
1785
1786 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1787 *buf = '\0';
1788 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1789 if (fbits & 1 << bit && (*p || !flags)) {
1790 if (*p)
1791 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1792 else
1793 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1794 if (bufsize <= nc) {
1795 if (b) {
1796 memcpy(b, "...", sizeof("..."));
1797 }
1798 return;
1799 }
1800 q += nc;
1801 bufsize -= nc;
1802 }
1803 }
1804
1805 /* generate CPU information. */
1806 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1807 {
1808 x86_def_t *def;
1809 char buf[256];
1810 int i;
1811
1812 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1813 def = &builtin_x86_defs[i];
1814 snprintf(buf, sizeof(buf), "%s", def->name);
1815 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1816 }
1817 #ifdef CONFIG_KVM
1818 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1819 "KVM processor with all supported host features "
1820 "(only available in KVM mode)");
1821 #endif
1822
1823 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1824 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1825 FeatureWordInfo *fw = &feature_word_info[i];
1826
1827 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1828 (*cpu_fprintf)(f, " %s\n", buf);
1829 }
1830 }
1831
1832 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1833 {
1834 CpuDefinitionInfoList *cpu_list = NULL;
1835 x86_def_t *def;
1836 int i;
1837
1838 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1839 CpuDefinitionInfoList *entry;
1840 CpuDefinitionInfo *info;
1841
1842 def = &builtin_x86_defs[i];
1843 info = g_malloc0(sizeof(*info));
1844 info->name = g_strdup(def->name);
1845
1846 entry = g_malloc0(sizeof(*entry));
1847 entry->value = info;
1848 entry->next = cpu_list;
1849 cpu_list = entry;
1850 }
1851
1852 return cpu_list;
1853 }
1854
1855 #ifdef CONFIG_KVM
1856 static void filter_features_for_kvm(X86CPU *cpu)
1857 {
1858 CPUX86State *env = &cpu->env;
1859 KVMState *s = kvm_state;
1860 FeatureWord w;
1861
1862 for (w = 0; w < FEATURE_WORDS; w++) {
1863 FeatureWordInfo *wi = &feature_word_info[w];
1864 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1865 wi->cpuid_ecx,
1866 wi->cpuid_reg);
1867 uint32_t requested_features = env->features[w];
1868 env->features[w] &= host_feat;
1869 cpu->filtered_features[w] = requested_features & ~env->features[w];
1870 }
1871 }
1872 #endif
1873
1874 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1875 {
1876 CPUX86State *env = &cpu->env;
1877 x86_def_t def1, *def = &def1;
1878
1879 memset(def, 0, sizeof(*def));
1880
1881 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
1882 error_setg(errp, "Unable to find CPU definition: %s", name);
1883 return;
1884 }
1885
1886 if (kvm_enabled()) {
1887 def->features[FEAT_KVM] |= kvm_default_features;
1888 }
1889 def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1890
1891 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1892 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1893 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1894 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1895 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1896 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1897 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1898 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1899 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1900 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1901 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1902 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1903 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1904 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1905 env->cpuid_xlevel2 = def->xlevel2;
1906 cpu->cache_info_passthrough = def->cache_info_passthrough;
1907
1908 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1909 }
1910
1911 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1912 Error **errp)
1913 {
1914 X86CPU *cpu = NULL;
1915 gchar **model_pieces;
1916 char *name, *features;
1917 char *typename;
1918 Error *error = NULL;
1919
1920 model_pieces = g_strsplit(cpu_model, ",", 2);
1921 if (!model_pieces[0]) {
1922 error_setg(&error, "Invalid/empty CPU model name");
1923 goto out;
1924 }
1925 name = model_pieces[0];
1926 features = model_pieces[1];
1927
1928 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1929 #ifndef CONFIG_USER_ONLY
1930 if (icc_bridge == NULL) {
1931 error_setg(&error, "Invalid icc-bridge value");
1932 goto out;
1933 }
1934 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1935 object_unref(OBJECT(cpu));
1936 #endif
1937
1938 cpu_x86_register(cpu, name, &error);
1939 if (error) {
1940 goto out;
1941 }
1942
1943 /* Emulate per-model subclasses for global properties */
1944 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1945 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1946 g_free(typename);
1947 if (error) {
1948 goto out;
1949 }
1950
1951 cpu_x86_parse_featurestr(cpu, features, &error);
1952 if (error) {
1953 goto out;
1954 }
1955
1956 out:
1957 if (error != NULL) {
1958 error_propagate(errp, error);
1959 object_unref(OBJECT(cpu));
1960 cpu = NULL;
1961 }
1962 g_strfreev(model_pieces);
1963 return cpu;
1964 }
1965
1966 X86CPU *cpu_x86_init(const char *cpu_model)
1967 {
1968 Error *error = NULL;
1969 X86CPU *cpu;
1970
1971 cpu = cpu_x86_create(cpu_model, NULL, &error);
1972 if (error) {
1973 goto out;
1974 }
1975
1976 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1977
1978 out:
1979 if (error) {
1980 error_report("%s", error_get_pretty(error));
1981 error_free(error);
1982 if (cpu != NULL) {
1983 object_unref(OBJECT(cpu));
1984 cpu = NULL;
1985 }
1986 }
1987 return cpu;
1988 }
1989
1990 #if !defined(CONFIG_USER_ONLY)
1991
1992 void cpu_clear_apic_feature(CPUX86State *env)
1993 {
1994 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
1995 }
1996
1997 #endif /* !CONFIG_USER_ONLY */
1998
1999 /* Initialize list of CPU models, filling some non-static fields if necessary
2000 */
2001 void x86_cpudef_setup(void)
2002 {
2003 int i, j;
2004 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2005
2006 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2007 x86_def_t *def = &builtin_x86_defs[i];
2008
2009 /* Look for specific "cpudef" models that */
2010 /* have the QEMU version in .model_id */
2011 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2012 if (strcmp(model_with_versions[j], def->name) == 0) {
2013 pstrcpy(def->model_id, sizeof(def->model_id),
2014 "QEMU Virtual CPU version ");
2015 pstrcat(def->model_id, sizeof(def->model_id),
2016 qemu_get_version());
2017 break;
2018 }
2019 }
2020 }
2021 }
2022
2023 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2024 uint32_t *ecx, uint32_t *edx)
2025 {
2026 *ebx = env->cpuid_vendor1;
2027 *edx = env->cpuid_vendor2;
2028 *ecx = env->cpuid_vendor3;
2029 }
2030
2031 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2032 uint32_t *eax, uint32_t *ebx,
2033 uint32_t *ecx, uint32_t *edx)
2034 {
2035 X86CPU *cpu = x86_env_get_cpu(env);
2036 CPUState *cs = CPU(cpu);
2037
2038 /* test if maximum index reached */
2039 if (index & 0x80000000) {
2040 if (index > env->cpuid_xlevel) {
2041 if (env->cpuid_xlevel2 > 0) {
2042 /* Handle the Centaur's CPUID instruction. */
2043 if (index > env->cpuid_xlevel2) {
2044 index = env->cpuid_xlevel2;
2045 } else if (index < 0xC0000000) {
2046 index = env->cpuid_xlevel;
2047 }
2048 } else {
2049 /* Intel documentation states that invalid EAX input will
2050 * return the same information as EAX=cpuid_level
2051 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2052 */
2053 index = env->cpuid_level;
2054 }
2055 }
2056 } else {
2057 if (index > env->cpuid_level)
2058 index = env->cpuid_level;
2059 }
2060
2061 switch(index) {
2062 case 0:
2063 *eax = env->cpuid_level;
2064 get_cpuid_vendor(env, ebx, ecx, edx);
2065 break;
2066 case 1:
2067 *eax = env->cpuid_version;
2068 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2069 *ecx = env->features[FEAT_1_ECX];
2070 *edx = env->features[FEAT_1_EDX];
2071 if (cs->nr_cores * cs->nr_threads > 1) {
2072 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2073 *edx |= 1 << 28; /* HTT bit */
2074 }
2075 break;
2076 case 2:
2077 /* cache info: needed for Pentium Pro compatibility */
2078 if (cpu->cache_info_passthrough) {
2079 host_cpuid(index, 0, eax, ebx, ecx, edx);
2080 break;
2081 }
2082 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2083 *ebx = 0;
2084 *ecx = 0;
2085 *edx = (L1D_DESCRIPTOR << 16) | \
2086 (L1I_DESCRIPTOR << 8) | \
2087 (L2_DESCRIPTOR);
2088 break;
2089 case 4:
2090 /* cache info: needed for Core compatibility */
2091 if (cpu->cache_info_passthrough) {
2092 host_cpuid(index, count, eax, ebx, ecx, edx);
2093 *eax &= ~0xFC000000;
2094 } else {
2095 *eax = 0;
2096 switch (count) {
2097 case 0: /* L1 dcache info */
2098 *eax |= CPUID_4_TYPE_DCACHE | \
2099 CPUID_4_LEVEL(1) | \
2100 CPUID_4_SELF_INIT_LEVEL;
2101 *ebx = (L1D_LINE_SIZE - 1) | \
2102 ((L1D_PARTITIONS - 1) << 12) | \
2103 ((L1D_ASSOCIATIVITY - 1) << 22);
2104 *ecx = L1D_SETS - 1;
2105 *edx = CPUID_4_NO_INVD_SHARING;
2106 break;
2107 case 1: /* L1 icache info */
2108 *eax |= CPUID_4_TYPE_ICACHE | \
2109 CPUID_4_LEVEL(1) | \
2110 CPUID_4_SELF_INIT_LEVEL;
2111 *ebx = (L1I_LINE_SIZE - 1) | \
2112 ((L1I_PARTITIONS - 1) << 12) | \
2113 ((L1I_ASSOCIATIVITY - 1) << 22);
2114 *ecx = L1I_SETS - 1;
2115 *edx = CPUID_4_NO_INVD_SHARING;
2116 break;
2117 case 2: /* L2 cache info */
2118 *eax |= CPUID_4_TYPE_UNIFIED | \
2119 CPUID_4_LEVEL(2) | \
2120 CPUID_4_SELF_INIT_LEVEL;
2121 if (cs->nr_threads > 1) {
2122 *eax |= (cs->nr_threads - 1) << 14;
2123 }
2124 *ebx = (L2_LINE_SIZE - 1) | \
2125 ((L2_PARTITIONS - 1) << 12) | \
2126 ((L2_ASSOCIATIVITY - 1) << 22);
2127 *ecx = L2_SETS - 1;
2128 *edx = CPUID_4_NO_INVD_SHARING;
2129 break;
2130 default: /* end of info */
2131 *eax = 0;
2132 *ebx = 0;
2133 *ecx = 0;
2134 *edx = 0;
2135 break;
2136 }
2137 }
2138
2139 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2140 if ((*eax & 31) && cs->nr_cores > 1) {
2141 *eax |= (cs->nr_cores - 1) << 26;
2142 }
2143 break;
2144 case 5:
2145 /* mwait info: needed for Core compatibility */
2146 *eax = 0; /* Smallest monitor-line size in bytes */
2147 *ebx = 0; /* Largest monitor-line size in bytes */
2148 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2149 *edx = 0;
2150 break;
2151 case 6:
2152 /* Thermal and Power Leaf */
2153 *eax = 0;
2154 *ebx = 0;
2155 *ecx = 0;
2156 *edx = 0;
2157 break;
2158 case 7:
2159 /* Structured Extended Feature Flags Enumeration Leaf */
2160 if (count == 0) {
2161 *eax = 0; /* Maximum ECX value for sub-leaves */
2162 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2163 *ecx = 0; /* Reserved */
2164 *edx = 0; /* Reserved */
2165 } else {
2166 *eax = 0;
2167 *ebx = 0;
2168 *ecx = 0;
2169 *edx = 0;
2170 }
2171 break;
2172 case 9:
2173 /* Direct Cache Access Information Leaf */
2174 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2175 *ebx = 0;
2176 *ecx = 0;
2177 *edx = 0;
2178 break;
2179 case 0xA:
2180 /* Architectural Performance Monitoring Leaf */
2181 if (kvm_enabled() && cpu->enable_pmu) {
2182 KVMState *s = cs->kvm_state;
2183
2184 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2185 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2186 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2187 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2188 } else {
2189 *eax = 0;
2190 *ebx = 0;
2191 *ecx = 0;
2192 *edx = 0;
2193 }
2194 break;
2195 case 0xD: {
2196 KVMState *s = cs->kvm_state;
2197 uint64_t kvm_mask;
2198 int i;
2199
2200 /* Processor Extended State */
2201 *eax = 0;
2202 *ebx = 0;
2203 *ecx = 0;
2204 *edx = 0;
2205 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2206 break;
2207 }
2208 kvm_mask =
2209 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2210 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2211
2212 if (count == 0) {
2213 *ecx = 0x240;
2214 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2215 const ExtSaveArea *esa = &ext_save_areas[i];
2216 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2217 (kvm_mask & (1 << i)) != 0) {
2218 if (i < 32) {
2219 *eax |= 1 << i;
2220 } else {
2221 *edx |= 1 << (i - 32);
2222 }
2223 *ecx = MAX(*ecx, esa->offset + esa->size);
2224 }
2225 }
2226 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2227 *ebx = *ecx;
2228 } else if (count == 1) {
2229 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2230 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2231 const ExtSaveArea *esa = &ext_save_areas[count];
2232 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2233 (kvm_mask & (1 << count)) != 0) {
2234 *eax = esa->size;
2235 *ebx = esa->offset;
2236 }
2237 }
2238 break;
2239 }
2240 case 0x80000000:
2241 *eax = env->cpuid_xlevel;
2242 *ebx = env->cpuid_vendor1;
2243 *edx = env->cpuid_vendor2;
2244 *ecx = env->cpuid_vendor3;
2245 break;
2246 case 0x80000001:
2247 *eax = env->cpuid_version;
2248 *ebx = 0;
2249 *ecx = env->features[FEAT_8000_0001_ECX];
2250 *edx = env->features[FEAT_8000_0001_EDX];
2251
2252 /* The Linux kernel checks for the CMPLegacy bit and
2253 * discards multiple thread information if it is set.
2254 * So dont set it here for Intel to make Linux guests happy.
2255 */
2256 if (cs->nr_cores * cs->nr_threads > 1) {
2257 uint32_t tebx, tecx, tedx;
2258 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2259 if (tebx != CPUID_VENDOR_INTEL_1 ||
2260 tedx != CPUID_VENDOR_INTEL_2 ||
2261 tecx != CPUID_VENDOR_INTEL_3) {
2262 *ecx |= 1 << 1; /* CmpLegacy bit */
2263 }
2264 }
2265 break;
2266 case 0x80000002:
2267 case 0x80000003:
2268 case 0x80000004:
2269 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2270 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2271 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2272 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2273 break;
2274 case 0x80000005:
2275 /* cache info (L1 cache) */
2276 if (cpu->cache_info_passthrough) {
2277 host_cpuid(index, 0, eax, ebx, ecx, edx);
2278 break;
2279 }
2280 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2281 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2282 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2283 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2284 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2285 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2286 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2287 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2288 break;
2289 case 0x80000006:
2290 /* cache info (L2 cache) */
2291 if (cpu->cache_info_passthrough) {
2292 host_cpuid(index, 0, eax, ebx, ecx, edx);
2293 break;
2294 }
2295 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2296 (L2_DTLB_2M_ENTRIES << 16) | \
2297 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2298 (L2_ITLB_2M_ENTRIES);
2299 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2300 (L2_DTLB_4K_ENTRIES << 16) | \
2301 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2302 (L2_ITLB_4K_ENTRIES);
2303 *ecx = (L2_SIZE_KB_AMD << 16) | \
2304 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2305 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2306 *edx = ((L3_SIZE_KB/512) << 18) | \
2307 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2308 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2309 break;
2310 case 0x80000008:
2311 /* virtual & phys address size in low 2 bytes. */
2312 /* XXX: This value must match the one used in the MMU code. */
2313 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2314 /* 64 bit processor */
2315 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2316 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2317 } else {
2318 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2319 *eax = 0x00000024; /* 36 bits physical */
2320 } else {
2321 *eax = 0x00000020; /* 32 bits physical */
2322 }
2323 }
2324 *ebx = 0;
2325 *ecx = 0;
2326 *edx = 0;
2327 if (cs->nr_cores * cs->nr_threads > 1) {
2328 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2329 }
2330 break;
2331 case 0x8000000A:
2332 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2333 *eax = 0x00000001; /* SVM Revision */
2334 *ebx = 0x00000010; /* nr of ASIDs */
2335 *ecx = 0;
2336 *edx = env->features[FEAT_SVM]; /* optional features */
2337 } else {
2338 *eax = 0;
2339 *ebx = 0;
2340 *ecx = 0;
2341 *edx = 0;
2342 }
2343 break;
2344 case 0xC0000000:
2345 *eax = env->cpuid_xlevel2;
2346 *ebx = 0;
2347 *ecx = 0;
2348 *edx = 0;
2349 break;
2350 case 0xC0000001:
2351 /* Support for VIA CPU's CPUID instruction */
2352 *eax = env->cpuid_version;
2353 *ebx = 0;
2354 *ecx = 0;
2355 *edx = env->features[FEAT_C000_0001_EDX];
2356 break;
2357 case 0xC0000002:
2358 case 0xC0000003:
2359 case 0xC0000004:
2360 /* Reserved for the future, and now filled with zero */
2361 *eax = 0;
2362 *ebx = 0;
2363 *ecx = 0;
2364 *edx = 0;
2365 break;
2366 default:
2367 /* reserved values: zero */
2368 *eax = 0;
2369 *ebx = 0;
2370 *ecx = 0;
2371 *edx = 0;
2372 break;
2373 }
2374 }
2375
2376 /* CPUClass::reset() */
2377 static void x86_cpu_reset(CPUState *s)
2378 {
2379 X86CPU *cpu = X86_CPU(s);
2380 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2381 CPUX86State *env = &cpu->env;
2382 int i;
2383
2384 xcc->parent_reset(s);
2385
2386
2387 memset(env, 0, offsetof(CPUX86State, breakpoints));
2388
2389 tlb_flush(env, 1);
2390
2391 env->old_exception = -1;
2392
2393 /* init to reset state */
2394
2395 #ifdef CONFIG_SOFTMMU
2396 env->hflags |= HF_SOFTMMU_MASK;
2397 #endif
2398 env->hflags2 |= HF2_GIF_MASK;
2399
2400 cpu_x86_update_cr0(env, 0x60000010);
2401 env->a20_mask = ~0x0;
2402 env->smbase = 0x30000;
2403
2404 env->idt.limit = 0xffff;
2405 env->gdt.limit = 0xffff;
2406 env->ldt.limit = 0xffff;
2407 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2408 env->tr.limit = 0xffff;
2409 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2410
2411 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2412 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2413 DESC_R_MASK | DESC_A_MASK);
2414 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2415 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2416 DESC_A_MASK);
2417 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2418 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2419 DESC_A_MASK);
2420 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2421 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2422 DESC_A_MASK);
2423 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2424 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2425 DESC_A_MASK);
2426 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2427 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2428 DESC_A_MASK);
2429
2430 env->eip = 0xfff0;
2431 env->regs[R_EDX] = env->cpuid_version;
2432
2433 env->eflags = 0x2;
2434
2435 /* FPU init */
2436 for (i = 0; i < 8; i++) {
2437 env->fptags[i] = 1;
2438 }
2439 env->fpuc = 0x37f;
2440
2441 env->mxcsr = 0x1f80;
2442 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2443
2444 env->pat = 0x0007040600070406ULL;
2445 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2446
2447 memset(env->dr, 0, sizeof(env->dr));
2448 env->dr[6] = DR6_FIXED_1;
2449 env->dr[7] = DR7_FIXED_1;
2450 cpu_breakpoint_remove_all(env, BP_CPU);
2451 cpu_watchpoint_remove_all(env, BP_CPU);
2452
2453 #if !defined(CONFIG_USER_ONLY)
2454 /* We hard-wire the BSP to the first CPU. */
2455 if (s->cpu_index == 0) {
2456 apic_designate_bsp(env->apic_state);
2457 }
2458
2459 s->halted = !cpu_is_bsp(cpu);
2460 #endif
2461 }
2462
2463 #ifndef CONFIG_USER_ONLY
2464 bool cpu_is_bsp(X86CPU *cpu)
2465 {
2466 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2467 }
2468
2469 /* TODO: remove me, when reset over QOM tree is implemented */
2470 static void x86_cpu_machine_reset_cb(void *opaque)
2471 {
2472 X86CPU *cpu = opaque;
2473 cpu_reset(CPU(cpu));
2474 }
2475 #endif
2476
2477 static void mce_init(X86CPU *cpu)
2478 {
2479 CPUX86State *cenv = &cpu->env;
2480 unsigned int bank;
2481
2482 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2483 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2484 (CPUID_MCE | CPUID_MCA)) {
2485 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2486 cenv->mcg_ctl = ~(uint64_t)0;
2487 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2488 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2489 }
2490 }
2491 }
2492
2493 #ifndef CONFIG_USER_ONLY
2494 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2495 {
2496 CPUX86State *env = &cpu->env;
2497 DeviceState *dev = DEVICE(cpu);
2498 APICCommonState *apic;
2499 const char *apic_type = "apic";
2500
2501 if (kvm_irqchip_in_kernel()) {
2502 apic_type = "kvm-apic";
2503 } else if (xen_enabled()) {
2504 apic_type = "xen-apic";
2505 }
2506
2507 env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2508 if (env->apic_state == NULL) {
2509 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2510 return;
2511 }
2512
2513 object_property_add_child(OBJECT(cpu), "apic",
2514 OBJECT(env->apic_state), NULL);
2515 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2516 /* TODO: convert to link<> */
2517 apic = APIC_COMMON(env->apic_state);
2518 apic->cpu = cpu;
2519 }
2520
2521 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2522 {
2523 CPUX86State *env = &cpu->env;
2524
2525 if (env->apic_state == NULL) {
2526 return;
2527 }
2528
2529 if (qdev_init(env->apic_state)) {
2530 error_setg(errp, "APIC device '%s' could not be initialized",
2531 object_get_typename(OBJECT(env->apic_state)));
2532 return;
2533 }
2534 }
2535 #else
2536 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2537 {
2538 }
2539 #endif
2540
2541 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2542 {
2543 CPUState *cs = CPU(dev);
2544 X86CPU *cpu = X86_CPU(dev);
2545 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2546 CPUX86State *env = &cpu->env;
2547 Error *local_err = NULL;
2548
2549 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2550 env->cpuid_level = 7;
2551 }
2552
2553 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2554 * CPUID[1].EDX.
2555 */
2556 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2557 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2558 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2559 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2560 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2561 & CPUID_EXT2_AMD_ALIASES);
2562 }
2563
2564 if (!kvm_enabled()) {
2565 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2566 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2567 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2568 #ifdef TARGET_X86_64
2569 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2570 #endif
2571 );
2572 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2573 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2574 } else {
2575 if (check_cpuid && kvm_check_features_against_host(cpu)
2576 && enforce_cpuid) {
2577 error_setg(&local_err,
2578 "Host's CPU doesn't support requested features");
2579 goto out;
2580 }
2581 #ifdef CONFIG_KVM
2582 filter_features_for_kvm(cpu);
2583 #endif
2584 }
2585
2586 #ifndef CONFIG_USER_ONLY
2587 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2588
2589 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2590 x86_cpu_apic_create(cpu, &local_err);
2591 if (local_err != NULL) {
2592 goto out;
2593 }
2594 }
2595 #endif
2596
2597 mce_init(cpu);
2598 qemu_init_vcpu(cs);
2599
2600 x86_cpu_apic_realize(cpu, &local_err);
2601 if (local_err != NULL) {
2602 goto out;
2603 }
2604 cpu_reset(cs);
2605
2606 xcc->parent_realize(dev, &local_err);
2607 out:
2608 if (local_err != NULL) {
2609 error_propagate(errp, local_err);
2610 return;
2611 }
2612 }
2613
2614 /* Enables contiguous-apic-ID mode, for compatibility */
2615 static bool compat_apic_id_mode;
2616
2617 void enable_compat_apic_id_mode(void)
2618 {
2619 compat_apic_id_mode = true;
2620 }
2621
2622 /* Calculates initial APIC ID for a specific CPU index
2623 *
2624 * Currently we need to be able to calculate the APIC ID from the CPU index
2625 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2626 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2627 * all CPUs up to max_cpus.
2628 */
2629 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2630 {
2631 uint32_t correct_id;
2632 static bool warned;
2633
2634 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2635 if (compat_apic_id_mode) {
2636 if (cpu_index != correct_id && !warned) {
2637 error_report("APIC IDs set in compatibility mode, "
2638 "CPU topology won't match the configuration");
2639 warned = true;
2640 }
2641 return cpu_index;
2642 } else {
2643 return correct_id;
2644 }
2645 }
2646
2647 static void x86_cpu_initfn(Object *obj)
2648 {
2649 CPUState *cs = CPU(obj);
2650 X86CPU *cpu = X86_CPU(obj);
2651 CPUX86State *env = &cpu->env;
2652 static int inited;
2653
2654 cs->env_ptr = env;
2655 cpu_exec_init(env);
2656
2657 object_property_add(obj, "family", "int",
2658 x86_cpuid_version_get_family,
2659 x86_cpuid_version_set_family, NULL, NULL, NULL);
2660 object_property_add(obj, "model", "int",
2661 x86_cpuid_version_get_model,
2662 x86_cpuid_version_set_model, NULL, NULL, NULL);
2663 object_property_add(obj, "stepping", "int",
2664 x86_cpuid_version_get_stepping,
2665 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2666 object_property_add(obj, "level", "int",
2667 x86_cpuid_get_level,
2668 x86_cpuid_set_level, NULL, NULL, NULL);
2669 object_property_add(obj, "xlevel", "int",
2670 x86_cpuid_get_xlevel,
2671 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2672 object_property_add_str(obj, "vendor",
2673 x86_cpuid_get_vendor,
2674 x86_cpuid_set_vendor, NULL);
2675 object_property_add_str(obj, "model-id",
2676 x86_cpuid_get_model_id,
2677 x86_cpuid_set_model_id, NULL);
2678 object_property_add(obj, "tsc-frequency", "int",
2679 x86_cpuid_get_tsc_freq,
2680 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2681 object_property_add(obj, "apic-id", "int",
2682 x86_cpuid_get_apic_id,
2683 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2684 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2685 x86_cpu_get_feature_words,
2686 NULL, NULL, (void *)env->features, NULL);
2687 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2688 x86_cpu_get_feature_words,
2689 NULL, NULL, (void *)cpu->filtered_features, NULL);
2690
2691 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2692 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2693
2694 /* init various static tables used in TCG mode */
2695 if (tcg_enabled() && !inited) {
2696 inited = 1;
2697 optimize_flags_init();
2698 #ifndef CONFIG_USER_ONLY
2699 cpu_set_debug_excp_handler(breakpoint_handler);
2700 #endif
2701 }
2702 }
2703
2704 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2705 {
2706 X86CPU *cpu = X86_CPU(cs);
2707 CPUX86State *env = &cpu->env;
2708
2709 return env->cpuid_apic_id;
2710 }
2711
2712 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2713 {
2714 X86CPU *cpu = X86_CPU(cs);
2715
2716 return cpu->env.cr[0] & CR0_PG_MASK;
2717 }
2718
2719 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2720 {
2721 X86CPU *cpu = X86_CPU(cs);
2722
2723 cpu->env.eip = value;
2724 }
2725
2726 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2727 {
2728 X86CPU *cpu = X86_CPU(cs);
2729
2730 cpu->env.eip = tb->pc - tb->cs_base;
2731 }
2732
2733 static Property x86_cpu_properties[] = {
2734 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2735 DEFINE_PROP_END_OF_LIST()
2736 };
2737
2738 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2739 {
2740 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2741 CPUClass *cc = CPU_CLASS(oc);
2742 DeviceClass *dc = DEVICE_CLASS(oc);
2743
2744 xcc->parent_realize = dc->realize;
2745 dc->realize = x86_cpu_realizefn;
2746 dc->bus_type = TYPE_ICC_BUS;
2747 dc->props = x86_cpu_properties;
2748
2749 xcc->parent_reset = cc->reset;
2750 cc->reset = x86_cpu_reset;
2751 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2752
2753 cc->do_interrupt = x86_cpu_do_interrupt;
2754 cc->dump_state = x86_cpu_dump_state;
2755 cc->set_pc = x86_cpu_set_pc;
2756 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2757 cc->gdb_read_register = x86_cpu_gdb_read_register;
2758 cc->gdb_write_register = x86_cpu_gdb_write_register;
2759 cc->get_arch_id = x86_cpu_get_arch_id;
2760 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2761 #ifndef CONFIG_USER_ONLY
2762 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2763 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2764 cc->write_elf64_note = x86_cpu_write_elf64_note;
2765 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2766 cc->write_elf32_note = x86_cpu_write_elf32_note;
2767 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2768 cc->vmsd = &vmstate_x86_cpu;
2769 #endif
2770 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2771 }
2772
2773 static const TypeInfo x86_cpu_type_info = {
2774 .name = TYPE_X86_CPU,
2775 .parent = TYPE_CPU,
2776 .instance_size = sizeof(X86CPU),
2777 .instance_init = x86_cpu_initfn,
2778 .abstract = false,
2779 .class_size = sizeof(X86CPUClass),
2780 .class_init = x86_cpu_common_class_init,
2781 };
2782
2783 static void x86_cpu_register_types(void)
2784 {
2785 type_register_static(&x86_cpu_type_info);
2786 }
2787
2788 type_init(x86_cpu_register_types)
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