2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #define TARGET_LONG_BITS 64
28 #define TARGET_LONG_BITS 32
31 /* target supports implicit self modifying code */
32 #define TARGET_HAS_SMC
33 /* support for self modifying code even if the modified instruction is
34 close to the modifying instruction */
35 #define TARGET_HAS_PRECISE_SMC
37 #define TARGET_HAS_ICE 1
40 #define ELF_MACHINE EM_X86_64
42 #define ELF_MACHINE EM_386
47 #include "softfloat.h"
49 #if defined(__i386__) && !defined(CONFIG_SOFTMMU) && !defined(__APPLE__)
78 /* segment descriptor fields */
79 #define DESC_G_MASK (1 << 23)
80 #define DESC_B_SHIFT 22
81 #define DESC_B_MASK (1 << DESC_B_SHIFT)
82 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
83 #define DESC_L_MASK (1 << DESC_L_SHIFT)
84 #define DESC_AVL_MASK (1 << 20)
85 #define DESC_P_MASK (1 << 15)
86 #define DESC_DPL_SHIFT 13
87 #define DESC_DPL_MASK (1 << DESC_DPL_SHIFT)
88 #define DESC_S_MASK (1 << 12)
89 #define DESC_TYPE_SHIFT 8
90 #define DESC_A_MASK (1 << 8)
92 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
93 #define DESC_C_MASK (1 << 10) /* code: conforming */
94 #define DESC_R_MASK (1 << 9) /* code: readable */
96 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
97 #define DESC_W_MASK (1 << 9) /* data: writable */
99 #define DESC_TSS_BUSY_MASK (1 << 9)
110 #define IOPL_SHIFT 12
113 #define TF_MASK 0x00000100
114 #define IF_MASK 0x00000200
115 #define DF_MASK 0x00000400
116 #define IOPL_MASK 0x00003000
117 #define NT_MASK 0x00004000
118 #define RF_MASK 0x00010000
119 #define VM_MASK 0x00020000
120 #define AC_MASK 0x00040000
121 #define VIF_MASK 0x00080000
122 #define VIP_MASK 0x00100000
123 #define ID_MASK 0x00200000
125 /* hidden flags - used internally by qemu to represent additional cpu
126 states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
127 using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
130 #define HF_CPL_SHIFT 0
131 /* true if soft mmu is being used */
132 #define HF_SOFTMMU_SHIFT 2
133 /* true if hardware interrupts must be disabled for next instruction */
134 #define HF_INHIBIT_IRQ_SHIFT 3
135 /* 16 or 32 segments */
136 #define HF_CS32_SHIFT 4
137 #define HF_SS32_SHIFT 5
138 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
139 #define HF_ADDSEG_SHIFT 6
140 /* copy of CR0.PE (protected mode) */
141 #define HF_PE_SHIFT 7
142 #define HF_TF_SHIFT 8 /* must be same as eflags */
143 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
144 #define HF_EM_SHIFT 10
145 #define HF_TS_SHIFT 11
146 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
147 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
148 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
149 #define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */
150 #define HF_VM_SHIFT 17 /* must be same as eflags */
151 #define HF_HALTED_SHIFT 18 /* CPU halted */
152 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
153 #define HF_GIF_SHIFT 20 /* if set CPU takes interrupts */
154 #define HF_HIF_SHIFT 21 /* shadow copy of IF_MASK when in SVM */
156 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
157 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
158 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
159 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
160 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
161 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
162 #define HF_PE_MASK (1 << HF_PE_SHIFT)
163 #define HF_TF_MASK (1 << HF_TF_SHIFT)
164 #define HF_MP_MASK (1 << HF_MP_SHIFT)
165 #define HF_EM_MASK (1 << HF_EM_SHIFT)
166 #define HF_TS_MASK (1 << HF_TS_SHIFT)
167 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
168 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
169 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
170 #define HF_HALTED_MASK (1 << HF_HALTED_SHIFT)
171 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
172 #define HF_GIF_MASK (1 << HF_GIF_SHIFT)
173 #define HF_HIF_MASK (1 << HF_HIF_SHIFT)
175 #define CR0_PE_MASK (1 << 0)
176 #define CR0_MP_MASK (1 << 1)
177 #define CR0_EM_MASK (1 << 2)
178 #define CR0_TS_MASK (1 << 3)
179 #define CR0_ET_MASK (1 << 4)
180 #define CR0_NE_MASK (1 << 5)
181 #define CR0_WP_MASK (1 << 16)
182 #define CR0_AM_MASK (1 << 18)
183 #define CR0_PG_MASK (1 << 31)
185 #define CR4_VME_MASK (1 << 0)
186 #define CR4_PVI_MASK (1 << 1)
187 #define CR4_TSD_MASK (1 << 2)
188 #define CR4_DE_MASK (1 << 3)
189 #define CR4_PSE_MASK (1 << 4)
190 #define CR4_PAE_MASK (1 << 5)
191 #define CR4_PGE_MASK (1 << 7)
192 #define CR4_PCE_MASK (1 << 8)
193 #define CR4_OSFXSR_MASK (1 << 9)
194 #define CR4_OSXMMEXCPT_MASK (1 << 10)
196 #define PG_PRESENT_BIT 0
198 #define PG_USER_BIT 2
201 #define PG_ACCESSED_BIT 5
202 #define PG_DIRTY_BIT 6
204 #define PG_GLOBAL_BIT 8
207 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
208 #define PG_RW_MASK (1 << PG_RW_BIT)
209 #define PG_USER_MASK (1 << PG_USER_BIT)
210 #define PG_PWT_MASK (1 << PG_PWT_BIT)
211 #define PG_PCD_MASK (1 << PG_PCD_BIT)
212 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
213 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
214 #define PG_PSE_MASK (1 << PG_PSE_BIT)
215 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
216 #define PG_NX_MASK (1LL << PG_NX_BIT)
218 #define PG_ERROR_W_BIT 1
220 #define PG_ERROR_P_MASK 0x01
221 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
222 #define PG_ERROR_U_MASK 0x04
223 #define PG_ERROR_RSVD_MASK 0x08
224 #define PG_ERROR_I_D_MASK 0x10
226 #define MSR_IA32_APICBASE 0x1b
227 #define MSR_IA32_APICBASE_BSP (1<<8)
228 #define MSR_IA32_APICBASE_ENABLE (1<<11)
229 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
231 #define MSR_IA32_SYSENTER_CS 0x174
232 #define MSR_IA32_SYSENTER_ESP 0x175
233 #define MSR_IA32_SYSENTER_EIP 0x176
235 #define MSR_MCG_CAP 0x179
236 #define MSR_MCG_STATUS 0x17a
237 #define MSR_MCG_CTL 0x17b
239 #define MSR_PAT 0x277
241 #define MSR_EFER 0xc0000080
243 #define MSR_EFER_SCE (1 << 0)
244 #define MSR_EFER_LME (1 << 8)
245 #define MSR_EFER_LMA (1 << 10)
246 #define MSR_EFER_NXE (1 << 11)
247 #define MSR_EFER_FFXSR (1 << 14)
249 #define MSR_STAR 0xc0000081
250 #define MSR_LSTAR 0xc0000082
251 #define MSR_CSTAR 0xc0000083
252 #define MSR_FMASK 0xc0000084
253 #define MSR_FSBASE 0xc0000100
254 #define MSR_GSBASE 0xc0000101
255 #define MSR_KERNELGSBASE 0xc0000102
257 #define MSR_VM_HSAVE_PA 0xc0010117
259 /* cpuid_features bits */
260 #define CPUID_FP87 (1 << 0)
261 #define CPUID_VME (1 << 1)
262 #define CPUID_DE (1 << 2)
263 #define CPUID_PSE (1 << 3)
264 #define CPUID_TSC (1 << 4)
265 #define CPUID_MSR (1 << 5)
266 #define CPUID_PAE (1 << 6)
267 #define CPUID_MCE (1 << 7)
268 #define CPUID_CX8 (1 << 8)
269 #define CPUID_APIC (1 << 9)
270 #define CPUID_SEP (1 << 11) /* sysenter/sysexit */
271 #define CPUID_MTRR (1 << 12)
272 #define CPUID_PGE (1 << 13)
273 #define CPUID_MCA (1 << 14)
274 #define CPUID_CMOV (1 << 15)
275 #define CPUID_PAT (1 << 16)
276 #define CPUID_PSE36 (1 << 17)
277 #define CPUID_PN (1 << 18)
278 #define CPUID_CLFLUSH (1 << 19)
279 #define CPUID_DTS (1 << 21)
280 #define CPUID_ACPI (1 << 22)
281 #define CPUID_MMX (1 << 23)
282 #define CPUID_FXSR (1 << 24)
283 #define CPUID_SSE (1 << 25)
284 #define CPUID_SSE2 (1 << 26)
285 #define CPUID_SS (1 << 27)
286 #define CPUID_HT (1 << 28)
287 #define CPUID_TM (1 << 29)
288 #define CPUID_IA64 (1 << 30)
289 #define CPUID_PBE (1 << 31)
291 #define CPUID_EXT_SSE3 (1 << 0)
292 #define CPUID_EXT_MONITOR (1 << 3)
293 #define CPUID_EXT_DSCPL (1 << 4)
294 #define CPUID_EXT_VMX (1 << 5)
295 #define CPUID_EXT_SMX (1 << 6)
296 #define CPUID_EXT_EST (1 << 7)
297 #define CPUID_EXT_TM2 (1 << 8)
298 #define CPUID_EXT_SSSE3 (1 << 9)
299 #define CPUID_EXT_CID (1 << 10)
300 #define CPUID_EXT_CX16 (1 << 13)
301 #define CPUID_EXT_XTPR (1 << 14)
302 #define CPUID_EXT_DCA (1 << 17)
303 #define CPUID_EXT_POPCNT (1 << 22)
305 #define CPUID_EXT2_SYSCALL (1 << 11)
306 #define CPUID_EXT2_MP (1 << 19)
307 #define CPUID_EXT2_NX (1 << 20)
308 #define CPUID_EXT2_MMXEXT (1 << 22)
309 #define CPUID_EXT2_FFXSR (1 << 25)
310 #define CPUID_EXT2_PDPE1GB (1 << 26)
311 #define CPUID_EXT2_RDTSCP (1 << 27)
312 #define CPUID_EXT2_LM (1 << 29)
313 #define CPUID_EXT2_3DNOWEXT (1 << 30)
314 #define CPUID_EXT2_3DNOW (1 << 31)
316 #define CPUID_EXT3_LAHF_LM (1 << 0)
317 #define CPUID_EXT3_CMP_LEG (1 << 1)
318 #define CPUID_EXT3_SVM (1 << 2)
319 #define CPUID_EXT3_EXTAPIC (1 << 3)
320 #define CPUID_EXT3_CR8LEG (1 << 4)
321 #define CPUID_EXT3_ABM (1 << 5)
322 #define CPUID_EXT3_SSE4A (1 << 6)
323 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
324 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
325 #define CPUID_EXT3_OSVW (1 << 9)
326 #define CPUID_EXT3_IBS (1 << 10)
328 #define EXCP00_DIVZ 0
329 #define EXCP01_SSTP 1
331 #define EXCP03_INT3 3
332 #define EXCP04_INTO 4
333 #define EXCP05_BOUND 5
334 #define EXCP06_ILLOP 6
335 #define EXCP07_PREX 7
336 #define EXCP08_DBLE 8
337 #define EXCP09_XERR 9
338 #define EXCP0A_TSS 10
339 #define EXCP0B_NOSEG 11
340 #define EXCP0C_STACK 12
341 #define EXCP0D_GPF 13
342 #define EXCP0E_PAGE 14
343 #define EXCP10_COPR 16
344 #define EXCP11_ALGN 17
345 #define EXCP12_MCHK 18
348 CC_OP_DYNAMIC
, /* must use dynamic code to get cc_op */
349 CC_OP_EFLAGS
, /* all cc are explicitely computed, CC_SRC = flags */
351 CC_OP_MULB
, /* modify all flags, C, O = (CC_SRC != 0) */
356 CC_OP_ADDB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
361 CC_OP_ADCB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
366 CC_OP_SUBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
371 CC_OP_SBBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
376 CC_OP_LOGICB
, /* modify all flags, CC_DST = res */
381 CC_OP_INCB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
386 CC_OP_DECB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
391 CC_OP_SHLB
, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
396 CC_OP_SARB
, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
405 #define USE_X86LDOUBLE
408 #ifdef USE_X86LDOUBLE
409 typedef floatx80 CPU86_LDouble
;
411 typedef float64 CPU86_LDouble
;
414 typedef struct SegmentCache
{
437 #ifdef WORDS_BIGENDIAN
438 #define XMM_B(n) _b[15 - (n)]
439 #define XMM_W(n) _w[7 - (n)]
440 #define XMM_L(n) _l[3 - (n)]
441 #define XMM_S(n) _s[3 - (n)]
442 #define XMM_Q(n) _q[1 - (n)]
443 #define XMM_D(n) _d[1 - (n)]
445 #define MMX_B(n) _b[7 - (n)]
446 #define MMX_W(n) _w[3 - (n)]
447 #define MMX_L(n) _l[1 - (n)]
449 #define XMM_B(n) _b[n]
450 #define XMM_W(n) _w[n]
451 #define XMM_L(n) _l[n]
452 #define XMM_S(n) _s[n]
453 #define XMM_Q(n) _q[n]
454 #define XMM_D(n) _d[n]
456 #define MMX_B(n) _b[n]
457 #define MMX_W(n) _w[n]
458 #define MMX_L(n) _l[n]
463 #define CPU_NB_REGS 16
465 #define CPU_NB_REGS 8
468 #define NB_MMU_MODES 2
470 typedef struct CPUX86State
{
471 #if TARGET_LONG_BITS > HOST_LONG_BITS
472 /* temporaries if we cannot store them in host registers */
473 target_ulong t0
, t1
, t2
;
476 /* standard registers */
477 target_ulong regs
[CPU_NB_REGS
];
479 target_ulong eflags
; /* eflags register. During CPU emulation, CC
480 flags and DF are set to zero because they are
483 /* emulator internal eflags handling */
487 int32_t df
; /* D flag : 1 if D = 0, -1 if D = 1 */
488 uint32_t hflags
; /* hidden flags, see HF_xxx constants */
491 SegmentCache segs
[6]; /* selector values */
494 SegmentCache gdt
; /* only base and limit are used */
495 SegmentCache idt
; /* only base and limit are used */
497 target_ulong cr
[5]; /* NOTE: cr1 is unused */
501 unsigned int fpstt
; /* top of stack index */
504 uint8_t fptags
[8]; /* 0 = valid, 1 = empty */
506 #ifdef USE_X86LDOUBLE
507 CPU86_LDouble d
__attribute__((aligned(16)));
514 /* emulator internal variables */
515 float_status fp_status
;
524 float_status sse_status
;
526 XMMReg xmm_regs
[CPU_NB_REGS
];
530 /* sysenter registers */
531 uint32_t sysenter_cs
;
532 uint32_t sysenter_esp
;
533 uint32_t sysenter_eip
;
537 target_phys_addr_t vm_hsave
;
538 target_phys_addr_t vm_vmcb
;
540 uint16_t intercept_cr_read
;
541 uint16_t intercept_cr_write
;
542 uint16_t intercept_dr_read
;
543 uint16_t intercept_dr_write
;
544 uint32_t intercept_exceptions
;
550 target_ulong kernelgsbase
;
555 /* temporary data for USE_CODE_COPY mode */
559 int native_fp_regs
; /* if true, the FPU state is in the native CPU regs */
562 /* exception/interrupt handling */
566 int exception_is_int
;
567 target_ulong exception_next_eip
;
568 target_ulong dr
[8]; /* debug registers */
570 int interrupt_request
;
571 int user_mode_only
; /* user mode only simulation */
572 int old_exception
; /* exception in flight */
576 /* processor features (e.g. for CPUID insn) */
577 uint32_t cpuid_level
;
578 uint32_t cpuid_vendor1
;
579 uint32_t cpuid_vendor2
;
580 uint32_t cpuid_vendor3
;
581 uint32_t cpuid_version
;
582 uint32_t cpuid_features
;
583 uint32_t cpuid_ext_features
;
584 uint32_t cpuid_xlevel
;
585 uint32_t cpuid_model
[12];
586 uint32_t cpuid_ext2_features
;
587 uint32_t cpuid_ext3_features
;
588 uint32_t cpuid_apic_id
;
594 /* in order to simplify APIC support, we leave this pointer to the
596 struct APICState
*apic_state
;
599 CPUX86State
*cpu_x86_init(void);
600 int cpu_x86_exec(CPUX86State
*s
);
601 void cpu_x86_close(CPUX86State
*s
);
602 int x86_find_cpu_by_name (const unsigned char *name
);
603 void x86_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
,
605 int cpu_get_pic_interrupt(CPUX86State
*s
);
606 /* MSDOS compatibility mode FPU exception support */
607 void cpu_set_ferr(CPUX86State
*s
);
609 /* this function must always be used to load data in the segment
610 cache: it synchronizes the hflags with the segment cache values */
611 static inline void cpu_x86_load_seg_cache(CPUX86State
*env
,
612 int seg_reg
, unsigned int selector
,
618 unsigned int new_hflags
;
620 sc
= &env
->segs
[seg_reg
];
621 sc
->selector
= selector
;
626 /* update the hidden flags */
628 if (seg_reg
== R_CS
) {
630 if ((env
->hflags
& HF_LMA_MASK
) && (flags
& DESC_L_MASK
)) {
632 env
->hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
633 env
->hflags
&= ~(HF_ADDSEG_MASK
);
637 /* legacy / compatibility case */
638 new_hflags
= (env
->segs
[R_CS
].flags
& DESC_B_MASK
)
639 >> (DESC_B_SHIFT
- HF_CS32_SHIFT
);
640 env
->hflags
= (env
->hflags
& ~(HF_CS32_MASK
| HF_CS64_MASK
)) |
644 new_hflags
= (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
645 >> (DESC_B_SHIFT
- HF_SS32_SHIFT
);
646 if (env
->hflags
& HF_CS64_MASK
) {
647 /* zero base assumed for DS, ES and SS in long mode */
648 } else if (!(env
->cr
[0] & CR0_PE_MASK
) ||
649 (env
->eflags
& VM_MASK
) ||
650 !(env
->hflags
& HF_CS32_MASK
)) {
651 /* XXX: try to avoid this test. The problem comes from the
652 fact that is real mode or vm86 mode we only modify the
653 'base' and 'selector' fields of the segment cache to go
654 faster. A solution may be to force addseg to one in
656 new_hflags
|= HF_ADDSEG_MASK
;
658 new_hflags
|= ((env
->segs
[R_DS
].base
|
659 env
->segs
[R_ES
].base
|
660 env
->segs
[R_SS
].base
) != 0) <<
663 env
->hflags
= (env
->hflags
&
664 ~(HF_SS32_MASK
| HF_ADDSEG_MASK
)) | new_hflags
;
668 /* wrapper, just in case memory mappings must be changed */
669 static inline void cpu_x86_set_cpl(CPUX86State
*s
, int cpl
)
672 s
->hflags
= (s
->hflags
& ~HF_CPL_MASK
) | cpl
;
674 #error HF_CPL_MASK is hardcoded
678 /* used for debug or cpu save/restore */
679 void cpu_get_fp80(uint64_t *pmant
, uint16_t *pexp
, CPU86_LDouble f
);
680 CPU86_LDouble
cpu_set_fp80(uint64_t mant
, uint16_t upper
);
682 /* the following helpers are only usable in user mode simulation as
683 they can trigger unexpected exceptions */
684 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
);
685 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
);
686 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
);
688 /* you can call this signal handler from your SIGBUS and SIGSEGV
689 signal handlers to inform the virtual CPU of exceptions. non zero
690 is returned if the signal was handled by the virtual CPU. */
691 int cpu_x86_signal_handler(int host_signum
, void *pinfo
,
693 void cpu_x86_set_a20(CPUX86State
*env
, int a20_state
);
695 uint64_t cpu_get_tsc(CPUX86State
*env
);
697 void cpu_set_apic_base(CPUX86State
*env
, uint64_t val
);
698 uint64_t cpu_get_apic_base(CPUX86State
*env
);
699 void cpu_set_apic_tpr(CPUX86State
*env
, uint8_t val
);
700 #ifndef NO_CPU_IO_DEFS
701 uint8_t cpu_get_apic_tpr(CPUX86State
*env
);
703 void cpu_smm_update(CPUX86State
*env
);
705 /* will be suppressed */
706 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
);
709 #define X86_DUMP_FPU 0x0001 /* dump FPU state too */
710 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
713 static inline int cpu_get_time_fast(void)
716 asm volatile("rdtsc" : "=a" (low
), "=d" (high
));
721 #define TARGET_PAGE_BITS 12
723 #define CPUState CPUX86State
724 #define cpu_init cpu_x86_init
725 #define cpu_exec cpu_x86_exec
726 #define cpu_gen_code cpu_x86_gen_code
727 #define cpu_signal_handler cpu_x86_signal_handler
728 #define cpu_list x86_cpu_list
730 /* MMU modes definitions */
731 #define MMU_MODE0_SUFFIX _kernel
732 #define MMU_MODE1_SUFFIX _user
733 #define MMU_USER_IDX 1
734 static inline int cpu_mmu_index (CPUState
*env
)
736 return (env
->hflags
& HF_CPL_MASK
) == 3 ? 1 : 0;
743 #endif /* CPU_I386_H */