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1 /*
2 * x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <math.h>
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "qemu/aes.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #define FPU_RC_MASK 0xc00
28 #define FPU_RC_NEAR 0x000
29 #define FPU_RC_DOWN 0x400
30 #define FPU_RC_UP 0x800
31 #define FPU_RC_CHOP 0xc00
32
33 #define MAXTAN 9223372036854775808.0
34
35 /* the following deal with x86 long double-precision numbers */
36 #define MAXEXPD 0x7fff
37 #define EXPBIAS 16383
38 #define EXPD(fp) (fp.l.upper & 0x7fff)
39 #define SIGND(fp) ((fp.l.upper) & 0x8000)
40 #define MANTD(fp) (fp.l.lower)
41 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
42
43 #define FPUS_IE (1 << 0)
44 #define FPUS_DE (1 << 1)
45 #define FPUS_ZE (1 << 2)
46 #define FPUS_OE (1 << 3)
47 #define FPUS_UE (1 << 4)
48 #define FPUS_PE (1 << 5)
49 #define FPUS_SF (1 << 6)
50 #define FPUS_SE (1 << 7)
51 #define FPUS_B (1 << 15)
52
53 #define FPUC_EM 0x3f
54
55 #define floatx80_lg2 make_floatx80(0x3ffd, 0x9a209a84fbcff799LL)
56 #define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
57 #define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
58
59 static inline void fpush(CPUX86State *env)
60 {
61 env->fpstt = (env->fpstt - 1) & 7;
62 env->fptags[env->fpstt] = 0; /* validate stack entry */
63 }
64
65 static inline void fpop(CPUX86State *env)
66 {
67 env->fptags[env->fpstt] = 1; /* invalidate stack entry */
68 env->fpstt = (env->fpstt + 1) & 7;
69 }
70
71 static inline floatx80 helper_fldt(CPUX86State *env, target_ulong ptr)
72 {
73 CPU_LDoubleU temp;
74
75 temp.l.lower = cpu_ldq_data(env, ptr);
76 temp.l.upper = cpu_lduw_data(env, ptr + 8);
77 return temp.d;
78 }
79
80 static inline void helper_fstt(CPUX86State *env, floatx80 f, target_ulong ptr)
81 {
82 CPU_LDoubleU temp;
83
84 temp.d = f;
85 cpu_stq_data(env, ptr, temp.l.lower);
86 cpu_stw_data(env, ptr + 8, temp.l.upper);
87 }
88
89 /* x87 FPU helpers */
90
91 static inline double floatx80_to_double(CPUX86State *env, floatx80 a)
92 {
93 union {
94 float64 f64;
95 double d;
96 } u;
97
98 u.f64 = floatx80_to_float64(a, &env->fp_status);
99 return u.d;
100 }
101
102 static inline floatx80 double_to_floatx80(CPUX86State *env, double a)
103 {
104 union {
105 float64 f64;
106 double d;
107 } u;
108
109 u.d = a;
110 return float64_to_floatx80(u.f64, &env->fp_status);
111 }
112
113 static void fpu_set_exception(CPUX86State *env, int mask)
114 {
115 env->fpus |= mask;
116 if (env->fpus & (~env->fpuc & FPUC_EM)) {
117 env->fpus |= FPUS_SE | FPUS_B;
118 }
119 }
120
121 static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
122 {
123 if (floatx80_is_zero(b)) {
124 fpu_set_exception(env, FPUS_ZE);
125 }
126 return floatx80_div(a, b, &env->fp_status);
127 }
128
129 static void fpu_raise_exception(CPUX86State *env)
130 {
131 if (env->cr[0] & CR0_NE_MASK) {
132 raise_exception(env, EXCP10_COPR);
133 }
134 #if !defined(CONFIG_USER_ONLY)
135 else {
136 cpu_set_ferr(env);
137 }
138 #endif
139 }
140
141 void helper_flds_FT0(CPUX86State *env, uint32_t val)
142 {
143 union {
144 float32 f;
145 uint32_t i;
146 } u;
147
148 u.i = val;
149 FT0 = float32_to_floatx80(u.f, &env->fp_status);
150 }
151
152 void helper_fldl_FT0(CPUX86State *env, uint64_t val)
153 {
154 union {
155 float64 f;
156 uint64_t i;
157 } u;
158
159 u.i = val;
160 FT0 = float64_to_floatx80(u.f, &env->fp_status);
161 }
162
163 void helper_fildl_FT0(CPUX86State *env, int32_t val)
164 {
165 FT0 = int32_to_floatx80(val, &env->fp_status);
166 }
167
168 void helper_flds_ST0(CPUX86State *env, uint32_t val)
169 {
170 int new_fpstt;
171 union {
172 float32 f;
173 uint32_t i;
174 } u;
175
176 new_fpstt = (env->fpstt - 1) & 7;
177 u.i = val;
178 env->fpregs[new_fpstt].d = float32_to_floatx80(u.f, &env->fp_status);
179 env->fpstt = new_fpstt;
180 env->fptags[new_fpstt] = 0; /* validate stack entry */
181 }
182
183 void helper_fldl_ST0(CPUX86State *env, uint64_t val)
184 {
185 int new_fpstt;
186 union {
187 float64 f;
188 uint64_t i;
189 } u;
190
191 new_fpstt = (env->fpstt - 1) & 7;
192 u.i = val;
193 env->fpregs[new_fpstt].d = float64_to_floatx80(u.f, &env->fp_status);
194 env->fpstt = new_fpstt;
195 env->fptags[new_fpstt] = 0; /* validate stack entry */
196 }
197
198 void helper_fildl_ST0(CPUX86State *env, int32_t val)
199 {
200 int new_fpstt;
201
202 new_fpstt = (env->fpstt - 1) & 7;
203 env->fpregs[new_fpstt].d = int32_to_floatx80(val, &env->fp_status);
204 env->fpstt = new_fpstt;
205 env->fptags[new_fpstt] = 0; /* validate stack entry */
206 }
207
208 void helper_fildll_ST0(CPUX86State *env, int64_t val)
209 {
210 int new_fpstt;
211
212 new_fpstt = (env->fpstt - 1) & 7;
213 env->fpregs[new_fpstt].d = int64_to_floatx80(val, &env->fp_status);
214 env->fpstt = new_fpstt;
215 env->fptags[new_fpstt] = 0; /* validate stack entry */
216 }
217
218 uint32_t helper_fsts_ST0(CPUX86State *env)
219 {
220 union {
221 float32 f;
222 uint32_t i;
223 } u;
224
225 u.f = floatx80_to_float32(ST0, &env->fp_status);
226 return u.i;
227 }
228
229 uint64_t helper_fstl_ST0(CPUX86State *env)
230 {
231 union {
232 float64 f;
233 uint64_t i;
234 } u;
235
236 u.f = floatx80_to_float64(ST0, &env->fp_status);
237 return u.i;
238 }
239
240 int32_t helper_fist_ST0(CPUX86State *env)
241 {
242 int32_t val;
243
244 val = floatx80_to_int32(ST0, &env->fp_status);
245 if (val != (int16_t)val) {
246 val = -32768;
247 }
248 return val;
249 }
250
251 int32_t helper_fistl_ST0(CPUX86State *env)
252 {
253 int32_t val;
254
255 val = floatx80_to_int32(ST0, &env->fp_status);
256 return val;
257 }
258
259 int64_t helper_fistll_ST0(CPUX86State *env)
260 {
261 int64_t val;
262
263 val = floatx80_to_int64(ST0, &env->fp_status);
264 return val;
265 }
266
267 int32_t helper_fistt_ST0(CPUX86State *env)
268 {
269 int32_t val;
270
271 val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
272 if (val != (int16_t)val) {
273 val = -32768;
274 }
275 return val;
276 }
277
278 int32_t helper_fisttl_ST0(CPUX86State *env)
279 {
280 int32_t val;
281
282 val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
283 return val;
284 }
285
286 int64_t helper_fisttll_ST0(CPUX86State *env)
287 {
288 int64_t val;
289
290 val = floatx80_to_int64_round_to_zero(ST0, &env->fp_status);
291 return val;
292 }
293
294 void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)
295 {
296 int new_fpstt;
297
298 new_fpstt = (env->fpstt - 1) & 7;
299 env->fpregs[new_fpstt].d = helper_fldt(env, ptr);
300 env->fpstt = new_fpstt;
301 env->fptags[new_fpstt] = 0; /* validate stack entry */
302 }
303
304 void helper_fstt_ST0(CPUX86State *env, target_ulong ptr)
305 {
306 helper_fstt(env, ST0, ptr);
307 }
308
309 void helper_fpush(CPUX86State *env)
310 {
311 fpush(env);
312 }
313
314 void helper_fpop(CPUX86State *env)
315 {
316 fpop(env);
317 }
318
319 void helper_fdecstp(CPUX86State *env)
320 {
321 env->fpstt = (env->fpstt - 1) & 7;
322 env->fpus &= ~0x4700;
323 }
324
325 void helper_fincstp(CPUX86State *env)
326 {
327 env->fpstt = (env->fpstt + 1) & 7;
328 env->fpus &= ~0x4700;
329 }
330
331 /* FPU move */
332
333 void helper_ffree_STN(CPUX86State *env, int st_index)
334 {
335 env->fptags[(env->fpstt + st_index) & 7] = 1;
336 }
337
338 void helper_fmov_ST0_FT0(CPUX86State *env)
339 {
340 ST0 = FT0;
341 }
342
343 void helper_fmov_FT0_STN(CPUX86State *env, int st_index)
344 {
345 FT0 = ST(st_index);
346 }
347
348 void helper_fmov_ST0_STN(CPUX86State *env, int st_index)
349 {
350 ST0 = ST(st_index);
351 }
352
353 void helper_fmov_STN_ST0(CPUX86State *env, int st_index)
354 {
355 ST(st_index) = ST0;
356 }
357
358 void helper_fxchg_ST0_STN(CPUX86State *env, int st_index)
359 {
360 floatx80 tmp;
361
362 tmp = ST(st_index);
363 ST(st_index) = ST0;
364 ST0 = tmp;
365 }
366
367 /* FPU operations */
368
369 static const int fcom_ccval[4] = {0x0100, 0x4000, 0x0000, 0x4500};
370
371 void helper_fcom_ST0_FT0(CPUX86State *env)
372 {
373 int ret;
374
375 ret = floatx80_compare(ST0, FT0, &env->fp_status);
376 env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
377 }
378
379 void helper_fucom_ST0_FT0(CPUX86State *env)
380 {
381 int ret;
382
383 ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
384 env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
385 }
386
387 static const int fcomi_ccval[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
388
389 void helper_fcomi_ST0_FT0(CPUX86State *env)
390 {
391 int eflags;
392 int ret;
393
394 ret = floatx80_compare(ST0, FT0, &env->fp_status);
395 eflags = cpu_cc_compute_all(env, CC_OP);
396 eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
397 CC_SRC = eflags;
398 }
399
400 void helper_fucomi_ST0_FT0(CPUX86State *env)
401 {
402 int eflags;
403 int ret;
404
405 ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
406 eflags = cpu_cc_compute_all(env, CC_OP);
407 eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
408 CC_SRC = eflags;
409 }
410
411 void helper_fadd_ST0_FT0(CPUX86State *env)
412 {
413 ST0 = floatx80_add(ST0, FT0, &env->fp_status);
414 }
415
416 void helper_fmul_ST0_FT0(CPUX86State *env)
417 {
418 ST0 = floatx80_mul(ST0, FT0, &env->fp_status);
419 }
420
421 void helper_fsub_ST0_FT0(CPUX86State *env)
422 {
423 ST0 = floatx80_sub(ST0, FT0, &env->fp_status);
424 }
425
426 void helper_fsubr_ST0_FT0(CPUX86State *env)
427 {
428 ST0 = floatx80_sub(FT0, ST0, &env->fp_status);
429 }
430
431 void helper_fdiv_ST0_FT0(CPUX86State *env)
432 {
433 ST0 = helper_fdiv(env, ST0, FT0);
434 }
435
436 void helper_fdivr_ST0_FT0(CPUX86State *env)
437 {
438 ST0 = helper_fdiv(env, FT0, ST0);
439 }
440
441 /* fp operations between STN and ST0 */
442
443 void helper_fadd_STN_ST0(CPUX86State *env, int st_index)
444 {
445 ST(st_index) = floatx80_add(ST(st_index), ST0, &env->fp_status);
446 }
447
448 void helper_fmul_STN_ST0(CPUX86State *env, int st_index)
449 {
450 ST(st_index) = floatx80_mul(ST(st_index), ST0, &env->fp_status);
451 }
452
453 void helper_fsub_STN_ST0(CPUX86State *env, int st_index)
454 {
455 ST(st_index) = floatx80_sub(ST(st_index), ST0, &env->fp_status);
456 }
457
458 void helper_fsubr_STN_ST0(CPUX86State *env, int st_index)
459 {
460 ST(st_index) = floatx80_sub(ST0, ST(st_index), &env->fp_status);
461 }
462
463 void helper_fdiv_STN_ST0(CPUX86State *env, int st_index)
464 {
465 floatx80 *p;
466
467 p = &ST(st_index);
468 *p = helper_fdiv(env, *p, ST0);
469 }
470
471 void helper_fdivr_STN_ST0(CPUX86State *env, int st_index)
472 {
473 floatx80 *p;
474
475 p = &ST(st_index);
476 *p = helper_fdiv(env, ST0, *p);
477 }
478
479 /* misc FPU operations */
480 void helper_fchs_ST0(CPUX86State *env)
481 {
482 ST0 = floatx80_chs(ST0);
483 }
484
485 void helper_fabs_ST0(CPUX86State *env)
486 {
487 ST0 = floatx80_abs(ST0);
488 }
489
490 void helper_fld1_ST0(CPUX86State *env)
491 {
492 ST0 = floatx80_one;
493 }
494
495 void helper_fldl2t_ST0(CPUX86State *env)
496 {
497 ST0 = floatx80_l2t;
498 }
499
500 void helper_fldl2e_ST0(CPUX86State *env)
501 {
502 ST0 = floatx80_l2e;
503 }
504
505 void helper_fldpi_ST0(CPUX86State *env)
506 {
507 ST0 = floatx80_pi;
508 }
509
510 void helper_fldlg2_ST0(CPUX86State *env)
511 {
512 ST0 = floatx80_lg2;
513 }
514
515 void helper_fldln2_ST0(CPUX86State *env)
516 {
517 ST0 = floatx80_ln2;
518 }
519
520 void helper_fldz_ST0(CPUX86State *env)
521 {
522 ST0 = floatx80_zero;
523 }
524
525 void helper_fldz_FT0(CPUX86State *env)
526 {
527 FT0 = floatx80_zero;
528 }
529
530 uint32_t helper_fnstsw(CPUX86State *env)
531 {
532 return (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
533 }
534
535 uint32_t helper_fnstcw(CPUX86State *env)
536 {
537 return env->fpuc;
538 }
539
540 static void update_fp_status(CPUX86State *env)
541 {
542 int rnd_type;
543
544 /* set rounding mode */
545 switch (env->fpuc & FPU_RC_MASK) {
546 default:
547 case FPU_RC_NEAR:
548 rnd_type = float_round_nearest_even;
549 break;
550 case FPU_RC_DOWN:
551 rnd_type = float_round_down;
552 break;
553 case FPU_RC_UP:
554 rnd_type = float_round_up;
555 break;
556 case FPU_RC_CHOP:
557 rnd_type = float_round_to_zero;
558 break;
559 }
560 set_float_rounding_mode(rnd_type, &env->fp_status);
561 switch ((env->fpuc >> 8) & 3) {
562 case 0:
563 rnd_type = 32;
564 break;
565 case 2:
566 rnd_type = 64;
567 break;
568 case 3:
569 default:
570 rnd_type = 80;
571 break;
572 }
573 set_floatx80_rounding_precision(rnd_type, &env->fp_status);
574 }
575
576 void helper_fldcw(CPUX86State *env, uint32_t val)
577 {
578 env->fpuc = val;
579 update_fp_status(env);
580 }
581
582 void helper_fclex(CPUX86State *env)
583 {
584 env->fpus &= 0x7f00;
585 }
586
587 void helper_fwait(CPUX86State *env)
588 {
589 if (env->fpus & FPUS_SE) {
590 fpu_raise_exception(env);
591 }
592 }
593
594 void helper_fninit(CPUX86State *env)
595 {
596 env->fpus = 0;
597 env->fpstt = 0;
598 env->fpuc = 0x37f;
599 env->fptags[0] = 1;
600 env->fptags[1] = 1;
601 env->fptags[2] = 1;
602 env->fptags[3] = 1;
603 env->fptags[4] = 1;
604 env->fptags[5] = 1;
605 env->fptags[6] = 1;
606 env->fptags[7] = 1;
607 }
608
609 /* BCD ops */
610
611 void helper_fbld_ST0(CPUX86State *env, target_ulong ptr)
612 {
613 floatx80 tmp;
614 uint64_t val;
615 unsigned int v;
616 int i;
617
618 val = 0;
619 for (i = 8; i >= 0; i--) {
620 v = cpu_ldub_data(env, ptr + i);
621 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
622 }
623 tmp = int64_to_floatx80(val, &env->fp_status);
624 if (cpu_ldub_data(env, ptr + 9) & 0x80) {
625 floatx80_chs(tmp);
626 }
627 fpush(env);
628 ST0 = tmp;
629 }
630
631 void helper_fbst_ST0(CPUX86State *env, target_ulong ptr)
632 {
633 int v;
634 target_ulong mem_ref, mem_end;
635 int64_t val;
636
637 val = floatx80_to_int64(ST0, &env->fp_status);
638 mem_ref = ptr;
639 mem_end = mem_ref + 9;
640 if (val < 0) {
641 cpu_stb_data(env, mem_end, 0x80);
642 val = -val;
643 } else {
644 cpu_stb_data(env, mem_end, 0x00);
645 }
646 while (mem_ref < mem_end) {
647 if (val == 0) {
648 break;
649 }
650 v = val % 100;
651 val = val / 100;
652 v = ((v / 10) << 4) | (v % 10);
653 cpu_stb_data(env, mem_ref++, v);
654 }
655 while (mem_ref < mem_end) {
656 cpu_stb_data(env, mem_ref++, 0);
657 }
658 }
659
660 void helper_f2xm1(CPUX86State *env)
661 {
662 double val = floatx80_to_double(env, ST0);
663
664 val = pow(2.0, val) - 1.0;
665 ST0 = double_to_floatx80(env, val);
666 }
667
668 void helper_fyl2x(CPUX86State *env)
669 {
670 double fptemp = floatx80_to_double(env, ST0);
671
672 if (fptemp > 0.0) {
673 fptemp = log(fptemp) / log(2.0); /* log2(ST) */
674 fptemp *= floatx80_to_double(env, ST1);
675 ST1 = double_to_floatx80(env, fptemp);
676 fpop(env);
677 } else {
678 env->fpus &= ~0x4700;
679 env->fpus |= 0x400;
680 }
681 }
682
683 void helper_fptan(CPUX86State *env)
684 {
685 double fptemp = floatx80_to_double(env, ST0);
686
687 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
688 env->fpus |= 0x400;
689 } else {
690 fptemp = tan(fptemp);
691 ST0 = double_to_floatx80(env, fptemp);
692 fpush(env);
693 ST0 = floatx80_one;
694 env->fpus &= ~0x400; /* C2 <-- 0 */
695 /* the above code is for |arg| < 2**52 only */
696 }
697 }
698
699 void helper_fpatan(CPUX86State *env)
700 {
701 double fptemp, fpsrcop;
702
703 fpsrcop = floatx80_to_double(env, ST1);
704 fptemp = floatx80_to_double(env, ST0);
705 ST1 = double_to_floatx80(env, atan2(fpsrcop, fptemp));
706 fpop(env);
707 }
708
709 void helper_fxtract(CPUX86State *env)
710 {
711 CPU_LDoubleU temp;
712
713 temp.d = ST0;
714
715 if (floatx80_is_zero(ST0)) {
716 /* Easy way to generate -inf and raising division by 0 exception */
717 ST0 = floatx80_div(floatx80_chs(floatx80_one), floatx80_zero,
718 &env->fp_status);
719 fpush(env);
720 ST0 = temp.d;
721 } else {
722 int expdif;
723
724 expdif = EXPD(temp) - EXPBIAS;
725 /* DP exponent bias */
726 ST0 = int32_to_floatx80(expdif, &env->fp_status);
727 fpush(env);
728 BIASEXPONENT(temp);
729 ST0 = temp.d;
730 }
731 }
732
733 void helper_fprem1(CPUX86State *env)
734 {
735 double st0, st1, dblq, fpsrcop, fptemp;
736 CPU_LDoubleU fpsrcop1, fptemp1;
737 int expdif;
738 signed long long int q;
739
740 st0 = floatx80_to_double(env, ST0);
741 st1 = floatx80_to_double(env, ST1);
742
743 if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
744 ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
745 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
746 return;
747 }
748
749 fpsrcop = st0;
750 fptemp = st1;
751 fpsrcop1.d = ST0;
752 fptemp1.d = ST1;
753 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
754
755 if (expdif < 0) {
756 /* optimisation? taken from the AMD docs */
757 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
758 /* ST0 is unchanged */
759 return;
760 }
761
762 if (expdif < 53) {
763 dblq = fpsrcop / fptemp;
764 /* round dblq towards nearest integer */
765 dblq = rint(dblq);
766 st0 = fpsrcop - fptemp * dblq;
767
768 /* convert dblq to q by truncating towards zero */
769 if (dblq < 0.0) {
770 q = (signed long long int)(-dblq);
771 } else {
772 q = (signed long long int)dblq;
773 }
774
775 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
776 /* (C0,C3,C1) <-- (q2,q1,q0) */
777 env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */
778 env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
779 env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */
780 } else {
781 env->fpus |= 0x400; /* C2 <-- 1 */
782 fptemp = pow(2.0, expdif - 50);
783 fpsrcop = (st0 / st1) / fptemp;
784 /* fpsrcop = integer obtained by chopping */
785 fpsrcop = (fpsrcop < 0.0) ?
786 -(floor(fabs(fpsrcop))) : floor(fpsrcop);
787 st0 -= (st1 * fpsrcop * fptemp);
788 }
789 ST0 = double_to_floatx80(env, st0);
790 }
791
792 void helper_fprem(CPUX86State *env)
793 {
794 double st0, st1, dblq, fpsrcop, fptemp;
795 CPU_LDoubleU fpsrcop1, fptemp1;
796 int expdif;
797 signed long long int q;
798
799 st0 = floatx80_to_double(env, ST0);
800 st1 = floatx80_to_double(env, ST1);
801
802 if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
803 ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
804 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
805 return;
806 }
807
808 fpsrcop = st0;
809 fptemp = st1;
810 fpsrcop1.d = ST0;
811 fptemp1.d = ST1;
812 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
813
814 if (expdif < 0) {
815 /* optimisation? taken from the AMD docs */
816 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
817 /* ST0 is unchanged */
818 return;
819 }
820
821 if (expdif < 53) {
822 dblq = fpsrcop / fptemp; /* ST0 / ST1 */
823 /* round dblq towards zero */
824 dblq = (dblq < 0.0) ? ceil(dblq) : floor(dblq);
825 st0 = fpsrcop - fptemp * dblq; /* fpsrcop is ST0 */
826
827 /* convert dblq to q by truncating towards zero */
828 if (dblq < 0.0) {
829 q = (signed long long int)(-dblq);
830 } else {
831 q = (signed long long int)dblq;
832 }
833
834 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
835 /* (C0,C3,C1) <-- (q2,q1,q0) */
836 env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */
837 env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
838 env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */
839 } else {
840 int N = 32 + (expdif % 32); /* as per AMD docs */
841
842 env->fpus |= 0x400; /* C2 <-- 1 */
843 fptemp = pow(2.0, (double)(expdif - N));
844 fpsrcop = (st0 / st1) / fptemp;
845 /* fpsrcop = integer obtained by chopping */
846 fpsrcop = (fpsrcop < 0.0) ?
847 -(floor(fabs(fpsrcop))) : floor(fpsrcop);
848 st0 -= (st1 * fpsrcop * fptemp);
849 }
850 ST0 = double_to_floatx80(env, st0);
851 }
852
853 void helper_fyl2xp1(CPUX86State *env)
854 {
855 double fptemp = floatx80_to_double(env, ST0);
856
857 if ((fptemp + 1.0) > 0.0) {
858 fptemp = log(fptemp + 1.0) / log(2.0); /* log2(ST + 1.0) */
859 fptemp *= floatx80_to_double(env, ST1);
860 ST1 = double_to_floatx80(env, fptemp);
861 fpop(env);
862 } else {
863 env->fpus &= ~0x4700;
864 env->fpus |= 0x400;
865 }
866 }
867
868 void helper_fsqrt(CPUX86State *env)
869 {
870 if (floatx80_is_neg(ST0)) {
871 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
872 env->fpus |= 0x400;
873 }
874 ST0 = floatx80_sqrt(ST0, &env->fp_status);
875 }
876
877 void helper_fsincos(CPUX86State *env)
878 {
879 double fptemp = floatx80_to_double(env, ST0);
880
881 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
882 env->fpus |= 0x400;
883 } else {
884 ST0 = double_to_floatx80(env, sin(fptemp));
885 fpush(env);
886 ST0 = double_to_floatx80(env, cos(fptemp));
887 env->fpus &= ~0x400; /* C2 <-- 0 */
888 /* the above code is for |arg| < 2**63 only */
889 }
890 }
891
892 void helper_frndint(CPUX86State *env)
893 {
894 ST0 = floatx80_round_to_int(ST0, &env->fp_status);
895 }
896
897 void helper_fscale(CPUX86State *env)
898 {
899 if (floatx80_is_any_nan(ST1)) {
900 ST0 = ST1;
901 } else {
902 int n = floatx80_to_int32_round_to_zero(ST1, &env->fp_status);
903 ST0 = floatx80_scalbn(ST0, n, &env->fp_status);
904 }
905 }
906
907 void helper_fsin(CPUX86State *env)
908 {
909 double fptemp = floatx80_to_double(env, ST0);
910
911 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
912 env->fpus |= 0x400;
913 } else {
914 ST0 = double_to_floatx80(env, sin(fptemp));
915 env->fpus &= ~0x400; /* C2 <-- 0 */
916 /* the above code is for |arg| < 2**53 only */
917 }
918 }
919
920 void helper_fcos(CPUX86State *env)
921 {
922 double fptemp = floatx80_to_double(env, ST0);
923
924 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
925 env->fpus |= 0x400;
926 } else {
927 ST0 = double_to_floatx80(env, cos(fptemp));
928 env->fpus &= ~0x400; /* C2 <-- 0 */
929 /* the above code is for |arg| < 2**63 only */
930 }
931 }
932
933 void helper_fxam_ST0(CPUX86State *env)
934 {
935 CPU_LDoubleU temp;
936 int expdif;
937
938 temp.d = ST0;
939
940 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
941 if (SIGND(temp)) {
942 env->fpus |= 0x200; /* C1 <-- 1 */
943 }
944
945 /* XXX: test fptags too */
946 expdif = EXPD(temp);
947 if (expdif == MAXEXPD) {
948 if (MANTD(temp) == 0x8000000000000000ULL) {
949 env->fpus |= 0x500; /* Infinity */
950 } else {
951 env->fpus |= 0x100; /* NaN */
952 }
953 } else if (expdif == 0) {
954 if (MANTD(temp) == 0) {
955 env->fpus |= 0x4000; /* Zero */
956 } else {
957 env->fpus |= 0x4400; /* Denormal */
958 }
959 } else {
960 env->fpus |= 0x400;
961 }
962 }
963
964 void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
965 {
966 int fpus, fptag, exp, i;
967 uint64_t mant;
968 CPU_LDoubleU tmp;
969
970 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
971 fptag = 0;
972 for (i = 7; i >= 0; i--) {
973 fptag <<= 2;
974 if (env->fptags[i]) {
975 fptag |= 3;
976 } else {
977 tmp.d = env->fpregs[i].d;
978 exp = EXPD(tmp);
979 mant = MANTD(tmp);
980 if (exp == 0 && mant == 0) {
981 /* zero */
982 fptag |= 1;
983 } else if (exp == 0 || exp == MAXEXPD
984 || (mant & (1LL << 63)) == 0) {
985 /* NaNs, infinity, denormal */
986 fptag |= 2;
987 }
988 }
989 }
990 if (data32) {
991 /* 32 bit */
992 cpu_stl_data(env, ptr, env->fpuc);
993 cpu_stl_data(env, ptr + 4, fpus);
994 cpu_stl_data(env, ptr + 8, fptag);
995 cpu_stl_data(env, ptr + 12, 0); /* fpip */
996 cpu_stl_data(env, ptr + 16, 0); /* fpcs */
997 cpu_stl_data(env, ptr + 20, 0); /* fpoo */
998 cpu_stl_data(env, ptr + 24, 0); /* fpos */
999 } else {
1000 /* 16 bit */
1001 cpu_stw_data(env, ptr, env->fpuc);
1002 cpu_stw_data(env, ptr + 2, fpus);
1003 cpu_stw_data(env, ptr + 4, fptag);
1004 cpu_stw_data(env, ptr + 6, 0);
1005 cpu_stw_data(env, ptr + 8, 0);
1006 cpu_stw_data(env, ptr + 10, 0);
1007 cpu_stw_data(env, ptr + 12, 0);
1008 }
1009 }
1010
1011 void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
1012 {
1013 int i, fpus, fptag;
1014
1015 if (data32) {
1016 env->fpuc = cpu_lduw_data(env, ptr);
1017 fpus = cpu_lduw_data(env, ptr + 4);
1018 fptag = cpu_lduw_data(env, ptr + 8);
1019 } else {
1020 env->fpuc = cpu_lduw_data(env, ptr);
1021 fpus = cpu_lduw_data(env, ptr + 2);
1022 fptag = cpu_lduw_data(env, ptr + 4);
1023 }
1024 env->fpstt = (fpus >> 11) & 7;
1025 env->fpus = fpus & ~0x3800;
1026 for (i = 0; i < 8; i++) {
1027 env->fptags[i] = ((fptag & 3) == 3);
1028 fptag >>= 2;
1029 }
1030 }
1031
1032 void helper_fsave(CPUX86State *env, target_ulong ptr, int data32)
1033 {
1034 floatx80 tmp;
1035 int i;
1036
1037 helper_fstenv(env, ptr, data32);
1038
1039 ptr += (14 << data32);
1040 for (i = 0; i < 8; i++) {
1041 tmp = ST(i);
1042 helper_fstt(env, tmp, ptr);
1043 ptr += 10;
1044 }
1045
1046 /* fninit */
1047 env->fpus = 0;
1048 env->fpstt = 0;
1049 env->fpuc = 0x37f;
1050 env->fptags[0] = 1;
1051 env->fptags[1] = 1;
1052 env->fptags[2] = 1;
1053 env->fptags[3] = 1;
1054 env->fptags[4] = 1;
1055 env->fptags[5] = 1;
1056 env->fptags[6] = 1;
1057 env->fptags[7] = 1;
1058 }
1059
1060 void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)
1061 {
1062 floatx80 tmp;
1063 int i;
1064
1065 helper_fldenv(env, ptr, data32);
1066 ptr += (14 << data32);
1067
1068 for (i = 0; i < 8; i++) {
1069 tmp = helper_fldt(env, ptr);
1070 ST(i) = tmp;
1071 ptr += 10;
1072 }
1073 }
1074
1075 #if defined(CONFIG_USER_ONLY)
1076 void cpu_x86_fsave(CPUX86State *env, target_ulong ptr, int data32)
1077 {
1078 helper_fsave(env, ptr, data32);
1079 }
1080
1081 void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
1082 {
1083 helper_frstor(env, ptr, data32);
1084 }
1085 #endif
1086
1087 void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)
1088 {
1089 int fpus, fptag, i, nb_xmm_regs;
1090 floatx80 tmp;
1091 target_ulong addr;
1092
1093 /* The operand must be 16 byte aligned */
1094 if (ptr & 0xf) {
1095 raise_exception(env, EXCP0D_GPF);
1096 }
1097
1098 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1099 fptag = 0;
1100 for (i = 0; i < 8; i++) {
1101 fptag |= (env->fptags[i] << i);
1102 }
1103 cpu_stw_data(env, ptr, env->fpuc);
1104 cpu_stw_data(env, ptr + 2, fpus);
1105 cpu_stw_data(env, ptr + 4, fptag ^ 0xff);
1106 #ifdef TARGET_X86_64
1107 if (data64) {
1108 cpu_stq_data(env, ptr + 0x08, 0); /* rip */
1109 cpu_stq_data(env, ptr + 0x10, 0); /* rdp */
1110 } else
1111 #endif
1112 {
1113 cpu_stl_data(env, ptr + 0x08, 0); /* eip */
1114 cpu_stl_data(env, ptr + 0x0c, 0); /* sel */
1115 cpu_stl_data(env, ptr + 0x10, 0); /* dp */
1116 cpu_stl_data(env, ptr + 0x14, 0); /* sel */
1117 }
1118
1119 addr = ptr + 0x20;
1120 for (i = 0; i < 8; i++) {
1121 tmp = ST(i);
1122 helper_fstt(env, tmp, addr);
1123 addr += 16;
1124 }
1125
1126 if (env->cr[4] & CR4_OSFXSR_MASK) {
1127 /* XXX: finish it */
1128 cpu_stl_data(env, ptr + 0x18, env->mxcsr); /* mxcsr */
1129 cpu_stl_data(env, ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
1130 if (env->hflags & HF_CS64_MASK) {
1131 nb_xmm_regs = 16;
1132 } else {
1133 nb_xmm_regs = 8;
1134 }
1135 addr = ptr + 0xa0;
1136 /* Fast FXSAVE leaves out the XMM registers */
1137 if (!(env->efer & MSR_EFER_FFXSR)
1138 || (env->hflags & HF_CPL_MASK)
1139 || !(env->hflags & HF_LMA_MASK)) {
1140 for (i = 0; i < nb_xmm_regs; i++) {
1141 cpu_stq_data(env, addr, env->xmm_regs[i].XMM_Q(0));
1142 cpu_stq_data(env, addr + 8, env->xmm_regs[i].XMM_Q(1));
1143 addr += 16;
1144 }
1145 }
1146 }
1147 }
1148
1149 void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)
1150 {
1151 int i, fpus, fptag, nb_xmm_regs;
1152 floatx80 tmp;
1153 target_ulong addr;
1154
1155 /* The operand must be 16 byte aligned */
1156 if (ptr & 0xf) {
1157 raise_exception(env, EXCP0D_GPF);
1158 }
1159
1160 env->fpuc = cpu_lduw_data(env, ptr);
1161 fpus = cpu_lduw_data(env, ptr + 2);
1162 fptag = cpu_lduw_data(env, ptr + 4);
1163 env->fpstt = (fpus >> 11) & 7;
1164 env->fpus = fpus & ~0x3800;
1165 fptag ^= 0xff;
1166 for (i = 0; i < 8; i++) {
1167 env->fptags[i] = ((fptag >> i) & 1);
1168 }
1169
1170 addr = ptr + 0x20;
1171 for (i = 0; i < 8; i++) {
1172 tmp = helper_fldt(env, addr);
1173 ST(i) = tmp;
1174 addr += 16;
1175 }
1176
1177 if (env->cr[4] & CR4_OSFXSR_MASK) {
1178 /* XXX: finish it */
1179 cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18));
1180 /* cpu_ldl_data(env, ptr + 0x1c); */
1181 if (env->hflags & HF_CS64_MASK) {
1182 nb_xmm_regs = 16;
1183 } else {
1184 nb_xmm_regs = 8;
1185 }
1186 addr = ptr + 0xa0;
1187 /* Fast FXRESTORE leaves out the XMM registers */
1188 if (!(env->efer & MSR_EFER_FFXSR)
1189 || (env->hflags & HF_CPL_MASK)
1190 || !(env->hflags & HF_LMA_MASK)) {
1191 for (i = 0; i < nb_xmm_regs; i++) {
1192 env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr);
1193 env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8);
1194 addr += 16;
1195 }
1196 }
1197 }
1198 }
1199
1200 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f)
1201 {
1202 CPU_LDoubleU temp;
1203
1204 temp.d = f;
1205 *pmant = temp.l.lower;
1206 *pexp = temp.l.upper;
1207 }
1208
1209 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper)
1210 {
1211 CPU_LDoubleU temp;
1212
1213 temp.l.upper = upper;
1214 temp.l.lower = mant;
1215 return temp.d;
1216 }
1217
1218 /* MMX/SSE */
1219 /* XXX: optimize by storing fptt and fptags in the static cpu state */
1220
1221 #define SSE_DAZ 0x0040
1222 #define SSE_RC_MASK 0x6000
1223 #define SSE_RC_NEAR 0x0000
1224 #define SSE_RC_DOWN 0x2000
1225 #define SSE_RC_UP 0x4000
1226 #define SSE_RC_CHOP 0x6000
1227 #define SSE_FZ 0x8000
1228
1229 void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1230 {
1231 int rnd_type;
1232
1233 env->mxcsr = mxcsr;
1234
1235 /* set rounding mode */
1236 switch (mxcsr & SSE_RC_MASK) {
1237 default:
1238 case SSE_RC_NEAR:
1239 rnd_type = float_round_nearest_even;
1240 break;
1241 case SSE_RC_DOWN:
1242 rnd_type = float_round_down;
1243 break;
1244 case SSE_RC_UP:
1245 rnd_type = float_round_up;
1246 break;
1247 case SSE_RC_CHOP:
1248 rnd_type = float_round_to_zero;
1249 break;
1250 }
1251 set_float_rounding_mode(rnd_type, &env->sse_status);
1252
1253 /* set denormals are zero */
1254 set_flush_inputs_to_zero((mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status);
1255
1256 /* set flush to zero */
1257 set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status);
1258 }
1259
1260 void helper_ldmxcsr(CPUX86State *env, uint32_t val)
1261 {
1262 cpu_set_mxcsr(env, val);
1263 }
1264
1265 void helper_enter_mmx(CPUX86State *env)
1266 {
1267 env->fpstt = 0;
1268 *(uint32_t *)(env->fptags) = 0;
1269 *(uint32_t *)(env->fptags + 4) = 0;
1270 }
1271
1272 void helper_emms(CPUX86State *env)
1273 {
1274 /* set to empty state */
1275 *(uint32_t *)(env->fptags) = 0x01010101;
1276 *(uint32_t *)(env->fptags + 4) = 0x01010101;
1277 }
1278
1279 /* XXX: suppress */
1280 void helper_movq(CPUX86State *env, void *d, void *s)
1281 {
1282 *(uint64_t *)d = *(uint64_t *)s;
1283 }
1284
1285 #define SHIFT 0
1286 #include "ops_sse.h"
1287
1288 #define SHIFT 1
1289 #include "ops_sse.h"
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