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more fpu functions - x86_64 fixes
[mirror_qemu.git] / target-i386 / helper.c
1 /*
2 * i386 helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21
22 //#define DEBUG_PCALL
23
24 #if 0
25 #define raise_exception_err(a, b)\
26 do {\
27 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
28 (raise_exception_err)(a, b);\
29 } while (0)
30 #endif
31
32 const uint8_t parity_table[256] = {
33 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
34 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
35 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
36 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
37 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
38 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
41 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
42 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
43 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
44 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
45 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
46 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
47 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
49 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
50 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
53 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
54 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
58 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
59 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
61 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
62 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
63 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
65 };
66
67 /* modulo 17 table */
68 const uint8_t rclw_table[32] = {
69 0, 1, 2, 3, 4, 5, 6, 7,
70 8, 9,10,11,12,13,14,15,
71 16, 0, 1, 2, 3, 4, 5, 6,
72 7, 8, 9,10,11,12,13,14,
73 };
74
75 /* modulo 9 table */
76 const uint8_t rclb_table[32] = {
77 0, 1, 2, 3, 4, 5, 6, 7,
78 8, 0, 1, 2, 3, 4, 5, 6,
79 7, 8, 0, 1, 2, 3, 4, 5,
80 6, 7, 8, 0, 1, 2, 3, 4,
81 };
82
83 const CPU86_LDouble f15rk[7] =
84 {
85 0.00000000000000000000L,
86 1.00000000000000000000L,
87 3.14159265358979323851L, /*pi*/
88 0.30102999566398119523L, /*lg2*/
89 0.69314718055994530943L, /*ln2*/
90 1.44269504088896340739L, /*l2e*/
91 3.32192809488736234781L, /*l2t*/
92 };
93
94 /* thread support */
95
96 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
97
98 void cpu_lock(void)
99 {
100 spin_lock(&global_cpu_lock);
101 }
102
103 void cpu_unlock(void)
104 {
105 spin_unlock(&global_cpu_lock);
106 }
107
108 void cpu_loop_exit(void)
109 {
110 /* NOTE: the register at this point must be saved by hand because
111 longjmp restore them */
112 regs_to_env();
113 longjmp(env->jmp_env, 1);
114 }
115
116 /* return non zero if error */
117 static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
118 int selector)
119 {
120 SegmentCache *dt;
121 int index;
122 target_ulong ptr;
123
124 if (selector & 0x4)
125 dt = &env->ldt;
126 else
127 dt = &env->gdt;
128 index = selector & ~7;
129 if ((index + 7) > dt->limit)
130 return -1;
131 ptr = dt->base + index;
132 *e1_ptr = ldl_kernel(ptr);
133 *e2_ptr = ldl_kernel(ptr + 4);
134 return 0;
135 }
136
137 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
138 {
139 unsigned int limit;
140 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
141 if (e2 & DESC_G_MASK)
142 limit = (limit << 12) | 0xfff;
143 return limit;
144 }
145
146 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
147 {
148 return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
149 }
150
151 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
152 {
153 sc->base = get_seg_base(e1, e2);
154 sc->limit = get_seg_limit(e1, e2);
155 sc->flags = e2;
156 }
157
158 /* init the segment cache in vm86 mode. */
159 static inline void load_seg_vm(int seg, int selector)
160 {
161 selector &= 0xffff;
162 cpu_x86_load_seg_cache(env, seg, selector,
163 (selector << 4), 0xffff, 0);
164 }
165
166 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
167 uint32_t *esp_ptr, int dpl)
168 {
169 int type, index, shift;
170
171 #if 0
172 {
173 int i;
174 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
175 for(i=0;i<env->tr.limit;i++) {
176 printf("%02x ", env->tr.base[i]);
177 if ((i & 7) == 7) printf("\n");
178 }
179 printf("\n");
180 }
181 #endif
182
183 if (!(env->tr.flags & DESC_P_MASK))
184 cpu_abort(env, "invalid tss");
185 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
186 if ((type & 7) != 1)
187 cpu_abort(env, "invalid tss type");
188 shift = type >> 3;
189 index = (dpl * 4 + 2) << shift;
190 if (index + (4 << shift) - 1 > env->tr.limit)
191 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
192 if (shift == 0) {
193 *esp_ptr = lduw_kernel(env->tr.base + index);
194 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
195 } else {
196 *esp_ptr = ldl_kernel(env->tr.base + index);
197 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
198 }
199 }
200
201 /* XXX: merge with load_seg() */
202 static void tss_load_seg(int seg_reg, int selector)
203 {
204 uint32_t e1, e2;
205 int rpl, dpl, cpl;
206
207 if ((selector & 0xfffc) != 0) {
208 if (load_segment(&e1, &e2, selector) != 0)
209 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
210 if (!(e2 & DESC_S_MASK))
211 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
212 rpl = selector & 3;
213 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
214 cpl = env->hflags & HF_CPL_MASK;
215 if (seg_reg == R_CS) {
216 if (!(e2 & DESC_CS_MASK))
217 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
218 if (dpl != rpl)
219 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
220 if ((e2 & DESC_C_MASK) && dpl > rpl)
221 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
222
223 } else if (seg_reg == R_SS) {
224 /* SS must be writable data */
225 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
226 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
227 if (dpl != cpl || dpl != rpl)
228 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
229 } else {
230 /* not readable code */
231 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
232 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
233 /* if data or non conforming code, checks the rights */
234 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
235 if (dpl < cpl || dpl < rpl)
236 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
237 }
238 }
239 if (!(e2 & DESC_P_MASK))
240 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
241 cpu_x86_load_seg_cache(env, seg_reg, selector,
242 get_seg_base(e1, e2),
243 get_seg_limit(e1, e2),
244 e2);
245 } else {
246 if (seg_reg == R_SS || seg_reg == R_CS)
247 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
248 }
249 }
250
251 #define SWITCH_TSS_JMP 0
252 #define SWITCH_TSS_IRET 1
253 #define SWITCH_TSS_CALL 2
254
255 /* XXX: restore CPU state in registers (PowerPC case) */
256 static void switch_tss(int tss_selector,
257 uint32_t e1, uint32_t e2, int source,
258 uint32_t next_eip)
259 {
260 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
261 target_ulong tss_base;
262 uint32_t new_regs[8], new_segs[6];
263 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
264 uint32_t old_eflags, eflags_mask;
265 SegmentCache *dt;
266 int index;
267 target_ulong ptr;
268
269 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
270 #ifdef DEBUG_PCALL
271 if (loglevel & CPU_LOG_PCALL)
272 fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
273 #endif
274
275 /* if task gate, we read the TSS segment and we load it */
276 if (type == 5) {
277 if (!(e2 & DESC_P_MASK))
278 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
279 tss_selector = e1 >> 16;
280 if (tss_selector & 4)
281 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
282 if (load_segment(&e1, &e2, tss_selector) != 0)
283 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
284 if (e2 & DESC_S_MASK)
285 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
286 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
287 if ((type & 7) != 1)
288 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
289 }
290
291 if (!(e2 & DESC_P_MASK))
292 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
293
294 if (type & 8)
295 tss_limit_max = 103;
296 else
297 tss_limit_max = 43;
298 tss_limit = get_seg_limit(e1, e2);
299 tss_base = get_seg_base(e1, e2);
300 if ((tss_selector & 4) != 0 ||
301 tss_limit < tss_limit_max)
302 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
303 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
304 if (old_type & 8)
305 old_tss_limit_max = 103;
306 else
307 old_tss_limit_max = 43;
308
309 /* read all the registers from the new TSS */
310 if (type & 8) {
311 /* 32 bit */
312 new_cr3 = ldl_kernel(tss_base + 0x1c);
313 new_eip = ldl_kernel(tss_base + 0x20);
314 new_eflags = ldl_kernel(tss_base + 0x24);
315 for(i = 0; i < 8; i++)
316 new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
317 for(i = 0; i < 6; i++)
318 new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
319 new_ldt = lduw_kernel(tss_base + 0x60);
320 new_trap = ldl_kernel(tss_base + 0x64);
321 } else {
322 /* 16 bit */
323 new_cr3 = 0;
324 new_eip = lduw_kernel(tss_base + 0x0e);
325 new_eflags = lduw_kernel(tss_base + 0x10);
326 for(i = 0; i < 8; i++)
327 new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;
328 for(i = 0; i < 4; i++)
329 new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
330 new_ldt = lduw_kernel(tss_base + 0x2a);
331 new_segs[R_FS] = 0;
332 new_segs[R_GS] = 0;
333 new_trap = 0;
334 }
335
336 /* NOTE: we must avoid memory exceptions during the task switch,
337 so we make dummy accesses before */
338 /* XXX: it can still fail in some cases, so a bigger hack is
339 necessary to valid the TLB after having done the accesses */
340
341 v1 = ldub_kernel(env->tr.base);
342 v2 = ldub(env->tr.base + old_tss_limit_max);
343 stb_kernel(env->tr.base, v1);
344 stb_kernel(env->tr.base + old_tss_limit_max, v2);
345
346 /* clear busy bit (it is restartable) */
347 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
348 target_ulong ptr;
349 uint32_t e2;
350 ptr = env->gdt.base + (env->tr.selector & ~7);
351 e2 = ldl_kernel(ptr + 4);
352 e2 &= ~DESC_TSS_BUSY_MASK;
353 stl_kernel(ptr + 4, e2);
354 }
355 old_eflags = compute_eflags();
356 if (source == SWITCH_TSS_IRET)
357 old_eflags &= ~NT_MASK;
358
359 /* save the current state in the old TSS */
360 if (type & 8) {
361 /* 32 bit */
362 stl_kernel(env->tr.base + 0x20, next_eip);
363 stl_kernel(env->tr.base + 0x24, old_eflags);
364 stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
365 stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
366 stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
367 stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
368 stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
369 stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
370 stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
371 stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
372 for(i = 0; i < 6; i++)
373 stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
374 } else {
375 /* 16 bit */
376 stw_kernel(env->tr.base + 0x0e, next_eip);
377 stw_kernel(env->tr.base + 0x10, old_eflags);
378 stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
379 stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
380 stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
381 stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
382 stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
383 stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
384 stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
385 stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
386 for(i = 0; i < 4; i++)
387 stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
388 }
389
390 /* now if an exception occurs, it will occurs in the next task
391 context */
392
393 if (source == SWITCH_TSS_CALL) {
394 stw_kernel(tss_base, env->tr.selector);
395 new_eflags |= NT_MASK;
396 }
397
398 /* set busy bit */
399 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
400 target_ulong ptr;
401 uint32_t e2;
402 ptr = env->gdt.base + (tss_selector & ~7);
403 e2 = ldl_kernel(ptr + 4);
404 e2 |= DESC_TSS_BUSY_MASK;
405 stl_kernel(ptr + 4, e2);
406 }
407
408 /* set the new CPU state */
409 /* from this point, any exception which occurs can give problems */
410 env->cr[0] |= CR0_TS_MASK;
411 env->hflags |= HF_TS_MASK;
412 env->tr.selector = tss_selector;
413 env->tr.base = tss_base;
414 env->tr.limit = tss_limit;
415 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
416
417 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
418 cpu_x86_update_cr3(env, new_cr3);
419 }
420
421 /* load all registers without an exception, then reload them with
422 possible exception */
423 env->eip = new_eip;
424 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
425 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
426 if (!(type & 8))
427 eflags_mask &= 0xffff;
428 load_eflags(new_eflags, eflags_mask);
429 /* XXX: what to do in 16 bit case ? */
430 EAX = new_regs[0];
431 ECX = new_regs[1];
432 EDX = new_regs[2];
433 EBX = new_regs[3];
434 ESP = new_regs[4];
435 EBP = new_regs[5];
436 ESI = new_regs[6];
437 EDI = new_regs[7];
438 if (new_eflags & VM_MASK) {
439 for(i = 0; i < 6; i++)
440 load_seg_vm(i, new_segs[i]);
441 /* in vm86, CPL is always 3 */
442 cpu_x86_set_cpl(env, 3);
443 } else {
444 /* CPL is set the RPL of CS */
445 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
446 /* first just selectors as the rest may trigger exceptions */
447 for(i = 0; i < 6; i++)
448 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
449 }
450
451 env->ldt.selector = new_ldt & ~4;
452 env->ldt.base = 0;
453 env->ldt.limit = 0;
454 env->ldt.flags = 0;
455
456 /* load the LDT */
457 if (new_ldt & 4)
458 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
459
460 if ((new_ldt & 0xfffc) != 0) {
461 dt = &env->gdt;
462 index = new_ldt & ~7;
463 if ((index + 7) > dt->limit)
464 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
465 ptr = dt->base + index;
466 e1 = ldl_kernel(ptr);
467 e2 = ldl_kernel(ptr + 4);
468 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
469 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
470 if (!(e2 & DESC_P_MASK))
471 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
472 load_seg_cache_raw_dt(&env->ldt, e1, e2);
473 }
474
475 /* load the segments */
476 if (!(new_eflags & VM_MASK)) {
477 tss_load_seg(R_CS, new_segs[R_CS]);
478 tss_load_seg(R_SS, new_segs[R_SS]);
479 tss_load_seg(R_ES, new_segs[R_ES]);
480 tss_load_seg(R_DS, new_segs[R_DS]);
481 tss_load_seg(R_FS, new_segs[R_FS]);
482 tss_load_seg(R_GS, new_segs[R_GS]);
483 }
484
485 /* check that EIP is in the CS segment limits */
486 if (new_eip > env->segs[R_CS].limit) {
487 /* XXX: different exception if CALL ? */
488 raise_exception_err(EXCP0D_GPF, 0);
489 }
490 }
491
492 /* check if Port I/O is allowed in TSS */
493 static inline void check_io(int addr, int size)
494 {
495 int io_offset, val, mask;
496
497 /* TSS must be a valid 32 bit one */
498 if (!(env->tr.flags & DESC_P_MASK) ||
499 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
500 env->tr.limit < 103)
501 goto fail;
502 io_offset = lduw_kernel(env->tr.base + 0x66);
503 io_offset += (addr >> 3);
504 /* Note: the check needs two bytes */
505 if ((io_offset + 1) > env->tr.limit)
506 goto fail;
507 val = lduw_kernel(env->tr.base + io_offset);
508 val >>= (addr & 7);
509 mask = (1 << size) - 1;
510 /* all bits must be zero to allow the I/O */
511 if ((val & mask) != 0) {
512 fail:
513 raise_exception_err(EXCP0D_GPF, 0);
514 }
515 }
516
517 void check_iob_T0(void)
518 {
519 check_io(T0, 1);
520 }
521
522 void check_iow_T0(void)
523 {
524 check_io(T0, 2);
525 }
526
527 void check_iol_T0(void)
528 {
529 check_io(T0, 4);
530 }
531
532 void check_iob_DX(void)
533 {
534 check_io(EDX & 0xffff, 1);
535 }
536
537 void check_iow_DX(void)
538 {
539 check_io(EDX & 0xffff, 2);
540 }
541
542 void check_iol_DX(void)
543 {
544 check_io(EDX & 0xffff, 4);
545 }
546
547 static inline unsigned int get_sp_mask(unsigned int e2)
548 {
549 if (e2 & DESC_B_MASK)
550 return 0xffffffff;
551 else
552 return 0xffff;
553 }
554
555 /* XXX: add a is_user flag to have proper security support */
556 #define PUSHW(ssp, sp, sp_mask, val)\
557 {\
558 sp -= 2;\
559 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
560 }
561
562 #define PUSHL(ssp, sp, sp_mask, val)\
563 {\
564 sp -= 4;\
565 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
566 }
567
568 #define POPW(ssp, sp, sp_mask, val)\
569 {\
570 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
571 sp += 2;\
572 }
573
574 #define POPL(ssp, sp, sp_mask, val)\
575 {\
576 val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
577 sp += 4;\
578 }
579
580 /* protected mode interrupt */
581 static void do_interrupt_protected(int intno, int is_int, int error_code,
582 unsigned int next_eip, int is_hw)
583 {
584 SegmentCache *dt;
585 target_ulong ptr, ssp;
586 int type, dpl, selector, ss_dpl, cpl, sp_mask;
587 int has_error_code, new_stack, shift;
588 uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
589 uint32_t old_eip;
590
591 has_error_code = 0;
592 if (!is_int && !is_hw) {
593 switch(intno) {
594 case 8:
595 case 10:
596 case 11:
597 case 12:
598 case 13:
599 case 14:
600 case 17:
601 has_error_code = 1;
602 break;
603 }
604 }
605 if (is_int)
606 old_eip = next_eip;
607 else
608 old_eip = env->eip;
609
610 dt = &env->idt;
611 if (intno * 8 + 7 > dt->limit)
612 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
613 ptr = dt->base + intno * 8;
614 e1 = ldl_kernel(ptr);
615 e2 = ldl_kernel(ptr + 4);
616 /* check gate type */
617 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
618 switch(type) {
619 case 5: /* task gate */
620 /* must do that check here to return the correct error code */
621 if (!(e2 & DESC_P_MASK))
622 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
623 switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
624 if (has_error_code) {
625 int mask;
626 /* push the error code */
627 shift = (env->segs[R_CS].flags >> DESC_B_SHIFT) & 1;
628 if (env->segs[R_SS].flags & DESC_B_MASK)
629 mask = 0xffffffff;
630 else
631 mask = 0xffff;
632 esp = (ESP - (2 << shift)) & mask;
633 ssp = env->segs[R_SS].base + esp;
634 if (shift)
635 stl_kernel(ssp, error_code);
636 else
637 stw_kernel(ssp, error_code);
638 ESP = (esp & mask) | (ESP & ~mask);
639 }
640 return;
641 case 6: /* 286 interrupt gate */
642 case 7: /* 286 trap gate */
643 case 14: /* 386 interrupt gate */
644 case 15: /* 386 trap gate */
645 break;
646 default:
647 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
648 break;
649 }
650 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
651 cpl = env->hflags & HF_CPL_MASK;
652 /* check privledge if software int */
653 if (is_int && dpl < cpl)
654 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
655 /* check valid bit */
656 if (!(e2 & DESC_P_MASK))
657 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
658 selector = e1 >> 16;
659 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
660 if ((selector & 0xfffc) == 0)
661 raise_exception_err(EXCP0D_GPF, 0);
662
663 if (load_segment(&e1, &e2, selector) != 0)
664 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
665 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
666 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
667 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
668 if (dpl > cpl)
669 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
670 if (!(e2 & DESC_P_MASK))
671 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
672 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
673 /* to inner priviledge */
674 get_ss_esp_from_tss(&ss, &esp, dpl);
675 if ((ss & 0xfffc) == 0)
676 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
677 if ((ss & 3) != dpl)
678 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
679 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
680 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
681 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
682 if (ss_dpl != dpl)
683 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
684 if (!(ss_e2 & DESC_S_MASK) ||
685 (ss_e2 & DESC_CS_MASK) ||
686 !(ss_e2 & DESC_W_MASK))
687 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
688 if (!(ss_e2 & DESC_P_MASK))
689 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
690 new_stack = 1;
691 sp_mask = get_sp_mask(ss_e2);
692 ssp = get_seg_base(ss_e1, ss_e2);
693 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
694 /* to same priviledge */
695 if (env->eflags & VM_MASK)
696 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
697 new_stack = 0;
698 sp_mask = get_sp_mask(env->segs[R_SS].flags);
699 ssp = env->segs[R_SS].base;
700 esp = ESP;
701 dpl = cpl;
702 } else {
703 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
704 new_stack = 0; /* avoid warning */
705 sp_mask = 0; /* avoid warning */
706 ssp = 0; /* avoid warning */
707 esp = 0; /* avoid warning */
708 }
709
710 shift = type >> 3;
711
712 #if 0
713 /* XXX: check that enough room is available */
714 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
715 if (env->eflags & VM_MASK)
716 push_size += 8;
717 push_size <<= shift;
718 #endif
719 if (shift == 1) {
720 if (new_stack) {
721 if (env->eflags & VM_MASK) {
722 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
723 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
724 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
725 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
726 }
727 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
728 PUSHL(ssp, esp, sp_mask, ESP);
729 }
730 PUSHL(ssp, esp, sp_mask, compute_eflags());
731 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
732 PUSHL(ssp, esp, sp_mask, old_eip);
733 if (has_error_code) {
734 PUSHL(ssp, esp, sp_mask, error_code);
735 }
736 } else {
737 if (new_stack) {
738 if (env->eflags & VM_MASK) {
739 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
740 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
741 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
742 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
743 }
744 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
745 PUSHW(ssp, esp, sp_mask, ESP);
746 }
747 PUSHW(ssp, esp, sp_mask, compute_eflags());
748 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
749 PUSHW(ssp, esp, sp_mask, old_eip);
750 if (has_error_code) {
751 PUSHW(ssp, esp, sp_mask, error_code);
752 }
753 }
754
755 if (new_stack) {
756 if (env->eflags & VM_MASK) {
757 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
758 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
759 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
760 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
761 }
762 ss = (ss & ~3) | dpl;
763 cpu_x86_load_seg_cache(env, R_SS, ss,
764 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
765 }
766 ESP = (ESP & ~sp_mask) | (esp & sp_mask);
767
768 selector = (selector & ~3) | dpl;
769 cpu_x86_load_seg_cache(env, R_CS, selector,
770 get_seg_base(e1, e2),
771 get_seg_limit(e1, e2),
772 e2);
773 cpu_x86_set_cpl(env, dpl);
774 env->eip = offset;
775
776 /* interrupt gate clear IF mask */
777 if ((type & 1) == 0) {
778 env->eflags &= ~IF_MASK;
779 }
780 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
781 }
782
783 #ifdef TARGET_X86_64
784
785 #define PUSHQ(sp, val)\
786 {\
787 sp -= 8;\
788 stq_kernel(sp, (val));\
789 }
790
791 #define POPQ(sp, val)\
792 {\
793 val = ldq_kernel(sp);\
794 sp += 8;\
795 }
796
797 static inline target_ulong get_rsp_from_tss(int level)
798 {
799 int index;
800
801 #if 0
802 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
803 env->tr.base, env->tr.limit);
804 #endif
805
806 if (!(env->tr.flags & DESC_P_MASK))
807 cpu_abort(env, "invalid tss");
808 index = 8 * level + 4;
809 if ((index + 7) > env->tr.limit)
810 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
811 return ldq_kernel(env->tr.base + index);
812 }
813
814 /* 64 bit interrupt */
815 static void do_interrupt64(int intno, int is_int, int error_code,
816 target_ulong next_eip, int is_hw)
817 {
818 SegmentCache *dt;
819 target_ulong ptr;
820 int type, dpl, selector, cpl, ist;
821 int has_error_code, new_stack;
822 uint32_t e1, e2, e3, ss;
823 target_ulong old_eip, esp, offset;
824
825 has_error_code = 0;
826 if (!is_int && !is_hw) {
827 switch(intno) {
828 case 8:
829 case 10:
830 case 11:
831 case 12:
832 case 13:
833 case 14:
834 case 17:
835 has_error_code = 1;
836 break;
837 }
838 }
839 if (is_int)
840 old_eip = next_eip;
841 else
842 old_eip = env->eip;
843
844 dt = &env->idt;
845 if (intno * 16 + 15 > dt->limit)
846 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
847 ptr = dt->base + intno * 16;
848 e1 = ldl_kernel(ptr);
849 e2 = ldl_kernel(ptr + 4);
850 e3 = ldl_kernel(ptr + 8);
851 /* check gate type */
852 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
853 switch(type) {
854 case 14: /* 386 interrupt gate */
855 case 15: /* 386 trap gate */
856 break;
857 default:
858 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
859 break;
860 }
861 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
862 cpl = env->hflags & HF_CPL_MASK;
863 /* check privledge if software int */
864 if (is_int && dpl < cpl)
865 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
866 /* check valid bit */
867 if (!(e2 & DESC_P_MASK))
868 raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
869 selector = e1 >> 16;
870 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
871 ist = e2 & 7;
872 if ((selector & 0xfffc) == 0)
873 raise_exception_err(EXCP0D_GPF, 0);
874
875 if (load_segment(&e1, &e2, selector) != 0)
876 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
877 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
878 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
879 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
880 if (dpl > cpl)
881 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
882 if (!(e2 & DESC_P_MASK))
883 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
884 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK))
885 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
886 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
887 /* to inner priviledge */
888 if (ist != 0)
889 esp = get_rsp_from_tss(ist + 3);
890 else
891 esp = get_rsp_from_tss(dpl);
892 ss = 0;
893 new_stack = 1;
894 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
895 /* to same priviledge */
896 if (env->eflags & VM_MASK)
897 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
898 new_stack = 0;
899 esp = ESP & ~0xf; /* align stack */
900 dpl = cpl;
901 } else {
902 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
903 new_stack = 0; /* avoid warning */
904 esp = 0; /* avoid warning */
905 }
906
907 PUSHQ(esp, env->segs[R_SS].selector);
908 PUSHQ(esp, ESP);
909 PUSHQ(esp, compute_eflags());
910 PUSHQ(esp, env->segs[R_CS].selector);
911 PUSHQ(esp, old_eip);
912 if (has_error_code) {
913 PUSHQ(esp, error_code);
914 }
915
916 if (new_stack) {
917 ss = 0 | dpl;
918 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
919 }
920 ESP = esp;
921
922 selector = (selector & ~3) | dpl;
923 cpu_x86_load_seg_cache(env, R_CS, selector,
924 get_seg_base(e1, e2),
925 get_seg_limit(e1, e2),
926 e2);
927 cpu_x86_set_cpl(env, dpl);
928 env->eip = offset;
929
930 /* interrupt gate clear IF mask */
931 if ((type & 1) == 0) {
932 env->eflags &= ~IF_MASK;
933 }
934 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
935 }
936
937 void helper_syscall(int next_eip_addend)
938 {
939 int selector;
940
941 if (!(env->efer & MSR_EFER_SCE)) {
942 raise_exception_err(EXCP06_ILLOP, 0);
943 }
944 selector = (env->star >> 32) & 0xffff;
945 if (env->hflags & HF_LMA_MASK) {
946 ECX = env->eip + next_eip_addend;
947 env->regs[11] = compute_eflags();
948
949 cpu_x86_set_cpl(env, 0);
950 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
951 0, 0xffffffff,
952 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
953 DESC_S_MASK |
954 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
955 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
956 0, 0xffffffff,
957 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
958 DESC_S_MASK |
959 DESC_W_MASK | DESC_A_MASK);
960 env->eflags &= ~env->fmask;
961 if (env->hflags & HF_CS64_MASK)
962 env->eip = env->lstar;
963 else
964 env->eip = env->cstar;
965 } else {
966 ECX = (uint32_t)(env->eip + next_eip_addend);
967
968 cpu_x86_set_cpl(env, 0);
969 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
970 0, 0xffffffff,
971 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
972 DESC_S_MASK |
973 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
974 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
975 0, 0xffffffff,
976 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
977 DESC_S_MASK |
978 DESC_W_MASK | DESC_A_MASK);
979 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
980 env->eip = (uint32_t)env->star;
981 }
982 }
983
984 void helper_sysret(int dflag)
985 {
986 int cpl, selector;
987
988 cpl = env->hflags & HF_CPL_MASK;
989 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
990 raise_exception_err(EXCP0D_GPF, 0);
991 }
992 selector = (env->star >> 48) & 0xffff;
993 if (env->hflags & HF_LMA_MASK) {
994 if (dflag == 2) {
995 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
996 0, 0xffffffff,
997 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
998 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
999 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1000 DESC_L_MASK);
1001 env->eip = ECX;
1002 } else {
1003 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1004 0, 0xffffffff,
1005 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1006 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1007 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1008 env->eip = (uint32_t)ECX;
1009 }
1010 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1011 0, 0xffffffff,
1012 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1013 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1014 DESC_W_MASK | DESC_A_MASK);
1015 load_eflags((uint32_t)(env->regs[11]), 0xffffffff);
1016 cpu_x86_set_cpl(env, 3);
1017 } else {
1018 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1019 0, 0xffffffff,
1020 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1021 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1022 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1023 env->eip = (uint32_t)ECX;
1024 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1025 0, 0xffffffff,
1026 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1027 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1028 DESC_W_MASK | DESC_A_MASK);
1029 env->eflags |= IF_MASK;
1030 cpu_x86_set_cpl(env, 3);
1031 }
1032 }
1033 #endif
1034
1035 /* real mode interrupt */
1036 static void do_interrupt_real(int intno, int is_int, int error_code,
1037 unsigned int next_eip)
1038 {
1039 SegmentCache *dt;
1040 target_ulong ptr, ssp;
1041 int selector;
1042 uint32_t offset, esp;
1043 uint32_t old_cs, old_eip;
1044
1045 /* real mode (simpler !) */
1046 dt = &env->idt;
1047 if (intno * 4 + 3 > dt->limit)
1048 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1049 ptr = dt->base + intno * 4;
1050 offset = lduw_kernel(ptr);
1051 selector = lduw_kernel(ptr + 2);
1052 esp = ESP;
1053 ssp = env->segs[R_SS].base;
1054 if (is_int)
1055 old_eip = next_eip;
1056 else
1057 old_eip = env->eip;
1058 old_cs = env->segs[R_CS].selector;
1059 /* XXX: use SS segment size ? */
1060 PUSHW(ssp, esp, 0xffff, compute_eflags());
1061 PUSHW(ssp, esp, 0xffff, old_cs);
1062 PUSHW(ssp, esp, 0xffff, old_eip);
1063
1064 /* update processor state */
1065 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1066 env->eip = offset;
1067 env->segs[R_CS].selector = selector;
1068 env->segs[R_CS].base = (selector << 4);
1069 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1070 }
1071
1072 /* fake user mode interrupt */
1073 void do_interrupt_user(int intno, int is_int, int error_code,
1074 target_ulong next_eip)
1075 {
1076 SegmentCache *dt;
1077 target_ulong ptr;
1078 int dpl, cpl;
1079 uint32_t e2;
1080
1081 dt = &env->idt;
1082 ptr = dt->base + (intno * 8);
1083 e2 = ldl_kernel(ptr + 4);
1084
1085 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1086 cpl = env->hflags & HF_CPL_MASK;
1087 /* check privledge if software int */
1088 if (is_int && dpl < cpl)
1089 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1090
1091 /* Since we emulate only user space, we cannot do more than
1092 exiting the emulation with the suitable exception and error
1093 code */
1094 if (is_int)
1095 EIP = next_eip;
1096 }
1097
1098 /*
1099 * Begin execution of an interruption. is_int is TRUE if coming from
1100 * the int instruction. next_eip is the EIP value AFTER the interrupt
1101 * instruction. It is only relevant if is_int is TRUE.
1102 */
1103 void do_interrupt(int intno, int is_int, int error_code,
1104 target_ulong next_eip, int is_hw)
1105 {
1106 #ifdef DEBUG_PCALL
1107 if (loglevel & (CPU_LOG_PCALL | CPU_LOG_INT)) {
1108 if ((env->cr[0] & CR0_PE_MASK)) {
1109 static int count;
1110 fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1111 count, intno, error_code, is_int,
1112 env->hflags & HF_CPL_MASK,
1113 env->segs[R_CS].selector, EIP,
1114 (int)env->segs[R_CS].base + EIP,
1115 env->segs[R_SS].selector, ESP);
1116 if (intno == 0x0e) {
1117 fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1118 } else {
1119 fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1120 }
1121 fprintf(logfile, "\n");
1122 #if 0
1123 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1124 {
1125 int i;
1126 uint8_t *ptr;
1127 fprintf(logfile, " code=");
1128 ptr = env->segs[R_CS].base + env->eip;
1129 for(i = 0; i < 16; i++) {
1130 fprintf(logfile, " %02x", ldub(ptr + i));
1131 }
1132 fprintf(logfile, "\n");
1133 }
1134 #endif
1135 count++;
1136 }
1137 }
1138 #endif
1139 if (env->cr[0] & CR0_PE_MASK) {
1140 #if TARGET_X86_64
1141 if (env->hflags & HF_LMA_MASK) {
1142 do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1143 } else
1144 #endif
1145 {
1146 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1147 }
1148 } else {
1149 do_interrupt_real(intno, is_int, error_code, next_eip);
1150 }
1151 }
1152
1153 /*
1154 * Signal an interruption. It is executed in the main CPU loop.
1155 * is_int is TRUE if coming from the int instruction. next_eip is the
1156 * EIP value AFTER the interrupt instruction. It is only relevant if
1157 * is_int is TRUE.
1158 */
1159 void raise_interrupt(int intno, int is_int, int error_code,
1160 int next_eip_addend)
1161 {
1162 env->exception_index = intno;
1163 env->error_code = error_code;
1164 env->exception_is_int = is_int;
1165 env->exception_next_eip = env->eip + next_eip_addend;
1166 cpu_loop_exit();
1167 }
1168
1169 /* same as raise_exception_err, but do not restore global registers */
1170 static void raise_exception_err_norestore(int exception_index, int error_code)
1171 {
1172 env->exception_index = exception_index;
1173 env->error_code = error_code;
1174 env->exception_is_int = 0;
1175 env->exception_next_eip = 0;
1176 longjmp(env->jmp_env, 1);
1177 }
1178
1179 /* shortcuts to generate exceptions */
1180
1181 void (raise_exception_err)(int exception_index, int error_code)
1182 {
1183 raise_interrupt(exception_index, 0, error_code, 0);
1184 }
1185
1186 void raise_exception(int exception_index)
1187 {
1188 raise_interrupt(exception_index, 0, 0, 0);
1189 }
1190
1191 #ifdef BUGGY_GCC_DIV64
1192 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1193 call it from another function */
1194 uint32_t div32(uint32_t *q_ptr, uint64_t num, uint32_t den)
1195 {
1196 *q_ptr = num / den;
1197 return num % den;
1198 }
1199
1200 int32_t idiv32(int32_t *q_ptr, int64_t num, int32_t den)
1201 {
1202 *q_ptr = num / den;
1203 return num % den;
1204 }
1205 #endif
1206
1207 void helper_divl_EAX_T0(void)
1208 {
1209 unsigned int den, q, r;
1210 uint64_t num;
1211
1212 num = EAX | ((uint64_t)EDX << 32);
1213 den = T0;
1214 if (den == 0) {
1215 raise_exception(EXCP00_DIVZ);
1216 }
1217 #ifdef BUGGY_GCC_DIV64
1218 r = div32(&q, num, den);
1219 #else
1220 q = (num / den);
1221 r = (num % den);
1222 #endif
1223 EAX = (uint32_t)q;
1224 EDX = (uint32_t)r;
1225 }
1226
1227 void helper_idivl_EAX_T0(void)
1228 {
1229 int den, q, r;
1230 int64_t num;
1231
1232 num = EAX | ((uint64_t)EDX << 32);
1233 den = T0;
1234 if (den == 0) {
1235 raise_exception(EXCP00_DIVZ);
1236 }
1237 #ifdef BUGGY_GCC_DIV64
1238 r = idiv32(&q, num, den);
1239 #else
1240 q = (num / den);
1241 r = (num % den);
1242 #endif
1243 EAX = (uint32_t)q;
1244 EDX = (uint32_t)r;
1245 }
1246
1247 void helper_cmpxchg8b(void)
1248 {
1249 uint64_t d;
1250 int eflags;
1251
1252 eflags = cc_table[CC_OP].compute_all();
1253 d = ldq(A0);
1254 if (d == (((uint64_t)EDX << 32) | EAX)) {
1255 stq(A0, ((uint64_t)ECX << 32) | EBX);
1256 eflags |= CC_Z;
1257 } else {
1258 EDX = d >> 32;
1259 EAX = d;
1260 eflags &= ~CC_Z;
1261 }
1262 CC_SRC = eflags;
1263 }
1264
1265 void helper_cpuid(void)
1266 {
1267 switch((uint32_t)EAX) {
1268 case 0:
1269 EAX = 2; /* max EAX index supported */
1270 EBX = env->cpuid_vendor1;
1271 EDX = env->cpuid_vendor2;
1272 ECX = env->cpuid_vendor3;
1273 break;
1274 case 1:
1275 EAX = env->cpuid_version;
1276 EBX = 0;
1277 ECX = 0;
1278 EDX = env->cpuid_features;
1279 break;
1280 default:
1281 /* cache info: needed for Pentium Pro compatibility */
1282 EAX = 0x410601;
1283 EBX = 0;
1284 ECX = 0;
1285 EDX = 0;
1286 break;
1287 #ifdef TARGET_X86_64
1288 case 0x80000000:
1289 EAX = 0x80000008;
1290 EBX = env->cpuid_vendor1;
1291 EDX = env->cpuid_vendor2;
1292 ECX = env->cpuid_vendor3;
1293 break;
1294 case 0x80000001:
1295 EAX = env->cpuid_features;
1296 EBX = 0;
1297 ECX = 0;
1298 /* long mode + syscall/sysret features */
1299 EDX = (env->cpuid_features & 0x0183F3FF) | (1 << 29) | (1 << 11);
1300 break;
1301 case 0x80000008:
1302 /* virtual & phys address size in low 2 bytes. */
1303 EAX = 0x00003028;
1304 EBX = 0;
1305 ECX = 0;
1306 EDX = 0;
1307 break;
1308 #endif
1309 }
1310 }
1311
1312 void helper_enter_level(int level, int data32)
1313 {
1314 target_ulong ssp;
1315 uint32_t esp_mask, esp, ebp;
1316
1317 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1318 ssp = env->segs[R_SS].base;
1319 ebp = EBP;
1320 esp = ESP;
1321 if (data32) {
1322 /* 32 bit */
1323 esp -= 4;
1324 while (--level) {
1325 esp -= 4;
1326 ebp -= 4;
1327 stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1328 }
1329 esp -= 4;
1330 stl(ssp + (esp & esp_mask), T1);
1331 } else {
1332 /* 16 bit */
1333 esp -= 2;
1334 while (--level) {
1335 esp -= 2;
1336 ebp -= 2;
1337 stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1338 }
1339 esp -= 2;
1340 stw(ssp + (esp & esp_mask), T1);
1341 }
1342 }
1343
1344 void helper_lldt_T0(void)
1345 {
1346 int selector;
1347 SegmentCache *dt;
1348 uint32_t e1, e2;
1349 int index, entry_limit;
1350 target_ulong ptr;
1351
1352 selector = T0 & 0xffff;
1353 if ((selector & 0xfffc) == 0) {
1354 /* XXX: NULL selector case: invalid LDT */
1355 env->ldt.base = 0;
1356 env->ldt.limit = 0;
1357 } else {
1358 if (selector & 0x4)
1359 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1360 dt = &env->gdt;
1361 index = selector & ~7;
1362 #ifdef TARGET_X86_64
1363 if (env->hflags & HF_LMA_MASK)
1364 entry_limit = 15;
1365 else
1366 #endif
1367 entry_limit = 7;
1368 if ((index + entry_limit) > dt->limit)
1369 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1370 ptr = dt->base + index;
1371 e1 = ldl_kernel(ptr);
1372 e2 = ldl_kernel(ptr + 4);
1373 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1374 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1375 if (!(e2 & DESC_P_MASK))
1376 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1377 #ifdef TARGET_X86_64
1378 if (env->hflags & HF_LMA_MASK) {
1379 uint32_t e3;
1380 e3 = ldl_kernel(ptr + 8);
1381 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1382 env->ldt.base |= (target_ulong)e3 << 32;
1383 } else
1384 #endif
1385 {
1386 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1387 }
1388 }
1389 env->ldt.selector = selector;
1390 }
1391
1392 void helper_ltr_T0(void)
1393 {
1394 int selector;
1395 SegmentCache *dt;
1396 uint32_t e1, e2;
1397 int index, type, entry_limit;
1398 target_ulong ptr;
1399
1400 selector = T0 & 0xffff;
1401 if ((selector & 0xfffc) == 0) {
1402 /* NULL selector case: invalid TR */
1403 env->tr.base = 0;
1404 env->tr.limit = 0;
1405 env->tr.flags = 0;
1406 } else {
1407 if (selector & 0x4)
1408 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1409 dt = &env->gdt;
1410 index = selector & ~7;
1411 #ifdef TARGET_X86_64
1412 if (env->hflags & HF_LMA_MASK)
1413 entry_limit = 15;
1414 else
1415 #endif
1416 entry_limit = 7;
1417 if ((index + entry_limit) > dt->limit)
1418 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1419 ptr = dt->base + index;
1420 e1 = ldl_kernel(ptr);
1421 e2 = ldl_kernel(ptr + 4);
1422 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1423 if ((e2 & DESC_S_MASK) ||
1424 (type != 1 && type != 9))
1425 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1426 if (!(e2 & DESC_P_MASK))
1427 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1428 #ifdef TARGET_X86_64
1429 if (env->hflags & HF_LMA_MASK) {
1430 uint32_t e3;
1431 e3 = ldl_kernel(ptr + 8);
1432 load_seg_cache_raw_dt(&env->tr, e1, e2);
1433 env->tr.base |= (target_ulong)e3 << 32;
1434 } else
1435 #endif
1436 {
1437 load_seg_cache_raw_dt(&env->tr, e1, e2);
1438 }
1439 e2 |= DESC_TSS_BUSY_MASK;
1440 stl_kernel(ptr + 4, e2);
1441 }
1442 env->tr.selector = selector;
1443 }
1444
1445 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1446 void load_seg(int seg_reg, int selector)
1447 {
1448 uint32_t e1, e2;
1449 int cpl, dpl, rpl;
1450 SegmentCache *dt;
1451 int index;
1452 target_ulong ptr;
1453
1454 selector &= 0xffff;
1455 if ((selector & 0xfffc) == 0) {
1456 /* null selector case */
1457 if (seg_reg == R_SS
1458 #ifdef TARGET_X86_64
1459 && !(env->hflags & HF_CS64_MASK)
1460 #endif
1461 )
1462 raise_exception_err(EXCP0D_GPF, 0);
1463 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1464 } else {
1465
1466 if (selector & 0x4)
1467 dt = &env->ldt;
1468 else
1469 dt = &env->gdt;
1470 index = selector & ~7;
1471 if ((index + 7) > dt->limit)
1472 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1473 ptr = dt->base + index;
1474 e1 = ldl_kernel(ptr);
1475 e2 = ldl_kernel(ptr + 4);
1476
1477 if (!(e2 & DESC_S_MASK))
1478 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1479 rpl = selector & 3;
1480 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1481 cpl = env->hflags & HF_CPL_MASK;
1482 if (seg_reg == R_SS) {
1483 /* must be writable segment */
1484 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
1485 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1486 if (rpl != cpl || dpl != cpl)
1487 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1488 } else {
1489 /* must be readable segment */
1490 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
1491 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1492
1493 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1494 /* if not conforming code, test rights */
1495 if (dpl < cpl || dpl < rpl)
1496 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1497 }
1498 }
1499
1500 if (!(e2 & DESC_P_MASK)) {
1501 if (seg_reg == R_SS)
1502 raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
1503 else
1504 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1505 }
1506
1507 /* set the access bit if not already set */
1508 if (!(e2 & DESC_A_MASK)) {
1509 e2 |= DESC_A_MASK;
1510 stl_kernel(ptr + 4, e2);
1511 }
1512
1513 cpu_x86_load_seg_cache(env, seg_reg, selector,
1514 get_seg_base(e1, e2),
1515 get_seg_limit(e1, e2),
1516 e2);
1517 #if 0
1518 fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1519 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1520 #endif
1521 }
1522 }
1523
1524 /* protected mode jump */
1525 void helper_ljmp_protected_T0_T1(int next_eip)
1526 {
1527 int new_cs, gate_cs, type;
1528 uint32_t e1, e2, cpl, dpl, rpl, limit;
1529 target_ulong new_eip;
1530
1531 new_cs = T0;
1532 new_eip = T1;
1533 if ((new_cs & 0xfffc) == 0)
1534 raise_exception_err(EXCP0D_GPF, 0);
1535 if (load_segment(&e1, &e2, new_cs) != 0)
1536 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1537 cpl = env->hflags & HF_CPL_MASK;
1538 if (e2 & DESC_S_MASK) {
1539 if (!(e2 & DESC_CS_MASK))
1540 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1541 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1542 if (e2 & DESC_C_MASK) {
1543 /* conforming code segment */
1544 if (dpl > cpl)
1545 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1546 } else {
1547 /* non conforming code segment */
1548 rpl = new_cs & 3;
1549 if (rpl > cpl)
1550 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1551 if (dpl != cpl)
1552 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1553 }
1554 if (!(e2 & DESC_P_MASK))
1555 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1556 limit = get_seg_limit(e1, e2);
1557 if (new_eip > limit &&
1558 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
1559 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1560 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1561 get_seg_base(e1, e2), limit, e2);
1562 EIP = new_eip;
1563 } else {
1564 /* jump to call or task gate */
1565 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1566 rpl = new_cs & 3;
1567 cpl = env->hflags & HF_CPL_MASK;
1568 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1569 switch(type) {
1570 case 1: /* 286 TSS */
1571 case 9: /* 386 TSS */
1572 case 5: /* task gate */
1573 if (dpl < cpl || dpl < rpl)
1574 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1575 switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1576 break;
1577 case 4: /* 286 call gate */
1578 case 12: /* 386 call gate */
1579 if ((dpl < cpl) || (dpl < rpl))
1580 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1581 if (!(e2 & DESC_P_MASK))
1582 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1583 gate_cs = e1 >> 16;
1584 new_eip = (e1 & 0xffff);
1585 if (type == 12)
1586 new_eip |= (e2 & 0xffff0000);
1587 if (load_segment(&e1, &e2, gate_cs) != 0)
1588 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1589 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1590 /* must be code segment */
1591 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1592 (DESC_S_MASK | DESC_CS_MASK)))
1593 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1594 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1595 (!(e2 & DESC_C_MASK) && (dpl != cpl)))
1596 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1597 if (!(e2 & DESC_P_MASK))
1598 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
1599 limit = get_seg_limit(e1, e2);
1600 if (new_eip > limit)
1601 raise_exception_err(EXCP0D_GPF, 0);
1602 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1603 get_seg_base(e1, e2), limit, e2);
1604 EIP = new_eip;
1605 break;
1606 default:
1607 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1608 break;
1609 }
1610 }
1611 }
1612
1613 /* real mode call */
1614 void helper_lcall_real_T0_T1(int shift, int next_eip)
1615 {
1616 int new_cs, new_eip;
1617 uint32_t esp, esp_mask;
1618 target_ulong ssp;
1619
1620 new_cs = T0;
1621 new_eip = T1;
1622 esp = ESP;
1623 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1624 ssp = env->segs[R_SS].base;
1625 if (shift) {
1626 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1627 PUSHL(ssp, esp, esp_mask, next_eip);
1628 } else {
1629 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1630 PUSHW(ssp, esp, esp_mask, next_eip);
1631 }
1632
1633 ESP = (ESP & ~esp_mask) | (esp & esp_mask);
1634 env->eip = new_eip;
1635 env->segs[R_CS].selector = new_cs;
1636 env->segs[R_CS].base = (new_cs << 4);
1637 }
1638
1639 /* protected mode call */
1640 void helper_lcall_protected_T0_T1(int shift, int next_eip)
1641 {
1642 int new_cs, new_eip, new_stack, i;
1643 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1644 uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
1645 uint32_t val, limit, old_sp_mask;
1646 target_ulong ssp, old_ssp;
1647
1648 new_cs = T0;
1649 new_eip = T1;
1650 #ifdef DEBUG_PCALL
1651 if (loglevel & CPU_LOG_PCALL) {
1652 fprintf(logfile, "lcall %04x:%08x s=%d\n",
1653 new_cs, new_eip, shift);
1654 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1655 }
1656 #endif
1657 if ((new_cs & 0xfffc) == 0)
1658 raise_exception_err(EXCP0D_GPF, 0);
1659 if (load_segment(&e1, &e2, new_cs) != 0)
1660 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1661 cpl = env->hflags & HF_CPL_MASK;
1662 #ifdef DEBUG_PCALL
1663 if (loglevel & CPU_LOG_PCALL) {
1664 fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
1665 }
1666 #endif
1667 if (e2 & DESC_S_MASK) {
1668 if (!(e2 & DESC_CS_MASK))
1669 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1670 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1671 if (e2 & DESC_C_MASK) {
1672 /* conforming code segment */
1673 if (dpl > cpl)
1674 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1675 } else {
1676 /* non conforming code segment */
1677 rpl = new_cs & 3;
1678 if (rpl > cpl)
1679 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1680 if (dpl != cpl)
1681 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1682 }
1683 if (!(e2 & DESC_P_MASK))
1684 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1685
1686 sp = ESP;
1687 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1688 ssp = env->segs[R_SS].base;
1689 if (shift) {
1690 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1691 PUSHL(ssp, sp, sp_mask, next_eip);
1692 } else {
1693 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1694 PUSHW(ssp, sp, sp_mask, next_eip);
1695 }
1696
1697 limit = get_seg_limit(e1, e2);
1698 if (new_eip > limit)
1699 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1700 /* from this point, not restartable */
1701 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1702 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1703 get_seg_base(e1, e2), limit, e2);
1704 EIP = new_eip;
1705 } else {
1706 /* check gate type */
1707 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1708 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1709 rpl = new_cs & 3;
1710 switch(type) {
1711 case 1: /* available 286 TSS */
1712 case 9: /* available 386 TSS */
1713 case 5: /* task gate */
1714 if (dpl < cpl || dpl < rpl)
1715 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1716 switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1717 return;
1718 case 4: /* 286 call gate */
1719 case 12: /* 386 call gate */
1720 break;
1721 default:
1722 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1723 break;
1724 }
1725 shift = type >> 3;
1726
1727 if (dpl < cpl || dpl < rpl)
1728 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1729 /* check valid bit */
1730 if (!(e2 & DESC_P_MASK))
1731 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1732 selector = e1 >> 16;
1733 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1734 param_count = e2 & 0x1f;
1735 if ((selector & 0xfffc) == 0)
1736 raise_exception_err(EXCP0D_GPF, 0);
1737
1738 if (load_segment(&e1, &e2, selector) != 0)
1739 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1740 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
1741 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1742 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1743 if (dpl > cpl)
1744 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1745 if (!(e2 & DESC_P_MASK))
1746 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1747
1748 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1749 /* to inner priviledge */
1750 get_ss_esp_from_tss(&ss, &sp, dpl);
1751 #ifdef DEBUG_PCALL
1752 if (loglevel & CPU_LOG_PCALL)
1753 fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
1754 ss, sp, param_count, ESP);
1755 #endif
1756 if ((ss & 0xfffc) == 0)
1757 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1758 if ((ss & 3) != dpl)
1759 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1760 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
1761 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1762 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1763 if (ss_dpl != dpl)
1764 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1765 if (!(ss_e2 & DESC_S_MASK) ||
1766 (ss_e2 & DESC_CS_MASK) ||
1767 !(ss_e2 & DESC_W_MASK))
1768 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1769 if (!(ss_e2 & DESC_P_MASK))
1770 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
1771
1772 // push_size = ((param_count * 2) + 8) << shift;
1773
1774 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1775 old_ssp = env->segs[R_SS].base;
1776
1777 sp_mask = get_sp_mask(ss_e2);
1778 ssp = get_seg_base(ss_e1, ss_e2);
1779 if (shift) {
1780 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
1781 PUSHL(ssp, sp, sp_mask, ESP);
1782 for(i = param_count - 1; i >= 0; i--) {
1783 val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
1784 PUSHL(ssp, sp, sp_mask, val);
1785 }
1786 } else {
1787 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
1788 PUSHW(ssp, sp, sp_mask, ESP);
1789 for(i = param_count - 1; i >= 0; i--) {
1790 val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
1791 PUSHW(ssp, sp, sp_mask, val);
1792 }
1793 }
1794 new_stack = 1;
1795 } else {
1796 /* to same priviledge */
1797 sp = ESP;
1798 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1799 ssp = env->segs[R_SS].base;
1800 // push_size = (4 << shift);
1801 new_stack = 0;
1802 }
1803
1804 if (shift) {
1805 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1806 PUSHL(ssp, sp, sp_mask, next_eip);
1807 } else {
1808 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1809 PUSHW(ssp, sp, sp_mask, next_eip);
1810 }
1811
1812 /* from this point, not restartable */
1813
1814 if (new_stack) {
1815 ss = (ss & ~3) | dpl;
1816 cpu_x86_load_seg_cache(env, R_SS, ss,
1817 ssp,
1818 get_seg_limit(ss_e1, ss_e2),
1819 ss_e2);
1820 }
1821
1822 selector = (selector & ~3) | dpl;
1823 cpu_x86_load_seg_cache(env, R_CS, selector,
1824 get_seg_base(e1, e2),
1825 get_seg_limit(e1, e2),
1826 e2);
1827 cpu_x86_set_cpl(env, dpl);
1828 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1829 EIP = offset;
1830 }
1831 }
1832
1833 /* real and vm86 mode iret */
1834 void helper_iret_real(int shift)
1835 {
1836 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1837 target_ulong ssp;
1838 int eflags_mask;
1839
1840 sp_mask = 0xffff; /* XXXX: use SS segment size ? */
1841 sp = ESP;
1842 ssp = env->segs[R_SS].base;
1843 if (shift == 1) {
1844 /* 32 bits */
1845 POPL(ssp, sp, sp_mask, new_eip);
1846 POPL(ssp, sp, sp_mask, new_cs);
1847 new_cs &= 0xffff;
1848 POPL(ssp, sp, sp_mask, new_eflags);
1849 } else {
1850 /* 16 bits */
1851 POPW(ssp, sp, sp_mask, new_eip);
1852 POPW(ssp, sp, sp_mask, new_cs);
1853 POPW(ssp, sp, sp_mask, new_eflags);
1854 }
1855 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1856 load_seg_vm(R_CS, new_cs);
1857 env->eip = new_eip;
1858 if (env->eflags & VM_MASK)
1859 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | NT_MASK;
1860 else
1861 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | RF_MASK | NT_MASK;
1862 if (shift == 0)
1863 eflags_mask &= 0xffff;
1864 load_eflags(new_eflags, eflags_mask);
1865 }
1866
1867 static inline void validate_seg(int seg_reg, int cpl)
1868 {
1869 int dpl;
1870 uint32_t e2;
1871
1872 e2 = env->segs[seg_reg].flags;
1873 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1874 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1875 /* data or non conforming code segment */
1876 if (dpl < cpl) {
1877 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
1878 }
1879 }
1880 }
1881
1882 /* protected mode iret */
1883 static inline void helper_ret_protected(int shift, int is_iret, int addend)
1884 {
1885 uint32_t new_cs, new_eflags, new_ss;
1886 uint32_t new_es, new_ds, new_fs, new_gs;
1887 uint32_t e1, e2, ss_e1, ss_e2;
1888 int cpl, dpl, rpl, eflags_mask, iopl;
1889 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
1890
1891 #ifdef TARGET_X86_64
1892 if (shift == 2)
1893 sp_mask = -1;
1894 else
1895 #endif
1896 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1897 sp = ESP;
1898 ssp = env->segs[R_SS].base;
1899 new_eflags = 0; /* avoid warning */
1900 #ifdef TARGET_X86_64
1901 if (shift == 2) {
1902 POPQ(sp, new_eip);
1903 POPQ(sp, new_cs);
1904 new_cs &= 0xffff;
1905 if (is_iret) {
1906 POPQ(sp, new_eflags);
1907 }
1908 } else
1909 #endif
1910 if (shift == 1) {
1911 /* 32 bits */
1912 POPL(ssp, sp, sp_mask, new_eip);
1913 POPL(ssp, sp, sp_mask, new_cs);
1914 new_cs &= 0xffff;
1915 if (is_iret) {
1916 POPL(ssp, sp, sp_mask, new_eflags);
1917 if (new_eflags & VM_MASK)
1918 goto return_to_vm86;
1919 }
1920 } else {
1921 /* 16 bits */
1922 POPW(ssp, sp, sp_mask, new_eip);
1923 POPW(ssp, sp, sp_mask, new_cs);
1924 if (is_iret)
1925 POPW(ssp, sp, sp_mask, new_eflags);
1926 }
1927 #ifdef DEBUG_PCALL
1928 if (loglevel & CPU_LOG_PCALL) {
1929 fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
1930 new_cs, new_eip, shift, addend);
1931 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1932 }
1933 #endif
1934 if ((new_cs & 0xfffc) == 0)
1935 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1936 if (load_segment(&e1, &e2, new_cs) != 0)
1937 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1938 if (!(e2 & DESC_S_MASK) ||
1939 !(e2 & DESC_CS_MASK))
1940 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1941 cpl = env->hflags & HF_CPL_MASK;
1942 rpl = new_cs & 3;
1943 if (rpl < cpl)
1944 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1945 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1946 if (e2 & DESC_C_MASK) {
1947 if (dpl > rpl)
1948 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1949 } else {
1950 if (dpl != rpl)
1951 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1952 }
1953 if (!(e2 & DESC_P_MASK))
1954 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1955
1956 sp += addend;
1957 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
1958 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
1959 /* return to same priledge level */
1960 cpu_x86_load_seg_cache(env, R_CS, new_cs,
1961 get_seg_base(e1, e2),
1962 get_seg_limit(e1, e2),
1963 e2);
1964 } else {
1965 /* return to different priviledge level */
1966 #ifdef TARGET_X86_64
1967 if (shift == 2) {
1968 POPQ(sp, new_esp);
1969 POPQ(sp, new_ss);
1970 new_ss &= 0xffff;
1971 } else
1972 #endif
1973 if (shift == 1) {
1974 /* 32 bits */
1975 POPL(ssp, sp, sp_mask, new_esp);
1976 POPL(ssp, sp, sp_mask, new_ss);
1977 new_ss &= 0xffff;
1978 } else {
1979 /* 16 bits */
1980 POPW(ssp, sp, sp_mask, new_esp);
1981 POPW(ssp, sp, sp_mask, new_ss);
1982 }
1983 #ifdef DEBUG_PCALL
1984 if (loglevel & CPU_LOG_PCALL) {
1985 fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
1986 new_ss, new_esp);
1987 }
1988 #endif
1989 if ((env->hflags & HF_LMA_MASK) && (new_ss & 0xfffc) == 0) {
1990 /* NULL ss is allowed in long mode */
1991 cpu_x86_load_seg_cache(env, R_SS, new_ss,
1992 0, 0xffffffff,
1993 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1994 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
1995 DESC_W_MASK | DESC_A_MASK);
1996 } else {
1997 if ((new_ss & 3) != rpl)
1998 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
1999 if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2000 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2001 if (!(ss_e2 & DESC_S_MASK) ||
2002 (ss_e2 & DESC_CS_MASK) ||
2003 !(ss_e2 & DESC_W_MASK))
2004 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2005 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2006 if (dpl != rpl)
2007 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2008 if (!(ss_e2 & DESC_P_MASK))
2009 raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2010 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2011 get_seg_base(ss_e1, ss_e2),
2012 get_seg_limit(ss_e1, ss_e2),
2013 ss_e2);
2014 }
2015
2016 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2017 get_seg_base(e1, e2),
2018 get_seg_limit(e1, e2),
2019 e2);
2020 cpu_x86_set_cpl(env, rpl);
2021 sp = new_esp;
2022 #ifdef TARGET_X86_64
2023 if (shift == 2)
2024 sp_mask = -1;
2025 else
2026 #endif
2027 sp_mask = get_sp_mask(ss_e2);
2028
2029 /* validate data segments */
2030 validate_seg(R_ES, cpl);
2031 validate_seg(R_DS, cpl);
2032 validate_seg(R_FS, cpl);
2033 validate_seg(R_GS, cpl);
2034
2035 sp += addend;
2036 }
2037 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2038 env->eip = new_eip;
2039 if (is_iret) {
2040 /* NOTE: 'cpl' is the _old_ CPL */
2041 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2042 if (cpl == 0)
2043 eflags_mask |= IOPL_MASK;
2044 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2045 if (cpl <= iopl)
2046 eflags_mask |= IF_MASK;
2047 if (shift == 0)
2048 eflags_mask &= 0xffff;
2049 load_eflags(new_eflags, eflags_mask);
2050 }
2051 return;
2052
2053 return_to_vm86:
2054 POPL(ssp, sp, sp_mask, new_esp);
2055 POPL(ssp, sp, sp_mask, new_ss);
2056 POPL(ssp, sp, sp_mask, new_es);
2057 POPL(ssp, sp, sp_mask, new_ds);
2058 POPL(ssp, sp, sp_mask, new_fs);
2059 POPL(ssp, sp, sp_mask, new_gs);
2060
2061 /* modify processor state */
2062 load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK |
2063 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK);
2064 load_seg_vm(R_CS, new_cs & 0xffff);
2065 cpu_x86_set_cpl(env, 3);
2066 load_seg_vm(R_SS, new_ss & 0xffff);
2067 load_seg_vm(R_ES, new_es & 0xffff);
2068 load_seg_vm(R_DS, new_ds & 0xffff);
2069 load_seg_vm(R_FS, new_fs & 0xffff);
2070 load_seg_vm(R_GS, new_gs & 0xffff);
2071
2072 env->eip = new_eip & 0xffff;
2073 ESP = new_esp;
2074 }
2075
2076 void helper_iret_protected(int shift, int next_eip)
2077 {
2078 int tss_selector, type;
2079 uint32_t e1, e2;
2080
2081 /* specific case for TSS */
2082 if (env->eflags & NT_MASK) {
2083 #ifdef TARGET_X86_64
2084 if (env->hflags & HF_LMA_MASK)
2085 raise_exception_err(EXCP0D_GPF, 0);
2086 #endif
2087 tss_selector = lduw_kernel(env->tr.base + 0);
2088 if (tss_selector & 4)
2089 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2090 if (load_segment(&e1, &e2, tss_selector) != 0)
2091 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2092 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2093 /* NOTE: we check both segment and busy TSS */
2094 if (type != 3)
2095 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2096 switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2097 } else {
2098 helper_ret_protected(shift, 1, 0);
2099 }
2100 }
2101
2102 void helper_lret_protected(int shift, int addend)
2103 {
2104 helper_ret_protected(shift, 0, addend);
2105 }
2106
2107 void helper_sysenter(void)
2108 {
2109 if (env->sysenter_cs == 0) {
2110 raise_exception_err(EXCP0D_GPF, 0);
2111 }
2112 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2113 cpu_x86_set_cpl(env, 0);
2114 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2115 0, 0xffffffff,
2116 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2117 DESC_S_MASK |
2118 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2119 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2120 0, 0xffffffff,
2121 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2122 DESC_S_MASK |
2123 DESC_W_MASK | DESC_A_MASK);
2124 ESP = env->sysenter_esp;
2125 EIP = env->sysenter_eip;
2126 }
2127
2128 void helper_sysexit(void)
2129 {
2130 int cpl;
2131
2132 cpl = env->hflags & HF_CPL_MASK;
2133 if (env->sysenter_cs == 0 || cpl != 0) {
2134 raise_exception_err(EXCP0D_GPF, 0);
2135 }
2136 cpu_x86_set_cpl(env, 3);
2137 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
2138 0, 0xffffffff,
2139 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2140 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2141 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2142 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3,
2143 0, 0xffffffff,
2144 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2145 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2146 DESC_W_MASK | DESC_A_MASK);
2147 ESP = ECX;
2148 EIP = EDX;
2149 }
2150
2151 void helper_movl_crN_T0(int reg)
2152 {
2153 #if !defined(CONFIG_USER_ONLY)
2154 switch(reg) {
2155 case 0:
2156 cpu_x86_update_cr0(env, T0);
2157 break;
2158 case 3:
2159 cpu_x86_update_cr3(env, T0);
2160 break;
2161 case 4:
2162 cpu_x86_update_cr4(env, T0);
2163 break;
2164 case 8:
2165 cpu_set_apic_tpr(env, T0);
2166 break;
2167 default:
2168 env->cr[reg] = T0;
2169 break;
2170 }
2171 #endif
2172 }
2173
2174 /* XXX: do more */
2175 void helper_movl_drN_T0(int reg)
2176 {
2177 env->dr[reg] = T0;
2178 }
2179
2180 void helper_invlpg(unsigned int addr)
2181 {
2182 cpu_x86_flush_tlb(env, addr);
2183 }
2184
2185 void helper_rdtsc(void)
2186 {
2187 uint64_t val;
2188
2189 val = cpu_get_tsc(env);
2190 EAX = (uint32_t)(val);
2191 EDX = (uint32_t)(val >> 32);
2192 }
2193
2194 #if defined(CONFIG_USER_ONLY)
2195 void helper_wrmsr(void)
2196 {
2197 }
2198
2199 void helper_rdmsr(void)
2200 {
2201 }
2202 #else
2203 void helper_wrmsr(void)
2204 {
2205 uint64_t val;
2206
2207 val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2208
2209 switch((uint32_t)ECX) {
2210 case MSR_IA32_SYSENTER_CS:
2211 env->sysenter_cs = val & 0xffff;
2212 break;
2213 case MSR_IA32_SYSENTER_ESP:
2214 env->sysenter_esp = val;
2215 break;
2216 case MSR_IA32_SYSENTER_EIP:
2217 env->sysenter_eip = val;
2218 break;
2219 case MSR_IA32_APICBASE:
2220 cpu_set_apic_base(env, val);
2221 break;
2222 #ifdef TARGET_X86_64
2223 case MSR_EFER:
2224 #define MSR_EFER_UPDATE_MASK (MSR_EFER_SCE | MSR_EFER_LME | \
2225 MSR_EFER_NXE | MSR_EFER_FFXSR)
2226 env->efer = (env->efer & ~MSR_EFER_UPDATE_MASK) |
2227 (val & MSR_EFER_UPDATE_MASK);
2228 break;
2229 case MSR_STAR:
2230 env->star = val;
2231 break;
2232 case MSR_LSTAR:
2233 env->lstar = val;
2234 break;
2235 case MSR_CSTAR:
2236 env->cstar = val;
2237 break;
2238 case MSR_FMASK:
2239 env->fmask = val;
2240 break;
2241 case MSR_FSBASE:
2242 env->segs[R_FS].base = val;
2243 break;
2244 case MSR_GSBASE:
2245 env->segs[R_GS].base = val;
2246 break;
2247 case MSR_KERNELGSBASE:
2248 env->kernelgsbase = val;
2249 break;
2250 #endif
2251 default:
2252 /* XXX: exception ? */
2253 break;
2254 }
2255 }
2256
2257 void helper_rdmsr(void)
2258 {
2259 uint64_t val;
2260 switch((uint32_t)ECX) {
2261 case MSR_IA32_SYSENTER_CS:
2262 val = env->sysenter_cs;
2263 break;
2264 case MSR_IA32_SYSENTER_ESP:
2265 val = env->sysenter_esp;
2266 break;
2267 case MSR_IA32_SYSENTER_EIP:
2268 val = env->sysenter_eip;
2269 break;
2270 case MSR_IA32_APICBASE:
2271 val = cpu_get_apic_base(env);
2272 break;
2273 #ifdef TARGET_X86_64
2274 case MSR_EFER:
2275 val = env->efer;
2276 break;
2277 case MSR_STAR:
2278 val = env->star;
2279 break;
2280 case MSR_LSTAR:
2281 val = env->lstar;
2282 break;
2283 case MSR_CSTAR:
2284 val = env->cstar;
2285 break;
2286 case MSR_FMASK:
2287 val = env->fmask;
2288 break;
2289 case MSR_FSBASE:
2290 val = env->segs[R_FS].base;
2291 break;
2292 case MSR_GSBASE:
2293 val = env->segs[R_GS].base;
2294 break;
2295 case MSR_KERNELGSBASE:
2296 val = env->kernelgsbase;
2297 break;
2298 #endif
2299 default:
2300 /* XXX: exception ? */
2301 val = 0;
2302 break;
2303 }
2304 EAX = (uint32_t)(val);
2305 EDX = (uint32_t)(val >> 32);
2306 }
2307 #endif
2308
2309 void helper_lsl(void)
2310 {
2311 unsigned int selector, limit;
2312 uint32_t e1, e2;
2313 int rpl, dpl, cpl, type;
2314
2315 CC_SRC = cc_table[CC_OP].compute_all() & ~CC_Z;
2316 selector = T0 & 0xffff;
2317 if (load_segment(&e1, &e2, selector) != 0)
2318 return;
2319 rpl = selector & 3;
2320 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2321 cpl = env->hflags & HF_CPL_MASK;
2322 if (e2 & DESC_S_MASK) {
2323 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2324 /* conforming */
2325 } else {
2326 if (dpl < cpl || dpl < rpl)
2327 return;
2328 }
2329 } else {
2330 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2331 switch(type) {
2332 case 1:
2333 case 2:
2334 case 3:
2335 case 9:
2336 case 11:
2337 break;
2338 default:
2339 return;
2340 }
2341 if (dpl < cpl || dpl < rpl)
2342 return;
2343 }
2344 limit = get_seg_limit(e1, e2);
2345 T1 = limit;
2346 CC_SRC |= CC_Z;
2347 }
2348
2349 void helper_lar(void)
2350 {
2351 unsigned int selector;
2352 uint32_t e1, e2;
2353 int rpl, dpl, cpl, type;
2354
2355 CC_SRC = cc_table[CC_OP].compute_all() & ~CC_Z;
2356 selector = T0 & 0xffff;
2357 if ((selector & 0xfffc) == 0)
2358 return;
2359 if (load_segment(&e1, &e2, selector) != 0)
2360 return;
2361 rpl = selector & 3;
2362 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2363 cpl = env->hflags & HF_CPL_MASK;
2364 if (e2 & DESC_S_MASK) {
2365 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2366 /* conforming */
2367 } else {
2368 if (dpl < cpl || dpl < rpl)
2369 return;
2370 }
2371 } else {
2372 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2373 switch(type) {
2374 case 1:
2375 case 2:
2376 case 3:
2377 case 4:
2378 case 5:
2379 case 9:
2380 case 11:
2381 case 12:
2382 break;
2383 default:
2384 return;
2385 }
2386 if (dpl < cpl || dpl < rpl)
2387 return;
2388 }
2389 T1 = e2 & 0x00f0ff00;
2390 CC_SRC |= CC_Z;
2391 }
2392
2393 void helper_verr(void)
2394 {
2395 unsigned int selector;
2396 uint32_t e1, e2;
2397 int rpl, dpl, cpl;
2398
2399 CC_SRC = cc_table[CC_OP].compute_all() & ~CC_Z;
2400 selector = T0 & 0xffff;
2401 if ((selector & 0xfffc) == 0)
2402 return;
2403 if (load_segment(&e1, &e2, selector) != 0)
2404 return;
2405 if (!(e2 & DESC_S_MASK))
2406 return;
2407 rpl = selector & 3;
2408 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2409 cpl = env->hflags & HF_CPL_MASK;
2410 if (e2 & DESC_CS_MASK) {
2411 if (!(e2 & DESC_R_MASK))
2412 return;
2413 if (!(e2 & DESC_C_MASK)) {
2414 if (dpl < cpl || dpl < rpl)
2415 return;
2416 }
2417 } else {
2418 if (dpl < cpl || dpl < rpl)
2419 return;
2420 }
2421 CC_SRC |= CC_Z;
2422 }
2423
2424 void helper_verw(void)
2425 {
2426 unsigned int selector;
2427 uint32_t e1, e2;
2428 int rpl, dpl, cpl;
2429
2430 CC_SRC = cc_table[CC_OP].compute_all() & ~CC_Z;
2431 selector = T0 & 0xffff;
2432 if ((selector & 0xfffc) == 0)
2433 return;
2434 if (load_segment(&e1, &e2, selector) != 0)
2435 return;
2436 if (!(e2 & DESC_S_MASK))
2437 return;
2438 rpl = selector & 3;
2439 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2440 cpl = env->hflags & HF_CPL_MASK;
2441 if (e2 & DESC_CS_MASK) {
2442 return;
2443 } else {
2444 if (dpl < cpl || dpl < rpl)
2445 return;
2446 if (!(e2 & DESC_W_MASK))
2447 return;
2448 }
2449 CC_SRC |= CC_Z;
2450 }
2451
2452 /* FPU helpers */
2453
2454 void helper_fldt_ST0_A0(void)
2455 {
2456 int new_fpstt;
2457 new_fpstt = (env->fpstt - 1) & 7;
2458 env->fpregs[new_fpstt].d = helper_fldt(A0);
2459 env->fpstt = new_fpstt;
2460 env->fptags[new_fpstt] = 0; /* validate stack entry */
2461 }
2462
2463 void helper_fstt_ST0_A0(void)
2464 {
2465 helper_fstt(ST0, A0);
2466 }
2467
2468 void fpu_set_exception(int mask)
2469 {
2470 env->fpus |= mask;
2471 if (env->fpus & (~env->fpuc & FPUC_EM))
2472 env->fpus |= FPUS_SE | FPUS_B;
2473 }
2474
2475 CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
2476 {
2477 if (b == 0.0)
2478 fpu_set_exception(FPUS_ZE);
2479 return a / b;
2480 }
2481
2482 void fpu_raise_exception(void)
2483 {
2484 if (env->cr[0] & CR0_NE_MASK) {
2485 raise_exception(EXCP10_COPR);
2486 }
2487 #if !defined(CONFIG_USER_ONLY)
2488 else {
2489 cpu_set_ferr(env);
2490 }
2491 #endif
2492 }
2493
2494 /* BCD ops */
2495
2496 void helper_fbld_ST0_A0(void)
2497 {
2498 CPU86_LDouble tmp;
2499 uint64_t val;
2500 unsigned int v;
2501 int i;
2502
2503 val = 0;
2504 for(i = 8; i >= 0; i--) {
2505 v = ldub(A0 + i);
2506 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
2507 }
2508 tmp = val;
2509 if (ldub(A0 + 9) & 0x80)
2510 tmp = -tmp;
2511 fpush();
2512 ST0 = tmp;
2513 }
2514
2515 void helper_fbst_ST0_A0(void)
2516 {
2517 CPU86_LDouble tmp;
2518 int v;
2519 target_ulong mem_ref, mem_end;
2520 int64_t val;
2521
2522 tmp = rint(ST0);
2523 val = (int64_t)tmp;
2524 mem_ref = A0;
2525 mem_end = mem_ref + 9;
2526 if (val < 0) {
2527 stb(mem_end, 0x80);
2528 val = -val;
2529 } else {
2530 stb(mem_end, 0x00);
2531 }
2532 while (mem_ref < mem_end) {
2533 if (val == 0)
2534 break;
2535 v = val % 100;
2536 val = val / 100;
2537 v = ((v / 10) << 4) | (v % 10);
2538 stb(mem_ref++, v);
2539 }
2540 while (mem_ref < mem_end) {
2541 stb(mem_ref++, 0);
2542 }
2543 }
2544
2545 void helper_f2xm1(void)
2546 {
2547 ST0 = pow(2.0,ST0) - 1.0;
2548 }
2549
2550 void helper_fyl2x(void)
2551 {
2552 CPU86_LDouble fptemp;
2553
2554 fptemp = ST0;
2555 if (fptemp>0.0){
2556 fptemp = log(fptemp)/log(2.0); /* log2(ST) */
2557 ST1 *= fptemp;
2558 fpop();
2559 } else {
2560 env->fpus &= (~0x4700);
2561 env->fpus |= 0x400;
2562 }
2563 }
2564
2565 void helper_fptan(void)
2566 {
2567 CPU86_LDouble fptemp;
2568
2569 fptemp = ST0;
2570 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2571 env->fpus |= 0x400;
2572 } else {
2573 ST0 = tan(fptemp);
2574 fpush();
2575 ST0 = 1.0;
2576 env->fpus &= (~0x400); /* C2 <-- 0 */
2577 /* the above code is for |arg| < 2**52 only */
2578 }
2579 }
2580
2581 void helper_fpatan(void)
2582 {
2583 CPU86_LDouble fptemp, fpsrcop;
2584
2585 fpsrcop = ST1;
2586 fptemp = ST0;
2587 ST1 = atan2(fpsrcop,fptemp);
2588 fpop();
2589 }
2590
2591 void helper_fxtract(void)
2592 {
2593 CPU86_LDoubleU temp;
2594 unsigned int expdif;
2595
2596 temp.d = ST0;
2597 expdif = EXPD(temp) - EXPBIAS;
2598 /*DP exponent bias*/
2599 ST0 = expdif;
2600 fpush();
2601 BIASEXPONENT(temp);
2602 ST0 = temp.d;
2603 }
2604
2605 void helper_fprem1(void)
2606 {
2607 CPU86_LDouble dblq, fpsrcop, fptemp;
2608 CPU86_LDoubleU fpsrcop1, fptemp1;
2609 int expdif;
2610 int q;
2611
2612 fpsrcop = ST0;
2613 fptemp = ST1;
2614 fpsrcop1.d = fpsrcop;
2615 fptemp1.d = fptemp;
2616 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2617 if (expdif < 53) {
2618 dblq = fpsrcop / fptemp;
2619 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2620 ST0 = fpsrcop - fptemp*dblq;
2621 q = (int)dblq; /* cutting off top bits is assumed here */
2622 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2623 /* (C0,C1,C3) <-- (q2,q1,q0) */
2624 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2625 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2626 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2627 } else {
2628 env->fpus |= 0x400; /* C2 <-- 1 */
2629 fptemp = pow(2.0, expdif-50);
2630 fpsrcop = (ST0 / ST1) / fptemp;
2631 /* fpsrcop = integer obtained by rounding to the nearest */
2632 fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
2633 floor(fpsrcop): ceil(fpsrcop);
2634 ST0 -= (ST1 * fpsrcop * fptemp);
2635 }
2636 }
2637
2638 void helper_fprem(void)
2639 {
2640 CPU86_LDouble dblq, fpsrcop, fptemp;
2641 CPU86_LDoubleU fpsrcop1, fptemp1;
2642 int expdif;
2643 int q;
2644
2645 fpsrcop = ST0;
2646 fptemp = ST1;
2647 fpsrcop1.d = fpsrcop;
2648 fptemp1.d = fptemp;
2649 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2650 if ( expdif < 53 ) {
2651 dblq = fpsrcop / fptemp;
2652 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2653 ST0 = fpsrcop - fptemp*dblq;
2654 q = (int)dblq; /* cutting off top bits is assumed here */
2655 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2656 /* (C0,C1,C3) <-- (q2,q1,q0) */
2657 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2658 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2659 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2660 } else {
2661 env->fpus |= 0x400; /* C2 <-- 1 */
2662 fptemp = pow(2.0, expdif-50);
2663 fpsrcop = (ST0 / ST1) / fptemp;
2664 /* fpsrcop = integer obtained by chopping */
2665 fpsrcop = (fpsrcop < 0.0)?
2666 -(floor(fabs(fpsrcop))): floor(fpsrcop);
2667 ST0 -= (ST1 * fpsrcop * fptemp);
2668 }
2669 }
2670
2671 void helper_fyl2xp1(void)
2672 {
2673 CPU86_LDouble fptemp;
2674
2675 fptemp = ST0;
2676 if ((fptemp+1.0)>0.0) {
2677 fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
2678 ST1 *= fptemp;
2679 fpop();
2680 } else {
2681 env->fpus &= (~0x4700);
2682 env->fpus |= 0x400;
2683 }
2684 }
2685
2686 void helper_fsqrt(void)
2687 {
2688 CPU86_LDouble fptemp;
2689
2690 fptemp = ST0;
2691 if (fptemp<0.0) {
2692 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2693 env->fpus |= 0x400;
2694 }
2695 ST0 = sqrt(fptemp);
2696 }
2697
2698 void helper_fsincos(void)
2699 {
2700 CPU86_LDouble fptemp;
2701
2702 fptemp = ST0;
2703 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2704 env->fpus |= 0x400;
2705 } else {
2706 ST0 = sin(fptemp);
2707 fpush();
2708 ST0 = cos(fptemp);
2709 env->fpus &= (~0x400); /* C2 <-- 0 */
2710 /* the above code is for |arg| < 2**63 only */
2711 }
2712 }
2713
2714 void helper_frndint(void)
2715 {
2716 CPU86_LDouble a;
2717
2718 a = ST0;
2719 #ifdef __arm__
2720 switch(env->fpuc & RC_MASK) {
2721 default:
2722 case RC_NEAR:
2723 asm("rndd %0, %1" : "=f" (a) : "f"(a));
2724 break;
2725 case RC_DOWN:
2726 asm("rnddm %0, %1" : "=f" (a) : "f"(a));
2727 break;
2728 case RC_UP:
2729 asm("rnddp %0, %1" : "=f" (a) : "f"(a));
2730 break;
2731 case RC_CHOP:
2732 asm("rnddz %0, %1" : "=f" (a) : "f"(a));
2733 break;
2734 }
2735 #else
2736 a = rint(a);
2737 #endif
2738 ST0 = a;
2739 }
2740
2741 void helper_fscale(void)
2742 {
2743 CPU86_LDouble fpsrcop, fptemp;
2744
2745 fpsrcop = 2.0;
2746 fptemp = pow(fpsrcop,ST1);
2747 ST0 *= fptemp;
2748 }
2749
2750 void helper_fsin(void)
2751 {
2752 CPU86_LDouble fptemp;
2753
2754 fptemp = ST0;
2755 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2756 env->fpus |= 0x400;
2757 } else {
2758 ST0 = sin(fptemp);
2759 env->fpus &= (~0x400); /* C2 <-- 0 */
2760 /* the above code is for |arg| < 2**53 only */
2761 }
2762 }
2763
2764 void helper_fcos(void)
2765 {
2766 CPU86_LDouble fptemp;
2767
2768 fptemp = ST0;
2769 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2770 env->fpus |= 0x400;
2771 } else {
2772 ST0 = cos(fptemp);
2773 env->fpus &= (~0x400); /* C2 <-- 0 */
2774 /* the above code is for |arg5 < 2**63 only */
2775 }
2776 }
2777
2778 void helper_fxam_ST0(void)
2779 {
2780 CPU86_LDoubleU temp;
2781 int expdif;
2782
2783 temp.d = ST0;
2784
2785 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2786 if (SIGND(temp))
2787 env->fpus |= 0x200; /* C1 <-- 1 */
2788
2789 expdif = EXPD(temp);
2790 if (expdif == MAXEXPD) {
2791 if (MANTD(temp) == 0)
2792 env->fpus |= 0x500 /*Infinity*/;
2793 else
2794 env->fpus |= 0x100 /*NaN*/;
2795 } else if (expdif == 0) {
2796 if (MANTD(temp) == 0)
2797 env->fpus |= 0x4000 /*Zero*/;
2798 else
2799 env->fpus |= 0x4400 /*Denormal*/;
2800 } else {
2801 env->fpus |= 0x400;
2802 }
2803 }
2804
2805 void helper_fstenv(target_ulong ptr, int data32)
2806 {
2807 int fpus, fptag, exp, i;
2808 uint64_t mant;
2809 CPU86_LDoubleU tmp;
2810
2811 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
2812 fptag = 0;
2813 for (i=7; i>=0; i--) {
2814 fptag <<= 2;
2815 if (env->fptags[i]) {
2816 fptag |= 3;
2817 } else {
2818 tmp.d = env->fpregs[i].d;
2819 exp = EXPD(tmp);
2820 mant = MANTD(tmp);
2821 if (exp == 0 && mant == 0) {
2822 /* zero */
2823 fptag |= 1;
2824 } else if (exp == 0 || exp == MAXEXPD
2825 #ifdef USE_X86LDOUBLE
2826 || (mant & (1LL << 63)) == 0
2827 #endif
2828 ) {
2829 /* NaNs, infinity, denormal */
2830 fptag |= 2;
2831 }
2832 }
2833 }
2834 if (data32) {
2835 /* 32 bit */
2836 stl(ptr, env->fpuc);
2837 stl(ptr + 4, fpus);
2838 stl(ptr + 8, fptag);
2839 stl(ptr + 12, 0); /* fpip */
2840 stl(ptr + 16, 0); /* fpcs */
2841 stl(ptr + 20, 0); /* fpoo */
2842 stl(ptr + 24, 0); /* fpos */
2843 } else {
2844 /* 16 bit */
2845 stw(ptr, env->fpuc);
2846 stw(ptr + 2, fpus);
2847 stw(ptr + 4, fptag);
2848 stw(ptr + 6, 0);
2849 stw(ptr + 8, 0);
2850 stw(ptr + 10, 0);
2851 stw(ptr + 12, 0);
2852 }
2853 }
2854
2855 void helper_fldenv(target_ulong ptr, int data32)
2856 {
2857 int i, fpus, fptag;
2858
2859 if (data32) {
2860 env->fpuc = lduw(ptr);
2861 fpus = lduw(ptr + 4);
2862 fptag = lduw(ptr + 8);
2863 }
2864 else {
2865 env->fpuc = lduw(ptr);
2866 fpus = lduw(ptr + 2);
2867 fptag = lduw(ptr + 4);
2868 }
2869 env->fpstt = (fpus >> 11) & 7;
2870 env->fpus = fpus & ~0x3800;
2871 for(i = 0;i < 8; i++) {
2872 env->fptags[i] = ((fptag & 3) == 3);
2873 fptag >>= 2;
2874 }
2875 }
2876
2877 void helper_fsave(target_ulong ptr, int data32)
2878 {
2879 CPU86_LDouble tmp;
2880 int i;
2881
2882 helper_fstenv(ptr, data32);
2883
2884 ptr += (14 << data32);
2885 for(i = 0;i < 8; i++) {
2886 tmp = ST(i);
2887 helper_fstt(tmp, ptr);
2888 ptr += 10;
2889 }
2890
2891 /* fninit */
2892 env->fpus = 0;
2893 env->fpstt = 0;
2894 env->fpuc = 0x37f;
2895 env->fptags[0] = 1;
2896 env->fptags[1] = 1;
2897 env->fptags[2] = 1;
2898 env->fptags[3] = 1;
2899 env->fptags[4] = 1;
2900 env->fptags[5] = 1;
2901 env->fptags[6] = 1;
2902 env->fptags[7] = 1;
2903 }
2904
2905 void helper_frstor(target_ulong ptr, int data32)
2906 {
2907 CPU86_LDouble tmp;
2908 int i;
2909
2910 helper_fldenv(ptr, data32);
2911 ptr += (14 << data32);
2912
2913 for(i = 0;i < 8; i++) {
2914 tmp = helper_fldt(ptr);
2915 ST(i) = tmp;
2916 ptr += 10;
2917 }
2918 }
2919
2920 void helper_fxsave(target_ulong ptr, int data64)
2921 {
2922 int fpus, fptag, i, nb_xmm_regs;
2923 CPU86_LDouble tmp;
2924 target_ulong addr;
2925
2926 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
2927 fptag = 0;
2928 for(i = 0; i < 8; i++) {
2929 fptag |= (env->fptags[i] << i);
2930 }
2931 stw(ptr, env->fpuc);
2932 stw(ptr + 2, fpus);
2933 stw(ptr + 4, fptag ^ 0xff);
2934
2935 addr = ptr + 0x20;
2936 for(i = 0;i < 8; i++) {
2937 tmp = ST(i);
2938 helper_fstt(tmp, addr);
2939 addr += 16;
2940 }
2941
2942 if (env->cr[4] & CR4_OSFXSR_MASK) {
2943 /* XXX: finish it */
2944 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
2945 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
2946 nb_xmm_regs = 8 << data64;
2947 addr = ptr + 0xa0;
2948 for(i = 0; i < nb_xmm_regs; i++) {
2949 stq(addr, env->xmm_regs[i].XMM_Q(0));
2950 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
2951 addr += 16;
2952 }
2953 }
2954 }
2955
2956 void helper_fxrstor(target_ulong ptr, int data64)
2957 {
2958 int i, fpus, fptag, nb_xmm_regs;
2959 CPU86_LDouble tmp;
2960 target_ulong addr;
2961
2962 env->fpuc = lduw(ptr);
2963 fpus = lduw(ptr + 2);
2964 fptag = lduw(ptr + 4);
2965 env->fpstt = (fpus >> 11) & 7;
2966 env->fpus = fpus & ~0x3800;
2967 fptag ^= 0xff;
2968 for(i = 0;i < 8; i++) {
2969 env->fptags[i] = ((fptag >> i) & 1);
2970 }
2971
2972 addr = ptr + 0x20;
2973 for(i = 0;i < 8; i++) {
2974 tmp = helper_fldt(addr);
2975 ST(i) = tmp;
2976 addr += 16;
2977 }
2978
2979 if (env->cr[4] & CR4_OSFXSR_MASK) {
2980 /* XXX: finish it, endianness */
2981 env->mxcsr = ldl(ptr + 0x18);
2982 //ldl(ptr + 0x1c);
2983 nb_xmm_regs = 8 << data64;
2984 addr = ptr + 0xa0;
2985 for(i = 0; i < nb_xmm_regs; i++) {
2986 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
2987 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
2988 addr += 16;
2989 }
2990 }
2991 }
2992
2993 #ifndef USE_X86LDOUBLE
2994
2995 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
2996 {
2997 CPU86_LDoubleU temp;
2998 int e;
2999
3000 temp.d = f;
3001 /* mantissa */
3002 *pmant = (MANTD(temp) << 11) | (1LL << 63);
3003 /* exponent + sign */
3004 e = EXPD(temp) - EXPBIAS + 16383;
3005 e |= SIGND(temp) >> 16;
3006 *pexp = e;
3007 }
3008
3009 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3010 {
3011 CPU86_LDoubleU temp;
3012 int e;
3013 uint64_t ll;
3014
3015 /* XXX: handle overflow ? */
3016 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3017 e |= (upper >> 4) & 0x800; /* sign */
3018 ll = (mant >> 11) & ((1LL << 52) - 1);
3019 #ifdef __arm__
3020 temp.l.upper = (e << 20) | (ll >> 32);
3021 temp.l.lower = ll;
3022 #else
3023 temp.ll = ll | ((uint64_t)e << 52);
3024 #endif
3025 return temp.d;
3026 }
3027
3028 #else
3029
3030 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3031 {
3032 CPU86_LDoubleU temp;
3033
3034 temp.d = f;
3035 *pmant = temp.l.lower;
3036 *pexp = temp.l.upper;
3037 }
3038
3039 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3040 {
3041 CPU86_LDoubleU temp;
3042
3043 temp.l.upper = upper;
3044 temp.l.lower = mant;
3045 return temp.d;
3046 }
3047 #endif
3048
3049 #ifdef TARGET_X86_64
3050
3051 //#define DEBUG_MULDIV
3052
3053 static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3054 {
3055 *plow += a;
3056 /* carry test */
3057 if (*plow < a)
3058 (*phigh)++;
3059 *phigh += b;
3060 }
3061
3062 static void neg128(uint64_t *plow, uint64_t *phigh)
3063 {
3064 *plow = ~ *plow;
3065 *phigh = ~ *phigh;
3066 add128(plow, phigh, 1, 0);
3067 }
3068
3069 static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3070 {
3071 uint32_t a0, a1, b0, b1;
3072 uint64_t v;
3073
3074 a0 = a;
3075 a1 = a >> 32;
3076
3077 b0 = b;
3078 b1 = b >> 32;
3079
3080 v = (uint64_t)a0 * (uint64_t)b0;
3081 *plow = v;
3082 *phigh = 0;
3083
3084 v = (uint64_t)a0 * (uint64_t)b1;
3085 add128(plow, phigh, v << 32, v >> 32);
3086
3087 v = (uint64_t)a1 * (uint64_t)b0;
3088 add128(plow, phigh, v << 32, v >> 32);
3089
3090 v = (uint64_t)a1 * (uint64_t)b1;
3091 *phigh += v;
3092 #ifdef DEBUG_MULDIV
3093 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
3094 a, b, *phigh, *plow);
3095 #endif
3096 }
3097
3098 static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
3099 {
3100 int sa, sb;
3101 sa = (a < 0);
3102 if (sa)
3103 a = -a;
3104 sb = (b < 0);
3105 if (sb)
3106 b = -b;
3107 mul64(plow, phigh, a, b);
3108 if (sa ^ sb) {
3109 neg128(plow, phigh);
3110 }
3111 }
3112
3113 /* XXX: overflow support */
3114 static void div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
3115 {
3116 uint64_t q, r, a1, a0;
3117 int i, qb;
3118
3119 a0 = *plow;
3120 a1 = *phigh;
3121 if (a1 == 0) {
3122 q = a0 / b;
3123 r = a0 % b;
3124 *plow = q;
3125 *phigh = r;
3126 } else {
3127 /* XXX: use a better algorithm */
3128 for(i = 0; i < 64; i++) {
3129 a1 = (a1 << 1) | (a0 >> 63);
3130 if (a1 >= b) {
3131 a1 -= b;
3132 qb = 1;
3133 } else {
3134 qb = 0;
3135 }
3136 a0 = (a0 << 1) | qb;
3137 }
3138 #if defined(DEBUG_MULDIV)
3139 printf("div: 0x%016llx%016llx / 0x%016llx: q=0x%016llx r=0x%016llx\n",
3140 *phigh, *plow, b, a0, a1);
3141 #endif
3142 *plow = a0;
3143 *phigh = a1;
3144 }
3145 }
3146
3147 static void idiv64(uint64_t *plow, uint64_t *phigh, uint64_t b)
3148 {
3149 int sa, sb;
3150 sa = ((int64_t)*phigh < 0);
3151 if (sa)
3152 neg128(plow, phigh);
3153 sb = (b < 0);
3154 if (sb)
3155 b = -b;
3156 div64(plow, phigh, b);
3157 if (sa ^ sb)
3158 *plow = - *plow;
3159 if (sb)
3160 *phigh = - *phigh;
3161 }
3162
3163 void helper_mulq_EAX_T0(void)
3164 {
3165 uint64_t r0, r1;
3166
3167 mul64(&r0, &r1, EAX, T0);
3168 EAX = r0;
3169 EDX = r1;
3170 CC_DST = r0;
3171 CC_SRC = r1;
3172 }
3173
3174 void helper_imulq_EAX_T0(void)
3175 {
3176 uint64_t r0, r1;
3177
3178 imul64(&r0, &r1, EAX, T0);
3179 EAX = r0;
3180 EDX = r1;
3181 CC_DST = r0;
3182 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3183 }
3184
3185 void helper_imulq_T0_T1(void)
3186 {
3187 uint64_t r0, r1;
3188
3189 imul64(&r0, &r1, T0, T1);
3190 T0 = r0;
3191 CC_DST = r0;
3192 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3193 }
3194
3195 void helper_divq_EAX_T0(void)
3196 {
3197 uint64_t r0, r1;
3198 if (T0 == 0) {
3199 raise_exception(EXCP00_DIVZ);
3200 }
3201 r0 = EAX;
3202 r1 = EDX;
3203 div64(&r0, &r1, T0);
3204 EAX = r0;
3205 EDX = r1;
3206 }
3207
3208 void helper_idivq_EAX_T0(void)
3209 {
3210 uint64_t r0, r1;
3211 if (T0 == 0) {
3212 raise_exception(EXCP00_DIVZ);
3213 }
3214 r0 = EAX;
3215 r1 = EDX;
3216 idiv64(&r0, &r1, T0);
3217 EAX = r0;
3218 EDX = r1;
3219 }
3220
3221 #endif
3222
3223 /* XXX: do it */
3224 int fpu_isnan(double a)
3225 {
3226 return 0;
3227 }
3228
3229 float approx_rsqrt(float a)
3230 {
3231 return 1.0 / sqrt(a);
3232 }
3233
3234 float approx_rcp(float a)
3235 {
3236 return 1.0 / a;
3237 }
3238
3239 /* XXX: find a better solution */
3240 double helper_sqrt(double a)
3241 {
3242 return sqrt(a);
3243 }
3244
3245 /* XXX: move that to another file */
3246 #if defined(__powerpc__)
3247 /* better to call an helper on ppc */
3248 float int32_to_float32(int32_t a)
3249 {
3250 return (float)a;
3251 }
3252
3253 double int32_to_float64(int32_t a)
3254 {
3255 return (double)a;
3256 }
3257 #endif
3258
3259 #if !defined(CONFIG_USER_ONLY)
3260
3261 #define MMUSUFFIX _mmu
3262 #define GETPC() (__builtin_return_address(0))
3263
3264 #define SHIFT 0
3265 #include "softmmu_template.h"
3266
3267 #define SHIFT 1
3268 #include "softmmu_template.h"
3269
3270 #define SHIFT 2
3271 #include "softmmu_template.h"
3272
3273 #define SHIFT 3
3274 #include "softmmu_template.h"
3275
3276 #endif
3277
3278 /* try to fill the TLB and return an exception if error. If retaddr is
3279 NULL, it means that the function was called in C code (i.e. not
3280 from generated code or from helper.c) */
3281 /* XXX: fix it to restore all registers */
3282 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
3283 {
3284 TranslationBlock *tb;
3285 int ret;
3286 unsigned long pc;
3287 CPUX86State *saved_env;
3288
3289 /* XXX: hack to restore env in all cases, even if not called from
3290 generated code */
3291 saved_env = env;
3292 env = cpu_single_env;
3293
3294 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
3295 if (ret) {
3296 if (retaddr) {
3297 /* now we have a real cpu fault */
3298 pc = (unsigned long)retaddr;
3299 tb = tb_find_pc(pc);
3300 if (tb) {
3301 /* the PC is inside the translated code. It means that we have
3302 a virtual CPU fault */
3303 cpu_restore_state(tb, env, pc, NULL);
3304 }
3305 }
3306 if (retaddr)
3307 raise_exception_err(EXCP0E_PAGE, env->error_code);
3308 else
3309 raise_exception_err_norestore(EXCP0E_PAGE, env->error_code);
3310 }
3311 env = saved_env;
3312 }
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