target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "cpu.h"
  27 #include "gdbstub.h"
  28 #include "host-utils.h"
  29 #include "hw/pc.h"
  30 #include "hw/apic.h"
  31 #include "ioport.h"
  32
  33 //#define DEBUG_KVM
  34
  35 #ifdef DEBUG_KVM
  36 #define DPRINTF(fmt, ...) \
  37     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  38 #else
  39 #define DPRINTF(fmt, ...) \
  40     do { } while (0)
  41 #endif
  42
  43 #define MSR_KVM_WALL_CLOCK  0x11
  44 #define MSR_KVM_SYSTEM_TIME 0x12
  45
  46 #ifndef BUS_MCEERR_AR
  47 #define BUS_MCEERR_AR 4
  48 #endif
  49 #ifndef BUS_MCEERR_AO
  50 #define BUS_MCEERR_AO 5
  51 #endif
  52
  53 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  54     KVM_CAP_INFO(SET_TSS_ADDR),
  55     KVM_CAP_INFO(EXT_CPUID),
  56     KVM_CAP_INFO(MP_STATE),
  57     KVM_CAP_LAST_INFO
  58 };
  59
  60 static bool has_msr_star;
  61 static bool has_msr_hsave_pa;
  62 static bool has_msr_tsc_deadline;
  63 static bool has_msr_async_pf_en;
  64 static bool has_msr_misc_enable;
  65 static int lm_capable_kernel;
  66
  67 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  68 {
  69     struct kvm_cpuid2 *cpuid;
  70     int r, size;
  71
  72     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  73     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  74     cpuid->nent = max;
  75     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  76     if (r == 0 && cpuid->nent >= max) {
  77         r = -E2BIG;
  78     }
  79     if (r < 0) {
  80         if (r == -E2BIG) {
  81             g_free(cpuid);
  82             return NULL;
  83         } else {
  84             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  85                     strerror(-r));
  86             exit(1);
  87         }
  88     }
  89     return cpuid;
  90 }
  91
  92 struct kvm_para_features {
  93     int cap;
  94     int feature;
  95 } para_features[] = {
  96     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
  97     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
  98     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
  99     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 100     { -1, -1 }
 101 };
 102
 103 static int get_para_features(KVMState *s)
 104 {
 105     int i, features = 0;
 106
 107     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 108         if (kvm_check_extension(s, para_features[i].cap)) {
 109             features |= (1 << para_features[i].feature);
 110         }
 111     }
 112
 113     return features;
 114 }
 115
 116
 117 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 118                                       uint32_t index, int reg)
 119 {
 120     struct kvm_cpuid2 *cpuid;
 121     int i, max;
 122     uint32_t ret = 0;
 123     uint32_t cpuid_1_edx;
 124     int has_kvm_features = 0;
 125
 126     max = 1;
 127     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 128         max *= 2;
 129     }
 130
 131     for (i = 0; i < cpuid->nent; ++i) {
 132         if (cpuid->entries[i].function == function &&
 133             cpuid->entries[i].index == index) {
 134             if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
 135                 has_kvm_features = 1;
 136             }
 137             switch (reg) {
 138             case R_EAX:
 139                 ret = cpuid->entries[i].eax;
 140                 break;
 141             case R_EBX:
 142                 ret = cpuid->entries[i].ebx;
 143                 break;
 144             case R_ECX:
 145                 ret = cpuid->entries[i].ecx;
 146                 break;
 147             case R_EDX:
 148                 ret = cpuid->entries[i].edx;
 149                 switch (function) {
 150                 case 1:
 151                     /* KVM before 2.6.30 misreports the following features */
 152                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 153                     break;
 154                 case 0x80000001:
 155                     /* On Intel, kvm returns cpuid according to the Intel spec,
 156                      * so add missing bits according to the AMD spec:
 157                      */
 158                     cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 159                     ret |= cpuid_1_edx & 0x183f7ff;
 160                     break;
 161                 }
 162                 break;
 163             }
 164         }
 165     }
 166
 167     g_free(cpuid);
 168
 169     /* fallback for older kernels */
 170     if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
 171         ret = get_para_features(s);
 172     }
 173
 174     return ret;
 175 }
 176
 177 typedef struct HWPoisonPage {
 178     ram_addr_t ram_addr;
 179     QLIST_ENTRY(HWPoisonPage) list;
 180 } HWPoisonPage;
 181
 182 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 183     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 184
 185 static void kvm_unpoison_all(void *param)
 186 {
 187     HWPoisonPage *page, *next_page;
 188
 189     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 190         QLIST_REMOVE(page, list);
 191         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 192         g_free(page);
 193     }
 194 }
 195
 196 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 197 {
 198     HWPoisonPage *page;
 199
 200     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 201         if (page->ram_addr == ram_addr) {
 202             return;
 203         }
 204     }
 205     page = g_malloc(sizeof(HWPoisonPage));
 206     page->ram_addr = ram_addr;
 207     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 208 }
 209
 210 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 211                                      int *max_banks)
 212 {
 213     int r;
 214
 215     r = kvm_check_extension(s, KVM_CAP_MCE);
 216     if (r > 0) {
 217         *max_banks = r;
 218         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 219     }
 220     return -ENOSYS;
 221 }
 222
 223 static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
 224 {
 225     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 226                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 227     uint64_t mcg_status = MCG_STATUS_MCIP;
 228
 229     if (code == BUS_MCEERR_AR) {
 230         status |= MCI_STATUS_AR | 0x134;
 231         mcg_status |= MCG_STATUS_EIPV;
 232     } else {
 233         status |= 0xc0;
 234         mcg_status |= MCG_STATUS_RIPV;
 235     }
 236     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 237                        (MCM_ADDR_PHYS << 6) | 0xc,
 238                        cpu_x86_support_mca_broadcast(env) ?
 239                        MCE_INJECT_BROADCAST : 0);
 240 }
 241
 242 static void hardware_memory_error(void)
 243 {
 244     fprintf(stderr, "Hardware memory error!\n");
 245     exit(1);
 246 }
 247
 248 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
 249 {
 250     ram_addr_t ram_addr;
 251     target_phys_addr_t paddr;
 252
 253     if ((env->mcg_cap & MCG_SER_P) && addr
 254         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 255         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 256             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 257             fprintf(stderr, "Hardware memory error for memory used by "
 258                     "QEMU itself instead of guest system!\n");
 259             /* Hope we are lucky for AO MCE */
 260             if (code == BUS_MCEERR_AO) {
 261                 return 0;
 262             } else {
 263                 hardware_memory_error();
 264             }
 265         }
 266         kvm_hwpoison_page_add(ram_addr);
 267         kvm_mce_inject(env, paddr, code);
 268     } else {
 269         if (code == BUS_MCEERR_AO) {
 270             return 0;
 271         } else if (code == BUS_MCEERR_AR) {
 272             hardware_memory_error();
 273         } else {
 274             return 1;
 275         }
 276     }
 277     return 0;
 278 }
 279
 280 int kvm_arch_on_sigbus(int code, void *addr)
 281 {
 282     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 283         ram_addr_t ram_addr;
 284         target_phys_addr_t paddr;
 285
 286         /* Hope we are lucky for AO MCE */
 287         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 288             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 289                                                 &paddr)) {
 290             fprintf(stderr, "Hardware memory error for memory used by "
 291                     "QEMU itself instead of guest system!: %p\n", addr);
 292             return 0;
 293         }
 294         kvm_hwpoison_page_add(ram_addr);
 295         kvm_mce_inject(first_cpu, paddr, code);
 296     } else {
 297         if (code == BUS_MCEERR_AO) {
 298             return 0;
 299         } else if (code == BUS_MCEERR_AR) {
 300             hardware_memory_error();
 301         } else {
 302             return 1;
 303         }
 304     }
 305     return 0;
 306 }
 307
 308 static int kvm_inject_mce_oldstyle(CPUState *env)
 309 {
 310     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 311         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 312         struct kvm_x86_mce mce;
 313
 314         env->exception_injected = -1;
 315
 316         /*
 317          * There must be at least one bank in use if an MCE is pending.
 318          * Find it and use its values for the event injection.
 319          */
 320         for (bank = 0; bank < bank_num; bank++) {
 321             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 322                 break;
 323             }
 324         }
 325         assert(bank < bank_num);
 326
 327         mce.bank = bank;
 328         mce.status = env->mce_banks[bank * 4 + 1];
 329         mce.mcg_status = env->mcg_status;
 330         mce.addr = env->mce_banks[bank * 4 + 2];
 331         mce.misc = env->mce_banks[bank * 4 + 3];
 332
 333         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 334     }
 335     return 0;
 336 }
 337
 338 static void cpu_update_state(void *opaque, int running, RunState state)
 339 {
 340     CPUState *env = opaque;
 341
 342     if (running) {
 343         env->tsc_valid = false;
 344     }
 345 }
 346
 347 int kvm_arch_init_vcpu(CPUState *env)
 348 {
 349     struct {
 350         struct kvm_cpuid2 cpuid;
 351         struct kvm_cpuid_entry2 entries[100];
 352     } QEMU_PACKED cpuid_data;
 353     KVMState *s = env->kvm_state;
 354     uint32_t limit, i, j, cpuid_i;
 355     uint32_t unused;
 356     struct kvm_cpuid_entry2 *c;
 357     uint32_t signature[3];
 358     int r;
 359
 360     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 361
 362     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 363     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 364     env->cpuid_ext_features |= i;
 365
 366     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 367                                                              0, R_EDX);
 368     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 369                                                              0, R_ECX);
 370     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 371                                                              0, R_EDX);
 372
 373     cpuid_i = 0;
 374
 375     /* Paravirtualization CPUIDs */
 376     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 377     c = &cpuid_data.entries[cpuid_i++];
 378     memset(c, 0, sizeof(*c));
 379     c->function = KVM_CPUID_SIGNATURE;
 380     c->eax = 0;
 381     c->ebx = signature[0];
 382     c->ecx = signature[1];
 383     c->edx = signature[2];
 384
 385     c = &cpuid_data.entries[cpuid_i++];
 386     memset(c, 0, sizeof(*c));
 387     c->function = KVM_CPUID_FEATURES;
 388     c->eax = env->cpuid_kvm_features &
 389         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 390
 391     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 392
 393     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 394
 395     for (i = 0; i <= limit; i++) {
 396         c = &cpuid_data.entries[cpuid_i++];
 397
 398         switch (i) {
 399         case 2: {
 400             /* Keep reading function 2 till all the input is received */
 401             int times;
 402
 403             c->function = i;
 404             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 405                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 406             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 407             times = c->eax & 0xff;
 408
 409             for (j = 1; j < times; ++j) {
 410                 c = &cpuid_data.entries[cpuid_i++];
 411                 c->function = i;
 412                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 413                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 414             }
 415             break;
 416         }
 417         case 4:
 418         case 0xb:
 419         case 0xd:
 420             for (j = 0; ; j++) {
 421                 if (i == 0xd && j == 64) {
 422                     break;
 423                 }
 424                 c->function = i;
 425                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 426                 c->index = j;
 427                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 428
 429                 if (i == 4 && c->eax == 0) {
 430                     break;
 431                 }
 432                 if (i == 0xb && !(c->ecx & 0xff00)) {
 433                     break;
 434                 }
 435                 if (i == 0xd && c->eax == 0) {
 436                     continue;
 437                 }
 438                 c = &cpuid_data.entries[cpuid_i++];
 439             }
 440             break;
 441         default:
 442             c->function = i;
 443             c->flags = 0;
 444             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 445             break;
 446         }
 447     }
 448     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 449
 450     for (i = 0x80000000; i <= limit; i++) {
 451         c = &cpuid_data.entries[cpuid_i++];
 452
 453         c->function = i;
 454         c->flags = 0;
 455         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 456     }
 457
 458     /* Call Centaur's CPUID instructions they are supported. */
 459     if (env->cpuid_xlevel2 > 0) {
 460         env->cpuid_ext4_features &=
 461             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 462         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 463
 464         for (i = 0xC0000000; i <= limit; i++) {
 465             c = &cpuid_data.entries[cpuid_i++];
 466
 467             c->function = i;
 468             c->flags = 0;
 469             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 470         }
 471     }
 472
 473     cpuid_data.cpuid.nent = cpuid_i;
 474
 475     if (((env->cpuid_version >> 8)&0xF) >= 6
 476         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 477         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 478         uint64_t mcg_cap;
 479         int banks;
 480         int ret;
 481
 482         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 483         if (ret < 0) {
 484             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 485             return ret;
 486         }
 487
 488         if (banks > MCE_BANKS_DEF) {
 489             banks = MCE_BANKS_DEF;
 490         }
 491         mcg_cap &= MCE_CAP_DEF;
 492         mcg_cap |= banks;
 493         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 494         if (ret < 0) {
 495             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 496             return ret;
 497         }
 498
 499         env->mcg_cap = mcg_cap;
 500     }
 501
 502     qemu_add_vm_change_state_handler(cpu_update_state, env);
 503
 504     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 505     if (r) {
 506         return r;
 507     }
 508
 509     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 510     if (r && env->tsc_khz) {
 511         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 512         if (r < 0) {
 513             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 514             return r;
 515         }
 516     }
 517
 518     if (kvm_has_xsave()) {
 519         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 520     }
 521
 522     return 0;
 523 }
 524
 525 void kvm_arch_reset_vcpu(CPUState *env)
 526 {
 527     env->exception_injected = -1;
 528     env->interrupt_injected = -1;
 529     env->xcr0 = 1;
 530     if (kvm_irqchip_in_kernel()) {
 531         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 532                                           KVM_MP_STATE_UNINITIALIZED;
 533     } else {
 534         env->mp_state = KVM_MP_STATE_RUNNABLE;
 535     }
 536 }
 537
 538 static int kvm_get_supported_msrs(KVMState *s)
 539 {
 540     static int kvm_supported_msrs;
 541     int ret = 0;
 542
 543     /* first time */
 544     if (kvm_supported_msrs == 0) {
 545         struct kvm_msr_list msr_list, *kvm_msr_list;
 546
 547         kvm_supported_msrs = -1;
 548
 549         /* Obtain MSR list from KVM.  These are the MSRs that we must
 550          * save/restore */
 551         msr_list.nmsrs = 0;
 552         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 553         if (ret < 0 && ret != -E2BIG) {
 554             return ret;
 555         }
 556         /* Old kernel modules had a bug and could write beyond the provided
 557            memory. Allocate at least a safe amount of 1K. */
 558         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 559                                               msr_list.nmsrs *
 560                                               sizeof(msr_list.indices[0])));
 561
 562         kvm_msr_list->nmsrs = msr_list.nmsrs;
 563         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 564         if (ret >= 0) {
 565             int i;
 566
 567             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 568                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 569                     has_msr_star = true;
 570                     continue;
 571                 }
 572                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 573                     has_msr_hsave_pa = true;
 574                     continue;
 575                 }
 576                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 577                     has_msr_tsc_deadline = true;
 578                     continue;
 579                 }
 580                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 581                     has_msr_misc_enable = true;
 582                     continue;
 583                 }
 584             }
 585         }
 586
 587         g_free(kvm_msr_list);
 588     }
 589
 590     return ret;
 591 }
 592
 593 int kvm_arch_init(KVMState *s)
 594 {
 595     uint64_t identity_base = 0xfffbc000;
 596     int ret;
 597     struct utsname utsname;
 598
 599     ret = kvm_get_supported_msrs(s);
 600     if (ret < 0) {
 601         return ret;
 602     }
 603
 604     uname(&utsname);
 605     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 606
 607     /*
 608      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 609      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 610      * Since these must be part of guest physical memory, we need to allocate
 611      * them, both by setting their start addresses in the kernel and by
 612      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 613      *
 614      * Older KVM versions may not support setting the identity map base. In
 615      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 616      * size.
 617      */
 618     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 619         /* Allows up to 16M BIOSes. */
 620         identity_base = 0xfeffc000;
 621
 622         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 623         if (ret < 0) {
 624             return ret;
 625         }
 626     }
 627
 628     /* Set TSS base one page after EPT identity map. */
 629     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 630     if (ret < 0) {
 631         return ret;
 632     }
 633
 634     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 635     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 636     if (ret < 0) {
 637         fprintf(stderr, "e820_add_entry() table is full\n");
 638         return ret;
 639     }
 640     qemu_register_reset(kvm_unpoison_all, NULL);
 641
 642     return 0;
 643 }
 644
 645 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 646 {
 647     lhs->selector = rhs->selector;
 648     lhs->base = rhs->base;
 649     lhs->limit = rhs->limit;
 650     lhs->type = 3;
 651     lhs->present = 1;
 652     lhs->dpl = 3;
 653     lhs->db = 0;
 654     lhs->s = 1;
 655     lhs->l = 0;
 656     lhs->g = 0;
 657     lhs->avl = 0;
 658     lhs->unusable = 0;
 659 }
 660
 661 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 662 {
 663     unsigned flags = rhs->flags;
 664     lhs->selector = rhs->selector;
 665     lhs->base = rhs->base;
 666     lhs->limit = rhs->limit;
 667     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 668     lhs->present = (flags & DESC_P_MASK) != 0;
 669     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 670     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 671     lhs->s = (flags & DESC_S_MASK) != 0;
 672     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 673     lhs->g = (flags & DESC_G_MASK) != 0;
 674     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 675     lhs->unusable = 0;
 676 }
 677
 678 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 679 {
 680     lhs->selector = rhs->selector;
 681     lhs->base = rhs->base;
 682     lhs->limit = rhs->limit;
 683     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 684                  (rhs->present * DESC_P_MASK) |
 685                  (rhs->dpl << DESC_DPL_SHIFT) |
 686                  (rhs->db << DESC_B_SHIFT) |
 687                  (rhs->s * DESC_S_MASK) |
 688                  (rhs->l << DESC_L_SHIFT) |
 689                  (rhs->g * DESC_G_MASK) |
 690                  (rhs->avl * DESC_AVL_MASK);
 691 }
 692
 693 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 694 {
 695     if (set) {
 696         *kvm_reg = *qemu_reg;
 697     } else {
 698         *qemu_reg = *kvm_reg;
 699     }
 700 }
 701
 702 static int kvm_getput_regs(CPUState *env, int set)
 703 {
 704     struct kvm_regs regs;
 705     int ret = 0;
 706
 707     if (!set) {
 708         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 709         if (ret < 0) {
 710             return ret;
 711         }
 712     }
 713
 714     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 715     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 716     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 717     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 718     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 719     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 720     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 721     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 722 #ifdef TARGET_X86_64
 723     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 724     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 725     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 726     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 727     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 728     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 729     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 730     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 731 #endif
 732
 733     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 734     kvm_getput_reg(&regs.rip, &env->eip, set);
 735
 736     if (set) {
 737         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 738     }
 739
 740     return ret;
 741 }
 742
 743 static int kvm_put_fpu(CPUState *env)
 744 {
 745     struct kvm_fpu fpu;
 746     int i;
 747
 748     memset(&fpu, 0, sizeof fpu);
 749     fpu.fsw = env->fpus & ~(7 << 11);
 750     fpu.fsw |= (env->fpstt & 7) << 11;
 751     fpu.fcw = env->fpuc;
 752     fpu.last_opcode = env->fpop;
 753     fpu.last_ip = env->fpip;
 754     fpu.last_dp = env->fpdp;
 755     for (i = 0; i < 8; ++i) {
 756         fpu.ftwx |= (!env->fptags[i]) << i;
 757     }
 758     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 759     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 760     fpu.mxcsr = env->mxcsr;
 761
 762     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 763 }
 764
 765 #define XSAVE_FCW_FSW     0
 766 #define XSAVE_FTW_FOP     1
 767 #define XSAVE_CWD_RIP     2
 768 #define XSAVE_CWD_RDP     4
 769 #define XSAVE_MXCSR       6
 770 #define XSAVE_ST_SPACE    8
 771 #define XSAVE_XMM_SPACE   40
 772 #define XSAVE_XSTATE_BV   128
 773 #define XSAVE_YMMH_SPACE  144
 774
 775 static int kvm_put_xsave(CPUState *env)
 776 {
 777     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 778     uint16_t cwd, swd, twd;
 779     int i, r;
 780
 781     if (!kvm_has_xsave()) {
 782         return kvm_put_fpu(env);
 783     }
 784
 785     memset(xsave, 0, sizeof(struct kvm_xsave));
 786     twd = 0;
 787     swd = env->fpus & ~(7 << 11);
 788     swd |= (env->fpstt & 7) << 11;
 789     cwd = env->fpuc;
 790     for (i = 0; i < 8; ++i) {
 791         twd |= (!env->fptags[i]) << i;
 792     }
 793     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 794     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 795     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 796     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 797     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 798             sizeof env->fpregs);
 799     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 800             sizeof env->xmm_regs);
 801     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 802     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 803     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 804             sizeof env->ymmh_regs);
 805     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 806     return r;
 807 }
 808
 809 static int kvm_put_xcrs(CPUState *env)
 810 {
 811     struct kvm_xcrs xcrs;
 812
 813     if (!kvm_has_xcrs()) {
 814         return 0;
 815     }
 816
 817     xcrs.nr_xcrs = 1;
 818     xcrs.flags = 0;
 819     xcrs.xcrs[0].xcr = 0;
 820     xcrs.xcrs[0].value = env->xcr0;
 821     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 822 }
 823
 824 static int kvm_put_sregs(CPUState *env)
 825 {
 826     struct kvm_sregs sregs;
 827
 828     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 829     if (env->interrupt_injected >= 0) {
 830         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 831                 (uint64_t)1 << (env->interrupt_injected % 64);
 832     }
 833
 834     if ((env->eflags & VM_MASK)) {
 835         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 836         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 837         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 838         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 839         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 840         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 841     } else {
 842         set_seg(&sregs.cs, &env->segs[R_CS]);
 843         set_seg(&sregs.ds, &env->segs[R_DS]);
 844         set_seg(&sregs.es, &env->segs[R_ES]);
 845         set_seg(&sregs.fs, &env->segs[R_FS]);
 846         set_seg(&sregs.gs, &env->segs[R_GS]);
 847         set_seg(&sregs.ss, &env->segs[R_SS]);
 848     }
 849
 850     set_seg(&sregs.tr, &env->tr);
 851     set_seg(&sregs.ldt, &env->ldt);
 852
 853     sregs.idt.limit = env->idt.limit;
 854     sregs.idt.base = env->idt.base;
 855     sregs.gdt.limit = env->gdt.limit;
 856     sregs.gdt.base = env->gdt.base;
 857
 858     sregs.cr0 = env->cr[0];
 859     sregs.cr2 = env->cr[2];
 860     sregs.cr3 = env->cr[3];
 861     sregs.cr4 = env->cr[4];
 862
 863     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 864     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 865
 866     sregs.efer = env->efer;
 867
 868     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 869 }
 870
 871 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 872                               uint32_t index, uint64_t value)
 873 {
 874     entry->index = index;
 875     entry->data = value;
 876 }
 877
 878 static int kvm_put_msrs(CPUState *env, int level)
 879 {
 880     struct {
 881         struct kvm_msrs info;
 882         struct kvm_msr_entry entries[100];
 883     } msr_data;
 884     struct kvm_msr_entry *msrs = msr_data.entries;
 885     int n = 0;
 886
 887     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 888     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 889     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 890     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 891     if (has_msr_star) {
 892         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 893     }
 894     if (has_msr_hsave_pa) {
 895         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 896     }
 897     if (has_msr_tsc_deadline) {
 898         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
 899     }
 900     if (has_msr_misc_enable) {
 901         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
 902                           env->msr_ia32_misc_enable);
 903     }
 904 #ifdef TARGET_X86_64
 905     if (lm_capable_kernel) {
 906         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 907         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 908         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 909         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 910     }
 911 #endif
 912     if (level == KVM_PUT_FULL_STATE) {
 913         /*
 914          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 915          * writeback. Until this is fixed, we only write the offset to SMP
 916          * guests after migration, desynchronizing the VCPUs, but avoiding
 917          * huge jump-backs that would occur without any writeback at all.
 918          */
 919         if (smp_cpus == 1 || env->tsc != 0) {
 920             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 921         }
 922     }
 923     /*
 924      * The following paravirtual MSRs have side effects on the guest or are
 925      * too heavy for normal writeback. Limit them to reset or full state
 926      * updates.
 927      */
 928     if (level >= KVM_PUT_RESET_STATE) {
 929         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 930                           env->system_time_msr);
 931         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 932         if (has_msr_async_pf_en) {
 933             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
 934                               env->async_pf_en_msr);
 935         }
 936     }
 937     if (env->mcg_cap) {
 938         int i;
 939
 940         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 941         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 942         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 943             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 944         }
 945     }
 946
 947     msr_data.info.nmsrs = n;
 948
 949     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 950
 951 }
 952
 953
 954 static int kvm_get_fpu(CPUState *env)
 955 {
 956     struct kvm_fpu fpu;
 957     int i, ret;
 958
 959     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 960     if (ret < 0) {
 961         return ret;
 962     }
 963
 964     env->fpstt = (fpu.fsw >> 11) & 7;
 965     env->fpus = fpu.fsw;
 966     env->fpuc = fpu.fcw;
 967     env->fpop = fpu.last_opcode;
 968     env->fpip = fpu.last_ip;
 969     env->fpdp = fpu.last_dp;
 970     for (i = 0; i < 8; ++i) {
 971         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 972     }
 973     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 974     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 975     env->mxcsr = fpu.mxcsr;
 976
 977     return 0;
 978 }
 979
 980 static int kvm_get_xsave(CPUState *env)
 981 {
 982     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 983     int ret, i;
 984     uint16_t cwd, swd, twd;
 985
 986     if (!kvm_has_xsave()) {
 987         return kvm_get_fpu(env);
 988     }
 989
 990     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 991     if (ret < 0) {
 992         return ret;
 993     }
 994
 995     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
 996     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
 997     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
 998     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
 999     env->fpstt = (swd >> 11) & 7;
1000     env->fpus = swd;
1001     env->fpuc = cwd;
1002     for (i = 0; i < 8; ++i) {
1003         env->fptags[i] = !((twd >> i) & 1);
1004     }
1005     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1006     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1007     env->mxcsr = xsave->region[XSAVE_MXCSR];
1008     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1009             sizeof env->fpregs);
1010     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1011             sizeof env->xmm_regs);
1012     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1013     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1014             sizeof env->ymmh_regs);
1015     return 0;
1016 }
1017
1018 static int kvm_get_xcrs(CPUState *env)
1019 {
1020     int i, ret;
1021     struct kvm_xcrs xcrs;
1022
1023     if (!kvm_has_xcrs()) {
1024         return 0;
1025     }
1026
1027     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1028     if (ret < 0) {
1029         return ret;
1030     }
1031
1032     for (i = 0; i < xcrs.nr_xcrs; i++) {
1033         /* Only support xcr0 now */
1034         if (xcrs.xcrs[0].xcr == 0) {
1035             env->xcr0 = xcrs.xcrs[0].value;
1036             break;
1037         }
1038     }
1039     return 0;
1040 }
1041
1042 static int kvm_get_sregs(CPUState *env)
1043 {
1044     struct kvm_sregs sregs;
1045     uint32_t hflags;
1046     int bit, i, ret;
1047
1048     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1049     if (ret < 0) {
1050         return ret;
1051     }
1052
1053     /* There can only be one pending IRQ set in the bitmap at a time, so try
1054        to find it and save its number instead (-1 for none). */
1055     env->interrupt_injected = -1;
1056     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1057         if (sregs.interrupt_bitmap[i]) {
1058             bit = ctz64(sregs.interrupt_bitmap[i]);
1059             env->interrupt_injected = i * 64 + bit;
1060             break;
1061         }
1062     }
1063
1064     get_seg(&env->segs[R_CS], &sregs.cs);
1065     get_seg(&env->segs[R_DS], &sregs.ds);
1066     get_seg(&env->segs[R_ES], &sregs.es);
1067     get_seg(&env->segs[R_FS], &sregs.fs);
1068     get_seg(&env->segs[R_GS], &sregs.gs);
1069     get_seg(&env->segs[R_SS], &sregs.ss);
1070
1071     get_seg(&env->tr, &sregs.tr);
1072     get_seg(&env->ldt, &sregs.ldt);
1073
1074     env->idt.limit = sregs.idt.limit;
1075     env->idt.base = sregs.idt.base;
1076     env->gdt.limit = sregs.gdt.limit;
1077     env->gdt.base = sregs.gdt.base;
1078
1079     env->cr[0] = sregs.cr0;
1080     env->cr[2] = sregs.cr2;
1081     env->cr[3] = sregs.cr3;
1082     env->cr[4] = sregs.cr4;
1083
1084     env->efer = sregs.efer;
1085
1086     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1087
1088 #define HFLAG_COPY_MASK \
1089     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1090        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1091        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1092        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1093
1094     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1095     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1096     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1097                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1098     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1099     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1100                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1101
1102     if (env->efer & MSR_EFER_LMA) {
1103         hflags |= HF_LMA_MASK;
1104     }
1105
1106     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1107         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1108     } else {
1109         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1110                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1111         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1112                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1113         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1114             !(hflags & HF_CS32_MASK)) {
1115             hflags |= HF_ADDSEG_MASK;
1116         } else {
1117             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1118                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1119         }
1120     }
1121     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1122
1123     return 0;
1124 }
1125
1126 static int kvm_get_msrs(CPUState *env)
1127 {
1128     struct {
1129         struct kvm_msrs info;
1130         struct kvm_msr_entry entries[100];
1131     } msr_data;
1132     struct kvm_msr_entry *msrs = msr_data.entries;
1133     int ret, i, n;
1134
1135     n = 0;
1136     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1137     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1138     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1139     msrs[n++].index = MSR_PAT;
1140     if (has_msr_star) {
1141         msrs[n++].index = MSR_STAR;
1142     }
1143     if (has_msr_hsave_pa) {
1144         msrs[n++].index = MSR_VM_HSAVE_PA;
1145     }
1146     if (has_msr_tsc_deadline) {
1147         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1148     }
1149     if (has_msr_misc_enable) {
1150         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1151     }
1152
1153     if (!env->tsc_valid) {
1154         msrs[n++].index = MSR_IA32_TSC;
1155         env->tsc_valid = !runstate_is_running();
1156     }
1157
1158 #ifdef TARGET_X86_64
1159     if (lm_capable_kernel) {
1160         msrs[n++].index = MSR_CSTAR;
1161         msrs[n++].index = MSR_KERNELGSBASE;
1162         msrs[n++].index = MSR_FMASK;
1163         msrs[n++].index = MSR_LSTAR;
1164     }
1165 #endif
1166     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1167     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1168     if (has_msr_async_pf_en) {
1169         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1170     }
1171
1172     if (env->mcg_cap) {
1173         msrs[n++].index = MSR_MCG_STATUS;
1174         msrs[n++].index = MSR_MCG_CTL;
1175         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1176             msrs[n++].index = MSR_MC0_CTL + i;
1177         }
1178     }
1179
1180     msr_data.info.nmsrs = n;
1181     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1182     if (ret < 0) {
1183         return ret;
1184     }
1185
1186     for (i = 0; i < ret; i++) {
1187         switch (msrs[i].index) {
1188         case MSR_IA32_SYSENTER_CS:
1189             env->sysenter_cs = msrs[i].data;
1190             break;
1191         case MSR_IA32_SYSENTER_ESP:
1192             env->sysenter_esp = msrs[i].data;
1193             break;
1194         case MSR_IA32_SYSENTER_EIP:
1195             env->sysenter_eip = msrs[i].data;
1196             break;
1197         case MSR_PAT:
1198             env->pat = msrs[i].data;
1199             break;
1200         case MSR_STAR:
1201             env->star = msrs[i].data;
1202             break;
1203 #ifdef TARGET_X86_64
1204         case MSR_CSTAR:
1205             env->cstar = msrs[i].data;
1206             break;
1207         case MSR_KERNELGSBASE:
1208             env->kernelgsbase = msrs[i].data;
1209             break;
1210         case MSR_FMASK:
1211             env->fmask = msrs[i].data;
1212             break;
1213         case MSR_LSTAR:
1214             env->lstar = msrs[i].data;
1215             break;
1216 #endif
1217         case MSR_IA32_TSC:
1218             env->tsc = msrs[i].data;
1219             break;
1220         case MSR_IA32_TSCDEADLINE:
1221             env->tsc_deadline = msrs[i].data;
1222             break;
1223         case MSR_VM_HSAVE_PA:
1224             env->vm_hsave = msrs[i].data;
1225             break;
1226         case MSR_KVM_SYSTEM_TIME:
1227             env->system_time_msr = msrs[i].data;
1228             break;
1229         case MSR_KVM_WALL_CLOCK:
1230             env->wall_clock_msr = msrs[i].data;
1231             break;
1232         case MSR_MCG_STATUS:
1233             env->mcg_status = msrs[i].data;
1234             break;
1235         case MSR_MCG_CTL:
1236             env->mcg_ctl = msrs[i].data;
1237             break;
1238         case MSR_IA32_MISC_ENABLE:
1239             env->msr_ia32_misc_enable = msrs[i].data;
1240             break;
1241         default:
1242             if (msrs[i].index >= MSR_MC0_CTL &&
1243                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1244                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1245             }
1246             break;
1247         case MSR_KVM_ASYNC_PF_EN:
1248             env->async_pf_en_msr = msrs[i].data;
1249             break;
1250         }
1251     }
1252
1253     return 0;
1254 }
1255
1256 static int kvm_put_mp_state(CPUState *env)
1257 {
1258     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1259
1260     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1261 }
1262
1263 static int kvm_get_mp_state(CPUState *env)
1264 {
1265     struct kvm_mp_state mp_state;
1266     int ret;
1267
1268     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1269     if (ret < 0) {
1270         return ret;
1271     }
1272     env->mp_state = mp_state.mp_state;
1273     if (kvm_irqchip_in_kernel()) {
1274         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1275     }
1276     return 0;
1277 }
1278
1279 static int kvm_put_vcpu_events(CPUState *env, int level)
1280 {
1281     struct kvm_vcpu_events events;
1282
1283     if (!kvm_has_vcpu_events()) {
1284         return 0;
1285     }
1286
1287     events.exception.injected = (env->exception_injected >= 0);
1288     events.exception.nr = env->exception_injected;
1289     events.exception.has_error_code = env->has_error_code;
1290     events.exception.error_code = env->error_code;
1291
1292     events.interrupt.injected = (env->interrupt_injected >= 0);
1293     events.interrupt.nr = env->interrupt_injected;
1294     events.interrupt.soft = env->soft_interrupt;
1295
1296     events.nmi.injected = env->nmi_injected;
1297     events.nmi.pending = env->nmi_pending;
1298     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1299
1300     events.sipi_vector = env->sipi_vector;
1301
1302     events.flags = 0;
1303     if (level >= KVM_PUT_RESET_STATE) {
1304         events.flags |=
1305             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1306     }
1307
1308     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1309 }
1310
1311 static int kvm_get_vcpu_events(CPUState *env)
1312 {
1313     struct kvm_vcpu_events events;
1314     int ret;
1315
1316     if (!kvm_has_vcpu_events()) {
1317         return 0;
1318     }
1319
1320     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1321     if (ret < 0) {
1322        return ret;
1323     }
1324     env->exception_injected =
1325        events.exception.injected ? events.exception.nr : -1;
1326     env->has_error_code = events.exception.has_error_code;
1327     env->error_code = events.exception.error_code;
1328
1329     env->interrupt_injected =
1330         events.interrupt.injected ? events.interrupt.nr : -1;
1331     env->soft_interrupt = events.interrupt.soft;
1332
1333     env->nmi_injected = events.nmi.injected;
1334     env->nmi_pending = events.nmi.pending;
1335     if (events.nmi.masked) {
1336         env->hflags2 |= HF2_NMI_MASK;
1337     } else {
1338         env->hflags2 &= ~HF2_NMI_MASK;
1339     }
1340
1341     env->sipi_vector = events.sipi_vector;
1342
1343     return 0;
1344 }
1345
1346 static int kvm_guest_debug_workarounds(CPUState *env)
1347 {
1348     int ret = 0;
1349     unsigned long reinject_trap = 0;
1350
1351     if (!kvm_has_vcpu_events()) {
1352         if (env->exception_injected == 1) {
1353             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1354         } else if (env->exception_injected == 3) {
1355             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1356         }
1357         env->exception_injected = -1;
1358     }
1359
1360     /*
1361      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1362      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1363      * by updating the debug state once again if single-stepping is on.
1364      * Another reason to call kvm_update_guest_debug here is a pending debug
1365      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1366      * reinject them via SET_GUEST_DEBUG.
1367      */
1368     if (reinject_trap ||
1369         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1370         ret = kvm_update_guest_debug(env, reinject_trap);
1371     }
1372     return ret;
1373 }
1374
1375 static int kvm_put_debugregs(CPUState *env)
1376 {
1377     struct kvm_debugregs dbgregs;
1378     int i;
1379
1380     if (!kvm_has_debugregs()) {
1381         return 0;
1382     }
1383
1384     for (i = 0; i < 4; i++) {
1385         dbgregs.db[i] = env->dr[i];
1386     }
1387     dbgregs.dr6 = env->dr[6];
1388     dbgregs.dr7 = env->dr[7];
1389     dbgregs.flags = 0;
1390
1391     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1392 }
1393
1394 static int kvm_get_debugregs(CPUState *env)
1395 {
1396     struct kvm_debugregs dbgregs;
1397     int i, ret;
1398
1399     if (!kvm_has_debugregs()) {
1400         return 0;
1401     }
1402
1403     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1404     if (ret < 0) {
1405         return ret;
1406     }
1407     for (i = 0; i < 4; i++) {
1408         env->dr[i] = dbgregs.db[i];
1409     }
1410     env->dr[4] = env->dr[6] = dbgregs.dr6;
1411     env->dr[5] = env->dr[7] = dbgregs.dr7;
1412
1413     return 0;
1414 }
1415
1416 int kvm_arch_put_registers(CPUState *env, int level)
1417 {
1418     int ret;
1419
1420     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1421
1422     ret = kvm_getput_regs(env, 1);
1423     if (ret < 0) {
1424         return ret;
1425     }
1426     ret = kvm_put_xsave(env);
1427     if (ret < 0) {
1428         return ret;
1429     }
1430     ret = kvm_put_xcrs(env);
1431     if (ret < 0) {
1432         return ret;
1433     }
1434     ret = kvm_put_sregs(env);
1435     if (ret < 0) {
1436         return ret;
1437     }
1438     /* must be before kvm_put_msrs */
1439     ret = kvm_inject_mce_oldstyle(env);
1440     if (ret < 0) {
1441         return ret;
1442     }
1443     ret = kvm_put_msrs(env, level);
1444     if (ret < 0) {
1445         return ret;
1446     }
1447     if (level >= KVM_PUT_RESET_STATE) {
1448         ret = kvm_put_mp_state(env);
1449         if (ret < 0) {
1450             return ret;
1451         }
1452     }
1453     ret = kvm_put_vcpu_events(env, level);
1454     if (ret < 0) {
1455         return ret;
1456     }
1457     ret = kvm_put_debugregs(env);
1458     if (ret < 0) {
1459         return ret;
1460     }
1461     /* must be last */
1462     ret = kvm_guest_debug_workarounds(env);
1463     if (ret < 0) {
1464         return ret;
1465     }
1466     return 0;
1467 }
1468
1469 int kvm_arch_get_registers(CPUState *env)
1470 {
1471     int ret;
1472
1473     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1474
1475     ret = kvm_getput_regs(env, 0);
1476     if (ret < 0) {
1477         return ret;
1478     }
1479     ret = kvm_get_xsave(env);
1480     if (ret < 0) {
1481         return ret;
1482     }
1483     ret = kvm_get_xcrs(env);
1484     if (ret < 0) {
1485         return ret;
1486     }
1487     ret = kvm_get_sregs(env);
1488     if (ret < 0) {
1489         return ret;
1490     }
1491     ret = kvm_get_msrs(env);
1492     if (ret < 0) {
1493         return ret;
1494     }
1495     ret = kvm_get_mp_state(env);
1496     if (ret < 0) {
1497         return ret;
1498     }
1499     ret = kvm_get_vcpu_events(env);
1500     if (ret < 0) {
1501         return ret;
1502     }
1503     ret = kvm_get_debugregs(env);
1504     if (ret < 0) {
1505         return ret;
1506     }
1507     return 0;
1508 }
1509
1510 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1511 {
1512     int ret;
1513
1514     /* Inject NMI */
1515     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1516         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1517         DPRINTF("injected NMI\n");
1518         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1519         if (ret < 0) {
1520             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1521                     strerror(-ret));
1522         }
1523     }
1524
1525     if (!kvm_irqchip_in_kernel()) {
1526         /* Force the VCPU out of its inner loop to process the INIT request */
1527         if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1528             env->exit_request = 1;
1529         }
1530
1531         /* Try to inject an interrupt if the guest can accept it */
1532         if (run->ready_for_interrupt_injection &&
1533             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1534             (env->eflags & IF_MASK)) {
1535             int irq;
1536
1537             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1538             irq = cpu_get_pic_interrupt(env);
1539             if (irq >= 0) {
1540                 struct kvm_interrupt intr;
1541
1542                 intr.irq = irq;
1543                 DPRINTF("injected interrupt %d\n", irq);
1544                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1545                 if (ret < 0) {
1546                     fprintf(stderr,
1547                             "KVM: injection failed, interrupt lost (%s)\n",
1548                             strerror(-ret));
1549                 }
1550             }
1551         }
1552
1553         /* If we have an interrupt but the guest is not ready to receive an
1554          * interrupt, request an interrupt window exit.  This will
1555          * cause a return to userspace as soon as the guest is ready to
1556          * receive interrupts. */
1557         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1558             run->request_interrupt_window = 1;
1559         } else {
1560             run->request_interrupt_window = 0;
1561         }
1562
1563         DPRINTF("setting tpr\n");
1564         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1565     }
1566 }
1567
1568 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1569 {
1570     if (run->if_flag) {
1571         env->eflags |= IF_MASK;
1572     } else {
1573         env->eflags &= ~IF_MASK;
1574     }
1575     cpu_set_apic_tpr(env->apic_state, run->cr8);
1576     cpu_set_apic_base(env->apic_state, run->apic_base);
1577 }
1578
1579 int kvm_arch_process_async_events(CPUState *env)
1580 {
1581     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1582         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1583         assert(env->mcg_cap);
1584
1585         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1586
1587         kvm_cpu_synchronize_state(env);
1588
1589         if (env->exception_injected == EXCP08_DBLE) {
1590             /* this means triple fault */
1591             qemu_system_reset_request();
1592             env->exit_request = 1;
1593             return 0;
1594         }
1595         env->exception_injected = EXCP12_MCHK;
1596         env->has_error_code = 0;
1597
1598         env->halted = 0;
1599         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1600             env->mp_state = KVM_MP_STATE_RUNNABLE;
1601         }
1602     }
1603
1604     if (kvm_irqchip_in_kernel()) {
1605         return 0;
1606     }
1607
1608     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1609          (env->eflags & IF_MASK)) ||
1610         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1611         env->halted = 0;
1612     }
1613     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1614         kvm_cpu_synchronize_state(env);
1615         do_cpu_init(env);
1616     }
1617     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1618         kvm_cpu_synchronize_state(env);
1619         do_cpu_sipi(env);
1620     }
1621
1622     return env->halted;
1623 }
1624
1625 static int kvm_handle_halt(CPUState *env)
1626 {
1627     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1628           (env->eflags & IF_MASK)) &&
1629         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1630         env->halted = 1;
1631         return EXCP_HLT;
1632     }
1633
1634     return 0;
1635 }
1636
1637 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1638 {
1639     static const uint8_t int3 = 0xcc;
1640
1641     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1642         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1643         return -EINVAL;
1644     }
1645     return 0;
1646 }
1647
1648 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1649 {
1650     uint8_t int3;
1651
1652     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1653         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1654         return -EINVAL;
1655     }
1656     return 0;
1657 }
1658
1659 static struct {
1660     target_ulong addr;
1661     int len;
1662     int type;
1663 } hw_breakpoint[4];
1664
1665 static int nb_hw_breakpoint;
1666
1667 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1668 {
1669     int n;
1670
1671     for (n = 0; n < nb_hw_breakpoint; n++) {
1672         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1673             (hw_breakpoint[n].len == len || len == -1)) {
1674             return n;
1675         }
1676     }
1677     return -1;
1678 }
1679
1680 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1681                                   target_ulong len, int type)
1682 {
1683     switch (type) {
1684     case GDB_BREAKPOINT_HW:
1685         len = 1;
1686         break;
1687     case GDB_WATCHPOINT_WRITE:
1688     case GDB_WATCHPOINT_ACCESS:
1689         switch (len) {
1690         case 1:
1691             break;
1692         case 2:
1693         case 4:
1694         case 8:
1695             if (addr & (len - 1)) {
1696                 return -EINVAL;
1697             }
1698             break;
1699         default:
1700             return -EINVAL;
1701         }
1702         break;
1703     default:
1704         return -ENOSYS;
1705     }
1706
1707     if (nb_hw_breakpoint == 4) {
1708         return -ENOBUFS;
1709     }
1710     if (find_hw_breakpoint(addr, len, type) >= 0) {
1711         return -EEXIST;
1712     }
1713     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1714     hw_breakpoint[nb_hw_breakpoint].len = len;
1715     hw_breakpoint[nb_hw_breakpoint].type = type;
1716     nb_hw_breakpoint++;
1717
1718     return 0;
1719 }
1720
1721 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1722                                   target_ulong len, int type)
1723 {
1724     int n;
1725
1726     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1727     if (n < 0) {
1728         return -ENOENT;
1729     }
1730     nb_hw_breakpoint--;
1731     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1732
1733     return 0;
1734 }
1735
1736 void kvm_arch_remove_all_hw_breakpoints(void)
1737 {
1738     nb_hw_breakpoint = 0;
1739 }
1740
1741 static CPUWatchpoint hw_watchpoint;
1742
1743 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1744 {
1745     int ret = 0;
1746     int n;
1747
1748     if (arch_info->exception == 1) {
1749         if (arch_info->dr6 & (1 << 14)) {
1750             if (cpu_single_env->singlestep_enabled) {
1751                 ret = EXCP_DEBUG;
1752             }
1753         } else {
1754             for (n = 0; n < 4; n++) {
1755                 if (arch_info->dr6 & (1 << n)) {
1756                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1757                     case 0x0:
1758                         ret = EXCP_DEBUG;
1759                         break;
1760                     case 0x1:
1761                         ret = EXCP_DEBUG;
1762                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1763                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1764                         hw_watchpoint.flags = BP_MEM_WRITE;
1765                         break;
1766                     case 0x3:
1767                         ret = EXCP_DEBUG;
1768                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1769                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1770                         hw_watchpoint.flags = BP_MEM_ACCESS;
1771                         break;
1772                     }
1773                 }
1774             }
1775         }
1776     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1777         ret = EXCP_DEBUG;
1778     }
1779     if (ret == 0) {
1780         cpu_synchronize_state(cpu_single_env);
1781         assert(cpu_single_env->exception_injected == -1);
1782
1783         /* pass to guest */
1784         cpu_single_env->exception_injected = arch_info->exception;
1785         cpu_single_env->has_error_code = 0;
1786     }
1787
1788     return ret;
1789 }
1790
1791 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1792 {
1793     const uint8_t type_code[] = {
1794         [GDB_BREAKPOINT_HW] = 0x0,
1795         [GDB_WATCHPOINT_WRITE] = 0x1,
1796         [GDB_WATCHPOINT_ACCESS] = 0x3
1797     };
1798     const uint8_t len_code[] = {
1799         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1800     };
1801     int n;
1802
1803     if (kvm_sw_breakpoints_active(env)) {
1804         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1805     }
1806     if (nb_hw_breakpoint > 0) {
1807         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1808         dbg->arch.debugreg[7] = 0x0600;
1809         for (n = 0; n < nb_hw_breakpoint; n++) {
1810             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1811             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1812                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1813                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1814         }
1815     }
1816 }
1817
1818 static bool host_supports_vmx(void)
1819 {
1820     uint32_t ecx, unused;
1821
1822     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1823     return ecx & CPUID_EXT_VMX;
1824 }
1825
1826 #define VMX_INVALID_GUEST_STATE 0x80000021
1827
1828 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1829 {
1830     uint64_t code;
1831     int ret;
1832
1833     switch (run->exit_reason) {
1834     case KVM_EXIT_HLT:
1835         DPRINTF("handle_hlt\n");
1836         ret = kvm_handle_halt(env);
1837         break;
1838     case KVM_EXIT_SET_TPR:
1839         ret = 0;
1840         break;
1841     case KVM_EXIT_FAIL_ENTRY:
1842         code = run->fail_entry.hardware_entry_failure_reason;
1843         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1844                 code);
1845         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1846             fprintf(stderr,
1847                     "\nIf you're running a guest on an Intel machine without "
1848                         "unrestricted mode\n"
1849                     "support, the failure can be most likely due to the guest "
1850                         "entering an invalid\n"
1851                     "state for Intel VT. For example, the guest maybe running "
1852                         "in big real mode\n"
1853                     "which is not supported on less recent Intel processors."
1854                         "\n\n");
1855         }
1856         ret = -1;
1857         break;
1858     case KVM_EXIT_EXCEPTION:
1859         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1860                 run->ex.exception, run->ex.error_code);
1861         ret = -1;
1862         break;
1863     case KVM_EXIT_DEBUG:
1864         DPRINTF("kvm_exit_debug\n");
1865         ret = kvm_handle_debug(&run->debug.arch);
1866         break;
1867     default:
1868         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1869         ret = -1;
1870         break;
1871     }
1872
1873     return ret;
1874 }
1875
1876 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1877 {
1878     return !(env->cr[0] & CR0_PE_MASK) ||
1879            ((env->segs[R_CS].selector  & 3) != 3);
1880 }