4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
19 #include <linux/kvm.h>
21 #include "qemu-common.h"
29 #define dprintf(fmt, ...) \
30 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
32 #define dprintf(fmt, ...) \
36 int kvm_arch_init_vcpu(CPUState
*env
)
39 struct kvm_cpuid cpuid
;
40 struct kvm_cpuid_entry entries
[100];
41 } __attribute__((packed
)) cpuid_data
;
42 uint32_t limit
, i
, cpuid_i
;
43 uint32_t eax
, ebx
, ecx
, edx
;
47 cpu_x86_cpuid(env
, 0, &eax
, &ebx
, &ecx
, &edx
);
50 for (i
= 0; i
<= limit
; i
++) {
51 struct kvm_cpuid_entry
*c
= &cpuid_data
.entries
[cpuid_i
++];
53 cpu_x86_cpuid(env
, i
, &eax
, &ebx
, &ecx
, &edx
);
61 cpu_x86_cpuid(env
, 0x80000000, &eax
, &ebx
, &ecx
, &edx
);
64 for (i
= 0x80000000; i
<= limit
; i
++) {
65 struct kvm_cpuid_entry
*c
= &cpuid_data
.entries
[cpuid_i
++];
67 cpu_x86_cpuid(env
, i
, &eax
, &ebx
, &ecx
, &edx
);
75 cpuid_data
.cpuid
.nent
= cpuid_i
;
77 return kvm_vcpu_ioctl(env
, KVM_SET_CPUID
, &cpuid_data
);
80 static int kvm_has_msr_star(CPUState
*env
)
82 static int has_msr_star
;
86 if (has_msr_star
== 0) {
87 struct kvm_msr_list msr_list
, *kvm_msr_list
;
91 /* Obtain MSR list from KVM. These are the MSRs that we must
94 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
98 kvm_msr_list
= qemu_mallocz(sizeof(msr_list
) +
99 msr_list
.nmsrs
* sizeof(msr_list
.indices
[0]));
101 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
102 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
106 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
107 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
117 if (has_msr_star
== 1)
122 int kvm_arch_init(KVMState
*s
, int smp_cpus
)
126 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
127 * directly. In order to use vm86 mode, a TSS is needed. Since this
128 * must be part of guest physical memory, we need to allocate it. Older
129 * versions of KVM just assumed that it would be at the end of physical
130 * memory but that doesn't work with more than 4GB of memory. We simply
131 * refuse to work with those older versions of KVM. */
132 ret
= kvm_ioctl(s
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_TSS_ADDR
);
134 fprintf(stderr
, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
138 /* this address is 3 pages before the bios, and the bios should present
139 * as unavaible memory. FIXME, need to ensure the e820 map deals with
142 return kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, 0xfffbd000);
145 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
147 lhs
->selector
= rhs
->selector
;
148 lhs
->base
= rhs
->base
;
149 lhs
->limit
= rhs
->limit
;
161 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
163 unsigned flags
= rhs
->flags
;
164 lhs
->selector
= rhs
->selector
;
165 lhs
->base
= rhs
->base
;
166 lhs
->limit
= rhs
->limit
;
167 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
168 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
169 lhs
->dpl
= rhs
->selector
& 3;
170 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
171 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
172 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
173 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
174 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
178 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
180 lhs
->selector
= rhs
->selector
;
181 lhs
->base
= rhs
->base
;
182 lhs
->limit
= rhs
->limit
;
184 (rhs
->type
<< DESC_TYPE_SHIFT
)
185 | (rhs
->present
* DESC_P_MASK
)
186 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
187 | (rhs
->db
<< DESC_B_SHIFT
)
188 | (rhs
->s
* DESC_S_MASK
)
189 | (rhs
->l
<< DESC_L_SHIFT
)
190 | (rhs
->g
* DESC_G_MASK
)
191 | (rhs
->avl
* DESC_AVL_MASK
);
194 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
197 *kvm_reg
= *qemu_reg
;
199 *qemu_reg
= *kvm_reg
;
202 static int kvm_getput_regs(CPUState
*env
, int set
)
204 struct kvm_regs regs
;
208 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
213 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
214 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
215 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
216 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
217 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
218 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
219 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
220 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
222 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
223 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
224 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
225 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
226 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
227 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
228 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
229 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
232 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
233 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
236 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
241 static int kvm_put_fpu(CPUState
*env
)
246 memset(&fpu
, 0, sizeof fpu
);
247 fpu
.fsw
= env
->fpus
& ~(7 << 11);
248 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
250 for (i
= 0; i
< 8; ++i
)
251 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
252 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
253 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
254 fpu
.mxcsr
= env
->mxcsr
;
256 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
259 static int kvm_put_sregs(CPUState
*env
)
261 struct kvm_sregs sregs
;
263 memcpy(sregs
.interrupt_bitmap
,
264 env
->interrupt_bitmap
,
265 sizeof(sregs
.interrupt_bitmap
));
267 if ((env
->eflags
& VM_MASK
)) {
268 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
269 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
270 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
271 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
272 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
273 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
275 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
276 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
277 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
278 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
279 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
280 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
282 if (env
->cr
[0] & CR0_PE_MASK
) {
283 /* force ss cpl to cs cpl */
284 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
285 (sregs
.cs
.selector
& 3);
286 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
290 set_seg(&sregs
.tr
, &env
->tr
);
291 set_seg(&sregs
.ldt
, &env
->ldt
);
293 sregs
.idt
.limit
= env
->idt
.limit
;
294 sregs
.idt
.base
= env
->idt
.base
;
295 sregs
.gdt
.limit
= env
->gdt
.limit
;
296 sregs
.gdt
.base
= env
->gdt
.base
;
298 sregs
.cr0
= env
->cr
[0];
299 sregs
.cr2
= env
->cr
[2];
300 sregs
.cr3
= env
->cr
[3];
301 sregs
.cr4
= env
->cr
[4];
303 sregs
.cr8
= cpu_get_apic_tpr(env
);
304 sregs
.apic_base
= cpu_get_apic_base(env
);
306 sregs
.efer
= env
->efer
;
308 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
311 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
312 uint32_t index
, uint64_t value
)
314 entry
->index
= index
;
318 static int kvm_put_msrs(CPUState
*env
)
321 struct kvm_msrs info
;
322 struct kvm_msr_entry entries
[100];
324 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
327 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
328 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
329 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
330 if (kvm_has_msr_star(env
))
331 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
332 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
334 /* FIXME if lm capable */
335 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
336 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
337 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
338 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
340 msr_data
.info
.nmsrs
= n
;
342 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
347 static int kvm_get_fpu(CPUState
*env
)
352 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
356 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
359 for (i
= 0; i
< 8; ++i
)
360 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
361 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
362 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
363 env
->mxcsr
= fpu
.mxcsr
;
368 static int kvm_get_sregs(CPUState
*env
)
370 struct kvm_sregs sregs
;
374 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
378 memcpy(env
->interrupt_bitmap
,
379 sregs
.interrupt_bitmap
,
380 sizeof(sregs
.interrupt_bitmap
));
382 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
383 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
384 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
385 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
386 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
387 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
389 get_seg(&env
->tr
, &sregs
.tr
);
390 get_seg(&env
->ldt
, &sregs
.ldt
);
392 env
->idt
.limit
= sregs
.idt
.limit
;
393 env
->idt
.base
= sregs
.idt
.base
;
394 env
->gdt
.limit
= sregs
.gdt
.limit
;
395 env
->gdt
.base
= sregs
.gdt
.base
;
397 env
->cr
[0] = sregs
.cr0
;
398 env
->cr
[2] = sregs
.cr2
;
399 env
->cr
[3] = sregs
.cr3
;
400 env
->cr
[4] = sregs
.cr4
;
402 cpu_set_apic_base(env
, sregs
.apic_base
);
404 env
->efer
= sregs
.efer
;
405 //cpu_set_apic_tpr(env, sregs.cr8);
407 #define HFLAG_COPY_MASK ~( \
408 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
409 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
410 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
411 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
415 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
416 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
417 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
418 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
419 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
420 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
421 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
423 if (env
->efer
& MSR_EFER_LMA
) {
424 hflags
|= HF_LMA_MASK
;
427 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
428 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
430 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
431 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
432 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
433 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
434 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
435 (env
->eflags
& VM_MASK
) ||
436 !(hflags
& HF_CS32_MASK
)) {
437 hflags
|= HF_ADDSEG_MASK
;
439 hflags
|= ((env
->segs
[R_DS
].base
|
440 env
->segs
[R_ES
].base
|
441 env
->segs
[R_SS
].base
) != 0) <<
445 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
450 static int kvm_get_msrs(CPUState
*env
)
453 struct kvm_msrs info
;
454 struct kvm_msr_entry entries
[100];
456 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
460 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
461 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
462 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
463 if (kvm_has_msr_star(env
))
464 msrs
[n
++].index
= MSR_STAR
;
465 msrs
[n
++].index
= MSR_IA32_TSC
;
467 /* FIXME lm_capable_kernel */
468 msrs
[n
++].index
= MSR_CSTAR
;
469 msrs
[n
++].index
= MSR_KERNELGSBASE
;
470 msrs
[n
++].index
= MSR_FMASK
;
471 msrs
[n
++].index
= MSR_LSTAR
;
473 msr_data
.info
.nmsrs
= n
;
474 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
478 for (i
= 0; i
< ret
; i
++) {
479 switch (msrs
[i
].index
) {
480 case MSR_IA32_SYSENTER_CS
:
481 env
->sysenter_cs
= msrs
[i
].data
;
483 case MSR_IA32_SYSENTER_ESP
:
484 env
->sysenter_esp
= msrs
[i
].data
;
486 case MSR_IA32_SYSENTER_EIP
:
487 env
->sysenter_eip
= msrs
[i
].data
;
490 env
->star
= msrs
[i
].data
;
494 env
->cstar
= msrs
[i
].data
;
496 case MSR_KERNELGSBASE
:
497 env
->kernelgsbase
= msrs
[i
].data
;
500 env
->fmask
= msrs
[i
].data
;
503 env
->lstar
= msrs
[i
].data
;
507 env
->tsc
= msrs
[i
].data
;
515 int kvm_arch_put_registers(CPUState
*env
)
519 ret
= kvm_getput_regs(env
, 1);
523 ret
= kvm_put_fpu(env
);
527 ret
= kvm_put_sregs(env
);
531 ret
= kvm_put_msrs(env
);
538 int kvm_arch_get_registers(CPUState
*env
)
542 ret
= kvm_getput_regs(env
, 0);
546 ret
= kvm_get_fpu(env
);
550 ret
= kvm_get_sregs(env
);
554 ret
= kvm_get_msrs(env
);
561 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
563 /* Try to inject an interrupt if the guest can accept it */
564 if (run
->ready_for_interrupt_injection
&&
565 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
566 (env
->eflags
& IF_MASK
)) {
569 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
570 irq
= cpu_get_pic_interrupt(env
);
572 struct kvm_interrupt intr
;
575 dprintf("injected interrupt %d\n", irq
);
576 kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
580 /* If we have an interrupt but the guest is not ready to receive an
581 * interrupt, request an interrupt window exit. This will
582 * cause a return to userspace as soon as the guest is ready to
583 * receive interrupts. */
584 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
))
585 run
->request_interrupt_window
= 1;
587 run
->request_interrupt_window
= 0;
589 dprintf("setting tpr\n");
590 run
->cr8
= cpu_get_apic_tpr(env
);
595 int kvm_arch_post_run(CPUState
*env
, struct kvm_run
*run
)
598 env
->eflags
|= IF_MASK
;
600 env
->eflags
&= ~IF_MASK
;
602 cpu_set_apic_tpr(env
, run
->cr8
);
603 cpu_set_apic_base(env
, run
->apic_base
);
608 static int kvm_handle_halt(CPUState
*env
)
610 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
611 (env
->eflags
& IF_MASK
)) &&
612 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
614 env
->exception_index
= EXCP_HLT
;
621 int kvm_arch_handle_exit(CPUState
*env
, struct kvm_run
*run
)
625 switch (run
->exit_reason
) {
627 dprintf("handle_hlt\n");
628 ret
= kvm_handle_halt(env
);