target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu/sysemu.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "exec/gdbstub.h"
  29 #include "qemu/host-utils.h"
  30 #include "qemu/config-file.h"
  31 #include "hw/i386/pc.h"
  32 #include "hw/i386/apic.h"
  33 #include "exec/ioport.h"
  34 #include "hyperv.h"
  35 #include "hw/pci/pci.h"
  36
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  58     KVM_CAP_INFO(SET_TSS_ADDR),
  59     KVM_CAP_INFO(EXT_CPUID),
  60     KVM_CAP_INFO(MP_STATE),
  61     KVM_CAP_LAST_INFO
  62 };
  63
  64 static bool has_msr_star;
  65 static bool has_msr_hsave_pa;
  66 static bool has_msr_tsc_adjust;
  67 static bool has_msr_tsc_deadline;
  68 static bool has_msr_async_pf_en;
  69 static bool has_msr_pv_eoi_en;
  70 static bool has_msr_misc_enable;
  71 static bool has_msr_kvm_steal_time;
  72 static int lm_capable_kernel;
  73
  74 static bool has_msr_architectural_pmu;
  75 static uint32_t num_architectural_pmu_counters;
  76
  77 bool kvm_allows_irq0_override(void)
  78 {
  79     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  80 }
  81
  82 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  83 {
  84     struct kvm_cpuid2 *cpuid;
  85     int r, size;
  86
  87     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  88     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  89     cpuid->nent = max;
  90     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  91     if (r == 0 && cpuid->nent >= max) {
  92         r = -E2BIG;
  93     }
  94     if (r < 0) {
  95         if (r == -E2BIG) {
  96             g_free(cpuid);
  97             return NULL;
  98         } else {
  99             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
 100                     strerror(-r));
 101             exit(1);
 102         }
 103     }
 104     return cpuid;
 105 }
 106
 107 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 108  * for all entries.
 109  */
 110 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 111 {
 112     struct kvm_cpuid2 *cpuid;
 113     int max = 1;
 114     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 115         max *= 2;
 116     }
 117     return cpuid;
 118 }
 119
 120 struct kvm_para_features {
 121     int cap;
 122     int feature;
 123 } para_features[] = {
 124     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 125     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 126     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 127     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 128     { -1, -1 }
 129 };
 130
 131 static int get_para_features(KVMState *s)
 132 {
 133     int i, features = 0;
 134
 135     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 136         if (kvm_check_extension(s, para_features[i].cap)) {
 137             features |= (1 << para_features[i].feature);
 138         }
 139     }
 140
 141     return features;
 142 }
 143
 144
 145 /* Returns the value for a specific register on the cpuid entry
 146  */
 147 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 148 {
 149     uint32_t ret = 0;
 150     switch (reg) {
 151     case R_EAX:
 152         ret = entry->eax;
 153         break;
 154     case R_EBX:
 155         ret = entry->ebx;
 156         break;
 157     case R_ECX:
 158         ret = entry->ecx;
 159         break;
 160     case R_EDX:
 161         ret = entry->edx;
 162         break;
 163     }
 164     return ret;
 165 }
 166
 167 /* Find matching entry for function/index on kvm_cpuid2 struct
 168  */
 169 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 170                                                  uint32_t function,
 171                                                  uint32_t index)
 172 {
 173     int i;
 174     for (i = 0; i < cpuid->nent; ++i) {
 175         if (cpuid->entries[i].function == function &&
 176             cpuid->entries[i].index == index) {
 177             return &cpuid->entries[i];
 178         }
 179     }
 180     /* not found: */
 181     return NULL;
 182 }
 183
 184 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 185                                       uint32_t index, int reg)
 186 {
 187     struct kvm_cpuid2 *cpuid;
 188     uint32_t ret = 0;
 189     uint32_t cpuid_1_edx;
 190     bool found = false;
 191
 192     cpuid = get_supported_cpuid(s);
 193
 194     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 195     if (entry) {
 196         found = true;
 197         ret = cpuid_entry_get_reg(entry, reg);
 198     }
 199
 200     /* Fixups for the data returned by KVM, below */
 201
 202     if (function == 1 && reg == R_EDX) {
 203         /* KVM before 2.6.30 misreports the following features */
 204         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 205     } else if (function == 1 && reg == R_ECX) {
 206         /* We can set the hypervisor flag, even if KVM does not return it on
 207          * GET_SUPPORTED_CPUID
 208          */
 209         ret |= CPUID_EXT_HYPERVISOR;
 210         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 211          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 212          * and the irqchip is in the kernel.
 213          */
 214         if (kvm_irqchip_in_kernel() &&
 215                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 216             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 217         }
 218
 219         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 220          * without the in-kernel irqchip
 221          */
 222         if (!kvm_irqchip_in_kernel()) {
 223             ret &= ~CPUID_EXT_X2APIC;
 224         }
 225     } else if (function == 0x80000001 && reg == R_EDX) {
 226         /* On Intel, kvm returns cpuid according to the Intel spec,
 227          * so add missing bits according to the AMD spec:
 228          */
 229         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 230         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 231     }
 232
 233     g_free(cpuid);
 234
 235     /* fallback for older kernels */
 236     if ((function == KVM_CPUID_FEATURES) && !found) {
 237         ret = get_para_features(s);
 238     }
 239
 240     return ret;
 241 }
 242
 243 typedef struct HWPoisonPage {
 244     ram_addr_t ram_addr;
 245     QLIST_ENTRY(HWPoisonPage) list;
 246 } HWPoisonPage;
 247
 248 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 249     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 250
 251 static void kvm_unpoison_all(void *param)
 252 {
 253     HWPoisonPage *page, *next_page;
 254
 255     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 256         QLIST_REMOVE(page, list);
 257         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 258         g_free(page);
 259     }
 260 }
 261
 262 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 263 {
 264     HWPoisonPage *page;
 265
 266     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 267         if (page->ram_addr == ram_addr) {
 268             return;
 269         }
 270     }
 271     page = g_malloc(sizeof(HWPoisonPage));
 272     page->ram_addr = ram_addr;
 273     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 274 }
 275
 276 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 277                                      int *max_banks)
 278 {
 279     int r;
 280
 281     r = kvm_check_extension(s, KVM_CAP_MCE);
 282     if (r > 0) {
 283         *max_banks = r;
 284         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 285     }
 286     return -ENOSYS;
 287 }
 288
 289 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 290 {
 291     CPUX86State *env = &cpu->env;
 292     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 293                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 294     uint64_t mcg_status = MCG_STATUS_MCIP;
 295
 296     if (code == BUS_MCEERR_AR) {
 297         status |= MCI_STATUS_AR | 0x134;
 298         mcg_status |= MCG_STATUS_EIPV;
 299     } else {
 300         status |= 0xc0;
 301         mcg_status |= MCG_STATUS_RIPV;
 302     }
 303     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 304                        (MCM_ADDR_PHYS << 6) | 0xc,
 305                        cpu_x86_support_mca_broadcast(env) ?
 306                        MCE_INJECT_BROADCAST : 0);
 307 }
 308
 309 static void hardware_memory_error(void)
 310 {
 311     fprintf(stderr, "Hardware memory error!\n");
 312     exit(1);
 313 }
 314
 315 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 316 {
 317     X86CPU *cpu = X86_CPU(c);
 318     CPUX86State *env = &cpu->env;
 319     ram_addr_t ram_addr;
 320     hwaddr paddr;
 321
 322     if ((env->mcg_cap & MCG_SER_P) && addr
 323         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 324         if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
 325             !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 326             fprintf(stderr, "Hardware memory error for memory used by "
 327                     "QEMU itself instead of guest system!\n");
 328             /* Hope we are lucky for AO MCE */
 329             if (code == BUS_MCEERR_AO) {
 330                 return 0;
 331             } else {
 332                 hardware_memory_error();
 333             }
 334         }
 335         kvm_hwpoison_page_add(ram_addr);
 336         kvm_mce_inject(cpu, paddr, code);
 337     } else {
 338         if (code == BUS_MCEERR_AO) {
 339             return 0;
 340         } else if (code == BUS_MCEERR_AR) {
 341             hardware_memory_error();
 342         } else {
 343             return 1;
 344         }
 345     }
 346     return 0;
 347 }
 348
 349 int kvm_arch_on_sigbus(int code, void *addr)
 350 {
 351     X86CPU *cpu = X86_CPU(first_cpu);
 352
 353     if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 354         ram_addr_t ram_addr;
 355         hwaddr paddr;
 356
 357         /* Hope we are lucky for AO MCE */
 358         if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
 359             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
 360                                                 addr, &paddr)) {
 361             fprintf(stderr, "Hardware memory error for memory used by "
 362                     "QEMU itself instead of guest system!: %p\n", addr);
 363             return 0;
 364         }
 365         kvm_hwpoison_page_add(ram_addr);
 366         kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
 367     } else {
 368         if (code == BUS_MCEERR_AO) {
 369             return 0;
 370         } else if (code == BUS_MCEERR_AR) {
 371             hardware_memory_error();
 372         } else {
 373             return 1;
 374         }
 375     }
 376     return 0;
 377 }
 378
 379 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 380 {
 381     CPUX86State *env = &cpu->env;
 382
 383     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 384         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 385         struct kvm_x86_mce mce;
 386
 387         env->exception_injected = -1;
 388
 389         /*
 390          * There must be at least one bank in use if an MCE is pending.
 391          * Find it and use its values for the event injection.
 392          */
 393         for (bank = 0; bank < bank_num; bank++) {
 394             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 395                 break;
 396             }
 397         }
 398         assert(bank < bank_num);
 399
 400         mce.bank = bank;
 401         mce.status = env->mce_banks[bank * 4 + 1];
 402         mce.mcg_status = env->mcg_status;
 403         mce.addr = env->mce_banks[bank * 4 + 2];
 404         mce.misc = env->mce_banks[bank * 4 + 3];
 405
 406         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 407     }
 408     return 0;
 409 }
 410
 411 static void cpu_update_state(void *opaque, int running, RunState state)
 412 {
 413     CPUX86State *env = opaque;
 414
 415     if (running) {
 416         env->tsc_valid = false;
 417     }
 418 }
 419
 420 unsigned long kvm_arch_vcpu_id(CPUState *cs)
 421 {
 422     X86CPU *cpu = X86_CPU(cs);
 423     return cpu->env.cpuid_apic_id;
 424 }
 425
 426 #define KVM_MAX_CPUID_ENTRIES  100
 427
 428 int kvm_arch_init_vcpu(CPUState *cs)
 429 {
 430     struct {
 431         struct kvm_cpuid2 cpuid;
 432         struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
 433     } QEMU_PACKED cpuid_data;
 434     X86CPU *cpu = X86_CPU(cs);
 435     CPUX86State *env = &cpu->env;
 436     uint32_t limit, i, j, cpuid_i;
 437     uint32_t unused;
 438     struct kvm_cpuid_entry2 *c;
 439     uint32_t signature[3];
 440     int r;
 441
 442     cpuid_i = 0;
 443
 444     /* Paravirtualization CPUIDs */
 445     c = &cpuid_data.entries[cpuid_i++];
 446     memset(c, 0, sizeof(*c));
 447     c->function = KVM_CPUID_SIGNATURE;
 448     if (!hyperv_enabled()) {
 449         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 450         c->eax = 0;
 451     } else {
 452         memcpy(signature, "Microsoft Hv", 12);
 453         c->eax = HYPERV_CPUID_MIN;
 454     }
 455     c->ebx = signature[0];
 456     c->ecx = signature[1];
 457     c->edx = signature[2];
 458
 459     c = &cpuid_data.entries[cpuid_i++];
 460     memset(c, 0, sizeof(*c));
 461     c->function = KVM_CPUID_FEATURES;
 462     c->eax = env->features[FEAT_KVM];
 463
 464     if (hyperv_enabled()) {
 465         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 466         c->eax = signature[0];
 467
 468         c = &cpuid_data.entries[cpuid_i++];
 469         memset(c, 0, sizeof(*c));
 470         c->function = HYPERV_CPUID_VERSION;
 471         c->eax = 0x00001bbc;
 472         c->ebx = 0x00060001;
 473
 474         c = &cpuid_data.entries[cpuid_i++];
 475         memset(c, 0, sizeof(*c));
 476         c->function = HYPERV_CPUID_FEATURES;
 477         if (hyperv_relaxed_timing_enabled()) {
 478             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 479         }
 480         if (hyperv_vapic_recommended()) {
 481             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 482             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 483         }
 484
 485         c = &cpuid_data.entries[cpuid_i++];
 486         memset(c, 0, sizeof(*c));
 487         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 488         if (hyperv_relaxed_timing_enabled()) {
 489             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 490         }
 491         if (hyperv_vapic_recommended()) {
 492             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 493         }
 494         c->ebx = hyperv_get_spinlock_retries();
 495
 496         c = &cpuid_data.entries[cpuid_i++];
 497         memset(c, 0, sizeof(*c));
 498         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 499         c->eax = 0x40;
 500         c->ebx = 0x40;
 501
 502         c = &cpuid_data.entries[cpuid_i++];
 503         memset(c, 0, sizeof(*c));
 504         c->function = KVM_CPUID_SIGNATURE_NEXT;
 505         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 506         c->eax = 0;
 507         c->ebx = signature[0];
 508         c->ecx = signature[1];
 509         c->edx = signature[2];
 510     }
 511
 512     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 513
 514     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 515
 516     has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
 517
 518     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 519
 520     for (i = 0; i <= limit; i++) {
 521         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 522             fprintf(stderr, "unsupported level value: 0x%x\n", limit);
 523             abort();
 524         }
 525         c = &cpuid_data.entries[cpuid_i++];
 526
 527         switch (i) {
 528         case 2: {
 529             /* Keep reading function 2 till all the input is received */
 530             int times;
 531
 532             c->function = i;
 533             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 534                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 535             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 536             times = c->eax & 0xff;
 537
 538             for (j = 1; j < times; ++j) {
 539                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 540                     fprintf(stderr, "cpuid_data is full, no space for "
 541                             "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
 542                     abort();
 543                 }
 544                 c = &cpuid_data.entries[cpuid_i++];
 545                 c->function = i;
 546                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 547                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 548             }
 549             break;
 550         }
 551         case 4:
 552         case 0xb:
 553         case 0xd:
 554             for (j = 0; ; j++) {
 555                 if (i == 0xd && j == 64) {
 556                     break;
 557                 }
 558                 c->function = i;
 559                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 560                 c->index = j;
 561                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 562
 563                 if (i == 4 && c->eax == 0) {
 564                     break;
 565                 }
 566                 if (i == 0xb && !(c->ecx & 0xff00)) {
 567                     break;
 568                 }
 569                 if (i == 0xd && c->eax == 0) {
 570                     continue;
 571                 }
 572                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 573                     fprintf(stderr, "cpuid_data is full, no space for "
 574                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
 575                     abort();
 576                 }
 577                 c = &cpuid_data.entries[cpuid_i++];
 578             }
 579             break;
 580         default:
 581             c->function = i;
 582             c->flags = 0;
 583             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 584             break;
 585         }
 586     }
 587
 588     if (limit >= 0x0a) {
 589         uint32_t ver;
 590
 591         cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
 592         if ((ver & 0xff) > 0) {
 593             has_msr_architectural_pmu = true;
 594             num_architectural_pmu_counters = (ver & 0xff00) >> 8;
 595
 596             /* Shouldn't be more than 32, since that's the number of bits
 597              * available in EBX to tell us _which_ counters are available.
 598              * Play it safe.
 599              */
 600             if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
 601                 num_architectural_pmu_counters = MAX_GP_COUNTERS;
 602             }
 603         }
 604     }
 605
 606     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 607
 608     for (i = 0x80000000; i <= limit; i++) {
 609         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 610             fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
 611             abort();
 612         }
 613         c = &cpuid_data.entries[cpuid_i++];
 614
 615         c->function = i;
 616         c->flags = 0;
 617         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 618     }
 619
 620     /* Call Centaur's CPUID instructions they are supported. */
 621     if (env->cpuid_xlevel2 > 0) {
 622         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 623
 624         for (i = 0xC0000000; i <= limit; i++) {
 625             if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 626                 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
 627                 abort();
 628             }
 629             c = &cpuid_data.entries[cpuid_i++];
 630
 631             c->function = i;
 632             c->flags = 0;
 633             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 634         }
 635     }
 636
 637     cpuid_data.cpuid.nent = cpuid_i;
 638
 639     if (((env->cpuid_version >> 8)&0xF) >= 6
 640         && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
 641            (CPUID_MCE | CPUID_MCA)
 642         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
 643         uint64_t mcg_cap;
 644         int banks;
 645         int ret;
 646
 647         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
 648         if (ret < 0) {
 649             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 650             return ret;
 651         }
 652
 653         if (banks > MCE_BANKS_DEF) {
 654             banks = MCE_BANKS_DEF;
 655         }
 656         mcg_cap &= MCE_CAP_DEF;
 657         mcg_cap |= banks;
 658         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
 659         if (ret < 0) {
 660             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 661             return ret;
 662         }
 663
 664         env->mcg_cap = mcg_cap;
 665     }
 666
 667     qemu_add_vm_change_state_handler(cpu_update_state, env);
 668
 669     cpuid_data.cpuid.padding = 0;
 670     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
 671     if (r) {
 672         return r;
 673     }
 674
 675     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
 676     if (r && env->tsc_khz) {
 677         r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
 678         if (r < 0) {
 679             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 680             return r;
 681         }
 682     }
 683
 684     if (kvm_has_xsave()) {
 685         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 686     }
 687
 688     return 0;
 689 }
 690
 691 void kvm_arch_reset_vcpu(CPUState *cs)
 692 {
 693     X86CPU *cpu = X86_CPU(cs);
 694     CPUX86State *env = &cpu->env;
 695
 696     env->exception_injected = -1;
 697     env->interrupt_injected = -1;
 698     env->xcr0 = 1;
 699     if (kvm_irqchip_in_kernel()) {
 700         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 701                                           KVM_MP_STATE_UNINITIALIZED;
 702     } else {
 703         env->mp_state = KVM_MP_STATE_RUNNABLE;
 704     }
 705 }
 706
 707 static int kvm_get_supported_msrs(KVMState *s)
 708 {
 709     static int kvm_supported_msrs;
 710     int ret = 0;
 711
 712     /* first time */
 713     if (kvm_supported_msrs == 0) {
 714         struct kvm_msr_list msr_list, *kvm_msr_list;
 715
 716         kvm_supported_msrs = -1;
 717
 718         /* Obtain MSR list from KVM.  These are the MSRs that we must
 719          * save/restore */
 720         msr_list.nmsrs = 0;
 721         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 722         if (ret < 0 && ret != -E2BIG) {
 723             return ret;
 724         }
 725         /* Old kernel modules had a bug and could write beyond the provided
 726            memory. Allocate at least a safe amount of 1K. */
 727         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 728                                               msr_list.nmsrs *
 729                                               sizeof(msr_list.indices[0])));
 730
 731         kvm_msr_list->nmsrs = msr_list.nmsrs;
 732         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 733         if (ret >= 0) {
 734             int i;
 735
 736             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 737                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 738                     has_msr_star = true;
 739                     continue;
 740                 }
 741                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 742                     has_msr_hsave_pa = true;
 743                     continue;
 744                 }
 745                 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
 746                     has_msr_tsc_adjust = true;
 747                     continue;
 748                 }
 749                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 750                     has_msr_tsc_deadline = true;
 751                     continue;
 752                 }
 753                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 754                     has_msr_misc_enable = true;
 755                     continue;
 756                 }
 757             }
 758         }
 759
 760         g_free(kvm_msr_list);
 761     }
 762
 763     return ret;
 764 }
 765
 766 int kvm_arch_init(KVMState *s)
 767 {
 768     uint64_t identity_base = 0xfffbc000;
 769     uint64_t shadow_mem;
 770     int ret;
 771     struct utsname utsname;
 772
 773     ret = kvm_get_supported_msrs(s);
 774     if (ret < 0) {
 775         return ret;
 776     }
 777
 778     uname(&utsname);
 779     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 780
 781     /*
 782      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 783      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 784      * Since these must be part of guest physical memory, we need to allocate
 785      * them, both by setting their start addresses in the kernel and by
 786      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 787      *
 788      * Older KVM versions may not support setting the identity map base. In
 789      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 790      * size.
 791      */
 792     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 793         /* Allows up to 16M BIOSes. */
 794         identity_base = 0xfeffc000;
 795
 796         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 797         if (ret < 0) {
 798             return ret;
 799         }
 800     }
 801
 802     /* Set TSS base one page after EPT identity map. */
 803     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 804     if (ret < 0) {
 805         return ret;
 806     }
 807
 808     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 809     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 810     if (ret < 0) {
 811         fprintf(stderr, "e820_add_entry() table is full\n");
 812         return ret;
 813     }
 814     qemu_register_reset(kvm_unpoison_all, NULL);
 815
 816     shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
 817                                    "kvm_shadow_mem", -1);
 818     if (shadow_mem != -1) {
 819         shadow_mem /= 4096;
 820         ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 821         if (ret < 0) {
 822             return ret;
 823         }
 824     }
 825     return 0;
 826 }
 827
 828 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 829 {
 830     lhs->selector = rhs->selector;
 831     lhs->base = rhs->base;
 832     lhs->limit = rhs->limit;
 833     lhs->type = 3;
 834     lhs->present = 1;
 835     lhs->dpl = 3;
 836     lhs->db = 0;
 837     lhs->s = 1;
 838     lhs->l = 0;
 839     lhs->g = 0;
 840     lhs->avl = 0;
 841     lhs->unusable = 0;
 842 }
 843
 844 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 845 {
 846     unsigned flags = rhs->flags;
 847     lhs->selector = rhs->selector;
 848     lhs->base = rhs->base;
 849     lhs->limit = rhs->limit;
 850     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 851     lhs->present = (flags & DESC_P_MASK) != 0;
 852     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 853     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 854     lhs->s = (flags & DESC_S_MASK) != 0;
 855     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 856     lhs->g = (flags & DESC_G_MASK) != 0;
 857     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 858     lhs->unusable = 0;
 859     lhs->padding = 0;
 860 }
 861
 862 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 863 {
 864     lhs->selector = rhs->selector;
 865     lhs->base = rhs->base;
 866     lhs->limit = rhs->limit;
 867     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 868                  (rhs->present * DESC_P_MASK) |
 869                  (rhs->dpl << DESC_DPL_SHIFT) |
 870                  (rhs->db << DESC_B_SHIFT) |
 871                  (rhs->s * DESC_S_MASK) |
 872                  (rhs->l << DESC_L_SHIFT) |
 873                  (rhs->g * DESC_G_MASK) |
 874                  (rhs->avl * DESC_AVL_MASK);
 875 }
 876
 877 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 878 {
 879     if (set) {
 880         *kvm_reg = *qemu_reg;
 881     } else {
 882         *qemu_reg = *kvm_reg;
 883     }
 884 }
 885
 886 static int kvm_getput_regs(X86CPU *cpu, int set)
 887 {
 888     CPUX86State *env = &cpu->env;
 889     struct kvm_regs regs;
 890     int ret = 0;
 891
 892     if (!set) {
 893         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
 894         if (ret < 0) {
 895             return ret;
 896         }
 897     }
 898
 899     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 900     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 901     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 902     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 903     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 904     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 905     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 906     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 907 #ifdef TARGET_X86_64
 908     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 909     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 910     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 911     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 912     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 913     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 914     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 915     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 916 #endif
 917
 918     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 919     kvm_getput_reg(&regs.rip, &env->eip, set);
 920
 921     if (set) {
 922         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
 923     }
 924
 925     return ret;
 926 }
 927
 928 static int kvm_put_fpu(X86CPU *cpu)
 929 {
 930     CPUX86State *env = &cpu->env;
 931     struct kvm_fpu fpu;
 932     int i;
 933
 934     memset(&fpu, 0, sizeof fpu);
 935     fpu.fsw = env->fpus & ~(7 << 11);
 936     fpu.fsw |= (env->fpstt & 7) << 11;
 937     fpu.fcw = env->fpuc;
 938     fpu.last_opcode = env->fpop;
 939     fpu.last_ip = env->fpip;
 940     fpu.last_dp = env->fpdp;
 941     for (i = 0; i < 8; ++i) {
 942         fpu.ftwx |= (!env->fptags[i]) << i;
 943     }
 944     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 945     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 946     fpu.mxcsr = env->mxcsr;
 947
 948     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
 949 }
 950
 951 #define XSAVE_FCW_FSW     0
 952 #define XSAVE_FTW_FOP     1
 953 #define XSAVE_CWD_RIP     2
 954 #define XSAVE_CWD_RDP     4
 955 #define XSAVE_MXCSR       6
 956 #define XSAVE_ST_SPACE    8
 957 #define XSAVE_XMM_SPACE   40
 958 #define XSAVE_XSTATE_BV   128
 959 #define XSAVE_YMMH_SPACE  144
 960
 961 static int kvm_put_xsave(X86CPU *cpu)
 962 {
 963     CPUX86State *env = &cpu->env;
 964     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 965     uint16_t cwd, swd, twd;
 966     int i, r;
 967
 968     if (!kvm_has_xsave()) {
 969         return kvm_put_fpu(cpu);
 970     }
 971
 972     memset(xsave, 0, sizeof(struct kvm_xsave));
 973     twd = 0;
 974     swd = env->fpus & ~(7 << 11);
 975     swd |= (env->fpstt & 7) << 11;
 976     cwd = env->fpuc;
 977     for (i = 0; i < 8; ++i) {
 978         twd |= (!env->fptags[i]) << i;
 979     }
 980     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 981     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 982     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 983     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 984     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 985             sizeof env->fpregs);
 986     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 987             sizeof env->xmm_regs);
 988     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 989     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 990     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 991             sizeof env->ymmh_regs);
 992     r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
 993     return r;
 994 }
 995
 996 static int kvm_put_xcrs(X86CPU *cpu)
 997 {
 998     CPUX86State *env = &cpu->env;
 999     struct kvm_xcrs xcrs;
1000
1001     if (!kvm_has_xcrs()) {
1002         return 0;
1003     }
1004
1005     xcrs.nr_xcrs = 1;
1006     xcrs.flags = 0;
1007     xcrs.xcrs[0].xcr = 0;
1008     xcrs.xcrs[0].value = env->xcr0;
1009     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1010 }
1011
1012 static int kvm_put_sregs(X86CPU *cpu)
1013 {
1014     CPUX86State *env = &cpu->env;
1015     struct kvm_sregs sregs;
1016
1017     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1018     if (env->interrupt_injected >= 0) {
1019         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1020                 (uint64_t)1 << (env->interrupt_injected % 64);
1021     }
1022
1023     if ((env->eflags & VM_MASK)) {
1024         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1025         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1026         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1027         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1028         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1029         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1030     } else {
1031         set_seg(&sregs.cs, &env->segs[R_CS]);
1032         set_seg(&sregs.ds, &env->segs[R_DS]);
1033         set_seg(&sregs.es, &env->segs[R_ES]);
1034         set_seg(&sregs.fs, &env->segs[R_FS]);
1035         set_seg(&sregs.gs, &env->segs[R_GS]);
1036         set_seg(&sregs.ss, &env->segs[R_SS]);
1037     }
1038
1039     set_seg(&sregs.tr, &env->tr);
1040     set_seg(&sregs.ldt, &env->ldt);
1041
1042     sregs.idt.limit = env->idt.limit;
1043     sregs.idt.base = env->idt.base;
1044     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1045     sregs.gdt.limit = env->gdt.limit;
1046     sregs.gdt.base = env->gdt.base;
1047     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1048
1049     sregs.cr0 = env->cr[0];
1050     sregs.cr2 = env->cr[2];
1051     sregs.cr3 = env->cr[3];
1052     sregs.cr4 = env->cr[4];
1053
1054     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
1055     sregs.apic_base = cpu_get_apic_base(env->apic_state);
1056
1057     sregs.efer = env->efer;
1058
1059     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1060 }
1061
1062 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1063                               uint32_t index, uint64_t value)
1064 {
1065     entry->index = index;
1066     entry->data = value;
1067 }
1068
1069 static int kvm_put_msrs(X86CPU *cpu, int level)
1070 {
1071     CPUX86State *env = &cpu->env;
1072     struct {
1073         struct kvm_msrs info;
1074         struct kvm_msr_entry entries[100];
1075     } msr_data;
1076     struct kvm_msr_entry *msrs = msr_data.entries;
1077     int n = 0, i;
1078
1079     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1080     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1081     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1082     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1083     if (has_msr_star) {
1084         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1085     }
1086     if (has_msr_hsave_pa) {
1087         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1088     }
1089     if (has_msr_tsc_adjust) {
1090         kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1091     }
1092     if (has_msr_tsc_deadline) {
1093         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1094     }
1095     if (has_msr_misc_enable) {
1096         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1097                           env->msr_ia32_misc_enable);
1098     }
1099 #ifdef TARGET_X86_64
1100     if (lm_capable_kernel) {
1101         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1102         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1103         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1104         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1105     }
1106 #endif
1107     if (level == KVM_PUT_FULL_STATE) {
1108         /*
1109          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1110          * writeback. Until this is fixed, we only write the offset to SMP
1111          * guests after migration, desynchronizing the VCPUs, but avoiding
1112          * huge jump-backs that would occur without any writeback at all.
1113          */
1114         if (smp_cpus == 1 || env->tsc != 0) {
1115             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1116         }
1117     }
1118     /*
1119      * The following MSRs have side effects on the guest or are too heavy
1120      * for normal writeback. Limit them to reset or full state updates.
1121      */
1122     if (level >= KVM_PUT_RESET_STATE) {
1123         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1124                           env->system_time_msr);
1125         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1126         if (has_msr_async_pf_en) {
1127             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1128                               env->async_pf_en_msr);
1129         }
1130         if (has_msr_pv_eoi_en) {
1131             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1132                               env->pv_eoi_en_msr);
1133         }
1134         if (has_msr_kvm_steal_time) {
1135             kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1136                               env->steal_time_msr);
1137         }
1138         if (has_msr_architectural_pmu) {
1139             /* Stop the counter.  */
1140             kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1141             kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1142
1143             /* Set the counter values.  */
1144             for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1145                 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1146                                   env->msr_fixed_counters[i]);
1147             }
1148             for (i = 0; i < num_architectural_pmu_counters; i++) {
1149                 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1150                                   env->msr_gp_counters[i]);
1151                 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1152                                   env->msr_gp_evtsel[i]);
1153             }
1154             kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1155                               env->msr_global_status);
1156             kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1157                               env->msr_global_ovf_ctrl);
1158
1159             /* Now start the PMU.  */
1160             kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1161                               env->msr_fixed_ctr_ctrl);
1162             kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1163                               env->msr_global_ctrl);
1164         }
1165         if (hyperv_hypercall_available()) {
1166             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1167             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1168         }
1169         if (hyperv_vapic_recommended()) {
1170             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1171         }
1172         kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL, env->msr_ia32_feature_control);
1173     }
1174     if (env->mcg_cap) {
1175         int i;
1176
1177         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1178         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1179         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1180             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1181         }
1182     }
1183
1184     msr_data.info.nmsrs = n;
1185
1186     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1187
1188 }
1189
1190
1191 static int kvm_get_fpu(X86CPU *cpu)
1192 {
1193     CPUX86State *env = &cpu->env;
1194     struct kvm_fpu fpu;
1195     int i, ret;
1196
1197     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1198     if (ret < 0) {
1199         return ret;
1200     }
1201
1202     env->fpstt = (fpu.fsw >> 11) & 7;
1203     env->fpus = fpu.fsw;
1204     env->fpuc = fpu.fcw;
1205     env->fpop = fpu.last_opcode;
1206     env->fpip = fpu.last_ip;
1207     env->fpdp = fpu.last_dp;
1208     for (i = 0; i < 8; ++i) {
1209         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1210     }
1211     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1212     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1213     env->mxcsr = fpu.mxcsr;
1214
1215     return 0;
1216 }
1217
1218 static int kvm_get_xsave(X86CPU *cpu)
1219 {
1220     CPUX86State *env = &cpu->env;
1221     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1222     int ret, i;
1223     uint16_t cwd, swd, twd;
1224
1225     if (!kvm_has_xsave()) {
1226         return kvm_get_fpu(cpu);
1227     }
1228
1229     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1230     if (ret < 0) {
1231         return ret;
1232     }
1233
1234     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1235     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1236     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1237     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1238     env->fpstt = (swd >> 11) & 7;
1239     env->fpus = swd;
1240     env->fpuc = cwd;
1241     for (i = 0; i < 8; ++i) {
1242         env->fptags[i] = !((twd >> i) & 1);
1243     }
1244     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1245     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1246     env->mxcsr = xsave->region[XSAVE_MXCSR];
1247     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1248             sizeof env->fpregs);
1249     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1250             sizeof env->xmm_regs);
1251     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1252     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1253             sizeof env->ymmh_regs);
1254     return 0;
1255 }
1256
1257 static int kvm_get_xcrs(X86CPU *cpu)
1258 {
1259     CPUX86State *env = &cpu->env;
1260     int i, ret;
1261     struct kvm_xcrs xcrs;
1262
1263     if (!kvm_has_xcrs()) {
1264         return 0;
1265     }
1266
1267     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1268     if (ret < 0) {
1269         return ret;
1270     }
1271
1272     for (i = 0; i < xcrs.nr_xcrs; i++) {
1273         /* Only support xcr0 now */
1274         if (xcrs.xcrs[0].xcr == 0) {
1275             env->xcr0 = xcrs.xcrs[0].value;
1276             break;
1277         }
1278     }
1279     return 0;
1280 }
1281
1282 static int kvm_get_sregs(X86CPU *cpu)
1283 {
1284     CPUX86State *env = &cpu->env;
1285     struct kvm_sregs sregs;
1286     uint32_t hflags;
1287     int bit, i, ret;
1288
1289     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1290     if (ret < 0) {
1291         return ret;
1292     }
1293
1294     /* There can only be one pending IRQ set in the bitmap at a time, so try
1295        to find it and save its number instead (-1 for none). */
1296     env->interrupt_injected = -1;
1297     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1298         if (sregs.interrupt_bitmap[i]) {
1299             bit = ctz64(sregs.interrupt_bitmap[i]);
1300             env->interrupt_injected = i * 64 + bit;
1301             break;
1302         }
1303     }
1304
1305     get_seg(&env->segs[R_CS], &sregs.cs);
1306     get_seg(&env->segs[R_DS], &sregs.ds);
1307     get_seg(&env->segs[R_ES], &sregs.es);
1308     get_seg(&env->segs[R_FS], &sregs.fs);
1309     get_seg(&env->segs[R_GS], &sregs.gs);
1310     get_seg(&env->segs[R_SS], &sregs.ss);
1311
1312     get_seg(&env->tr, &sregs.tr);
1313     get_seg(&env->ldt, &sregs.ldt);
1314
1315     env->idt.limit = sregs.idt.limit;
1316     env->idt.base = sregs.idt.base;
1317     env->gdt.limit = sregs.gdt.limit;
1318     env->gdt.base = sregs.gdt.base;
1319
1320     env->cr[0] = sregs.cr0;
1321     env->cr[2] = sregs.cr2;
1322     env->cr[3] = sregs.cr3;
1323     env->cr[4] = sregs.cr4;
1324
1325     env->efer = sregs.efer;
1326
1327     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1328
1329 #define HFLAG_COPY_MASK \
1330     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1331        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1332        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1333        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1334
1335     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1336     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1337     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1338                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1339     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1340     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1341                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1342
1343     if (env->efer & MSR_EFER_LMA) {
1344         hflags |= HF_LMA_MASK;
1345     }
1346
1347     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1348         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1349     } else {
1350         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1351                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1352         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1353                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1354         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1355             !(hflags & HF_CS32_MASK)) {
1356             hflags |= HF_ADDSEG_MASK;
1357         } else {
1358             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1359                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1360         }
1361     }
1362     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1363
1364     return 0;
1365 }
1366
1367 static int kvm_get_msrs(X86CPU *cpu)
1368 {
1369     CPUX86State *env = &cpu->env;
1370     struct {
1371         struct kvm_msrs info;
1372         struct kvm_msr_entry entries[100];
1373     } msr_data;
1374     struct kvm_msr_entry *msrs = msr_data.entries;
1375     int ret, i, n;
1376
1377     n = 0;
1378     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1379     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1380     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1381     msrs[n++].index = MSR_PAT;
1382     if (has_msr_star) {
1383         msrs[n++].index = MSR_STAR;
1384     }
1385     if (has_msr_hsave_pa) {
1386         msrs[n++].index = MSR_VM_HSAVE_PA;
1387     }
1388     if (has_msr_tsc_adjust) {
1389         msrs[n++].index = MSR_TSC_ADJUST;
1390     }
1391     if (has_msr_tsc_deadline) {
1392         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1393     }
1394     if (has_msr_misc_enable) {
1395         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1396     }
1397     msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1398
1399     if (!env->tsc_valid) {
1400         msrs[n++].index = MSR_IA32_TSC;
1401         env->tsc_valid = !runstate_is_running();
1402     }
1403
1404 #ifdef TARGET_X86_64
1405     if (lm_capable_kernel) {
1406         msrs[n++].index = MSR_CSTAR;
1407         msrs[n++].index = MSR_KERNELGSBASE;
1408         msrs[n++].index = MSR_FMASK;
1409         msrs[n++].index = MSR_LSTAR;
1410     }
1411 #endif
1412     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1413     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1414     if (has_msr_async_pf_en) {
1415         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1416     }
1417     if (has_msr_pv_eoi_en) {
1418         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1419     }
1420     if (has_msr_kvm_steal_time) {
1421         msrs[n++].index = MSR_KVM_STEAL_TIME;
1422     }
1423     if (has_msr_architectural_pmu) {
1424         msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1425         msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1426         msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1427         msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1428         for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1429             msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1430         }
1431         for (i = 0; i < num_architectural_pmu_counters; i++) {
1432             msrs[n++].index = MSR_P6_PERFCTR0 + i;
1433             msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1434         }
1435     }
1436
1437     if (env->mcg_cap) {
1438         msrs[n++].index = MSR_MCG_STATUS;
1439         msrs[n++].index = MSR_MCG_CTL;
1440         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1441             msrs[n++].index = MSR_MC0_CTL + i;
1442         }
1443     }
1444
1445     msr_data.info.nmsrs = n;
1446     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1447     if (ret < 0) {
1448         return ret;
1449     }
1450
1451     for (i = 0; i < ret; i++) {
1452         uint32_t index = msrs[i].index;
1453         switch (index) {
1454         case MSR_IA32_SYSENTER_CS:
1455             env->sysenter_cs = msrs[i].data;
1456             break;
1457         case MSR_IA32_SYSENTER_ESP:
1458             env->sysenter_esp = msrs[i].data;
1459             break;
1460         case MSR_IA32_SYSENTER_EIP:
1461             env->sysenter_eip = msrs[i].data;
1462             break;
1463         case MSR_PAT:
1464             env->pat = msrs[i].data;
1465             break;
1466         case MSR_STAR:
1467             env->star = msrs[i].data;
1468             break;
1469 #ifdef TARGET_X86_64
1470         case MSR_CSTAR:
1471             env->cstar = msrs[i].data;
1472             break;
1473         case MSR_KERNELGSBASE:
1474             env->kernelgsbase = msrs[i].data;
1475             break;
1476         case MSR_FMASK:
1477             env->fmask = msrs[i].data;
1478             break;
1479         case MSR_LSTAR:
1480             env->lstar = msrs[i].data;
1481             break;
1482 #endif
1483         case MSR_IA32_TSC:
1484             env->tsc = msrs[i].data;
1485             break;
1486         case MSR_TSC_ADJUST:
1487             env->tsc_adjust = msrs[i].data;
1488             break;
1489         case MSR_IA32_TSCDEADLINE:
1490             env->tsc_deadline = msrs[i].data;
1491             break;
1492         case MSR_VM_HSAVE_PA:
1493             env->vm_hsave = msrs[i].data;
1494             break;
1495         case MSR_KVM_SYSTEM_TIME:
1496             env->system_time_msr = msrs[i].data;
1497             break;
1498         case MSR_KVM_WALL_CLOCK:
1499             env->wall_clock_msr = msrs[i].data;
1500             break;
1501         case MSR_MCG_STATUS:
1502             env->mcg_status = msrs[i].data;
1503             break;
1504         case MSR_MCG_CTL:
1505             env->mcg_ctl = msrs[i].data;
1506             break;
1507         case MSR_IA32_MISC_ENABLE:
1508             env->msr_ia32_misc_enable = msrs[i].data;
1509             break;
1510         case MSR_IA32_FEATURE_CONTROL:
1511             env->msr_ia32_feature_control = msrs[i].data;
1512         default:
1513             if (msrs[i].index >= MSR_MC0_CTL &&
1514                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1515                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1516             }
1517             break;
1518         case MSR_KVM_ASYNC_PF_EN:
1519             env->async_pf_en_msr = msrs[i].data;
1520             break;
1521         case MSR_KVM_PV_EOI_EN:
1522             env->pv_eoi_en_msr = msrs[i].data;
1523             break;
1524         case MSR_KVM_STEAL_TIME:
1525             env->steal_time_msr = msrs[i].data;
1526             break;
1527         case MSR_CORE_PERF_FIXED_CTR_CTRL:
1528             env->msr_fixed_ctr_ctrl = msrs[i].data;
1529             break;
1530         case MSR_CORE_PERF_GLOBAL_CTRL:
1531             env->msr_global_ctrl = msrs[i].data;
1532             break;
1533         case MSR_CORE_PERF_GLOBAL_STATUS:
1534             env->msr_global_status = msrs[i].data;
1535             break;
1536         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1537             env->msr_global_ovf_ctrl = msrs[i].data;
1538             break;
1539         case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1540             env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1541             break;
1542         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1543             env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1544             break;
1545         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1546             env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1547             break;
1548         }
1549     }
1550
1551     return 0;
1552 }
1553
1554 static int kvm_put_mp_state(X86CPU *cpu)
1555 {
1556     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1557
1558     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1559 }
1560
1561 static int kvm_get_mp_state(X86CPU *cpu)
1562 {
1563     CPUState *cs = CPU(cpu);
1564     CPUX86State *env = &cpu->env;
1565     struct kvm_mp_state mp_state;
1566     int ret;
1567
1568     ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1569     if (ret < 0) {
1570         return ret;
1571     }
1572     env->mp_state = mp_state.mp_state;
1573     if (kvm_irqchip_in_kernel()) {
1574         cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1575     }
1576     return 0;
1577 }
1578
1579 static int kvm_get_apic(X86CPU *cpu)
1580 {
1581     CPUX86State *env = &cpu->env;
1582     DeviceState *apic = env->apic_state;
1583     struct kvm_lapic_state kapic;
1584     int ret;
1585
1586     if (apic && kvm_irqchip_in_kernel()) {
1587         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1588         if (ret < 0) {
1589             return ret;
1590         }
1591
1592         kvm_get_apic_state(apic, &kapic);
1593     }
1594     return 0;
1595 }
1596
1597 static int kvm_put_apic(X86CPU *cpu)
1598 {
1599     CPUX86State *env = &cpu->env;
1600     DeviceState *apic = env->apic_state;
1601     struct kvm_lapic_state kapic;
1602
1603     if (apic && kvm_irqchip_in_kernel()) {
1604         kvm_put_apic_state(apic, &kapic);
1605
1606         return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1607     }
1608     return 0;
1609 }
1610
1611 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1612 {
1613     CPUX86State *env = &cpu->env;
1614     struct kvm_vcpu_events events;
1615
1616     if (!kvm_has_vcpu_events()) {
1617         return 0;
1618     }
1619
1620     events.exception.injected = (env->exception_injected >= 0);
1621     events.exception.nr = env->exception_injected;
1622     events.exception.has_error_code = env->has_error_code;
1623     events.exception.error_code = env->error_code;
1624     events.exception.pad = 0;
1625
1626     events.interrupt.injected = (env->interrupt_injected >= 0);
1627     events.interrupt.nr = env->interrupt_injected;
1628     events.interrupt.soft = env->soft_interrupt;
1629
1630     events.nmi.injected = env->nmi_injected;
1631     events.nmi.pending = env->nmi_pending;
1632     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1633     events.nmi.pad = 0;
1634
1635     events.sipi_vector = env->sipi_vector;
1636
1637     events.flags = 0;
1638     if (level >= KVM_PUT_RESET_STATE) {
1639         events.flags |=
1640             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1641     }
1642
1643     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1644 }
1645
1646 static int kvm_get_vcpu_events(X86CPU *cpu)
1647 {
1648     CPUX86State *env = &cpu->env;
1649     struct kvm_vcpu_events events;
1650     int ret;
1651
1652     if (!kvm_has_vcpu_events()) {
1653         return 0;
1654     }
1655
1656     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1657     if (ret < 0) {
1658        return ret;
1659     }
1660     env->exception_injected =
1661        events.exception.injected ? events.exception.nr : -1;
1662     env->has_error_code = events.exception.has_error_code;
1663     env->error_code = events.exception.error_code;
1664
1665     env->interrupt_injected =
1666         events.interrupt.injected ? events.interrupt.nr : -1;
1667     env->soft_interrupt = events.interrupt.soft;
1668
1669     env->nmi_injected = events.nmi.injected;
1670     env->nmi_pending = events.nmi.pending;
1671     if (events.nmi.masked) {
1672         env->hflags2 |= HF2_NMI_MASK;
1673     } else {
1674         env->hflags2 &= ~HF2_NMI_MASK;
1675     }
1676
1677     env->sipi_vector = events.sipi_vector;
1678
1679     return 0;
1680 }
1681
1682 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1683 {
1684     CPUState *cs = CPU(cpu);
1685     CPUX86State *env = &cpu->env;
1686     int ret = 0;
1687     unsigned long reinject_trap = 0;
1688
1689     if (!kvm_has_vcpu_events()) {
1690         if (env->exception_injected == 1) {
1691             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1692         } else if (env->exception_injected == 3) {
1693             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1694         }
1695         env->exception_injected = -1;
1696     }
1697
1698     /*
1699      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1700      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1701      * by updating the debug state once again if single-stepping is on.
1702      * Another reason to call kvm_update_guest_debug here is a pending debug
1703      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1704      * reinject them via SET_GUEST_DEBUG.
1705      */
1706     if (reinject_trap ||
1707         (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1708         ret = kvm_update_guest_debug(env, reinject_trap);
1709     }
1710     return ret;
1711 }
1712
1713 static int kvm_put_debugregs(X86CPU *cpu)
1714 {
1715     CPUX86State *env = &cpu->env;
1716     struct kvm_debugregs dbgregs;
1717     int i;
1718
1719     if (!kvm_has_debugregs()) {
1720         return 0;
1721     }
1722
1723     for (i = 0; i < 4; i++) {
1724         dbgregs.db[i] = env->dr[i];
1725     }
1726     dbgregs.dr6 = env->dr[6];
1727     dbgregs.dr7 = env->dr[7];
1728     dbgregs.flags = 0;
1729
1730     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1731 }
1732
1733 static int kvm_get_debugregs(X86CPU *cpu)
1734 {
1735     CPUX86State *env = &cpu->env;
1736     struct kvm_debugregs dbgregs;
1737     int i, ret;
1738
1739     if (!kvm_has_debugregs()) {
1740         return 0;
1741     }
1742
1743     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1744     if (ret < 0) {
1745         return ret;
1746     }
1747     for (i = 0; i < 4; i++) {
1748         env->dr[i] = dbgregs.db[i];
1749     }
1750     env->dr[4] = env->dr[6] = dbgregs.dr6;
1751     env->dr[5] = env->dr[7] = dbgregs.dr7;
1752
1753     return 0;
1754 }
1755
1756 int kvm_arch_put_registers(CPUState *cpu, int level)
1757 {
1758     X86CPU *x86_cpu = X86_CPU(cpu);
1759     int ret;
1760
1761     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1762
1763     ret = kvm_getput_regs(x86_cpu, 1);
1764     if (ret < 0) {
1765         return ret;
1766     }
1767     ret = kvm_put_xsave(x86_cpu);
1768     if (ret < 0) {
1769         return ret;
1770     }
1771     ret = kvm_put_xcrs(x86_cpu);
1772     if (ret < 0) {
1773         return ret;
1774     }
1775     ret = kvm_put_sregs(x86_cpu);
1776     if (ret < 0) {
1777         return ret;
1778     }
1779     /* must be before kvm_put_msrs */
1780     ret = kvm_inject_mce_oldstyle(x86_cpu);
1781     if (ret < 0) {
1782         return ret;
1783     }
1784     ret = kvm_put_msrs(x86_cpu, level);
1785     if (ret < 0) {
1786         return ret;
1787     }
1788     if (level >= KVM_PUT_RESET_STATE) {
1789         ret = kvm_put_mp_state(x86_cpu);
1790         if (ret < 0) {
1791             return ret;
1792         }
1793         ret = kvm_put_apic(x86_cpu);
1794         if (ret < 0) {
1795             return ret;
1796         }
1797     }
1798     ret = kvm_put_vcpu_events(x86_cpu, level);
1799     if (ret < 0) {
1800         return ret;
1801     }
1802     ret = kvm_put_debugregs(x86_cpu);
1803     if (ret < 0) {
1804         return ret;
1805     }
1806     /* must be last */
1807     ret = kvm_guest_debug_workarounds(x86_cpu);
1808     if (ret < 0) {
1809         return ret;
1810     }
1811     return 0;
1812 }
1813
1814 int kvm_arch_get_registers(CPUState *cs)
1815 {
1816     X86CPU *cpu = X86_CPU(cs);
1817     int ret;
1818
1819     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1820
1821     ret = kvm_getput_regs(cpu, 0);
1822     if (ret < 0) {
1823         return ret;
1824     }
1825     ret = kvm_get_xsave(cpu);
1826     if (ret < 0) {
1827         return ret;
1828     }
1829     ret = kvm_get_xcrs(cpu);
1830     if (ret < 0) {
1831         return ret;
1832     }
1833     ret = kvm_get_sregs(cpu);
1834     if (ret < 0) {
1835         return ret;
1836     }
1837     ret = kvm_get_msrs(cpu);
1838     if (ret < 0) {
1839         return ret;
1840     }
1841     ret = kvm_get_mp_state(cpu);
1842     if (ret < 0) {
1843         return ret;
1844     }
1845     ret = kvm_get_apic(cpu);
1846     if (ret < 0) {
1847         return ret;
1848     }
1849     ret = kvm_get_vcpu_events(cpu);
1850     if (ret < 0) {
1851         return ret;
1852     }
1853     ret = kvm_get_debugregs(cpu);
1854     if (ret < 0) {
1855         return ret;
1856     }
1857     return 0;
1858 }
1859
1860 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1861 {
1862     X86CPU *x86_cpu = X86_CPU(cpu);
1863     CPUX86State *env = &x86_cpu->env;
1864     int ret;
1865
1866     /* Inject NMI */
1867     if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
1868         cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
1869         DPRINTF("injected NMI\n");
1870         ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1871         if (ret < 0) {
1872             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1873                     strerror(-ret));
1874         }
1875     }
1876
1877     if (!kvm_irqchip_in_kernel()) {
1878         /* Force the VCPU out of its inner loop to process any INIT requests
1879          * or pending TPR access reports. */
1880         if (cpu->interrupt_request &
1881             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1882             cpu->exit_request = 1;
1883         }
1884
1885         /* Try to inject an interrupt if the guest can accept it */
1886         if (run->ready_for_interrupt_injection &&
1887             (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1888             (env->eflags & IF_MASK)) {
1889             int irq;
1890
1891             cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
1892             irq = cpu_get_pic_interrupt(env);
1893             if (irq >= 0) {
1894                 struct kvm_interrupt intr;
1895
1896                 intr.irq = irq;
1897                 DPRINTF("injected interrupt %d\n", irq);
1898                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
1899                 if (ret < 0) {
1900                     fprintf(stderr,
1901                             "KVM: injection failed, interrupt lost (%s)\n",
1902                             strerror(-ret));
1903                 }
1904             }
1905         }
1906
1907         /* If we have an interrupt but the guest is not ready to receive an
1908          * interrupt, request an interrupt window exit.  This will
1909          * cause a return to userspace as soon as the guest is ready to
1910          * receive interrupts. */
1911         if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
1912             run->request_interrupt_window = 1;
1913         } else {
1914             run->request_interrupt_window = 0;
1915         }
1916
1917         DPRINTF("setting tpr\n");
1918         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1919     }
1920 }
1921
1922 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
1923 {
1924     X86CPU *x86_cpu = X86_CPU(cpu);
1925     CPUX86State *env = &x86_cpu->env;
1926
1927     if (run->if_flag) {
1928         env->eflags |= IF_MASK;
1929     } else {
1930         env->eflags &= ~IF_MASK;
1931     }
1932     cpu_set_apic_tpr(env->apic_state, run->cr8);
1933     cpu_set_apic_base(env->apic_state, run->apic_base);
1934 }
1935
1936 int kvm_arch_process_async_events(CPUState *cs)
1937 {
1938     X86CPU *cpu = X86_CPU(cs);
1939     CPUX86State *env = &cpu->env;
1940
1941     if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
1942         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1943         assert(env->mcg_cap);
1944
1945         cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
1946
1947         kvm_cpu_synchronize_state(cs);
1948
1949         if (env->exception_injected == EXCP08_DBLE) {
1950             /* this means triple fault */
1951             qemu_system_reset_request();
1952             cs->exit_request = 1;
1953             return 0;
1954         }
1955         env->exception_injected = EXCP12_MCHK;
1956         env->has_error_code = 0;
1957
1958         cs->halted = 0;
1959         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1960             env->mp_state = KVM_MP_STATE_RUNNABLE;
1961         }
1962     }
1963
1964     if (kvm_irqchip_in_kernel()) {
1965         return 0;
1966     }
1967
1968     if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
1969         cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
1970         apic_poll_irq(env->apic_state);
1971     }
1972     if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1973          (env->eflags & IF_MASK)) ||
1974         (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
1975         cs->halted = 0;
1976     }
1977     if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
1978         kvm_cpu_synchronize_state(cs);
1979         do_cpu_init(cpu);
1980     }
1981     if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
1982         kvm_cpu_synchronize_state(cs);
1983         do_cpu_sipi(cpu);
1984     }
1985     if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
1986         cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
1987         kvm_cpu_synchronize_state(cs);
1988         apic_handle_tpr_access_report(env->apic_state, env->eip,
1989                                       env->tpr_access_type);
1990     }
1991
1992     return cs->halted;
1993 }
1994
1995 static int kvm_handle_halt(X86CPU *cpu)
1996 {
1997     CPUState *cs = CPU(cpu);
1998     CPUX86State *env = &cpu->env;
1999
2000     if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2001           (env->eflags & IF_MASK)) &&
2002         !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2003         cs->halted = 1;
2004         return EXCP_HLT;
2005     }
2006
2007     return 0;
2008 }
2009
2010 static int kvm_handle_tpr_access(X86CPU *cpu)
2011 {
2012     CPUX86State *env = &cpu->env;
2013     CPUState *cs = CPU(cpu);
2014     struct kvm_run *run = cs->kvm_run;
2015
2016     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
2017                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
2018                                                            : TPR_ACCESS_READ);
2019     return 1;
2020 }
2021
2022 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2023 {
2024     static const uint8_t int3 = 0xcc;
2025
2026     if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2027         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2028         return -EINVAL;
2029     }
2030     return 0;
2031 }
2032
2033 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2034 {
2035     uint8_t int3;
2036
2037     if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2038         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2039         return -EINVAL;
2040     }
2041     return 0;
2042 }
2043
2044 static struct {
2045     target_ulong addr;
2046     int len;
2047     int type;
2048 } hw_breakpoint[4];
2049
2050 static int nb_hw_breakpoint;
2051
2052 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2053 {
2054     int n;
2055
2056     for (n = 0; n < nb_hw_breakpoint; n++) {
2057         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2058             (hw_breakpoint[n].len == len || len == -1)) {
2059             return n;
2060         }
2061     }
2062     return -1;
2063 }
2064
2065 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2066                                   target_ulong len, int type)
2067 {
2068     switch (type) {
2069     case GDB_BREAKPOINT_HW:
2070         len = 1;
2071         break;
2072     case GDB_WATCHPOINT_WRITE:
2073     case GDB_WATCHPOINT_ACCESS:
2074         switch (len) {
2075         case 1:
2076             break;
2077         case 2:
2078         case 4:
2079         case 8:
2080             if (addr & (len - 1)) {
2081                 return -EINVAL;
2082             }
2083             break;
2084         default:
2085             return -EINVAL;
2086         }
2087         break;
2088     default:
2089         return -ENOSYS;
2090     }
2091
2092     if (nb_hw_breakpoint == 4) {
2093         return -ENOBUFS;
2094     }
2095     if (find_hw_breakpoint(addr, len, type) >= 0) {
2096         return -EEXIST;
2097     }
2098     hw_breakpoint[nb_hw_breakpoint].addr = addr;
2099     hw_breakpoint[nb_hw_breakpoint].len = len;
2100     hw_breakpoint[nb_hw_breakpoint].type = type;
2101     nb_hw_breakpoint++;
2102
2103     return 0;
2104 }
2105
2106 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2107                                   target_ulong len, int type)
2108 {
2109     int n;
2110
2111     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2112     if (n < 0) {
2113         return -ENOENT;
2114     }
2115     nb_hw_breakpoint--;
2116     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2117
2118     return 0;
2119 }
2120
2121 void kvm_arch_remove_all_hw_breakpoints(void)
2122 {
2123     nb_hw_breakpoint = 0;
2124 }
2125
2126 static CPUWatchpoint hw_watchpoint;
2127
2128 static int kvm_handle_debug(X86CPU *cpu,
2129                             struct kvm_debug_exit_arch *arch_info)
2130 {
2131     CPUState *cs = CPU(cpu);
2132     CPUX86State *env = &cpu->env;
2133     int ret = 0;
2134     int n;
2135
2136     if (arch_info->exception == 1) {
2137         if (arch_info->dr6 & (1 << 14)) {
2138             if (cs->singlestep_enabled) {
2139                 ret = EXCP_DEBUG;
2140             }
2141         } else {
2142             for (n = 0; n < 4; n++) {
2143                 if (arch_info->dr6 & (1 << n)) {
2144                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2145                     case 0x0:
2146                         ret = EXCP_DEBUG;
2147                         break;
2148                     case 0x1:
2149                         ret = EXCP_DEBUG;
2150                         env->watchpoint_hit = &hw_watchpoint;
2151                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2152                         hw_watchpoint.flags = BP_MEM_WRITE;
2153                         break;
2154                     case 0x3:
2155                         ret = EXCP_DEBUG;
2156                         env->watchpoint_hit = &hw_watchpoint;
2157                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2158                         hw_watchpoint.flags = BP_MEM_ACCESS;
2159                         break;
2160                     }
2161                 }
2162             }
2163         }
2164     } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2165         ret = EXCP_DEBUG;
2166     }
2167     if (ret == 0) {
2168         cpu_synchronize_state(CPU(cpu));
2169         assert(env->exception_injected == -1);
2170
2171         /* pass to guest */
2172         env->exception_injected = arch_info->exception;
2173         env->has_error_code = 0;
2174     }
2175
2176     return ret;
2177 }
2178
2179 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2180 {
2181     const uint8_t type_code[] = {
2182         [GDB_BREAKPOINT_HW] = 0x0,
2183         [GDB_WATCHPOINT_WRITE] = 0x1,
2184         [GDB_WATCHPOINT_ACCESS] = 0x3
2185     };
2186     const uint8_t len_code[] = {
2187         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2188     };
2189     int n;
2190
2191     if (kvm_sw_breakpoints_active(cpu)) {
2192         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2193     }
2194     if (nb_hw_breakpoint > 0) {
2195         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2196         dbg->arch.debugreg[7] = 0x0600;
2197         for (n = 0; n < nb_hw_breakpoint; n++) {
2198             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2199             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2200                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2201                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2202         }
2203     }
2204 }
2205
2206 static bool host_supports_vmx(void)
2207 {
2208     uint32_t ecx, unused;
2209
2210     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2211     return ecx & CPUID_EXT_VMX;
2212 }
2213
2214 #define VMX_INVALID_GUEST_STATE 0x80000021
2215
2216 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2217 {
2218     X86CPU *cpu = X86_CPU(cs);
2219     uint64_t code;
2220     int ret;
2221
2222     switch (run->exit_reason) {
2223     case KVM_EXIT_HLT:
2224         DPRINTF("handle_hlt\n");
2225         ret = kvm_handle_halt(cpu);
2226         break;
2227     case KVM_EXIT_SET_TPR:
2228         ret = 0;
2229         break;
2230     case KVM_EXIT_TPR_ACCESS:
2231         ret = kvm_handle_tpr_access(cpu);
2232         break;
2233     case KVM_EXIT_FAIL_ENTRY:
2234         code = run->fail_entry.hardware_entry_failure_reason;
2235         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2236                 code);
2237         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2238             fprintf(stderr,
2239                     "\nIf you're running a guest on an Intel machine without "
2240                         "unrestricted mode\n"
2241                     "support, the failure can be most likely due to the guest "
2242                         "entering an invalid\n"
2243                     "state for Intel VT. For example, the guest maybe running "
2244                         "in big real mode\n"
2245                     "which is not supported on less recent Intel processors."
2246                         "\n\n");
2247         }
2248         ret = -1;
2249         break;
2250     case KVM_EXIT_EXCEPTION:
2251         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2252                 run->ex.exception, run->ex.error_code);
2253         ret = -1;
2254         break;
2255     case KVM_EXIT_DEBUG:
2256         DPRINTF("kvm_exit_debug\n");
2257         ret = kvm_handle_debug(cpu, &run->debug.arch);
2258         break;
2259     default:
2260         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2261         ret = -1;
2262         break;
2263     }
2264
2265     return ret;
2266 }
2267
2268 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2269 {
2270     X86CPU *cpu = X86_CPU(cs);
2271     CPUX86State *env = &cpu->env;
2272
2273     kvm_cpu_synchronize_state(cs);
2274     return !(env->cr[0] & CR0_PE_MASK) ||
2275            ((env->segs[R_CS].selector  & 3) != 3);
2276 }
2277
2278 void kvm_arch_init_irq_routing(KVMState *s)
2279 {
2280     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2281         /* If kernel can't do irq routing, interrupt source
2282          * override 0->2 cannot be set up as required by HPET.
2283          * So we have to disable it.
2284          */
2285         no_hpet = 1;
2286     }
2287     /* We know at this point that we're using the in-kernel
2288      * irqchip, so we can use irqfds, and on x86 we know
2289      * we can use msi via irqfd and GSI routing.
2290      */
2291     kvm_irqfds_allowed = true;
2292     kvm_msi_via_irqfd_allowed = true;
2293     kvm_gsi_routing_allowed = true;
2294 }
2295
2296 /* Classic KVM device assignment interface. Will remain x86 only. */
2297 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2298                           uint32_t flags, uint32_t *dev_id)
2299 {
2300     struct kvm_assigned_pci_dev dev_data = {
2301         .segnr = dev_addr->domain,
2302         .busnr = dev_addr->bus,
2303         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2304         .flags = flags,
2305     };
2306     int ret;
2307
2308     dev_data.assigned_dev_id =
2309         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2310
2311     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2312     if (ret < 0) {
2313         return ret;
2314     }
2315
2316     *dev_id = dev_data.assigned_dev_id;
2317
2318     return 0;
2319 }
2320
2321 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2322 {
2323     struct kvm_assigned_pci_dev dev_data = {
2324         .assigned_dev_id = dev_id,
2325     };
2326
2327     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2328 }
2329
2330 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2331                                    uint32_t irq_type, uint32_t guest_irq)
2332 {
2333     struct kvm_assigned_irq assigned_irq = {
2334         .assigned_dev_id = dev_id,
2335         .guest_irq = guest_irq,
2336         .flags = irq_type,
2337     };
2338
2339     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2340         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2341     } else {
2342         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2343     }
2344 }
2345
2346 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2347                            uint32_t guest_irq)
2348 {
2349     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2350         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2351
2352     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2353 }
2354
2355 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2356 {
2357     struct kvm_assigned_pci_dev dev_data = {
2358         .assigned_dev_id = dev_id,
2359         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2360     };
2361
2362     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2363 }
2364
2365 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2366                                      uint32_t type)
2367 {
2368     struct kvm_assigned_irq assigned_irq = {
2369         .assigned_dev_id = dev_id,
2370         .flags = type,
2371     };
2372
2373     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2374 }
2375
2376 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2377 {
2378     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2379         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2380 }
2381
2382 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2383 {
2384     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2385                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2386 }
2387
2388 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2389 {
2390     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2391                                                 KVM_DEV_IRQ_HOST_MSI);
2392 }
2393
2394 bool kvm_device_msix_supported(KVMState *s)
2395 {
2396     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2397      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2398     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2399 }
2400
2401 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2402                                  uint32_t nr_vectors)
2403 {
2404     struct kvm_assigned_msix_nr msix_nr = {
2405         .assigned_dev_id = dev_id,
2406         .entry_nr = nr_vectors,
2407     };
2408
2409     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2410 }
2411
2412 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2413                                int virq)
2414 {
2415     struct kvm_assigned_msix_entry msix_entry = {
2416         .assigned_dev_id = dev_id,
2417         .gsi = virq,
2418         .entry = vector,
2419     };
2420
2421     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2422 }
2423
2424 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2425 {
2426     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2427                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2428 }
2429
2430 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2431 {
2432     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2433                                                 KVM_DEV_IRQ_HOST_MSIX);
2434 }