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[qemu.git] / target-i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu.h"
25 #include "kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "gdbstub.h"
29 #include "host-utils.h"
30 #include "hw/pc.h"
31 #include "hw/apic.h"
32 #include "ioport.h"
33 #include "hyperv.h"
34 #include "hw/pci.h"
35
36 //#define DEBUG_KVM
37
38 #ifdef DEBUG_KVM
39 #define DPRINTF(fmt, ...) \
40 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
41 #else
42 #define DPRINTF(fmt, ...) \
43 do { } while (0)
44 #endif
45
46 #define MSR_KVM_WALL_CLOCK 0x11
47 #define MSR_KVM_SYSTEM_TIME 0x12
48
49 #ifndef BUS_MCEERR_AR
50 #define BUS_MCEERR_AR 4
51 #endif
52 #ifndef BUS_MCEERR_AO
53 #define BUS_MCEERR_AO 5
54 #endif
55
56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
57 KVM_CAP_INFO(SET_TSS_ADDR),
58 KVM_CAP_INFO(EXT_CPUID),
59 KVM_CAP_INFO(MP_STATE),
60 KVM_CAP_LAST_INFO
61 };
62
63 static bool has_msr_star;
64 static bool has_msr_hsave_pa;
65 static bool has_msr_tsc_deadline;
66 static bool has_msr_async_pf_en;
67 static bool has_msr_pv_eoi_en;
68 static bool has_msr_misc_enable;
69 static int lm_capable_kernel;
70
71 bool kvm_allows_irq0_override(void)
72 {
73 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
74 }
75
76 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
77 {
78 struct kvm_cpuid2 *cpuid;
79 int r, size;
80
81 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
82 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
83 cpuid->nent = max;
84 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
85 if (r == 0 && cpuid->nent >= max) {
86 r = -E2BIG;
87 }
88 if (r < 0) {
89 if (r == -E2BIG) {
90 g_free(cpuid);
91 return NULL;
92 } else {
93 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
94 strerror(-r));
95 exit(1);
96 }
97 }
98 return cpuid;
99 }
100
101 struct kvm_para_features {
102 int cap;
103 int feature;
104 } para_features[] = {
105 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
106 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
107 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
108 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
109 { -1, -1 }
110 };
111
112 static int get_para_features(KVMState *s)
113 {
114 int i, features = 0;
115
116 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
117 if (kvm_check_extension(s, para_features[i].cap)) {
118 features |= (1 << para_features[i].feature);
119 }
120 }
121
122 return features;
123 }
124
125
126 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
127 uint32_t index, int reg)
128 {
129 struct kvm_cpuid2 *cpuid;
130 int i, max;
131 uint32_t ret = 0;
132 uint32_t cpuid_1_edx;
133 bool found = false;
134
135 max = 1;
136 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
137 max *= 2;
138 }
139
140 for (i = 0; i < cpuid->nent; ++i) {
141 if (cpuid->entries[i].function == function &&
142 cpuid->entries[i].index == index) {
143 found = true;
144 switch (reg) {
145 case R_EAX:
146 ret = cpuid->entries[i].eax;
147 break;
148 case R_EBX:
149 ret = cpuid->entries[i].ebx;
150 break;
151 case R_ECX:
152 ret = cpuid->entries[i].ecx;
153 break;
154 case R_EDX:
155 ret = cpuid->entries[i].edx;
156 break;
157 }
158 }
159 }
160
161 /* Fixups for the data returned by KVM, below */
162
163 if (reg == R_EDX) {
164 switch (function) {
165 case 1:
166 /* KVM before 2.6.30 misreports the following features */
167 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
168 break;
169 case 0x80000001:
170 /* On Intel, kvm returns cpuid according to the Intel spec,
171 * so add missing bits according to the AMD spec:
172 */
173 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
174 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
175 break;
176 }
177 }
178
179 g_free(cpuid);
180
181 /* fallback for older kernels */
182 if ((function == KVM_CPUID_FEATURES) && !found) {
183 ret = get_para_features(s);
184 }
185
186 return ret;
187 }
188
189 typedef struct HWPoisonPage {
190 ram_addr_t ram_addr;
191 QLIST_ENTRY(HWPoisonPage) list;
192 } HWPoisonPage;
193
194 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
195 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
196
197 static void kvm_unpoison_all(void *param)
198 {
199 HWPoisonPage *page, *next_page;
200
201 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
202 QLIST_REMOVE(page, list);
203 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
204 g_free(page);
205 }
206 }
207
208 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
209 {
210 HWPoisonPage *page;
211
212 QLIST_FOREACH(page, &hwpoison_page_list, list) {
213 if (page->ram_addr == ram_addr) {
214 return;
215 }
216 }
217 page = g_malloc(sizeof(HWPoisonPage));
218 page->ram_addr = ram_addr;
219 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
220 }
221
222 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
223 int *max_banks)
224 {
225 int r;
226
227 r = kvm_check_extension(s, KVM_CAP_MCE);
228 if (r > 0) {
229 *max_banks = r;
230 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
231 }
232 return -ENOSYS;
233 }
234
235 static void kvm_mce_inject(CPUX86State *env, hwaddr paddr, int code)
236 {
237 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
238 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
239 uint64_t mcg_status = MCG_STATUS_MCIP;
240
241 if (code == BUS_MCEERR_AR) {
242 status |= MCI_STATUS_AR | 0x134;
243 mcg_status |= MCG_STATUS_EIPV;
244 } else {
245 status |= 0xc0;
246 mcg_status |= MCG_STATUS_RIPV;
247 }
248 cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
249 (MCM_ADDR_PHYS << 6) | 0xc,
250 cpu_x86_support_mca_broadcast(env) ?
251 MCE_INJECT_BROADCAST : 0);
252 }
253
254 static void hardware_memory_error(void)
255 {
256 fprintf(stderr, "Hardware memory error!\n");
257 exit(1);
258 }
259
260 int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
261 {
262 ram_addr_t ram_addr;
263 hwaddr paddr;
264
265 if ((env->mcg_cap & MCG_SER_P) && addr
266 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
267 if (qemu_ram_addr_from_host(addr, &ram_addr) ||
268 !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
269 fprintf(stderr, "Hardware memory error for memory used by "
270 "QEMU itself instead of guest system!\n");
271 /* Hope we are lucky for AO MCE */
272 if (code == BUS_MCEERR_AO) {
273 return 0;
274 } else {
275 hardware_memory_error();
276 }
277 }
278 kvm_hwpoison_page_add(ram_addr);
279 kvm_mce_inject(env, paddr, code);
280 } else {
281 if (code == BUS_MCEERR_AO) {
282 return 0;
283 } else if (code == BUS_MCEERR_AR) {
284 hardware_memory_error();
285 } else {
286 return 1;
287 }
288 }
289 return 0;
290 }
291
292 int kvm_arch_on_sigbus(int code, void *addr)
293 {
294 if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
295 ram_addr_t ram_addr;
296 hwaddr paddr;
297
298 /* Hope we are lucky for AO MCE */
299 if (qemu_ram_addr_from_host(addr, &ram_addr) ||
300 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
301 &paddr)) {
302 fprintf(stderr, "Hardware memory error for memory used by "
303 "QEMU itself instead of guest system!: %p\n", addr);
304 return 0;
305 }
306 kvm_hwpoison_page_add(ram_addr);
307 kvm_mce_inject(first_cpu, paddr, code);
308 } else {
309 if (code == BUS_MCEERR_AO) {
310 return 0;
311 } else if (code == BUS_MCEERR_AR) {
312 hardware_memory_error();
313 } else {
314 return 1;
315 }
316 }
317 return 0;
318 }
319
320 static int kvm_inject_mce_oldstyle(CPUX86State *env)
321 {
322 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
323 unsigned int bank, bank_num = env->mcg_cap & 0xff;
324 struct kvm_x86_mce mce;
325
326 env->exception_injected = -1;
327
328 /*
329 * There must be at least one bank in use if an MCE is pending.
330 * Find it and use its values for the event injection.
331 */
332 for (bank = 0; bank < bank_num; bank++) {
333 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
334 break;
335 }
336 }
337 assert(bank < bank_num);
338
339 mce.bank = bank;
340 mce.status = env->mce_banks[bank * 4 + 1];
341 mce.mcg_status = env->mcg_status;
342 mce.addr = env->mce_banks[bank * 4 + 2];
343 mce.misc = env->mce_banks[bank * 4 + 3];
344
345 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
346 }
347 return 0;
348 }
349
350 static void cpu_update_state(void *opaque, int running, RunState state)
351 {
352 CPUX86State *env = opaque;
353
354 if (running) {
355 env->tsc_valid = false;
356 }
357 }
358
359 int kvm_arch_init_vcpu(CPUX86State *env)
360 {
361 struct {
362 struct kvm_cpuid2 cpuid;
363 struct kvm_cpuid_entry2 entries[100];
364 } QEMU_PACKED cpuid_data;
365 KVMState *s = env->kvm_state;
366 uint32_t limit, i, j, cpuid_i;
367 uint32_t unused;
368 struct kvm_cpuid_entry2 *c;
369 uint32_t signature[3];
370 int r;
371
372 env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
373
374 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
375 j = env->cpuid_ext_features & CPUID_EXT_TSC_DEADLINE_TIMER;
376 env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
377 env->cpuid_ext_features |= i;
378 if (j && kvm_irqchip_in_kernel() &&
379 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
380 env->cpuid_ext_features |= CPUID_EXT_TSC_DEADLINE_TIMER;
381 }
382
383 env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
384 0, R_EDX);
385 env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
386 0, R_ECX);
387 env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
388 0, R_EDX);
389
390 cpuid_i = 0;
391
392 /* Paravirtualization CPUIDs */
393 c = &cpuid_data.entries[cpuid_i++];
394 memset(c, 0, sizeof(*c));
395 c->function = KVM_CPUID_SIGNATURE;
396 if (!hyperv_enabled()) {
397 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
398 c->eax = 0;
399 } else {
400 memcpy(signature, "Microsoft Hv", 12);
401 c->eax = HYPERV_CPUID_MIN;
402 }
403 c->ebx = signature[0];
404 c->ecx = signature[1];
405 c->edx = signature[2];
406
407 c = &cpuid_data.entries[cpuid_i++];
408 memset(c, 0, sizeof(*c));
409 c->function = KVM_CPUID_FEATURES;
410 c->eax = env->cpuid_kvm_features &
411 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
412
413 if (hyperv_enabled()) {
414 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
415 c->eax = signature[0];
416
417 c = &cpuid_data.entries[cpuid_i++];
418 memset(c, 0, sizeof(*c));
419 c->function = HYPERV_CPUID_VERSION;
420 c->eax = 0x00001bbc;
421 c->ebx = 0x00060001;
422
423 c = &cpuid_data.entries[cpuid_i++];
424 memset(c, 0, sizeof(*c));
425 c->function = HYPERV_CPUID_FEATURES;
426 if (hyperv_relaxed_timing_enabled()) {
427 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
428 }
429 if (hyperv_vapic_recommended()) {
430 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
431 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
432 }
433
434 c = &cpuid_data.entries[cpuid_i++];
435 memset(c, 0, sizeof(*c));
436 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
437 if (hyperv_relaxed_timing_enabled()) {
438 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
439 }
440 if (hyperv_vapic_recommended()) {
441 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
442 }
443 c->ebx = hyperv_get_spinlock_retries();
444
445 c = &cpuid_data.entries[cpuid_i++];
446 memset(c, 0, sizeof(*c));
447 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
448 c->eax = 0x40;
449 c->ebx = 0x40;
450
451 c = &cpuid_data.entries[cpuid_i++];
452 memset(c, 0, sizeof(*c));
453 c->function = KVM_CPUID_SIGNATURE_NEXT;
454 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
455 c->eax = 0;
456 c->ebx = signature[0];
457 c->ecx = signature[1];
458 c->edx = signature[2];
459 }
460
461 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
462
463 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
464
465 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
466
467 for (i = 0; i <= limit; i++) {
468 c = &cpuid_data.entries[cpuid_i++];
469
470 switch (i) {
471 case 2: {
472 /* Keep reading function 2 till all the input is received */
473 int times;
474
475 c->function = i;
476 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
477 KVM_CPUID_FLAG_STATE_READ_NEXT;
478 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
479 times = c->eax & 0xff;
480
481 for (j = 1; j < times; ++j) {
482 c = &cpuid_data.entries[cpuid_i++];
483 c->function = i;
484 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
485 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486 }
487 break;
488 }
489 case 4:
490 case 0xb:
491 case 0xd:
492 for (j = 0; ; j++) {
493 if (i == 0xd && j == 64) {
494 break;
495 }
496 c->function = i;
497 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
498 c->index = j;
499 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
500
501 if (i == 4 && c->eax == 0) {
502 break;
503 }
504 if (i == 0xb && !(c->ecx & 0xff00)) {
505 break;
506 }
507 if (i == 0xd && c->eax == 0) {
508 continue;
509 }
510 c = &cpuid_data.entries[cpuid_i++];
511 }
512 break;
513 default:
514 c->function = i;
515 c->flags = 0;
516 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
517 break;
518 }
519 }
520 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
521
522 for (i = 0x80000000; i <= limit; i++) {
523 c = &cpuid_data.entries[cpuid_i++];
524
525 c->function = i;
526 c->flags = 0;
527 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
528 }
529
530 /* Call Centaur's CPUID instructions they are supported. */
531 if (env->cpuid_xlevel2 > 0) {
532 env->cpuid_ext4_features &=
533 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
534 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
535
536 for (i = 0xC0000000; i <= limit; i++) {
537 c = &cpuid_data.entries[cpuid_i++];
538
539 c->function = i;
540 c->flags = 0;
541 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
542 }
543 }
544
545 cpuid_data.cpuid.nent = cpuid_i;
546
547 if (((env->cpuid_version >> 8)&0xF) >= 6
548 && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
549 && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
550 uint64_t mcg_cap;
551 int banks;
552 int ret;
553
554 ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
555 if (ret < 0) {
556 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
557 return ret;
558 }
559
560 if (banks > MCE_BANKS_DEF) {
561 banks = MCE_BANKS_DEF;
562 }
563 mcg_cap &= MCE_CAP_DEF;
564 mcg_cap |= banks;
565 ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
566 if (ret < 0) {
567 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
568 return ret;
569 }
570
571 env->mcg_cap = mcg_cap;
572 }
573
574 qemu_add_vm_change_state_handler(cpu_update_state, env);
575
576 cpuid_data.cpuid.padding = 0;
577 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
578 if (r) {
579 return r;
580 }
581
582 r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
583 if (r && env->tsc_khz) {
584 r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
585 if (r < 0) {
586 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
587 return r;
588 }
589 }
590
591 if (kvm_has_xsave()) {
592 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
593 }
594
595 return 0;
596 }
597
598 void kvm_arch_reset_vcpu(CPUX86State *env)
599 {
600 X86CPU *cpu = x86_env_get_cpu(env);
601
602 env->exception_injected = -1;
603 env->interrupt_injected = -1;
604 env->xcr0 = 1;
605 if (kvm_irqchip_in_kernel()) {
606 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
607 KVM_MP_STATE_UNINITIALIZED;
608 } else {
609 env->mp_state = KVM_MP_STATE_RUNNABLE;
610 }
611 }
612
613 static int kvm_get_supported_msrs(KVMState *s)
614 {
615 static int kvm_supported_msrs;
616 int ret = 0;
617
618 /* first time */
619 if (kvm_supported_msrs == 0) {
620 struct kvm_msr_list msr_list, *kvm_msr_list;
621
622 kvm_supported_msrs = -1;
623
624 /* Obtain MSR list from KVM. These are the MSRs that we must
625 * save/restore */
626 msr_list.nmsrs = 0;
627 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
628 if (ret < 0 && ret != -E2BIG) {
629 return ret;
630 }
631 /* Old kernel modules had a bug and could write beyond the provided
632 memory. Allocate at least a safe amount of 1K. */
633 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
634 msr_list.nmsrs *
635 sizeof(msr_list.indices[0])));
636
637 kvm_msr_list->nmsrs = msr_list.nmsrs;
638 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
639 if (ret >= 0) {
640 int i;
641
642 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
643 if (kvm_msr_list->indices[i] == MSR_STAR) {
644 has_msr_star = true;
645 continue;
646 }
647 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
648 has_msr_hsave_pa = true;
649 continue;
650 }
651 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
652 has_msr_tsc_deadline = true;
653 continue;
654 }
655 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
656 has_msr_misc_enable = true;
657 continue;
658 }
659 }
660 }
661
662 g_free(kvm_msr_list);
663 }
664
665 return ret;
666 }
667
668 int kvm_arch_init(KVMState *s)
669 {
670 QemuOptsList *list = qemu_find_opts("machine");
671 uint64_t identity_base = 0xfffbc000;
672 uint64_t shadow_mem;
673 int ret;
674 struct utsname utsname;
675
676 ret = kvm_get_supported_msrs(s);
677 if (ret < 0) {
678 return ret;
679 }
680
681 uname(&utsname);
682 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
683
684 /*
685 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
686 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
687 * Since these must be part of guest physical memory, we need to allocate
688 * them, both by setting their start addresses in the kernel and by
689 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
690 *
691 * Older KVM versions may not support setting the identity map base. In
692 * that case we need to stick with the default, i.e. a 256K maximum BIOS
693 * size.
694 */
695 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
696 /* Allows up to 16M BIOSes. */
697 identity_base = 0xfeffc000;
698
699 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
700 if (ret < 0) {
701 return ret;
702 }
703 }
704
705 /* Set TSS base one page after EPT identity map. */
706 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
707 if (ret < 0) {
708 return ret;
709 }
710
711 /* Tell fw_cfg to notify the BIOS to reserve the range. */
712 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
713 if (ret < 0) {
714 fprintf(stderr, "e820_add_entry() table is full\n");
715 return ret;
716 }
717 qemu_register_reset(kvm_unpoison_all, NULL);
718
719 if (!QTAILQ_EMPTY(&list->head)) {
720 shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
721 "kvm_shadow_mem", -1);
722 if (shadow_mem != -1) {
723 shadow_mem /= 4096;
724 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
725 if (ret < 0) {
726 return ret;
727 }
728 }
729 }
730 return 0;
731 }
732
733 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
734 {
735 lhs->selector = rhs->selector;
736 lhs->base = rhs->base;
737 lhs->limit = rhs->limit;
738 lhs->type = 3;
739 lhs->present = 1;
740 lhs->dpl = 3;
741 lhs->db = 0;
742 lhs->s = 1;
743 lhs->l = 0;
744 lhs->g = 0;
745 lhs->avl = 0;
746 lhs->unusable = 0;
747 }
748
749 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
750 {
751 unsigned flags = rhs->flags;
752 lhs->selector = rhs->selector;
753 lhs->base = rhs->base;
754 lhs->limit = rhs->limit;
755 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
756 lhs->present = (flags & DESC_P_MASK) != 0;
757 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
758 lhs->db = (flags >> DESC_B_SHIFT) & 1;
759 lhs->s = (flags & DESC_S_MASK) != 0;
760 lhs->l = (flags >> DESC_L_SHIFT) & 1;
761 lhs->g = (flags & DESC_G_MASK) != 0;
762 lhs->avl = (flags & DESC_AVL_MASK) != 0;
763 lhs->unusable = 0;
764 lhs->padding = 0;
765 }
766
767 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
768 {
769 lhs->selector = rhs->selector;
770 lhs->base = rhs->base;
771 lhs->limit = rhs->limit;
772 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
773 (rhs->present * DESC_P_MASK) |
774 (rhs->dpl << DESC_DPL_SHIFT) |
775 (rhs->db << DESC_B_SHIFT) |
776 (rhs->s * DESC_S_MASK) |
777 (rhs->l << DESC_L_SHIFT) |
778 (rhs->g * DESC_G_MASK) |
779 (rhs->avl * DESC_AVL_MASK);
780 }
781
782 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
783 {
784 if (set) {
785 *kvm_reg = *qemu_reg;
786 } else {
787 *qemu_reg = *kvm_reg;
788 }
789 }
790
791 static int kvm_getput_regs(CPUX86State *env, int set)
792 {
793 struct kvm_regs regs;
794 int ret = 0;
795
796 if (!set) {
797 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
798 if (ret < 0) {
799 return ret;
800 }
801 }
802
803 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
804 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
805 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
806 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
807 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
808 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
809 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
810 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
811 #ifdef TARGET_X86_64
812 kvm_getput_reg(&regs.r8, &env->regs[8], set);
813 kvm_getput_reg(&regs.r9, &env->regs[9], set);
814 kvm_getput_reg(&regs.r10, &env->regs[10], set);
815 kvm_getput_reg(&regs.r11, &env->regs[11], set);
816 kvm_getput_reg(&regs.r12, &env->regs[12], set);
817 kvm_getput_reg(&regs.r13, &env->regs[13], set);
818 kvm_getput_reg(&regs.r14, &env->regs[14], set);
819 kvm_getput_reg(&regs.r15, &env->regs[15], set);
820 #endif
821
822 kvm_getput_reg(&regs.rflags, &env->eflags, set);
823 kvm_getput_reg(&regs.rip, &env->eip, set);
824
825 if (set) {
826 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
827 }
828
829 return ret;
830 }
831
832 static int kvm_put_fpu(CPUX86State *env)
833 {
834 struct kvm_fpu fpu;
835 int i;
836
837 memset(&fpu, 0, sizeof fpu);
838 fpu.fsw = env->fpus & ~(7 << 11);
839 fpu.fsw |= (env->fpstt & 7) << 11;
840 fpu.fcw = env->fpuc;
841 fpu.last_opcode = env->fpop;
842 fpu.last_ip = env->fpip;
843 fpu.last_dp = env->fpdp;
844 for (i = 0; i < 8; ++i) {
845 fpu.ftwx |= (!env->fptags[i]) << i;
846 }
847 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
848 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
849 fpu.mxcsr = env->mxcsr;
850
851 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
852 }
853
854 #define XSAVE_FCW_FSW 0
855 #define XSAVE_FTW_FOP 1
856 #define XSAVE_CWD_RIP 2
857 #define XSAVE_CWD_RDP 4
858 #define XSAVE_MXCSR 6
859 #define XSAVE_ST_SPACE 8
860 #define XSAVE_XMM_SPACE 40
861 #define XSAVE_XSTATE_BV 128
862 #define XSAVE_YMMH_SPACE 144
863
864 static int kvm_put_xsave(CPUX86State *env)
865 {
866 struct kvm_xsave* xsave = env->kvm_xsave_buf;
867 uint16_t cwd, swd, twd;
868 int i, r;
869
870 if (!kvm_has_xsave()) {
871 return kvm_put_fpu(env);
872 }
873
874 memset(xsave, 0, sizeof(struct kvm_xsave));
875 twd = 0;
876 swd = env->fpus & ~(7 << 11);
877 swd |= (env->fpstt & 7) << 11;
878 cwd = env->fpuc;
879 for (i = 0; i < 8; ++i) {
880 twd |= (!env->fptags[i]) << i;
881 }
882 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
883 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
884 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
885 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
886 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
887 sizeof env->fpregs);
888 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
889 sizeof env->xmm_regs);
890 xsave->region[XSAVE_MXCSR] = env->mxcsr;
891 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
892 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
893 sizeof env->ymmh_regs);
894 r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
895 return r;
896 }
897
898 static int kvm_put_xcrs(CPUX86State *env)
899 {
900 struct kvm_xcrs xcrs;
901
902 if (!kvm_has_xcrs()) {
903 return 0;
904 }
905
906 xcrs.nr_xcrs = 1;
907 xcrs.flags = 0;
908 xcrs.xcrs[0].xcr = 0;
909 xcrs.xcrs[0].value = env->xcr0;
910 return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
911 }
912
913 static int kvm_put_sregs(CPUX86State *env)
914 {
915 struct kvm_sregs sregs;
916
917 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
918 if (env->interrupt_injected >= 0) {
919 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
920 (uint64_t)1 << (env->interrupt_injected % 64);
921 }
922
923 if ((env->eflags & VM_MASK)) {
924 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
925 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
926 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
927 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
928 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
929 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
930 } else {
931 set_seg(&sregs.cs, &env->segs[R_CS]);
932 set_seg(&sregs.ds, &env->segs[R_DS]);
933 set_seg(&sregs.es, &env->segs[R_ES]);
934 set_seg(&sregs.fs, &env->segs[R_FS]);
935 set_seg(&sregs.gs, &env->segs[R_GS]);
936 set_seg(&sregs.ss, &env->segs[R_SS]);
937 }
938
939 set_seg(&sregs.tr, &env->tr);
940 set_seg(&sregs.ldt, &env->ldt);
941
942 sregs.idt.limit = env->idt.limit;
943 sregs.idt.base = env->idt.base;
944 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
945 sregs.gdt.limit = env->gdt.limit;
946 sregs.gdt.base = env->gdt.base;
947 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
948
949 sregs.cr0 = env->cr[0];
950 sregs.cr2 = env->cr[2];
951 sregs.cr3 = env->cr[3];
952 sregs.cr4 = env->cr[4];
953
954 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
955 sregs.apic_base = cpu_get_apic_base(env->apic_state);
956
957 sregs.efer = env->efer;
958
959 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
960 }
961
962 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
963 uint32_t index, uint64_t value)
964 {
965 entry->index = index;
966 entry->data = value;
967 }
968
969 static int kvm_put_msrs(CPUX86State *env, int level)
970 {
971 struct {
972 struct kvm_msrs info;
973 struct kvm_msr_entry entries[100];
974 } msr_data;
975 struct kvm_msr_entry *msrs = msr_data.entries;
976 int n = 0;
977
978 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
979 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
980 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
981 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
982 if (has_msr_star) {
983 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
984 }
985 if (has_msr_hsave_pa) {
986 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
987 }
988 if (has_msr_tsc_deadline) {
989 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
990 }
991 if (has_msr_misc_enable) {
992 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
993 env->msr_ia32_misc_enable);
994 }
995 #ifdef TARGET_X86_64
996 if (lm_capable_kernel) {
997 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
998 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
999 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1000 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1001 }
1002 #endif
1003 if (level == KVM_PUT_FULL_STATE) {
1004 /*
1005 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1006 * writeback. Until this is fixed, we only write the offset to SMP
1007 * guests after migration, desynchronizing the VCPUs, but avoiding
1008 * huge jump-backs that would occur without any writeback at all.
1009 */
1010 if (smp_cpus == 1 || env->tsc != 0) {
1011 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1012 }
1013 }
1014 /*
1015 * The following paravirtual MSRs have side effects on the guest or are
1016 * too heavy for normal writeback. Limit them to reset or full state
1017 * updates.
1018 */
1019 if (level >= KVM_PUT_RESET_STATE) {
1020 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1021 env->system_time_msr);
1022 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1023 if (has_msr_async_pf_en) {
1024 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1025 env->async_pf_en_msr);
1026 }
1027 if (has_msr_pv_eoi_en) {
1028 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1029 env->pv_eoi_en_msr);
1030 }
1031 if (hyperv_hypercall_available()) {
1032 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1033 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1034 }
1035 if (hyperv_vapic_recommended()) {
1036 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1037 }
1038 }
1039 if (env->mcg_cap) {
1040 int i;
1041
1042 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1043 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1044 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1045 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1046 }
1047 }
1048
1049 msr_data.info.nmsrs = n;
1050
1051 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1052
1053 }
1054
1055
1056 static int kvm_get_fpu(CPUX86State *env)
1057 {
1058 struct kvm_fpu fpu;
1059 int i, ret;
1060
1061 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1062 if (ret < 0) {
1063 return ret;
1064 }
1065
1066 env->fpstt = (fpu.fsw >> 11) & 7;
1067 env->fpus = fpu.fsw;
1068 env->fpuc = fpu.fcw;
1069 env->fpop = fpu.last_opcode;
1070 env->fpip = fpu.last_ip;
1071 env->fpdp = fpu.last_dp;
1072 for (i = 0; i < 8; ++i) {
1073 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1074 }
1075 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1076 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1077 env->mxcsr = fpu.mxcsr;
1078
1079 return 0;
1080 }
1081
1082 static int kvm_get_xsave(CPUX86State *env)
1083 {
1084 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1085 int ret, i;
1086 uint16_t cwd, swd, twd;
1087
1088 if (!kvm_has_xsave()) {
1089 return kvm_get_fpu(env);
1090 }
1091
1092 ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1093 if (ret < 0) {
1094 return ret;
1095 }
1096
1097 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1098 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1099 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1100 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1101 env->fpstt = (swd >> 11) & 7;
1102 env->fpus = swd;
1103 env->fpuc = cwd;
1104 for (i = 0; i < 8; ++i) {
1105 env->fptags[i] = !((twd >> i) & 1);
1106 }
1107 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1108 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1109 env->mxcsr = xsave->region[XSAVE_MXCSR];
1110 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1111 sizeof env->fpregs);
1112 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1113 sizeof env->xmm_regs);
1114 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1115 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1116 sizeof env->ymmh_regs);
1117 return 0;
1118 }
1119
1120 static int kvm_get_xcrs(CPUX86State *env)
1121 {
1122 int i, ret;
1123 struct kvm_xcrs xcrs;
1124
1125 if (!kvm_has_xcrs()) {
1126 return 0;
1127 }
1128
1129 ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1130 if (ret < 0) {
1131 return ret;
1132 }
1133
1134 for (i = 0; i < xcrs.nr_xcrs; i++) {
1135 /* Only support xcr0 now */
1136 if (xcrs.xcrs[0].xcr == 0) {
1137 env->xcr0 = xcrs.xcrs[0].value;
1138 break;
1139 }
1140 }
1141 return 0;
1142 }
1143
1144 static int kvm_get_sregs(CPUX86State *env)
1145 {
1146 struct kvm_sregs sregs;
1147 uint32_t hflags;
1148 int bit, i, ret;
1149
1150 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1151 if (ret < 0) {
1152 return ret;
1153 }
1154
1155 /* There can only be one pending IRQ set in the bitmap at a time, so try
1156 to find it and save its number instead (-1 for none). */
1157 env->interrupt_injected = -1;
1158 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1159 if (sregs.interrupt_bitmap[i]) {
1160 bit = ctz64(sregs.interrupt_bitmap[i]);
1161 env->interrupt_injected = i * 64 + bit;
1162 break;
1163 }
1164 }
1165
1166 get_seg(&env->segs[R_CS], &sregs.cs);
1167 get_seg(&env->segs[R_DS], &sregs.ds);
1168 get_seg(&env->segs[R_ES], &sregs.es);
1169 get_seg(&env->segs[R_FS], &sregs.fs);
1170 get_seg(&env->segs[R_GS], &sregs.gs);
1171 get_seg(&env->segs[R_SS], &sregs.ss);
1172
1173 get_seg(&env->tr, &sregs.tr);
1174 get_seg(&env->ldt, &sregs.ldt);
1175
1176 env->idt.limit = sregs.idt.limit;
1177 env->idt.base = sregs.idt.base;
1178 env->gdt.limit = sregs.gdt.limit;
1179 env->gdt.base = sregs.gdt.base;
1180
1181 env->cr[0] = sregs.cr0;
1182 env->cr[2] = sregs.cr2;
1183 env->cr[3] = sregs.cr3;
1184 env->cr[4] = sregs.cr4;
1185
1186 env->efer = sregs.efer;
1187
1188 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1189
1190 #define HFLAG_COPY_MASK \
1191 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1192 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1193 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1194 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1195
1196 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1197 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1198 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1199 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1200 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1201 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1202 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1203
1204 if (env->efer & MSR_EFER_LMA) {
1205 hflags |= HF_LMA_MASK;
1206 }
1207
1208 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1209 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1210 } else {
1211 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1212 (DESC_B_SHIFT - HF_CS32_SHIFT);
1213 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1214 (DESC_B_SHIFT - HF_SS32_SHIFT);
1215 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1216 !(hflags & HF_CS32_MASK)) {
1217 hflags |= HF_ADDSEG_MASK;
1218 } else {
1219 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1220 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1221 }
1222 }
1223 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1224
1225 return 0;
1226 }
1227
1228 static int kvm_get_msrs(CPUX86State *env)
1229 {
1230 struct {
1231 struct kvm_msrs info;
1232 struct kvm_msr_entry entries[100];
1233 } msr_data;
1234 struct kvm_msr_entry *msrs = msr_data.entries;
1235 int ret, i, n;
1236
1237 n = 0;
1238 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1239 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1240 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1241 msrs[n++].index = MSR_PAT;
1242 if (has_msr_star) {
1243 msrs[n++].index = MSR_STAR;
1244 }
1245 if (has_msr_hsave_pa) {
1246 msrs[n++].index = MSR_VM_HSAVE_PA;
1247 }
1248 if (has_msr_tsc_deadline) {
1249 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1250 }
1251 if (has_msr_misc_enable) {
1252 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1253 }
1254
1255 if (!env->tsc_valid) {
1256 msrs[n++].index = MSR_IA32_TSC;
1257 env->tsc_valid = !runstate_is_running();
1258 }
1259
1260 #ifdef TARGET_X86_64
1261 if (lm_capable_kernel) {
1262 msrs[n++].index = MSR_CSTAR;
1263 msrs[n++].index = MSR_KERNELGSBASE;
1264 msrs[n++].index = MSR_FMASK;
1265 msrs[n++].index = MSR_LSTAR;
1266 }
1267 #endif
1268 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1269 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1270 if (has_msr_async_pf_en) {
1271 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1272 }
1273 if (has_msr_pv_eoi_en) {
1274 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1275 }
1276
1277 if (env->mcg_cap) {
1278 msrs[n++].index = MSR_MCG_STATUS;
1279 msrs[n++].index = MSR_MCG_CTL;
1280 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1281 msrs[n++].index = MSR_MC0_CTL + i;
1282 }
1283 }
1284
1285 msr_data.info.nmsrs = n;
1286 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1287 if (ret < 0) {
1288 return ret;
1289 }
1290
1291 for (i = 0; i < ret; i++) {
1292 switch (msrs[i].index) {
1293 case MSR_IA32_SYSENTER_CS:
1294 env->sysenter_cs = msrs[i].data;
1295 break;
1296 case MSR_IA32_SYSENTER_ESP:
1297 env->sysenter_esp = msrs[i].data;
1298 break;
1299 case MSR_IA32_SYSENTER_EIP:
1300 env->sysenter_eip = msrs[i].data;
1301 break;
1302 case MSR_PAT:
1303 env->pat = msrs[i].data;
1304 break;
1305 case MSR_STAR:
1306 env->star = msrs[i].data;
1307 break;
1308 #ifdef TARGET_X86_64
1309 case MSR_CSTAR:
1310 env->cstar = msrs[i].data;
1311 break;
1312 case MSR_KERNELGSBASE:
1313 env->kernelgsbase = msrs[i].data;
1314 break;
1315 case MSR_FMASK:
1316 env->fmask = msrs[i].data;
1317 break;
1318 case MSR_LSTAR:
1319 env->lstar = msrs[i].data;
1320 break;
1321 #endif
1322 case MSR_IA32_TSC:
1323 env->tsc = msrs[i].data;
1324 break;
1325 case MSR_IA32_TSCDEADLINE:
1326 env->tsc_deadline = msrs[i].data;
1327 break;
1328 case MSR_VM_HSAVE_PA:
1329 env->vm_hsave = msrs[i].data;
1330 break;
1331 case MSR_KVM_SYSTEM_TIME:
1332 env->system_time_msr = msrs[i].data;
1333 break;
1334 case MSR_KVM_WALL_CLOCK:
1335 env->wall_clock_msr = msrs[i].data;
1336 break;
1337 case MSR_MCG_STATUS:
1338 env->mcg_status = msrs[i].data;
1339 break;
1340 case MSR_MCG_CTL:
1341 env->mcg_ctl = msrs[i].data;
1342 break;
1343 case MSR_IA32_MISC_ENABLE:
1344 env->msr_ia32_misc_enable = msrs[i].data;
1345 break;
1346 default:
1347 if (msrs[i].index >= MSR_MC0_CTL &&
1348 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1349 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1350 }
1351 break;
1352 case MSR_KVM_ASYNC_PF_EN:
1353 env->async_pf_en_msr = msrs[i].data;
1354 break;
1355 case MSR_KVM_PV_EOI_EN:
1356 env->pv_eoi_en_msr = msrs[i].data;
1357 break;
1358 }
1359 }
1360
1361 return 0;
1362 }
1363
1364 static int kvm_put_mp_state(CPUX86State *env)
1365 {
1366 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1367
1368 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1369 }
1370
1371 static int kvm_get_mp_state(CPUX86State *env)
1372 {
1373 struct kvm_mp_state mp_state;
1374 int ret;
1375
1376 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1377 if (ret < 0) {
1378 return ret;
1379 }
1380 env->mp_state = mp_state.mp_state;
1381 if (kvm_irqchip_in_kernel()) {
1382 env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1383 }
1384 return 0;
1385 }
1386
1387 static int kvm_get_apic(CPUX86State *env)
1388 {
1389 DeviceState *apic = env->apic_state;
1390 struct kvm_lapic_state kapic;
1391 int ret;
1392
1393 if (apic && kvm_irqchip_in_kernel()) {
1394 ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1395 if (ret < 0) {
1396 return ret;
1397 }
1398
1399 kvm_get_apic_state(apic, &kapic);
1400 }
1401 return 0;
1402 }
1403
1404 static int kvm_put_apic(CPUX86State *env)
1405 {
1406 DeviceState *apic = env->apic_state;
1407 struct kvm_lapic_state kapic;
1408
1409 if (apic && kvm_irqchip_in_kernel()) {
1410 kvm_put_apic_state(apic, &kapic);
1411
1412 return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1413 }
1414 return 0;
1415 }
1416
1417 static int kvm_put_vcpu_events(CPUX86State *env, int level)
1418 {
1419 struct kvm_vcpu_events events;
1420
1421 if (!kvm_has_vcpu_events()) {
1422 return 0;
1423 }
1424
1425 events.exception.injected = (env->exception_injected >= 0);
1426 events.exception.nr = env->exception_injected;
1427 events.exception.has_error_code = env->has_error_code;
1428 events.exception.error_code = env->error_code;
1429 events.exception.pad = 0;
1430
1431 events.interrupt.injected = (env->interrupt_injected >= 0);
1432 events.interrupt.nr = env->interrupt_injected;
1433 events.interrupt.soft = env->soft_interrupt;
1434
1435 events.nmi.injected = env->nmi_injected;
1436 events.nmi.pending = env->nmi_pending;
1437 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1438 events.nmi.pad = 0;
1439
1440 events.sipi_vector = env->sipi_vector;
1441
1442 events.flags = 0;
1443 if (level >= KVM_PUT_RESET_STATE) {
1444 events.flags |=
1445 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1446 }
1447
1448 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1449 }
1450
1451 static int kvm_get_vcpu_events(CPUX86State *env)
1452 {
1453 struct kvm_vcpu_events events;
1454 int ret;
1455
1456 if (!kvm_has_vcpu_events()) {
1457 return 0;
1458 }
1459
1460 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1461 if (ret < 0) {
1462 return ret;
1463 }
1464 env->exception_injected =
1465 events.exception.injected ? events.exception.nr : -1;
1466 env->has_error_code = events.exception.has_error_code;
1467 env->error_code = events.exception.error_code;
1468
1469 env->interrupt_injected =
1470 events.interrupt.injected ? events.interrupt.nr : -1;
1471 env->soft_interrupt = events.interrupt.soft;
1472
1473 env->nmi_injected = events.nmi.injected;
1474 env->nmi_pending = events.nmi.pending;
1475 if (events.nmi.masked) {
1476 env->hflags2 |= HF2_NMI_MASK;
1477 } else {
1478 env->hflags2 &= ~HF2_NMI_MASK;
1479 }
1480
1481 env->sipi_vector = events.sipi_vector;
1482
1483 return 0;
1484 }
1485
1486 static int kvm_guest_debug_workarounds(CPUX86State *env)
1487 {
1488 int ret = 0;
1489 unsigned long reinject_trap = 0;
1490
1491 if (!kvm_has_vcpu_events()) {
1492 if (env->exception_injected == 1) {
1493 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1494 } else if (env->exception_injected == 3) {
1495 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1496 }
1497 env->exception_injected = -1;
1498 }
1499
1500 /*
1501 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1502 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1503 * by updating the debug state once again if single-stepping is on.
1504 * Another reason to call kvm_update_guest_debug here is a pending debug
1505 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1506 * reinject them via SET_GUEST_DEBUG.
1507 */
1508 if (reinject_trap ||
1509 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1510 ret = kvm_update_guest_debug(env, reinject_trap);
1511 }
1512 return ret;
1513 }
1514
1515 static int kvm_put_debugregs(CPUX86State *env)
1516 {
1517 struct kvm_debugregs dbgregs;
1518 int i;
1519
1520 if (!kvm_has_debugregs()) {
1521 return 0;
1522 }
1523
1524 for (i = 0; i < 4; i++) {
1525 dbgregs.db[i] = env->dr[i];
1526 }
1527 dbgregs.dr6 = env->dr[6];
1528 dbgregs.dr7 = env->dr[7];
1529 dbgregs.flags = 0;
1530
1531 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1532 }
1533
1534 static int kvm_get_debugregs(CPUX86State *env)
1535 {
1536 struct kvm_debugregs dbgregs;
1537 int i, ret;
1538
1539 if (!kvm_has_debugregs()) {
1540 return 0;
1541 }
1542
1543 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1544 if (ret < 0) {
1545 return ret;
1546 }
1547 for (i = 0; i < 4; i++) {
1548 env->dr[i] = dbgregs.db[i];
1549 }
1550 env->dr[4] = env->dr[6] = dbgregs.dr6;
1551 env->dr[5] = env->dr[7] = dbgregs.dr7;
1552
1553 return 0;
1554 }
1555
1556 int kvm_arch_put_registers(CPUX86State *env, int level)
1557 {
1558 int ret;
1559
1560 assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1561
1562 ret = kvm_getput_regs(env, 1);
1563 if (ret < 0) {
1564 return ret;
1565 }
1566 ret = kvm_put_xsave(env);
1567 if (ret < 0) {
1568 return ret;
1569 }
1570 ret = kvm_put_xcrs(env);
1571 if (ret < 0) {
1572 return ret;
1573 }
1574 ret = kvm_put_sregs(env);
1575 if (ret < 0) {
1576 return ret;
1577 }
1578 /* must be before kvm_put_msrs */
1579 ret = kvm_inject_mce_oldstyle(env);
1580 if (ret < 0) {
1581 return ret;
1582 }
1583 ret = kvm_put_msrs(env, level);
1584 if (ret < 0) {
1585 return ret;
1586 }
1587 if (level >= KVM_PUT_RESET_STATE) {
1588 ret = kvm_put_mp_state(env);
1589 if (ret < 0) {
1590 return ret;
1591 }
1592 ret = kvm_put_apic(env);
1593 if (ret < 0) {
1594 return ret;
1595 }
1596 }
1597 ret = kvm_put_vcpu_events(env, level);
1598 if (ret < 0) {
1599 return ret;
1600 }
1601 ret = kvm_put_debugregs(env);
1602 if (ret < 0) {
1603 return ret;
1604 }
1605 /* must be last */
1606 ret = kvm_guest_debug_workarounds(env);
1607 if (ret < 0) {
1608 return ret;
1609 }
1610 return 0;
1611 }
1612
1613 int kvm_arch_get_registers(CPUX86State *env)
1614 {
1615 int ret;
1616
1617 assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1618
1619 ret = kvm_getput_regs(env, 0);
1620 if (ret < 0) {
1621 return ret;
1622 }
1623 ret = kvm_get_xsave(env);
1624 if (ret < 0) {
1625 return ret;
1626 }
1627 ret = kvm_get_xcrs(env);
1628 if (ret < 0) {
1629 return ret;
1630 }
1631 ret = kvm_get_sregs(env);
1632 if (ret < 0) {
1633 return ret;
1634 }
1635 ret = kvm_get_msrs(env);
1636 if (ret < 0) {
1637 return ret;
1638 }
1639 ret = kvm_get_mp_state(env);
1640 if (ret < 0) {
1641 return ret;
1642 }
1643 ret = kvm_get_apic(env);
1644 if (ret < 0) {
1645 return ret;
1646 }
1647 ret = kvm_get_vcpu_events(env);
1648 if (ret < 0) {
1649 return ret;
1650 }
1651 ret = kvm_get_debugregs(env);
1652 if (ret < 0) {
1653 return ret;
1654 }
1655 return 0;
1656 }
1657
1658 void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1659 {
1660 int ret;
1661
1662 /* Inject NMI */
1663 if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1664 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1665 DPRINTF("injected NMI\n");
1666 ret = kvm_vcpu_ioctl(env, KVM_NMI);
1667 if (ret < 0) {
1668 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1669 strerror(-ret));
1670 }
1671 }
1672
1673 if (!kvm_irqchip_in_kernel()) {
1674 /* Force the VCPU out of its inner loop to process any INIT requests
1675 * or pending TPR access reports. */
1676 if (env->interrupt_request &
1677 (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1678 env->exit_request = 1;
1679 }
1680
1681 /* Try to inject an interrupt if the guest can accept it */
1682 if (run->ready_for_interrupt_injection &&
1683 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1684 (env->eflags & IF_MASK)) {
1685 int irq;
1686
1687 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1688 irq = cpu_get_pic_interrupt(env);
1689 if (irq >= 0) {
1690 struct kvm_interrupt intr;
1691
1692 intr.irq = irq;
1693 DPRINTF("injected interrupt %d\n", irq);
1694 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1695 if (ret < 0) {
1696 fprintf(stderr,
1697 "KVM: injection failed, interrupt lost (%s)\n",
1698 strerror(-ret));
1699 }
1700 }
1701 }
1702
1703 /* If we have an interrupt but the guest is not ready to receive an
1704 * interrupt, request an interrupt window exit. This will
1705 * cause a return to userspace as soon as the guest is ready to
1706 * receive interrupts. */
1707 if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1708 run->request_interrupt_window = 1;
1709 } else {
1710 run->request_interrupt_window = 0;
1711 }
1712
1713 DPRINTF("setting tpr\n");
1714 run->cr8 = cpu_get_apic_tpr(env->apic_state);
1715 }
1716 }
1717
1718 void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1719 {
1720 if (run->if_flag) {
1721 env->eflags |= IF_MASK;
1722 } else {
1723 env->eflags &= ~IF_MASK;
1724 }
1725 cpu_set_apic_tpr(env->apic_state, run->cr8);
1726 cpu_set_apic_base(env->apic_state, run->apic_base);
1727 }
1728
1729 int kvm_arch_process_async_events(CPUX86State *env)
1730 {
1731 X86CPU *cpu = x86_env_get_cpu(env);
1732
1733 if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1734 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1735 assert(env->mcg_cap);
1736
1737 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1738
1739 kvm_cpu_synchronize_state(env);
1740
1741 if (env->exception_injected == EXCP08_DBLE) {
1742 /* this means triple fault */
1743 qemu_system_reset_request();
1744 env->exit_request = 1;
1745 return 0;
1746 }
1747 env->exception_injected = EXCP12_MCHK;
1748 env->has_error_code = 0;
1749
1750 env->halted = 0;
1751 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1752 env->mp_state = KVM_MP_STATE_RUNNABLE;
1753 }
1754 }
1755
1756 if (kvm_irqchip_in_kernel()) {
1757 return 0;
1758 }
1759
1760 if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1761 env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1762 apic_poll_irq(env->apic_state);
1763 }
1764 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1765 (env->eflags & IF_MASK)) ||
1766 (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1767 env->halted = 0;
1768 }
1769 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1770 kvm_cpu_synchronize_state(env);
1771 do_cpu_init(cpu);
1772 }
1773 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1774 kvm_cpu_synchronize_state(env);
1775 do_cpu_sipi(cpu);
1776 }
1777 if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1778 env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1779 kvm_cpu_synchronize_state(env);
1780 apic_handle_tpr_access_report(env->apic_state, env->eip,
1781 env->tpr_access_type);
1782 }
1783
1784 return env->halted;
1785 }
1786
1787 static int kvm_handle_halt(CPUX86State *env)
1788 {
1789 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1790 (env->eflags & IF_MASK)) &&
1791 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1792 env->halted = 1;
1793 return EXCP_HLT;
1794 }
1795
1796 return 0;
1797 }
1798
1799 static int kvm_handle_tpr_access(CPUX86State *env)
1800 {
1801 struct kvm_run *run = env->kvm_run;
1802
1803 apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1804 run->tpr_access.is_write ? TPR_ACCESS_WRITE
1805 : TPR_ACCESS_READ);
1806 return 1;
1807 }
1808
1809 int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1810 {
1811 static const uint8_t int3 = 0xcc;
1812
1813 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1814 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1815 return -EINVAL;
1816 }
1817 return 0;
1818 }
1819
1820 int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1821 {
1822 uint8_t int3;
1823
1824 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1825 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1826 return -EINVAL;
1827 }
1828 return 0;
1829 }
1830
1831 static struct {
1832 target_ulong addr;
1833 int len;
1834 int type;
1835 } hw_breakpoint[4];
1836
1837 static int nb_hw_breakpoint;
1838
1839 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1840 {
1841 int n;
1842
1843 for (n = 0; n < nb_hw_breakpoint; n++) {
1844 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1845 (hw_breakpoint[n].len == len || len == -1)) {
1846 return n;
1847 }
1848 }
1849 return -1;
1850 }
1851
1852 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1853 target_ulong len, int type)
1854 {
1855 switch (type) {
1856 case GDB_BREAKPOINT_HW:
1857 len = 1;
1858 break;
1859 case GDB_WATCHPOINT_WRITE:
1860 case GDB_WATCHPOINT_ACCESS:
1861 switch (len) {
1862 case 1:
1863 break;
1864 case 2:
1865 case 4:
1866 case 8:
1867 if (addr & (len - 1)) {
1868 return -EINVAL;
1869 }
1870 break;
1871 default:
1872 return -EINVAL;
1873 }
1874 break;
1875 default:
1876 return -ENOSYS;
1877 }
1878
1879 if (nb_hw_breakpoint == 4) {
1880 return -ENOBUFS;
1881 }
1882 if (find_hw_breakpoint(addr, len, type) >= 0) {
1883 return -EEXIST;
1884 }
1885 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1886 hw_breakpoint[nb_hw_breakpoint].len = len;
1887 hw_breakpoint[nb_hw_breakpoint].type = type;
1888 nb_hw_breakpoint++;
1889
1890 return 0;
1891 }
1892
1893 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1894 target_ulong len, int type)
1895 {
1896 int n;
1897
1898 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1899 if (n < 0) {
1900 return -ENOENT;
1901 }
1902 nb_hw_breakpoint--;
1903 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1904
1905 return 0;
1906 }
1907
1908 void kvm_arch_remove_all_hw_breakpoints(void)
1909 {
1910 nb_hw_breakpoint = 0;
1911 }
1912
1913 static CPUWatchpoint hw_watchpoint;
1914
1915 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1916 {
1917 int ret = 0;
1918 int n;
1919
1920 if (arch_info->exception == 1) {
1921 if (arch_info->dr6 & (1 << 14)) {
1922 if (cpu_single_env->singlestep_enabled) {
1923 ret = EXCP_DEBUG;
1924 }
1925 } else {
1926 for (n = 0; n < 4; n++) {
1927 if (arch_info->dr6 & (1 << n)) {
1928 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1929 case 0x0:
1930 ret = EXCP_DEBUG;
1931 break;
1932 case 0x1:
1933 ret = EXCP_DEBUG;
1934 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1935 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1936 hw_watchpoint.flags = BP_MEM_WRITE;
1937 break;
1938 case 0x3:
1939 ret = EXCP_DEBUG;
1940 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1941 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1942 hw_watchpoint.flags = BP_MEM_ACCESS;
1943 break;
1944 }
1945 }
1946 }
1947 }
1948 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1949 ret = EXCP_DEBUG;
1950 }
1951 if (ret == 0) {
1952 cpu_synchronize_state(cpu_single_env);
1953 assert(cpu_single_env->exception_injected == -1);
1954
1955 /* pass to guest */
1956 cpu_single_env->exception_injected = arch_info->exception;
1957 cpu_single_env->has_error_code = 0;
1958 }
1959
1960 return ret;
1961 }
1962
1963 void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
1964 {
1965 const uint8_t type_code[] = {
1966 [GDB_BREAKPOINT_HW] = 0x0,
1967 [GDB_WATCHPOINT_WRITE] = 0x1,
1968 [GDB_WATCHPOINT_ACCESS] = 0x3
1969 };
1970 const uint8_t len_code[] = {
1971 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1972 };
1973 int n;
1974
1975 if (kvm_sw_breakpoints_active(env)) {
1976 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1977 }
1978 if (nb_hw_breakpoint > 0) {
1979 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1980 dbg->arch.debugreg[7] = 0x0600;
1981 for (n = 0; n < nb_hw_breakpoint; n++) {
1982 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1983 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1984 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1985 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1986 }
1987 }
1988 }
1989
1990 static bool host_supports_vmx(void)
1991 {
1992 uint32_t ecx, unused;
1993
1994 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1995 return ecx & CPUID_EXT_VMX;
1996 }
1997
1998 #define VMX_INVALID_GUEST_STATE 0x80000021
1999
2000 int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
2001 {
2002 uint64_t code;
2003 int ret;
2004
2005 switch (run->exit_reason) {
2006 case KVM_EXIT_HLT:
2007 DPRINTF("handle_hlt\n");
2008 ret = kvm_handle_halt(env);
2009 break;
2010 case KVM_EXIT_SET_TPR:
2011 ret = 0;
2012 break;
2013 case KVM_EXIT_TPR_ACCESS:
2014 ret = kvm_handle_tpr_access(env);
2015 break;
2016 case KVM_EXIT_FAIL_ENTRY:
2017 code = run->fail_entry.hardware_entry_failure_reason;
2018 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2019 code);
2020 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2021 fprintf(stderr,
2022 "\nIf you're running a guest on an Intel machine without "
2023 "unrestricted mode\n"
2024 "support, the failure can be most likely due to the guest "
2025 "entering an invalid\n"
2026 "state for Intel VT. For example, the guest maybe running "
2027 "in big real mode\n"
2028 "which is not supported on less recent Intel processors."
2029 "\n\n");
2030 }
2031 ret = -1;
2032 break;
2033 case KVM_EXIT_EXCEPTION:
2034 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2035 run->ex.exception, run->ex.error_code);
2036 ret = -1;
2037 break;
2038 case KVM_EXIT_DEBUG:
2039 DPRINTF("kvm_exit_debug\n");
2040 ret = kvm_handle_debug(&run->debug.arch);
2041 break;
2042 default:
2043 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2044 ret = -1;
2045 break;
2046 }
2047
2048 return ret;
2049 }
2050
2051 bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2052 {
2053 kvm_cpu_synchronize_state(env);
2054 return !(env->cr[0] & CR0_PE_MASK) ||
2055 ((env->segs[R_CS].selector & 3) != 3);
2056 }
2057
2058 void kvm_arch_init_irq_routing(KVMState *s)
2059 {
2060 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2061 /* If kernel can't do irq routing, interrupt source
2062 * override 0->2 cannot be set up as required by HPET.
2063 * So we have to disable it.
2064 */
2065 no_hpet = 1;
2066 }
2067 /* We know at this point that we're using the in-kernel
2068 * irqchip, so we can use irqfds, and on x86 we know
2069 * we can use msi via irqfd and GSI routing.
2070 */
2071 kvm_irqfds_allowed = true;
2072 kvm_msi_via_irqfd_allowed = true;
2073 kvm_gsi_routing_allowed = true;
2074 }
2075
2076 /* Classic KVM device assignment interface. Will remain x86 only. */
2077 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2078 uint32_t flags, uint32_t *dev_id)
2079 {
2080 struct kvm_assigned_pci_dev dev_data = {
2081 .segnr = dev_addr->domain,
2082 .busnr = dev_addr->bus,
2083 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2084 .flags = flags,
2085 };
2086 int ret;
2087
2088 dev_data.assigned_dev_id =
2089 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2090
2091 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2092 if (ret < 0) {
2093 return ret;
2094 }
2095
2096 *dev_id = dev_data.assigned_dev_id;
2097
2098 return 0;
2099 }
2100
2101 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2102 {
2103 struct kvm_assigned_pci_dev dev_data = {
2104 .assigned_dev_id = dev_id,
2105 };
2106
2107 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2108 }
2109
2110 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2111 uint32_t irq_type, uint32_t guest_irq)
2112 {
2113 struct kvm_assigned_irq assigned_irq = {
2114 .assigned_dev_id = dev_id,
2115 .guest_irq = guest_irq,
2116 .flags = irq_type,
2117 };
2118
2119 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2120 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2121 } else {
2122 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2123 }
2124 }
2125
2126 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2127 uint32_t guest_irq)
2128 {
2129 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2130 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2131
2132 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2133 }
2134
2135 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2136 {
2137 struct kvm_assigned_pci_dev dev_data = {
2138 .assigned_dev_id = dev_id,
2139 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2140 };
2141
2142 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2143 }
2144
2145 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2146 uint32_t type)
2147 {
2148 struct kvm_assigned_irq assigned_irq = {
2149 .assigned_dev_id = dev_id,
2150 .flags = type,
2151 };
2152
2153 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2154 }
2155
2156 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2157 {
2158 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2159 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2160 }
2161
2162 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2163 {
2164 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2165 KVM_DEV_IRQ_GUEST_MSI, virq);
2166 }
2167
2168 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2169 {
2170 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2171 KVM_DEV_IRQ_HOST_MSI);
2172 }
2173
2174 bool kvm_device_msix_supported(KVMState *s)
2175 {
2176 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2177 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2178 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2179 }
2180
2181 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2182 uint32_t nr_vectors)
2183 {
2184 struct kvm_assigned_msix_nr msix_nr = {
2185 .assigned_dev_id = dev_id,
2186 .entry_nr = nr_vectors,
2187 };
2188
2189 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2190 }
2191
2192 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2193 int virq)
2194 {
2195 struct kvm_assigned_msix_entry msix_entry = {
2196 .assigned_dev_id = dev_id,
2197 .gsi = virq,
2198 .entry = vector,
2199 };
2200
2201 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2202 }
2203
2204 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2205 {
2206 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2207 KVM_DEV_IRQ_GUEST_MSIX, 0);
2208 }
2209
2210 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2211 {
2212 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2213 KVM_DEV_IRQ_HOST_MSIX);
2214 }
Qemu copy for testing