4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
19 #include <linux/kvm.h>
21 #include "qemu-common.h"
26 #include "host-utils.h"
32 #ifdef CONFIG_KVM_PARA
33 #include <linux/kvm_para.h>
39 #define DPRINTF(fmt, ...) \
40 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42 #define DPRINTF(fmt, ...) \
46 #define MSR_KVM_WALL_CLOCK 0x11
47 #define MSR_KVM_SYSTEM_TIME 0x12
50 #define BUS_MCEERR_AR 4
53 #define BUS_MCEERR_AO 5
56 #ifdef KVM_CAP_EXT_CPUID
58 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
60 struct kvm_cpuid2
*cpuid
;
63 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
64 cpuid
= (struct kvm_cpuid2
*)qemu_mallocz(size
);
66 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
67 if (r
== 0 && cpuid
->nent
>= max
) {
75 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
83 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
84 uint32_t index
, int reg
)
86 struct kvm_cpuid2
*cpuid
;
91 if (!kvm_check_extension(env
->kvm_state
, KVM_CAP_EXT_CPUID
)) {
96 while ((cpuid
= try_get_cpuid(env
->kvm_state
, max
)) == NULL
) {
100 for (i
= 0; i
< cpuid
->nent
; ++i
) {
101 if (cpuid
->entries
[i
].function
== function
&&
102 cpuid
->entries
[i
].index
== index
) {
105 ret
= cpuid
->entries
[i
].eax
;
108 ret
= cpuid
->entries
[i
].ebx
;
111 ret
= cpuid
->entries
[i
].ecx
;
114 ret
= cpuid
->entries
[i
].edx
;
117 /* KVM before 2.6.30 misreports the following features */
118 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
121 /* On Intel, kvm returns cpuid according to the Intel spec,
122 * so add missing bits according to the AMD spec:
124 cpuid_1_edx
= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
125 ret
|= cpuid_1_edx
& 0x183f7ff;
140 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
141 uint32_t index
, int reg
)
148 #ifdef CONFIG_KVM_PARA
149 struct kvm_para_features
{
152 } para_features
[] = {
153 #ifdef KVM_CAP_CLOCKSOURCE
154 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
156 #ifdef KVM_CAP_NOP_IO_DELAY
157 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
159 #ifdef KVM_CAP_PV_MMU
160 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
165 static int get_para_features(CPUState
*env
)
169 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
170 if (kvm_check_extension(env
->kvm_state
, para_features
[i
].cap
))
171 features
|= (1 << para_features
[i
].feature
);
179 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
184 r
= kvm_ioctl(s
, KVM_CHECK_EXTENSION
, KVM_CAP_MCE
);
187 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
192 static int kvm_setup_mce(CPUState
*env
, uint64_t *mcg_cap
)
194 return kvm_vcpu_ioctl(env
, KVM_X86_SETUP_MCE
, mcg_cap
);
197 static int kvm_set_mce(CPUState
*env
, struct kvm_x86_mce
*m
)
199 return kvm_vcpu_ioctl(env
, KVM_X86_SET_MCE
, m
);
202 static int kvm_get_msr(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
204 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
208 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
209 r
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, kmsrs
);
210 memcpy(msrs
, kmsrs
->entries
, n
* sizeof *msrs
);
215 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
216 static int kvm_mce_in_exception(CPUState
*env
)
218 struct kvm_msr_entry msr_mcg_status
= {
219 .index
= MSR_MCG_STATUS
,
223 r
= kvm_get_msr(env
, &msr_mcg_status
, 1);
224 if (r
== -1 || r
== 0) {
227 return !!(msr_mcg_status
.data
& MCG_STATUS_MCIP
);
230 struct kvm_x86_mce_data
233 struct kvm_x86_mce
*mce
;
237 static void kvm_do_inject_x86_mce(void *_data
)
239 struct kvm_x86_mce_data
*data
= _data
;
242 /* If there is an MCE exception being processed, ignore this SRAO MCE */
243 if ((data
->env
->mcg_cap
& MCG_SER_P
) &&
244 !(data
->mce
->status
& MCI_STATUS_AR
)) {
245 r
= kvm_mce_in_exception(data
->env
);
247 fprintf(stderr
, "Failed to get MCE status\n");
253 r
= kvm_set_mce(data
->env
, data
->mce
);
255 perror("kvm_set_mce FAILED");
256 if (data
->abort_on_error
) {
263 void kvm_inject_x86_mce(CPUState
*cenv
, int bank
, uint64_t status
,
264 uint64_t mcg_status
, uint64_t addr
, uint64_t misc
,
268 struct kvm_x86_mce mce
= {
271 .mcg_status
= mcg_status
,
275 struct kvm_x86_mce_data data
= {
280 if (!cenv
->mcg_cap
) {
281 fprintf(stderr
, "MCE support is not enabled!\n");
285 run_on_cpu(cenv
, kvm_do_inject_x86_mce
, &data
);
292 int kvm_arch_init_vcpu(CPUState
*env
)
295 struct kvm_cpuid2 cpuid
;
296 struct kvm_cpuid_entry2 entries
[100];
297 } __attribute__((packed
)) cpuid_data
;
298 uint32_t limit
, i
, j
, cpuid_i
;
300 struct kvm_cpuid_entry2
*c
;
301 #ifdef KVM_CPUID_SIGNATURE
302 uint32_t signature
[3];
305 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
307 env
->cpuid_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
309 i
= env
->cpuid_ext_features
& CPUID_EXT_HYPERVISOR
;
310 env
->cpuid_ext_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_ECX
);
311 env
->cpuid_ext_features
|= i
;
313 env
->cpuid_ext2_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
315 env
->cpuid_ext3_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
317 env
->cpuid_svm_features
&= kvm_arch_get_supported_cpuid(env
, 0x8000000A,
323 #ifdef CONFIG_KVM_PARA
324 /* Paravirtualization CPUIDs */
325 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
326 c
= &cpuid_data
.entries
[cpuid_i
++];
327 memset(c
, 0, sizeof(*c
));
328 c
->function
= KVM_CPUID_SIGNATURE
;
330 c
->ebx
= signature
[0];
331 c
->ecx
= signature
[1];
332 c
->edx
= signature
[2];
334 c
= &cpuid_data
.entries
[cpuid_i
++];
335 memset(c
, 0, sizeof(*c
));
336 c
->function
= KVM_CPUID_FEATURES
;
337 c
->eax
= env
->cpuid_kvm_features
& get_para_features(env
);
340 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
342 for (i
= 0; i
<= limit
; i
++) {
343 c
= &cpuid_data
.entries
[cpuid_i
++];
347 /* Keep reading function 2 till all the input is received */
351 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
352 KVM_CPUID_FLAG_STATE_READ_NEXT
;
353 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
354 times
= c
->eax
& 0xff;
356 for (j
= 1; j
< times
; ++j
) {
357 c
= &cpuid_data
.entries
[cpuid_i
++];
359 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
360 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
369 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
371 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
373 if (i
== 4 && c
->eax
== 0)
375 if (i
== 0xb && !(c
->ecx
& 0xff00))
377 if (i
== 0xd && c
->eax
== 0)
380 c
= &cpuid_data
.entries
[cpuid_i
++];
386 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
390 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
392 for (i
= 0x80000000; i
<= limit
; i
++) {
393 c
= &cpuid_data
.entries
[cpuid_i
++];
397 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
400 cpuid_data
.cpuid
.nent
= cpuid_i
;
403 if (((env
->cpuid_version
>> 8)&0xF) >= 6
404 && (env
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
405 && kvm_check_extension(env
->kvm_state
, KVM_CAP_MCE
) > 0) {
409 if (kvm_get_mce_cap_supported(env
->kvm_state
, &mcg_cap
, &banks
))
410 perror("kvm_get_mce_cap_supported FAILED");
412 if (banks
> MCE_BANKS_DEF
)
413 banks
= MCE_BANKS_DEF
;
414 mcg_cap
&= MCE_CAP_DEF
;
416 if (kvm_setup_mce(env
, &mcg_cap
))
417 perror("kvm_setup_mce FAILED");
419 env
->mcg_cap
= mcg_cap
;
424 return kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, &cpuid_data
);
427 void kvm_arch_reset_vcpu(CPUState
*env
)
429 env
->exception_injected
= -1;
430 env
->interrupt_injected
= -1;
431 env
->nmi_injected
= 0;
432 env
->nmi_pending
= 0;
433 if (kvm_irqchip_in_kernel()) {
434 env
->mp_state
= cpu_is_bsp(env
) ? KVM_MP_STATE_RUNNABLE
:
435 KVM_MP_STATE_UNINITIALIZED
;
437 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
441 static int kvm_has_msr_star(CPUState
*env
)
443 static int has_msr_star
;
447 if (has_msr_star
== 0) {
448 struct kvm_msr_list msr_list
, *kvm_msr_list
;
452 /* Obtain MSR list from KVM. These are the MSRs that we must
455 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
456 if (ret
< 0 && ret
!= -E2BIG
) {
459 /* Old kernel modules had a bug and could write beyond the provided
460 memory. Allocate at least a safe amount of 1K. */
461 kvm_msr_list
= qemu_mallocz(MAX(1024, sizeof(msr_list
) +
463 sizeof(msr_list
.indices
[0])));
465 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
466 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
470 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
471 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
481 if (has_msr_star
== 1)
486 static int kvm_init_identity_map_page(KVMState
*s
)
488 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
490 uint64_t addr
= 0xfffbc000;
492 if (!kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
496 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &addr
);
498 fprintf(stderr
, "kvm_set_identity_map_addr: %s\n", strerror(ret
));
505 int kvm_arch_init(KVMState
*s
, int smp_cpus
)
509 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
510 * directly. In order to use vm86 mode, a TSS is needed. Since this
511 * must be part of guest physical memory, we need to allocate it. Older
512 * versions of KVM just assumed that it would be at the end of physical
513 * memory but that doesn't work with more than 4GB of memory. We simply
514 * refuse to work with those older versions of KVM. */
515 ret
= kvm_ioctl(s
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_TSS_ADDR
);
517 fprintf(stderr
, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
521 /* this address is 3 pages before the bios, and the bios should present
522 * as unavaible memory. FIXME, need to ensure the e820 map deals with
526 * Tell fw_cfg to notify the BIOS to reserve the range.
528 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED
) < 0) {
529 perror("e820_add_entry() table is full");
532 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, 0xfffbd000);
537 return kvm_init_identity_map_page(s
);
540 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
542 lhs
->selector
= rhs
->selector
;
543 lhs
->base
= rhs
->base
;
544 lhs
->limit
= rhs
->limit
;
556 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
558 unsigned flags
= rhs
->flags
;
559 lhs
->selector
= rhs
->selector
;
560 lhs
->base
= rhs
->base
;
561 lhs
->limit
= rhs
->limit
;
562 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
563 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
564 lhs
->dpl
= rhs
->selector
& 3;
565 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
566 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
567 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
568 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
569 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
573 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
575 lhs
->selector
= rhs
->selector
;
576 lhs
->base
= rhs
->base
;
577 lhs
->limit
= rhs
->limit
;
579 (rhs
->type
<< DESC_TYPE_SHIFT
)
580 | (rhs
->present
* DESC_P_MASK
)
581 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
582 | (rhs
->db
<< DESC_B_SHIFT
)
583 | (rhs
->s
* DESC_S_MASK
)
584 | (rhs
->l
<< DESC_L_SHIFT
)
585 | (rhs
->g
* DESC_G_MASK
)
586 | (rhs
->avl
* DESC_AVL_MASK
);
589 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
592 *kvm_reg
= *qemu_reg
;
594 *qemu_reg
= *kvm_reg
;
597 static int kvm_getput_regs(CPUState
*env
, int set
)
599 struct kvm_regs regs
;
603 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
608 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
609 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
610 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
611 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
612 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
613 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
614 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
615 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
617 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
618 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
619 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
620 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
621 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
622 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
623 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
624 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
627 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
628 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
631 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
636 static int kvm_put_fpu(CPUState
*env
)
641 memset(&fpu
, 0, sizeof fpu
);
642 fpu
.fsw
= env
->fpus
& ~(7 << 11);
643 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
645 for (i
= 0; i
< 8; ++i
)
646 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
647 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
648 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
649 fpu
.mxcsr
= env
->mxcsr
;
651 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
655 #define XSAVE_CWD_RIP 2
656 #define XSAVE_CWD_RDP 4
657 #define XSAVE_MXCSR 6
658 #define XSAVE_ST_SPACE 8
659 #define XSAVE_XMM_SPACE 40
660 #define XSAVE_XSTATE_BV 128
661 #define XSAVE_YMMH_SPACE 144
664 static int kvm_put_xsave(CPUState
*env
)
668 struct kvm_xsave
* xsave
;
669 uint16_t cwd
, swd
, twd
, fop
;
671 if (!kvm_has_xsave())
672 return kvm_put_fpu(env
);
674 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
675 memset(xsave
, 0, sizeof(struct kvm_xsave
));
676 cwd
= swd
= twd
= fop
= 0;
677 swd
= env
->fpus
& ~(7 << 11);
678 swd
|= (env
->fpstt
& 7) << 11;
680 for (i
= 0; i
< 8; ++i
)
681 twd
|= (!env
->fptags
[i
]) << i
;
682 xsave
->region
[0] = (uint32_t)(swd
<< 16) + cwd
;
683 xsave
->region
[1] = (uint32_t)(fop
<< 16) + twd
;
684 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
686 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
687 sizeof env
->xmm_regs
);
688 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
689 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
690 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
691 sizeof env
->ymmh_regs
);
692 r
= kvm_vcpu_ioctl(env
, KVM_SET_XSAVE
, xsave
);
696 return kvm_put_fpu(env
);
700 static int kvm_put_xcrs(CPUState
*env
)
703 struct kvm_xcrs xcrs
;
710 xcrs
.xcrs
[0].xcr
= 0;
711 xcrs
.xcrs
[0].value
= env
->xcr0
;
712 return kvm_vcpu_ioctl(env
, KVM_SET_XCRS
, &xcrs
);
718 static int kvm_put_sregs(CPUState
*env
)
720 struct kvm_sregs sregs
;
722 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
723 if (env
->interrupt_injected
>= 0) {
724 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
725 (uint64_t)1 << (env
->interrupt_injected
% 64);
728 if ((env
->eflags
& VM_MASK
)) {
729 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
730 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
731 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
732 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
733 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
734 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
736 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
737 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
738 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
739 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
740 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
741 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
743 if (env
->cr
[0] & CR0_PE_MASK
) {
744 /* force ss cpl to cs cpl */
745 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
746 (sregs
.cs
.selector
& 3);
747 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
751 set_seg(&sregs
.tr
, &env
->tr
);
752 set_seg(&sregs
.ldt
, &env
->ldt
);
754 sregs
.idt
.limit
= env
->idt
.limit
;
755 sregs
.idt
.base
= env
->idt
.base
;
756 sregs
.gdt
.limit
= env
->gdt
.limit
;
757 sregs
.gdt
.base
= env
->gdt
.base
;
759 sregs
.cr0
= env
->cr
[0];
760 sregs
.cr2
= env
->cr
[2];
761 sregs
.cr3
= env
->cr
[3];
762 sregs
.cr4
= env
->cr
[4];
764 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
765 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
767 sregs
.efer
= env
->efer
;
769 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
772 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
773 uint32_t index
, uint64_t value
)
775 entry
->index
= index
;
779 static int kvm_put_msrs(CPUState
*env
, int level
)
782 struct kvm_msrs info
;
783 struct kvm_msr_entry entries
[100];
785 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
788 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
789 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
790 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
791 if (kvm_has_msr_star(env
))
792 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
794 /* FIXME if lm capable */
795 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
796 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
797 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
798 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
800 if (level
== KVM_PUT_FULL_STATE
) {
801 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
802 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
803 env
->system_time_msr
);
804 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
809 if (level
== KVM_PUT_RESET_STATE
)
810 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
811 else if (level
== KVM_PUT_FULL_STATE
) {
812 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
813 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
814 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++)
815 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
820 msr_data
.info
.nmsrs
= n
;
822 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
827 static int kvm_get_fpu(CPUState
*env
)
832 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
836 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
839 for (i
= 0; i
< 8; ++i
)
840 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
841 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
842 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
843 env
->mxcsr
= fpu
.mxcsr
;
848 static int kvm_get_xsave(CPUState
*env
)
851 struct kvm_xsave
* xsave
;
853 uint16_t cwd
, swd
, twd
, fop
;
855 if (!kvm_has_xsave())
856 return kvm_get_fpu(env
);
858 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
859 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XSAVE
, xsave
);
865 cwd
= (uint16_t)xsave
->region
[0];
866 swd
= (uint16_t)(xsave
->region
[0] >> 16);
867 twd
= (uint16_t)xsave
->region
[1];
868 fop
= (uint16_t)(xsave
->region
[1] >> 16);
869 env
->fpstt
= (swd
>> 11) & 7;
872 for (i
= 0; i
< 8; ++i
)
873 env
->fptags
[i
] = !((twd
>> i
) & 1);
874 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
875 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
877 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
878 sizeof env
->xmm_regs
);
879 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
880 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
881 sizeof env
->ymmh_regs
);
885 return kvm_get_fpu(env
);
889 static int kvm_get_xcrs(CPUState
*env
)
893 struct kvm_xcrs xcrs
;
898 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XCRS
, &xcrs
);
902 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++)
903 /* Only support xcr0 now */
904 if (xcrs
.xcrs
[0].xcr
== 0) {
905 env
->xcr0
= xcrs
.xcrs
[0].value
;
914 static int kvm_get_sregs(CPUState
*env
)
916 struct kvm_sregs sregs
;
920 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
924 /* There can only be one pending IRQ set in the bitmap at a time, so try
925 to find it and save its number instead (-1 for none). */
926 env
->interrupt_injected
= -1;
927 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
928 if (sregs
.interrupt_bitmap
[i
]) {
929 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
930 env
->interrupt_injected
= i
* 64 + bit
;
935 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
936 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
937 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
938 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
939 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
940 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
942 get_seg(&env
->tr
, &sregs
.tr
);
943 get_seg(&env
->ldt
, &sregs
.ldt
);
945 env
->idt
.limit
= sregs
.idt
.limit
;
946 env
->idt
.base
= sregs
.idt
.base
;
947 env
->gdt
.limit
= sregs
.gdt
.limit
;
948 env
->gdt
.base
= sregs
.gdt
.base
;
950 env
->cr
[0] = sregs
.cr0
;
951 env
->cr
[2] = sregs
.cr2
;
952 env
->cr
[3] = sregs
.cr3
;
953 env
->cr
[4] = sregs
.cr4
;
955 cpu_set_apic_base(env
->apic_state
, sregs
.apic_base
);
957 env
->efer
= sregs
.efer
;
958 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
960 #define HFLAG_COPY_MASK ~( \
961 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
962 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
963 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
964 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
968 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
969 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
970 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
971 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
972 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
973 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
974 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
976 if (env
->efer
& MSR_EFER_LMA
) {
977 hflags
|= HF_LMA_MASK
;
980 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
981 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
983 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
984 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
985 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
986 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
987 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
988 (env
->eflags
& VM_MASK
) ||
989 !(hflags
& HF_CS32_MASK
)) {
990 hflags
|= HF_ADDSEG_MASK
;
992 hflags
|= ((env
->segs
[R_DS
].base
|
993 env
->segs
[R_ES
].base
|
994 env
->segs
[R_SS
].base
) != 0) <<
998 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1003 static int kvm_get_msrs(CPUState
*env
)
1006 struct kvm_msrs info
;
1007 struct kvm_msr_entry entries
[100];
1009 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1013 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1014 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1015 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1016 if (kvm_has_msr_star(env
))
1017 msrs
[n
++].index
= MSR_STAR
;
1018 msrs
[n
++].index
= MSR_IA32_TSC
;
1019 #ifdef TARGET_X86_64
1020 /* FIXME lm_capable_kernel */
1021 msrs
[n
++].index
= MSR_CSTAR
;
1022 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1023 msrs
[n
++].index
= MSR_FMASK
;
1024 msrs
[n
++].index
= MSR_LSTAR
;
1026 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1027 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1031 msrs
[n
++].index
= MSR_MCG_STATUS
;
1032 msrs
[n
++].index
= MSR_MCG_CTL
;
1033 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++)
1034 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1038 msr_data
.info
.nmsrs
= n
;
1039 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
1043 for (i
= 0; i
< ret
; i
++) {
1044 switch (msrs
[i
].index
) {
1045 case MSR_IA32_SYSENTER_CS
:
1046 env
->sysenter_cs
= msrs
[i
].data
;
1048 case MSR_IA32_SYSENTER_ESP
:
1049 env
->sysenter_esp
= msrs
[i
].data
;
1051 case MSR_IA32_SYSENTER_EIP
:
1052 env
->sysenter_eip
= msrs
[i
].data
;
1055 env
->star
= msrs
[i
].data
;
1057 #ifdef TARGET_X86_64
1059 env
->cstar
= msrs
[i
].data
;
1061 case MSR_KERNELGSBASE
:
1062 env
->kernelgsbase
= msrs
[i
].data
;
1065 env
->fmask
= msrs
[i
].data
;
1068 env
->lstar
= msrs
[i
].data
;
1072 env
->tsc
= msrs
[i
].data
;
1074 case MSR_KVM_SYSTEM_TIME
:
1075 env
->system_time_msr
= msrs
[i
].data
;
1077 case MSR_KVM_WALL_CLOCK
:
1078 env
->wall_clock_msr
= msrs
[i
].data
;
1081 case MSR_MCG_STATUS
:
1082 env
->mcg_status
= msrs
[i
].data
;
1085 env
->mcg_ctl
= msrs
[i
].data
;
1090 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1091 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1092 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1102 static int kvm_put_mp_state(CPUState
*env
)
1104 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
1106 return kvm_vcpu_ioctl(env
, KVM_SET_MP_STATE
, &mp_state
);
1109 static int kvm_get_mp_state(CPUState
*env
)
1111 struct kvm_mp_state mp_state
;
1114 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MP_STATE
, &mp_state
);
1118 env
->mp_state
= mp_state
.mp_state
;
1122 static int kvm_put_vcpu_events(CPUState
*env
, int level
)
1124 #ifdef KVM_CAP_VCPU_EVENTS
1125 struct kvm_vcpu_events events
;
1127 if (!kvm_has_vcpu_events()) {
1131 events
.exception
.injected
= (env
->exception_injected
>= 0);
1132 events
.exception
.nr
= env
->exception_injected
;
1133 events
.exception
.has_error_code
= env
->has_error_code
;
1134 events
.exception
.error_code
= env
->error_code
;
1136 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1137 events
.interrupt
.nr
= env
->interrupt_injected
;
1138 events
.interrupt
.soft
= env
->soft_interrupt
;
1140 events
.nmi
.injected
= env
->nmi_injected
;
1141 events
.nmi
.pending
= env
->nmi_pending
;
1142 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1144 events
.sipi_vector
= env
->sipi_vector
;
1147 if (level
>= KVM_PUT_RESET_STATE
) {
1149 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1152 return kvm_vcpu_ioctl(env
, KVM_SET_VCPU_EVENTS
, &events
);
1158 static int kvm_get_vcpu_events(CPUState
*env
)
1160 #ifdef KVM_CAP_VCPU_EVENTS
1161 struct kvm_vcpu_events events
;
1164 if (!kvm_has_vcpu_events()) {
1168 ret
= kvm_vcpu_ioctl(env
, KVM_GET_VCPU_EVENTS
, &events
);
1172 env
->exception_injected
=
1173 events
.exception
.injected
? events
.exception
.nr
: -1;
1174 env
->has_error_code
= events
.exception
.has_error_code
;
1175 env
->error_code
= events
.exception
.error_code
;
1177 env
->interrupt_injected
=
1178 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1179 env
->soft_interrupt
= events
.interrupt
.soft
;
1181 env
->nmi_injected
= events
.nmi
.injected
;
1182 env
->nmi_pending
= events
.nmi
.pending
;
1183 if (events
.nmi
.masked
) {
1184 env
->hflags2
|= HF2_NMI_MASK
;
1186 env
->hflags2
&= ~HF2_NMI_MASK
;
1189 env
->sipi_vector
= events
.sipi_vector
;
1195 static int kvm_guest_debug_workarounds(CPUState
*env
)
1198 #ifdef KVM_CAP_SET_GUEST_DEBUG
1199 unsigned long reinject_trap
= 0;
1201 if (!kvm_has_vcpu_events()) {
1202 if (env
->exception_injected
== 1) {
1203 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1204 } else if (env
->exception_injected
== 3) {
1205 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1207 env
->exception_injected
= -1;
1211 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1212 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1213 * by updating the debug state once again if single-stepping is on.
1214 * Another reason to call kvm_update_guest_debug here is a pending debug
1215 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1216 * reinject them via SET_GUEST_DEBUG.
1218 if (reinject_trap
||
1219 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
1220 ret
= kvm_update_guest_debug(env
, reinject_trap
);
1222 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1226 static int kvm_put_debugregs(CPUState
*env
)
1228 #ifdef KVM_CAP_DEBUGREGS
1229 struct kvm_debugregs dbgregs
;
1232 if (!kvm_has_debugregs()) {
1236 for (i
= 0; i
< 4; i
++) {
1237 dbgregs
.db
[i
] = env
->dr
[i
];
1239 dbgregs
.dr6
= env
->dr
[6];
1240 dbgregs
.dr7
= env
->dr
[7];
1243 return kvm_vcpu_ioctl(env
, KVM_SET_DEBUGREGS
, &dbgregs
);
1249 static int kvm_get_debugregs(CPUState
*env
)
1251 #ifdef KVM_CAP_DEBUGREGS
1252 struct kvm_debugregs dbgregs
;
1255 if (!kvm_has_debugregs()) {
1259 ret
= kvm_vcpu_ioctl(env
, KVM_GET_DEBUGREGS
, &dbgregs
);
1263 for (i
= 0; i
< 4; i
++) {
1264 env
->dr
[i
] = dbgregs
.db
[i
];
1266 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1267 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1273 int kvm_arch_put_registers(CPUState
*env
, int level
)
1277 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1279 ret
= kvm_getput_regs(env
, 1);
1283 ret
= kvm_put_xsave(env
);
1287 ret
= kvm_put_xcrs(env
);
1291 ret
= kvm_put_sregs(env
);
1295 ret
= kvm_put_msrs(env
, level
);
1299 if (level
>= KVM_PUT_RESET_STATE
) {
1300 ret
= kvm_put_mp_state(env
);
1305 ret
= kvm_put_vcpu_events(env
, level
);
1310 ret
= kvm_guest_debug_workarounds(env
);
1314 ret
= kvm_put_debugregs(env
);
1321 int kvm_arch_get_registers(CPUState
*env
)
1325 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1327 ret
= kvm_getput_regs(env
, 0);
1331 ret
= kvm_get_xsave(env
);
1335 ret
= kvm_get_xcrs(env
);
1339 ret
= kvm_get_sregs(env
);
1343 ret
= kvm_get_msrs(env
);
1347 ret
= kvm_get_mp_state(env
);
1351 ret
= kvm_get_vcpu_events(env
);
1355 ret
= kvm_get_debugregs(env
);
1362 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1364 /* Try to inject an interrupt if the guest can accept it */
1365 if (run
->ready_for_interrupt_injection
&&
1366 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1367 (env
->eflags
& IF_MASK
)) {
1370 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1371 irq
= cpu_get_pic_interrupt(env
);
1373 struct kvm_interrupt intr
;
1376 DPRINTF("injected interrupt %d\n", irq
);
1377 kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
1381 /* If we have an interrupt but the guest is not ready to receive an
1382 * interrupt, request an interrupt window exit. This will
1383 * cause a return to userspace as soon as the guest is ready to
1384 * receive interrupts. */
1385 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
))
1386 run
->request_interrupt_window
= 1;
1388 run
->request_interrupt_window
= 0;
1390 DPRINTF("setting tpr\n");
1391 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1396 int kvm_arch_post_run(CPUState
*env
, struct kvm_run
*run
)
1399 env
->eflags
|= IF_MASK
;
1401 env
->eflags
&= ~IF_MASK
;
1403 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1404 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1409 int kvm_arch_process_irqchip_events(CPUState
*env
)
1411 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1412 kvm_cpu_synchronize_state(env
);
1414 env
->exception_index
= EXCP_HALTED
;
1417 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1418 kvm_cpu_synchronize_state(env
);
1425 static int kvm_handle_halt(CPUState
*env
)
1427 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1428 (env
->eflags
& IF_MASK
)) &&
1429 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1431 env
->exception_index
= EXCP_HLT
;
1438 int kvm_arch_handle_exit(CPUState
*env
, struct kvm_run
*run
)
1442 switch (run
->exit_reason
) {
1444 DPRINTF("handle_hlt\n");
1445 ret
= kvm_handle_halt(env
);
1452 #ifdef KVM_CAP_SET_GUEST_DEBUG
1453 int kvm_arch_insert_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1455 static const uint8_t int3
= 0xcc;
1457 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1458 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1))
1463 int kvm_arch_remove_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1467 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1468 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1))
1479 static int nb_hw_breakpoint
;
1481 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1485 for (n
= 0; n
< nb_hw_breakpoint
; n
++)
1486 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1487 (hw_breakpoint
[n
].len
== len
|| len
== -1))
1492 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1493 target_ulong len
, int type
)
1496 case GDB_BREAKPOINT_HW
:
1499 case GDB_WATCHPOINT_WRITE
:
1500 case GDB_WATCHPOINT_ACCESS
:
1507 if (addr
& (len
- 1))
1518 if (nb_hw_breakpoint
== 4)
1521 if (find_hw_breakpoint(addr
, len
, type
) >= 0)
1524 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1525 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1526 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1532 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1533 target_ulong len
, int type
)
1537 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1542 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1547 void kvm_arch_remove_all_hw_breakpoints(void)
1549 nb_hw_breakpoint
= 0;
1552 static CPUWatchpoint hw_watchpoint
;
1554 int kvm_arch_debug(struct kvm_debug_exit_arch
*arch_info
)
1559 if (arch_info
->exception
== 1) {
1560 if (arch_info
->dr6
& (1 << 14)) {
1561 if (cpu_single_env
->singlestep_enabled
)
1564 for (n
= 0; n
< 4; n
++)
1565 if (arch_info
->dr6
& (1 << n
))
1566 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1572 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1573 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1574 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1578 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1579 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1580 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1584 } else if (kvm_find_sw_breakpoint(cpu_single_env
, arch_info
->pc
))
1588 cpu_synchronize_state(cpu_single_env
);
1589 assert(cpu_single_env
->exception_injected
== -1);
1591 cpu_single_env
->exception_injected
= arch_info
->exception
;
1592 cpu_single_env
->has_error_code
= 0;
1598 void kvm_arch_update_guest_debug(CPUState
*env
, struct kvm_guest_debug
*dbg
)
1600 const uint8_t type_code
[] = {
1601 [GDB_BREAKPOINT_HW
] = 0x0,
1602 [GDB_WATCHPOINT_WRITE
] = 0x1,
1603 [GDB_WATCHPOINT_ACCESS
] = 0x3
1605 const uint8_t len_code
[] = {
1606 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1610 if (kvm_sw_breakpoints_active(env
))
1611 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1613 if (nb_hw_breakpoint
> 0) {
1614 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1615 dbg
->arch
.debugreg
[7] = 0x0600;
1616 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1617 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
1618 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
1619 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
1620 (len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
1623 /* Legal xcr0 for loading */
1626 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1628 bool kvm_arch_stop_on_emulation_error(CPUState
*env
)
1630 return !(env
->cr
[0] & CR0_PE_MASK
) ||
1631 ((env
->segs
[R_CS
].selector
& 3) != 3);
1634 static void hardware_memory_error(void)
1636 fprintf(stderr
, "Hardware memory error!\n");
1641 static void kvm_mce_broadcast_rest(CPUState
*env
)
1644 int family
, model
, cpuver
= env
->cpuid_version
;
1646 family
= (cpuver
>> 8) & 0xf;
1647 model
= ((cpuver
>> 12) & 0xf0) + ((cpuver
>> 4) & 0xf);
1649 /* Broadcast MCA signal for processor version 06H_EH and above */
1650 if ((family
== 6 && model
>= 14) || family
> 6) {
1651 for (cenv
= first_cpu
; cenv
!= NULL
; cenv
= cenv
->next_cpu
) {
1655 kvm_inject_x86_mce(cenv
, 1, MCI_STATUS_VAL
| MCI_STATUS_UC
,
1656 MCG_STATUS_MCIP
| MCG_STATUS_RIPV
, 0, 0, 1);
1662 int kvm_on_sigbus_vcpu(CPUState
*env
, int code
, void *addr
)
1664 #if defined(KVM_CAP_MCE)
1665 struct kvm_x86_mce mce
= {
1669 ram_addr_t ram_addr
;
1670 target_phys_addr_t paddr
;
1673 if ((env
->mcg_cap
& MCG_SER_P
) && addr
1674 && (code
== BUS_MCEERR_AR
1675 || code
== BUS_MCEERR_AO
)) {
1676 if (code
== BUS_MCEERR_AR
) {
1677 /* Fake an Intel architectural Data Load SRAR UCR */
1678 mce
.status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1679 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1680 | MCI_STATUS_AR
| 0x134;
1681 mce
.misc
= (MCM_ADDR_PHYS
<< 6) | 0xc;
1682 mce
.mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_EIPV
;
1685 * If there is an MCE excpetion being processed, ignore
1688 r
= kvm_mce_in_exception(env
);
1690 fprintf(stderr
, "Failed to get MCE status\n");
1694 /* Fake an Intel architectural Memory scrubbing UCR */
1695 mce
.status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1696 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1698 mce
.misc
= (MCM_ADDR_PHYS
<< 6) | 0xc;
1699 mce
.mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_RIPV
;
1701 vaddr
= (void *)addr
;
1702 if (qemu_ram_addr_from_host(vaddr
, &ram_addr
) ||
1703 !kvm_physical_memory_addr_from_ram(env
->kvm_state
, ram_addr
, &paddr
)) {
1704 fprintf(stderr
, "Hardware memory error for memory used by "
1705 "QEMU itself instead of guest system!\n");
1706 /* Hope we are lucky for AO MCE */
1707 if (code
== BUS_MCEERR_AO
) {
1710 hardware_memory_error();
1714 r
= kvm_set_mce(env
, &mce
);
1716 fprintf(stderr
, "kvm_set_mce: %s\n", strerror(errno
));
1719 kvm_mce_broadcast_rest(env
);
1723 if (code
== BUS_MCEERR_AO
) {
1725 } else if (code
== BUS_MCEERR_AR
) {
1726 hardware_memory_error();
1734 int kvm_on_sigbus(int code
, void *addr
)
1736 #if defined(KVM_CAP_MCE)
1737 if ((first_cpu
->mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
1740 ram_addr_t ram_addr
;
1741 target_phys_addr_t paddr
;
1743 /* Hope we are lucky for AO MCE */
1745 if (qemu_ram_addr_from_host(vaddr
, &ram_addr
) ||
1746 !kvm_physical_memory_addr_from_ram(first_cpu
->kvm_state
, ram_addr
, &paddr
)) {
1747 fprintf(stderr
, "Hardware memory error for memory used by "
1748 "QEMU itself instead of guest system!: %p\n", addr
);
1751 status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1752 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1754 kvm_inject_x86_mce(first_cpu
, 9, status
,
1755 MCG_STATUS_MCIP
| MCG_STATUS_RIPV
, paddr
,
1756 (MCM_ADDR_PHYS
<< 6) | 0xc, 1);
1757 kvm_mce_broadcast_rest(first_cpu
);
1761 if (code
== BUS_MCEERR_AO
) {
1763 } else if (code
== BUS_MCEERR_AR
) {
1764 hardware_memory_error();