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kvm-irqchip: i386: add hook for add/remove virq
[mirror_qemu.git] / target-i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38 #include "hw/i386/intel_iommu.h"
39
40 #include "exec/ioport.h"
41 #include "standard-headers/asm-x86/hyperv.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci/msi.h"
44 #include "migration/migration.h"
45 #include "exec/memattrs.h"
46 #include "trace.h"
47
48 //#define DEBUG_KVM
49
50 #ifdef DEBUG_KVM
51 #define DPRINTF(fmt, ...) \
52 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
53 #else
54 #define DPRINTF(fmt, ...) \
55 do { } while (0)
56 #endif
57
58 #define MSR_KVM_WALL_CLOCK 0x11
59 #define MSR_KVM_SYSTEM_TIME 0x12
60
61 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
62 * 255 kvm_msr_entry structs */
63 #define MSR_BUF_SIZE 4096
64
65 #ifndef BUS_MCEERR_AR
66 #define BUS_MCEERR_AR 4
67 #endif
68 #ifndef BUS_MCEERR_AO
69 #define BUS_MCEERR_AO 5
70 #endif
71
72 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
73 KVM_CAP_INFO(SET_TSS_ADDR),
74 KVM_CAP_INFO(EXT_CPUID),
75 KVM_CAP_INFO(MP_STATE),
76 KVM_CAP_LAST_INFO
77 };
78
79 static bool has_msr_star;
80 static bool has_msr_hsave_pa;
81 static bool has_msr_tsc_aux;
82 static bool has_msr_tsc_adjust;
83 static bool has_msr_tsc_deadline;
84 static bool has_msr_feature_control;
85 static bool has_msr_async_pf_en;
86 static bool has_msr_pv_eoi_en;
87 static bool has_msr_misc_enable;
88 static bool has_msr_smbase;
89 static bool has_msr_bndcfgs;
90 static bool has_msr_kvm_steal_time;
91 static int lm_capable_kernel;
92 static bool has_msr_hv_hypercall;
93 static bool has_msr_hv_vapic;
94 static bool has_msr_hv_tsc;
95 static bool has_msr_hv_crash;
96 static bool has_msr_hv_reset;
97 static bool has_msr_hv_vpindex;
98 static bool has_msr_hv_runtime;
99 static bool has_msr_hv_synic;
100 static bool has_msr_hv_stimer;
101 static bool has_msr_mtrr;
102 static bool has_msr_xss;
103
104 static bool has_msr_architectural_pmu;
105 static uint32_t num_architectural_pmu_counters;
106
107 static int has_xsave;
108 static int has_xcrs;
109 static int has_pit_state2;
110
111 static bool has_msr_mcg_ext_ctl;
112
113 static struct kvm_cpuid2 *cpuid_cache;
114
115 int kvm_has_pit_state2(void)
116 {
117 return has_pit_state2;
118 }
119
120 bool kvm_has_smm(void)
121 {
122 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
123 }
124
125 bool kvm_allows_irq0_override(void)
126 {
127 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
128 }
129
130 static int kvm_get_tsc(CPUState *cs)
131 {
132 X86CPU *cpu = X86_CPU(cs);
133 CPUX86State *env = &cpu->env;
134 struct {
135 struct kvm_msrs info;
136 struct kvm_msr_entry entries[1];
137 } msr_data;
138 int ret;
139
140 if (env->tsc_valid) {
141 return 0;
142 }
143
144 msr_data.info.nmsrs = 1;
145 msr_data.entries[0].index = MSR_IA32_TSC;
146 env->tsc_valid = !runstate_is_running();
147
148 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
149 if (ret < 0) {
150 return ret;
151 }
152
153 assert(ret == 1);
154 env->tsc = msr_data.entries[0].data;
155 return 0;
156 }
157
158 static inline void do_kvm_synchronize_tsc(void *arg)
159 {
160 CPUState *cpu = arg;
161
162 kvm_get_tsc(cpu);
163 }
164
165 void kvm_synchronize_all_tsc(void)
166 {
167 CPUState *cpu;
168
169 if (kvm_enabled()) {
170 CPU_FOREACH(cpu) {
171 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
172 }
173 }
174 }
175
176 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
177 {
178 struct kvm_cpuid2 *cpuid;
179 int r, size;
180
181 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
182 cpuid = g_malloc0(size);
183 cpuid->nent = max;
184 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
185 if (r == 0 && cpuid->nent >= max) {
186 r = -E2BIG;
187 }
188 if (r < 0) {
189 if (r == -E2BIG) {
190 g_free(cpuid);
191 return NULL;
192 } else {
193 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
194 strerror(-r));
195 exit(1);
196 }
197 }
198 return cpuid;
199 }
200
201 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
202 * for all entries.
203 */
204 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
205 {
206 struct kvm_cpuid2 *cpuid;
207 int max = 1;
208
209 if (cpuid_cache != NULL) {
210 return cpuid_cache;
211 }
212 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
213 max *= 2;
214 }
215 cpuid_cache = cpuid;
216 return cpuid;
217 }
218
219 static const struct kvm_para_features {
220 int cap;
221 int feature;
222 } para_features[] = {
223 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
224 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
225 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
226 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
227 };
228
229 static int get_para_features(KVMState *s)
230 {
231 int i, features = 0;
232
233 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
234 if (kvm_check_extension(s, para_features[i].cap)) {
235 features |= (1 << para_features[i].feature);
236 }
237 }
238
239 return features;
240 }
241
242
243 /* Returns the value for a specific register on the cpuid entry
244 */
245 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
246 {
247 uint32_t ret = 0;
248 switch (reg) {
249 case R_EAX:
250 ret = entry->eax;
251 break;
252 case R_EBX:
253 ret = entry->ebx;
254 break;
255 case R_ECX:
256 ret = entry->ecx;
257 break;
258 case R_EDX:
259 ret = entry->edx;
260 break;
261 }
262 return ret;
263 }
264
265 /* Find matching entry for function/index on kvm_cpuid2 struct
266 */
267 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
268 uint32_t function,
269 uint32_t index)
270 {
271 int i;
272 for (i = 0; i < cpuid->nent; ++i) {
273 if (cpuid->entries[i].function == function &&
274 cpuid->entries[i].index == index) {
275 return &cpuid->entries[i];
276 }
277 }
278 /* not found: */
279 return NULL;
280 }
281
282 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
283 uint32_t index, int reg)
284 {
285 struct kvm_cpuid2 *cpuid;
286 uint32_t ret = 0;
287 uint32_t cpuid_1_edx;
288 bool found = false;
289
290 cpuid = get_supported_cpuid(s);
291
292 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
293 if (entry) {
294 found = true;
295 ret = cpuid_entry_get_reg(entry, reg);
296 }
297
298 /* Fixups for the data returned by KVM, below */
299
300 if (function == 1 && reg == R_EDX) {
301 /* KVM before 2.6.30 misreports the following features */
302 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
303 } else if (function == 1 && reg == R_ECX) {
304 /* We can set the hypervisor flag, even if KVM does not return it on
305 * GET_SUPPORTED_CPUID
306 */
307 ret |= CPUID_EXT_HYPERVISOR;
308 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
309 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
310 * and the irqchip is in the kernel.
311 */
312 if (kvm_irqchip_in_kernel() &&
313 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
314 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
315 }
316
317 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
318 * without the in-kernel irqchip
319 */
320 if (!kvm_irqchip_in_kernel()) {
321 ret &= ~CPUID_EXT_X2APIC;
322 }
323 } else if (function == 6 && reg == R_EAX) {
324 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
325 } else if (function == 0x80000001 && reg == R_EDX) {
326 /* On Intel, kvm returns cpuid according to the Intel spec,
327 * so add missing bits according to the AMD spec:
328 */
329 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
330 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
331 }
332
333 /* fallback for older kernels */
334 if ((function == KVM_CPUID_FEATURES) && !found) {
335 ret = get_para_features(s);
336 }
337
338 return ret;
339 }
340
341 typedef struct HWPoisonPage {
342 ram_addr_t ram_addr;
343 QLIST_ENTRY(HWPoisonPage) list;
344 } HWPoisonPage;
345
346 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
347 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
348
349 static void kvm_unpoison_all(void *param)
350 {
351 HWPoisonPage *page, *next_page;
352
353 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
354 QLIST_REMOVE(page, list);
355 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
356 g_free(page);
357 }
358 }
359
360 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
361 {
362 HWPoisonPage *page;
363
364 QLIST_FOREACH(page, &hwpoison_page_list, list) {
365 if (page->ram_addr == ram_addr) {
366 return;
367 }
368 }
369 page = g_new(HWPoisonPage, 1);
370 page->ram_addr = ram_addr;
371 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
372 }
373
374 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
375 int *max_banks)
376 {
377 int r;
378
379 r = kvm_check_extension(s, KVM_CAP_MCE);
380 if (r > 0) {
381 *max_banks = r;
382 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
383 }
384 return -ENOSYS;
385 }
386
387 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
388 {
389 CPUState *cs = CPU(cpu);
390 CPUX86State *env = &cpu->env;
391 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
392 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
393 uint64_t mcg_status = MCG_STATUS_MCIP;
394 int flags = 0;
395
396 if (code == BUS_MCEERR_AR) {
397 status |= MCI_STATUS_AR | 0x134;
398 mcg_status |= MCG_STATUS_EIPV;
399 } else {
400 status |= 0xc0;
401 mcg_status |= MCG_STATUS_RIPV;
402 }
403
404 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
405 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
406 * guest kernel back into env->mcg_ext_ctl.
407 */
408 cpu_synchronize_state(cs);
409 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
410 mcg_status |= MCG_STATUS_LMCE;
411 flags = 0;
412 }
413
414 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
415 (MCM_ADDR_PHYS << 6) | 0xc, flags);
416 }
417
418 static void hardware_memory_error(void)
419 {
420 fprintf(stderr, "Hardware memory error!\n");
421 exit(1);
422 }
423
424 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
425 {
426 X86CPU *cpu = X86_CPU(c);
427 CPUX86State *env = &cpu->env;
428 ram_addr_t ram_addr;
429 hwaddr paddr;
430
431 if ((env->mcg_cap & MCG_SER_P) && addr
432 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
433 ram_addr = qemu_ram_addr_from_host(addr);
434 if (ram_addr == RAM_ADDR_INVALID ||
435 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
436 fprintf(stderr, "Hardware memory error for memory used by "
437 "QEMU itself instead of guest system!\n");
438 /* Hope we are lucky for AO MCE */
439 if (code == BUS_MCEERR_AO) {
440 return 0;
441 } else {
442 hardware_memory_error();
443 }
444 }
445 kvm_hwpoison_page_add(ram_addr);
446 kvm_mce_inject(cpu, paddr, code);
447 } else {
448 if (code == BUS_MCEERR_AO) {
449 return 0;
450 } else if (code == BUS_MCEERR_AR) {
451 hardware_memory_error();
452 } else {
453 return 1;
454 }
455 }
456 return 0;
457 }
458
459 int kvm_arch_on_sigbus(int code, void *addr)
460 {
461 X86CPU *cpu = X86_CPU(first_cpu);
462
463 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
464 ram_addr_t ram_addr;
465 hwaddr paddr;
466
467 /* Hope we are lucky for AO MCE */
468 ram_addr = qemu_ram_addr_from_host(addr);
469 if (ram_addr == RAM_ADDR_INVALID ||
470 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
471 addr, &paddr)) {
472 fprintf(stderr, "Hardware memory error for memory used by "
473 "QEMU itself instead of guest system!: %p\n", addr);
474 return 0;
475 }
476 kvm_hwpoison_page_add(ram_addr);
477 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
478 } else {
479 if (code == BUS_MCEERR_AO) {
480 return 0;
481 } else if (code == BUS_MCEERR_AR) {
482 hardware_memory_error();
483 } else {
484 return 1;
485 }
486 }
487 return 0;
488 }
489
490 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
491 {
492 CPUX86State *env = &cpu->env;
493
494 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
495 unsigned int bank, bank_num = env->mcg_cap & 0xff;
496 struct kvm_x86_mce mce;
497
498 env->exception_injected = -1;
499
500 /*
501 * There must be at least one bank in use if an MCE is pending.
502 * Find it and use its values for the event injection.
503 */
504 for (bank = 0; bank < bank_num; bank++) {
505 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
506 break;
507 }
508 }
509 assert(bank < bank_num);
510
511 mce.bank = bank;
512 mce.status = env->mce_banks[bank * 4 + 1];
513 mce.mcg_status = env->mcg_status;
514 mce.addr = env->mce_banks[bank * 4 + 2];
515 mce.misc = env->mce_banks[bank * 4 + 3];
516
517 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
518 }
519 return 0;
520 }
521
522 static void cpu_update_state(void *opaque, int running, RunState state)
523 {
524 CPUX86State *env = opaque;
525
526 if (running) {
527 env->tsc_valid = false;
528 }
529 }
530
531 unsigned long kvm_arch_vcpu_id(CPUState *cs)
532 {
533 X86CPU *cpu = X86_CPU(cs);
534 return cpu->apic_id;
535 }
536
537 #ifndef KVM_CPUID_SIGNATURE_NEXT
538 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
539 #endif
540
541 static bool hyperv_hypercall_available(X86CPU *cpu)
542 {
543 return cpu->hyperv_vapic ||
544 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
545 }
546
547 static bool hyperv_enabled(X86CPU *cpu)
548 {
549 CPUState *cs = CPU(cpu);
550 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
551 (hyperv_hypercall_available(cpu) ||
552 cpu->hyperv_time ||
553 cpu->hyperv_relaxed_timing ||
554 cpu->hyperv_crash ||
555 cpu->hyperv_reset ||
556 cpu->hyperv_vpindex ||
557 cpu->hyperv_runtime ||
558 cpu->hyperv_synic ||
559 cpu->hyperv_stimer);
560 }
561
562 static int kvm_arch_set_tsc_khz(CPUState *cs)
563 {
564 X86CPU *cpu = X86_CPU(cs);
565 CPUX86State *env = &cpu->env;
566 int r;
567
568 if (!env->tsc_khz) {
569 return 0;
570 }
571
572 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
573 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
574 -ENOTSUP;
575 if (r < 0) {
576 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
577 * TSC frequency doesn't match the one we want.
578 */
579 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
580 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
581 -ENOTSUP;
582 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
583 error_report("warning: TSC frequency mismatch between "
584 "VM (%" PRId64 " kHz) and host (%d kHz), "
585 "and TSC scaling unavailable",
586 env->tsc_khz, cur_freq);
587 return r;
588 }
589 }
590
591 return 0;
592 }
593
594 static int hyperv_handle_properties(CPUState *cs)
595 {
596 X86CPU *cpu = X86_CPU(cs);
597 CPUX86State *env = &cpu->env;
598
599 if (cpu->hyperv_relaxed_timing) {
600 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
601 }
602 if (cpu->hyperv_vapic) {
603 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
604 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
605 has_msr_hv_vapic = true;
606 }
607 if (cpu->hyperv_time &&
608 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
609 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
610 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
611 env->features[FEAT_HYPERV_EAX] |= 0x200;
612 has_msr_hv_tsc = true;
613 }
614 if (cpu->hyperv_crash && has_msr_hv_crash) {
615 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
616 }
617 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
618 if (cpu->hyperv_reset && has_msr_hv_reset) {
619 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
620 }
621 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
622 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
623 }
624 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
625 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
626 }
627 if (cpu->hyperv_synic) {
628 int sint;
629
630 if (!has_msr_hv_synic ||
631 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
632 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
633 return -ENOSYS;
634 }
635
636 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
637 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
638 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
639 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
640 }
641 }
642 if (cpu->hyperv_stimer) {
643 if (!has_msr_hv_stimer) {
644 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
645 return -ENOSYS;
646 }
647 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
648 }
649 return 0;
650 }
651
652 static Error *invtsc_mig_blocker;
653
654 #define KVM_MAX_CPUID_ENTRIES 100
655
656 int kvm_arch_init_vcpu(CPUState *cs)
657 {
658 struct {
659 struct kvm_cpuid2 cpuid;
660 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
661 } QEMU_PACKED cpuid_data;
662 X86CPU *cpu = X86_CPU(cs);
663 CPUX86State *env = &cpu->env;
664 uint32_t limit, i, j, cpuid_i;
665 uint32_t unused;
666 struct kvm_cpuid_entry2 *c;
667 uint32_t signature[3];
668 int kvm_base = KVM_CPUID_SIGNATURE;
669 int r;
670
671 memset(&cpuid_data, 0, sizeof(cpuid_data));
672
673 cpuid_i = 0;
674
675 /* Paravirtualization CPUIDs */
676 if (hyperv_enabled(cpu)) {
677 c = &cpuid_data.entries[cpuid_i++];
678 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
679 if (!cpu->hyperv_vendor_id) {
680 memcpy(signature, "Microsoft Hv", 12);
681 } else {
682 size_t len = strlen(cpu->hyperv_vendor_id);
683
684 if (len > 12) {
685 error_report("hv-vendor-id truncated to 12 characters");
686 len = 12;
687 }
688 memset(signature, 0, 12);
689 memcpy(signature, cpu->hyperv_vendor_id, len);
690 }
691 c->eax = HYPERV_CPUID_MIN;
692 c->ebx = signature[0];
693 c->ecx = signature[1];
694 c->edx = signature[2];
695
696 c = &cpuid_data.entries[cpuid_i++];
697 c->function = HYPERV_CPUID_INTERFACE;
698 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
699 c->eax = signature[0];
700 c->ebx = 0;
701 c->ecx = 0;
702 c->edx = 0;
703
704 c = &cpuid_data.entries[cpuid_i++];
705 c->function = HYPERV_CPUID_VERSION;
706 c->eax = 0x00001bbc;
707 c->ebx = 0x00060001;
708
709 c = &cpuid_data.entries[cpuid_i++];
710 c->function = HYPERV_CPUID_FEATURES;
711 r = hyperv_handle_properties(cs);
712 if (r) {
713 return r;
714 }
715 c->eax = env->features[FEAT_HYPERV_EAX];
716 c->ebx = env->features[FEAT_HYPERV_EBX];
717 c->edx = env->features[FEAT_HYPERV_EDX];
718
719 c = &cpuid_data.entries[cpuid_i++];
720 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
721 if (cpu->hyperv_relaxed_timing) {
722 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
723 }
724 if (has_msr_hv_vapic) {
725 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
726 }
727 c->ebx = cpu->hyperv_spinlock_attempts;
728
729 c = &cpuid_data.entries[cpuid_i++];
730 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
731 c->eax = 0x40;
732 c->ebx = 0x40;
733
734 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
735 has_msr_hv_hypercall = true;
736 }
737
738 if (cpu->expose_kvm) {
739 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
740 c = &cpuid_data.entries[cpuid_i++];
741 c->function = KVM_CPUID_SIGNATURE | kvm_base;
742 c->eax = KVM_CPUID_FEATURES | kvm_base;
743 c->ebx = signature[0];
744 c->ecx = signature[1];
745 c->edx = signature[2];
746
747 c = &cpuid_data.entries[cpuid_i++];
748 c->function = KVM_CPUID_FEATURES | kvm_base;
749 c->eax = env->features[FEAT_KVM];
750
751 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
752
753 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
754
755 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
756 }
757
758 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
759
760 for (i = 0; i <= limit; i++) {
761 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
762 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
763 abort();
764 }
765 c = &cpuid_data.entries[cpuid_i++];
766
767 switch (i) {
768 case 2: {
769 /* Keep reading function 2 till all the input is received */
770 int times;
771
772 c->function = i;
773 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
774 KVM_CPUID_FLAG_STATE_READ_NEXT;
775 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
776 times = c->eax & 0xff;
777
778 for (j = 1; j < times; ++j) {
779 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
780 fprintf(stderr, "cpuid_data is full, no space for "
781 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
782 abort();
783 }
784 c = &cpuid_data.entries[cpuid_i++];
785 c->function = i;
786 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
787 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
788 }
789 break;
790 }
791 case 4:
792 case 0xb:
793 case 0xd:
794 for (j = 0; ; j++) {
795 if (i == 0xd && j == 64) {
796 break;
797 }
798 c->function = i;
799 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
800 c->index = j;
801 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
802
803 if (i == 4 && c->eax == 0) {
804 break;
805 }
806 if (i == 0xb && !(c->ecx & 0xff00)) {
807 break;
808 }
809 if (i == 0xd && c->eax == 0) {
810 continue;
811 }
812 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
813 fprintf(stderr, "cpuid_data is full, no space for "
814 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
815 abort();
816 }
817 c = &cpuid_data.entries[cpuid_i++];
818 }
819 break;
820 default:
821 c->function = i;
822 c->flags = 0;
823 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
824 break;
825 }
826 }
827
828 if (limit >= 0x0a) {
829 uint32_t ver;
830
831 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
832 if ((ver & 0xff) > 0) {
833 has_msr_architectural_pmu = true;
834 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
835
836 /* Shouldn't be more than 32, since that's the number of bits
837 * available in EBX to tell us _which_ counters are available.
838 * Play it safe.
839 */
840 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
841 num_architectural_pmu_counters = MAX_GP_COUNTERS;
842 }
843 }
844 }
845
846 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
847
848 for (i = 0x80000000; i <= limit; i++) {
849 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
850 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
851 abort();
852 }
853 c = &cpuid_data.entries[cpuid_i++];
854
855 c->function = i;
856 c->flags = 0;
857 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
858 }
859
860 /* Call Centaur's CPUID instructions they are supported. */
861 if (env->cpuid_xlevel2 > 0) {
862 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
863
864 for (i = 0xC0000000; i <= limit; i++) {
865 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
866 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
867 abort();
868 }
869 c = &cpuid_data.entries[cpuid_i++];
870
871 c->function = i;
872 c->flags = 0;
873 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
874 }
875 }
876
877 cpuid_data.cpuid.nent = cpuid_i;
878
879 if (((env->cpuid_version >> 8)&0xF) >= 6
880 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
881 (CPUID_MCE | CPUID_MCA)
882 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
883 uint64_t mcg_cap, unsupported_caps;
884 int banks;
885 int ret;
886
887 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
888 if (ret < 0) {
889 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
890 return ret;
891 }
892
893 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
894 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
895 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
896 return -ENOTSUP;
897 }
898
899 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
900 if (unsupported_caps) {
901 if (unsupported_caps & MCG_LMCE_P) {
902 error_report("kvm: LMCE not supported");
903 return -ENOTSUP;
904 }
905 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
906 unsupported_caps);
907 }
908
909 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
910 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
911 if (ret < 0) {
912 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
913 return ret;
914 }
915 }
916
917 qemu_add_vm_change_state_handler(cpu_update_state, env);
918
919 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
920 if (c) {
921 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
922 !!(c->ecx & CPUID_EXT_SMX);
923 }
924
925 if (env->mcg_cap & MCG_LMCE_P) {
926 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
927 }
928
929 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
930 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
931 /* for migration */
932 error_setg(&invtsc_mig_blocker,
933 "State blocked by non-migratable CPU device"
934 " (invtsc flag)");
935 migrate_add_blocker(invtsc_mig_blocker);
936 /* for savevm */
937 vmstate_x86_cpu.unmigratable = 1;
938 }
939
940 cpuid_data.cpuid.padding = 0;
941 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
942 if (r) {
943 return r;
944 }
945
946 r = kvm_arch_set_tsc_khz(cs);
947 if (r < 0) {
948 return r;
949 }
950
951 /* vcpu's TSC frequency is either specified by user, or following
952 * the value used by KVM if the former is not present. In the
953 * latter case, we query it from KVM and record in env->tsc_khz,
954 * so that vcpu's TSC frequency can be migrated later via this field.
955 */
956 if (!env->tsc_khz) {
957 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
958 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
959 -ENOTSUP;
960 if (r > 0) {
961 env->tsc_khz = r;
962 }
963 }
964
965 if (has_xsave) {
966 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
967 }
968 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
969
970 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
971 has_msr_mtrr = true;
972 }
973 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
974 has_msr_tsc_aux = false;
975 }
976
977 return 0;
978 }
979
980 void kvm_arch_reset_vcpu(X86CPU *cpu)
981 {
982 CPUX86State *env = &cpu->env;
983
984 env->exception_injected = -1;
985 env->interrupt_injected = -1;
986 env->xcr0 = 1;
987 if (kvm_irqchip_in_kernel()) {
988 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
989 KVM_MP_STATE_UNINITIALIZED;
990 } else {
991 env->mp_state = KVM_MP_STATE_RUNNABLE;
992 }
993 }
994
995 void kvm_arch_do_init_vcpu(X86CPU *cpu)
996 {
997 CPUX86State *env = &cpu->env;
998
999 /* APs get directly into wait-for-SIPI state. */
1000 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1001 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1002 }
1003 }
1004
1005 static int kvm_get_supported_msrs(KVMState *s)
1006 {
1007 static int kvm_supported_msrs;
1008 int ret = 0;
1009
1010 /* first time */
1011 if (kvm_supported_msrs == 0) {
1012 struct kvm_msr_list msr_list, *kvm_msr_list;
1013
1014 kvm_supported_msrs = -1;
1015
1016 /* Obtain MSR list from KVM. These are the MSRs that we must
1017 * save/restore */
1018 msr_list.nmsrs = 0;
1019 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1020 if (ret < 0 && ret != -E2BIG) {
1021 return ret;
1022 }
1023 /* Old kernel modules had a bug and could write beyond the provided
1024 memory. Allocate at least a safe amount of 1K. */
1025 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1026 msr_list.nmsrs *
1027 sizeof(msr_list.indices[0])));
1028
1029 kvm_msr_list->nmsrs = msr_list.nmsrs;
1030 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1031 if (ret >= 0) {
1032 int i;
1033
1034 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1035 if (kvm_msr_list->indices[i] == MSR_STAR) {
1036 has_msr_star = true;
1037 continue;
1038 }
1039 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1040 has_msr_hsave_pa = true;
1041 continue;
1042 }
1043 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1044 has_msr_tsc_aux = true;
1045 continue;
1046 }
1047 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1048 has_msr_tsc_adjust = true;
1049 continue;
1050 }
1051 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1052 has_msr_tsc_deadline = true;
1053 continue;
1054 }
1055 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1056 has_msr_smbase = true;
1057 continue;
1058 }
1059 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1060 has_msr_misc_enable = true;
1061 continue;
1062 }
1063 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1064 has_msr_bndcfgs = true;
1065 continue;
1066 }
1067 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1068 has_msr_xss = true;
1069 continue;
1070 }
1071 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1072 has_msr_hv_crash = true;
1073 continue;
1074 }
1075 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1076 has_msr_hv_reset = true;
1077 continue;
1078 }
1079 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1080 has_msr_hv_vpindex = true;
1081 continue;
1082 }
1083 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1084 has_msr_hv_runtime = true;
1085 continue;
1086 }
1087 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1088 has_msr_hv_synic = true;
1089 continue;
1090 }
1091 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1092 has_msr_hv_stimer = true;
1093 continue;
1094 }
1095 }
1096 }
1097
1098 g_free(kvm_msr_list);
1099 }
1100
1101 return ret;
1102 }
1103
1104 static Notifier smram_machine_done;
1105 static KVMMemoryListener smram_listener;
1106 static AddressSpace smram_address_space;
1107 static MemoryRegion smram_as_root;
1108 static MemoryRegion smram_as_mem;
1109
1110 static void register_smram_listener(Notifier *n, void *unused)
1111 {
1112 MemoryRegion *smram =
1113 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1114
1115 /* Outer container... */
1116 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1117 memory_region_set_enabled(&smram_as_root, true);
1118
1119 /* ... with two regions inside: normal system memory with low
1120 * priority, and...
1121 */
1122 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1123 get_system_memory(), 0, ~0ull);
1124 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1125 memory_region_set_enabled(&smram_as_mem, true);
1126
1127 if (smram) {
1128 /* ... SMRAM with higher priority */
1129 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1130 memory_region_set_enabled(smram, true);
1131 }
1132
1133 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1134 kvm_memory_listener_register(kvm_state, &smram_listener,
1135 &smram_address_space, 1);
1136 }
1137
1138 int kvm_arch_init(MachineState *ms, KVMState *s)
1139 {
1140 uint64_t identity_base = 0xfffbc000;
1141 uint64_t shadow_mem;
1142 int ret;
1143 struct utsname utsname;
1144
1145 #ifdef KVM_CAP_XSAVE
1146 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1147 #endif
1148
1149 #ifdef KVM_CAP_XCRS
1150 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1151 #endif
1152
1153 #ifdef KVM_CAP_PIT_STATE2
1154 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1155 #endif
1156
1157 ret = kvm_get_supported_msrs(s);
1158 if (ret < 0) {
1159 return ret;
1160 }
1161
1162 uname(&utsname);
1163 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1164
1165 /*
1166 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1167 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1168 * Since these must be part of guest physical memory, we need to allocate
1169 * them, both by setting their start addresses in the kernel and by
1170 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1171 *
1172 * Older KVM versions may not support setting the identity map base. In
1173 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1174 * size.
1175 */
1176 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1177 /* Allows up to 16M BIOSes. */
1178 identity_base = 0xfeffc000;
1179
1180 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1181 if (ret < 0) {
1182 return ret;
1183 }
1184 }
1185
1186 /* Set TSS base one page after EPT identity map. */
1187 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1188 if (ret < 0) {
1189 return ret;
1190 }
1191
1192 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1193 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1194 if (ret < 0) {
1195 fprintf(stderr, "e820_add_entry() table is full\n");
1196 return ret;
1197 }
1198 qemu_register_reset(kvm_unpoison_all, NULL);
1199
1200 shadow_mem = machine_kvm_shadow_mem(ms);
1201 if (shadow_mem != -1) {
1202 shadow_mem /= 4096;
1203 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1204 if (ret < 0) {
1205 return ret;
1206 }
1207 }
1208
1209 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1210 smram_machine_done.notify = register_smram_listener;
1211 qemu_add_machine_init_done_notifier(&smram_machine_done);
1212 }
1213 return 0;
1214 }
1215
1216 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1217 {
1218 lhs->selector = rhs->selector;
1219 lhs->base = rhs->base;
1220 lhs->limit = rhs->limit;
1221 lhs->type = 3;
1222 lhs->present = 1;
1223 lhs->dpl = 3;
1224 lhs->db = 0;
1225 lhs->s = 1;
1226 lhs->l = 0;
1227 lhs->g = 0;
1228 lhs->avl = 0;
1229 lhs->unusable = 0;
1230 }
1231
1232 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1233 {
1234 unsigned flags = rhs->flags;
1235 lhs->selector = rhs->selector;
1236 lhs->base = rhs->base;
1237 lhs->limit = rhs->limit;
1238 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1239 lhs->present = (flags & DESC_P_MASK) != 0;
1240 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1241 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1242 lhs->s = (flags & DESC_S_MASK) != 0;
1243 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1244 lhs->g = (flags & DESC_G_MASK) != 0;
1245 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1246 lhs->unusable = !lhs->present;
1247 lhs->padding = 0;
1248 }
1249
1250 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1251 {
1252 lhs->selector = rhs->selector;
1253 lhs->base = rhs->base;
1254 lhs->limit = rhs->limit;
1255 if (rhs->unusable) {
1256 lhs->flags = 0;
1257 } else {
1258 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1259 (rhs->present * DESC_P_MASK) |
1260 (rhs->dpl << DESC_DPL_SHIFT) |
1261 (rhs->db << DESC_B_SHIFT) |
1262 (rhs->s * DESC_S_MASK) |
1263 (rhs->l << DESC_L_SHIFT) |
1264 (rhs->g * DESC_G_MASK) |
1265 (rhs->avl * DESC_AVL_MASK);
1266 }
1267 }
1268
1269 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1270 {
1271 if (set) {
1272 *kvm_reg = *qemu_reg;
1273 } else {
1274 *qemu_reg = *kvm_reg;
1275 }
1276 }
1277
1278 static int kvm_getput_regs(X86CPU *cpu, int set)
1279 {
1280 CPUX86State *env = &cpu->env;
1281 struct kvm_regs regs;
1282 int ret = 0;
1283
1284 if (!set) {
1285 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1286 if (ret < 0) {
1287 return ret;
1288 }
1289 }
1290
1291 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1292 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1293 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1294 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1295 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1296 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1297 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1298 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1299 #ifdef TARGET_X86_64
1300 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1301 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1302 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1303 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1304 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1305 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1306 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1307 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1308 #endif
1309
1310 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1311 kvm_getput_reg(&regs.rip, &env->eip, set);
1312
1313 if (set) {
1314 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1315 }
1316
1317 return ret;
1318 }
1319
1320 static int kvm_put_fpu(X86CPU *cpu)
1321 {
1322 CPUX86State *env = &cpu->env;
1323 struct kvm_fpu fpu;
1324 int i;
1325
1326 memset(&fpu, 0, sizeof fpu);
1327 fpu.fsw = env->fpus & ~(7 << 11);
1328 fpu.fsw |= (env->fpstt & 7) << 11;
1329 fpu.fcw = env->fpuc;
1330 fpu.last_opcode = env->fpop;
1331 fpu.last_ip = env->fpip;
1332 fpu.last_dp = env->fpdp;
1333 for (i = 0; i < 8; ++i) {
1334 fpu.ftwx |= (!env->fptags[i]) << i;
1335 }
1336 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1337 for (i = 0; i < CPU_NB_REGS; i++) {
1338 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1339 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1340 }
1341 fpu.mxcsr = env->mxcsr;
1342
1343 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1344 }
1345
1346 #define XSAVE_FCW_FSW 0
1347 #define XSAVE_FTW_FOP 1
1348 #define XSAVE_CWD_RIP 2
1349 #define XSAVE_CWD_RDP 4
1350 #define XSAVE_MXCSR 6
1351 #define XSAVE_ST_SPACE 8
1352 #define XSAVE_XMM_SPACE 40
1353 #define XSAVE_XSTATE_BV 128
1354 #define XSAVE_YMMH_SPACE 144
1355 #define XSAVE_BNDREGS 240
1356 #define XSAVE_BNDCSR 256
1357 #define XSAVE_OPMASK 272
1358 #define XSAVE_ZMM_Hi256 288
1359 #define XSAVE_Hi16_ZMM 416
1360 #define XSAVE_PKRU 672
1361
1362 #define XSAVE_BYTE_OFFSET(word_offset) \
1363 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1364
1365 #define ASSERT_OFFSET(word_offset, field) \
1366 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1367 offsetof(X86XSaveArea, field))
1368
1369 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1370 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1371 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1372 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1373 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1374 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1375 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1376 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1377 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1378 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1379 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1380 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1381 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1382 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1383 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1384
1385 static int kvm_put_xsave(X86CPU *cpu)
1386 {
1387 CPUX86State *env = &cpu->env;
1388 X86XSaveArea *xsave = env->kvm_xsave_buf;
1389 uint16_t cwd, swd, twd;
1390 int i;
1391
1392 if (!has_xsave) {
1393 return kvm_put_fpu(cpu);
1394 }
1395
1396 memset(xsave, 0, sizeof(struct kvm_xsave));
1397 twd = 0;
1398 swd = env->fpus & ~(7 << 11);
1399 swd |= (env->fpstt & 7) << 11;
1400 cwd = env->fpuc;
1401 for (i = 0; i < 8; ++i) {
1402 twd |= (!env->fptags[i]) << i;
1403 }
1404 xsave->legacy.fcw = cwd;
1405 xsave->legacy.fsw = swd;
1406 xsave->legacy.ftw = twd;
1407 xsave->legacy.fpop = env->fpop;
1408 xsave->legacy.fpip = env->fpip;
1409 xsave->legacy.fpdp = env->fpdp;
1410 memcpy(&xsave->legacy.fpregs, env->fpregs,
1411 sizeof env->fpregs);
1412 xsave->legacy.mxcsr = env->mxcsr;
1413 xsave->header.xstate_bv = env->xstate_bv;
1414 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1415 sizeof env->bnd_regs);
1416 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1417 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1418 sizeof env->opmask_regs);
1419
1420 for (i = 0; i < CPU_NB_REGS; i++) {
1421 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1422 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1423 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1424 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1425 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1426 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1427 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1428 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1429 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1430 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1431 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1432 }
1433
1434 #ifdef TARGET_X86_64
1435 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1436 16 * sizeof env->xmm_regs[16]);
1437 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1438 #endif
1439 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1440 }
1441
1442 static int kvm_put_xcrs(X86CPU *cpu)
1443 {
1444 CPUX86State *env = &cpu->env;
1445 struct kvm_xcrs xcrs = {};
1446
1447 if (!has_xcrs) {
1448 return 0;
1449 }
1450
1451 xcrs.nr_xcrs = 1;
1452 xcrs.flags = 0;
1453 xcrs.xcrs[0].xcr = 0;
1454 xcrs.xcrs[0].value = env->xcr0;
1455 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1456 }
1457
1458 static int kvm_put_sregs(X86CPU *cpu)
1459 {
1460 CPUX86State *env = &cpu->env;
1461 struct kvm_sregs sregs;
1462
1463 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1464 if (env->interrupt_injected >= 0) {
1465 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1466 (uint64_t)1 << (env->interrupt_injected % 64);
1467 }
1468
1469 if ((env->eflags & VM_MASK)) {
1470 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1471 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1472 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1473 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1474 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1475 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1476 } else {
1477 set_seg(&sregs.cs, &env->segs[R_CS]);
1478 set_seg(&sregs.ds, &env->segs[R_DS]);
1479 set_seg(&sregs.es, &env->segs[R_ES]);
1480 set_seg(&sregs.fs, &env->segs[R_FS]);
1481 set_seg(&sregs.gs, &env->segs[R_GS]);
1482 set_seg(&sregs.ss, &env->segs[R_SS]);
1483 }
1484
1485 set_seg(&sregs.tr, &env->tr);
1486 set_seg(&sregs.ldt, &env->ldt);
1487
1488 sregs.idt.limit = env->idt.limit;
1489 sregs.idt.base = env->idt.base;
1490 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1491 sregs.gdt.limit = env->gdt.limit;
1492 sregs.gdt.base = env->gdt.base;
1493 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1494
1495 sregs.cr0 = env->cr[0];
1496 sregs.cr2 = env->cr[2];
1497 sregs.cr3 = env->cr[3];
1498 sregs.cr4 = env->cr[4];
1499
1500 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1501 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1502
1503 sregs.efer = env->efer;
1504
1505 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1506 }
1507
1508 static void kvm_msr_buf_reset(X86CPU *cpu)
1509 {
1510 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1511 }
1512
1513 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1514 {
1515 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1516 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1517 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1518
1519 assert((void *)(entry + 1) <= limit);
1520
1521 entry->index = index;
1522 entry->reserved = 0;
1523 entry->data = value;
1524 msrs->nmsrs++;
1525 }
1526
1527 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1528 {
1529 CPUX86State *env = &cpu->env;
1530 int ret;
1531
1532 if (!has_msr_tsc_deadline) {
1533 return 0;
1534 }
1535
1536 kvm_msr_buf_reset(cpu);
1537 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1538
1539 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1540 if (ret < 0) {
1541 return ret;
1542 }
1543
1544 assert(ret == 1);
1545 return 0;
1546 }
1547
1548 /*
1549 * Provide a separate write service for the feature control MSR in order to
1550 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1551 * before writing any other state because forcibly leaving nested mode
1552 * invalidates the VCPU state.
1553 */
1554 static int kvm_put_msr_feature_control(X86CPU *cpu)
1555 {
1556 int ret;
1557
1558 if (!has_msr_feature_control) {
1559 return 0;
1560 }
1561
1562 kvm_msr_buf_reset(cpu);
1563 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL,
1564 cpu->env.msr_ia32_feature_control);
1565
1566 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1567 if (ret < 0) {
1568 return ret;
1569 }
1570
1571 assert(ret == 1);
1572 return 0;
1573 }
1574
1575 static int kvm_put_msrs(X86CPU *cpu, int level)
1576 {
1577 CPUX86State *env = &cpu->env;
1578 int i;
1579 int ret;
1580
1581 kvm_msr_buf_reset(cpu);
1582
1583 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1584 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1585 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1586 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1587 if (has_msr_star) {
1588 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1589 }
1590 if (has_msr_hsave_pa) {
1591 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1592 }
1593 if (has_msr_tsc_aux) {
1594 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1595 }
1596 if (has_msr_tsc_adjust) {
1597 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1598 }
1599 if (has_msr_misc_enable) {
1600 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1601 env->msr_ia32_misc_enable);
1602 }
1603 if (has_msr_smbase) {
1604 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1605 }
1606 if (has_msr_bndcfgs) {
1607 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1608 }
1609 if (has_msr_xss) {
1610 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1611 }
1612 #ifdef TARGET_X86_64
1613 if (lm_capable_kernel) {
1614 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1615 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1616 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1617 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1618 }
1619 #endif
1620 /*
1621 * The following MSRs have side effects on the guest or are too heavy
1622 * for normal writeback. Limit them to reset or full state updates.
1623 */
1624 if (level >= KVM_PUT_RESET_STATE) {
1625 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1626 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1627 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1628 if (has_msr_async_pf_en) {
1629 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1630 }
1631 if (has_msr_pv_eoi_en) {
1632 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1633 }
1634 if (has_msr_kvm_steal_time) {
1635 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1636 }
1637 if (has_msr_architectural_pmu) {
1638 /* Stop the counter. */
1639 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1640 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1641
1642 /* Set the counter values. */
1643 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1644 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1645 env->msr_fixed_counters[i]);
1646 }
1647 for (i = 0; i < num_architectural_pmu_counters; i++) {
1648 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1649 env->msr_gp_counters[i]);
1650 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1651 env->msr_gp_evtsel[i]);
1652 }
1653 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1654 env->msr_global_status);
1655 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1656 env->msr_global_ovf_ctrl);
1657
1658 /* Now start the PMU. */
1659 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1660 env->msr_fixed_ctr_ctrl);
1661 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1662 env->msr_global_ctrl);
1663 }
1664 if (has_msr_hv_hypercall) {
1665 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1666 env->msr_hv_guest_os_id);
1667 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1668 env->msr_hv_hypercall);
1669 }
1670 if (has_msr_hv_vapic) {
1671 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1672 env->msr_hv_vapic);
1673 }
1674 if (has_msr_hv_tsc) {
1675 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1676 }
1677 if (has_msr_hv_crash) {
1678 int j;
1679
1680 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1681 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1682 env->msr_hv_crash_params[j]);
1683
1684 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1685 HV_X64_MSR_CRASH_CTL_NOTIFY);
1686 }
1687 if (has_msr_hv_runtime) {
1688 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1689 }
1690 if (cpu->hyperv_synic) {
1691 int j;
1692
1693 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1694 env->msr_hv_synic_control);
1695 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1696 env->msr_hv_synic_version);
1697 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1698 env->msr_hv_synic_evt_page);
1699 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1700 env->msr_hv_synic_msg_page);
1701
1702 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1703 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1704 env->msr_hv_synic_sint[j]);
1705 }
1706 }
1707 if (has_msr_hv_stimer) {
1708 int j;
1709
1710 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1711 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1712 env->msr_hv_stimer_config[j]);
1713 }
1714
1715 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1716 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1717 env->msr_hv_stimer_count[j]);
1718 }
1719 }
1720 if (has_msr_mtrr) {
1721 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1722 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1723 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1724 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1725 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1726 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1727 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1728 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1729 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1730 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1731 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1732 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1733 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1734 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1735 env->mtrr_var[i].base);
1736 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i),
1737 env->mtrr_var[i].mask);
1738 }
1739 }
1740
1741 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1742 * kvm_put_msr_feature_control. */
1743 }
1744 if (env->mcg_cap) {
1745 int i;
1746
1747 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1748 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1749 if (has_msr_mcg_ext_ctl) {
1750 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1751 }
1752 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1753 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1754 }
1755 }
1756
1757 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1758 if (ret < 0) {
1759 return ret;
1760 }
1761
1762 assert(ret == cpu->kvm_msr_buf->nmsrs);
1763 return 0;
1764 }
1765
1766
1767 static int kvm_get_fpu(X86CPU *cpu)
1768 {
1769 CPUX86State *env = &cpu->env;
1770 struct kvm_fpu fpu;
1771 int i, ret;
1772
1773 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1774 if (ret < 0) {
1775 return ret;
1776 }
1777
1778 env->fpstt = (fpu.fsw >> 11) & 7;
1779 env->fpus = fpu.fsw;
1780 env->fpuc = fpu.fcw;
1781 env->fpop = fpu.last_opcode;
1782 env->fpip = fpu.last_ip;
1783 env->fpdp = fpu.last_dp;
1784 for (i = 0; i < 8; ++i) {
1785 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1786 }
1787 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1788 for (i = 0; i < CPU_NB_REGS; i++) {
1789 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1790 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1791 }
1792 env->mxcsr = fpu.mxcsr;
1793
1794 return 0;
1795 }
1796
1797 static int kvm_get_xsave(X86CPU *cpu)
1798 {
1799 CPUX86State *env = &cpu->env;
1800 X86XSaveArea *xsave = env->kvm_xsave_buf;
1801 int ret, i;
1802 uint16_t cwd, swd, twd;
1803
1804 if (!has_xsave) {
1805 return kvm_get_fpu(cpu);
1806 }
1807
1808 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1809 if (ret < 0) {
1810 return ret;
1811 }
1812
1813 cwd = xsave->legacy.fcw;
1814 swd = xsave->legacy.fsw;
1815 twd = xsave->legacy.ftw;
1816 env->fpop = xsave->legacy.fpop;
1817 env->fpstt = (swd >> 11) & 7;
1818 env->fpus = swd;
1819 env->fpuc = cwd;
1820 for (i = 0; i < 8; ++i) {
1821 env->fptags[i] = !((twd >> i) & 1);
1822 }
1823 env->fpip = xsave->legacy.fpip;
1824 env->fpdp = xsave->legacy.fpdp;
1825 env->mxcsr = xsave->legacy.mxcsr;
1826 memcpy(env->fpregs, &xsave->legacy.fpregs,
1827 sizeof env->fpregs);
1828 env->xstate_bv = xsave->header.xstate_bv;
1829 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1830 sizeof env->bnd_regs);
1831 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1832 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1833 sizeof env->opmask_regs);
1834
1835 for (i = 0; i < CPU_NB_REGS; i++) {
1836 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1837 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1838 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1839 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1840 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1841 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1842 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1843 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1844 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1845 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1846 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1847 }
1848
1849 #ifdef TARGET_X86_64
1850 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1851 16 * sizeof env->xmm_regs[16]);
1852 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1853 #endif
1854 return 0;
1855 }
1856
1857 static int kvm_get_xcrs(X86CPU *cpu)
1858 {
1859 CPUX86State *env = &cpu->env;
1860 int i, ret;
1861 struct kvm_xcrs xcrs;
1862
1863 if (!has_xcrs) {
1864 return 0;
1865 }
1866
1867 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1868 if (ret < 0) {
1869 return ret;
1870 }
1871
1872 for (i = 0; i < xcrs.nr_xcrs; i++) {
1873 /* Only support xcr0 now */
1874 if (xcrs.xcrs[i].xcr == 0) {
1875 env->xcr0 = xcrs.xcrs[i].value;
1876 break;
1877 }
1878 }
1879 return 0;
1880 }
1881
1882 static int kvm_get_sregs(X86CPU *cpu)
1883 {
1884 CPUX86State *env = &cpu->env;
1885 struct kvm_sregs sregs;
1886 uint32_t hflags;
1887 int bit, i, ret;
1888
1889 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1890 if (ret < 0) {
1891 return ret;
1892 }
1893
1894 /* There can only be one pending IRQ set in the bitmap at a time, so try
1895 to find it and save its number instead (-1 for none). */
1896 env->interrupt_injected = -1;
1897 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1898 if (sregs.interrupt_bitmap[i]) {
1899 bit = ctz64(sregs.interrupt_bitmap[i]);
1900 env->interrupt_injected = i * 64 + bit;
1901 break;
1902 }
1903 }
1904
1905 get_seg(&env->segs[R_CS], &sregs.cs);
1906 get_seg(&env->segs[R_DS], &sregs.ds);
1907 get_seg(&env->segs[R_ES], &sregs.es);
1908 get_seg(&env->segs[R_FS], &sregs.fs);
1909 get_seg(&env->segs[R_GS], &sregs.gs);
1910 get_seg(&env->segs[R_SS], &sregs.ss);
1911
1912 get_seg(&env->tr, &sregs.tr);
1913 get_seg(&env->ldt, &sregs.ldt);
1914
1915 env->idt.limit = sregs.idt.limit;
1916 env->idt.base = sregs.idt.base;
1917 env->gdt.limit = sregs.gdt.limit;
1918 env->gdt.base = sregs.gdt.base;
1919
1920 env->cr[0] = sregs.cr0;
1921 env->cr[2] = sregs.cr2;
1922 env->cr[3] = sregs.cr3;
1923 env->cr[4] = sregs.cr4;
1924
1925 env->efer = sregs.efer;
1926
1927 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1928
1929 #define HFLAG_COPY_MASK \
1930 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1931 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1932 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1933 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1934
1935 hflags = env->hflags & HFLAG_COPY_MASK;
1936 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1937 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1938 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1939 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1940 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1941
1942 if (env->cr[4] & CR4_OSFXSR_MASK) {
1943 hflags |= HF_OSFXSR_MASK;
1944 }
1945
1946 if (env->efer & MSR_EFER_LMA) {
1947 hflags |= HF_LMA_MASK;
1948 }
1949
1950 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1951 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1952 } else {
1953 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1954 (DESC_B_SHIFT - HF_CS32_SHIFT);
1955 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1956 (DESC_B_SHIFT - HF_SS32_SHIFT);
1957 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1958 !(hflags & HF_CS32_MASK)) {
1959 hflags |= HF_ADDSEG_MASK;
1960 } else {
1961 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1962 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1963 }
1964 }
1965 env->hflags = hflags;
1966
1967 return 0;
1968 }
1969
1970 static int kvm_get_msrs(X86CPU *cpu)
1971 {
1972 CPUX86State *env = &cpu->env;
1973 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1974 int ret, i;
1975
1976 kvm_msr_buf_reset(cpu);
1977
1978 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1979 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1980 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1981 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1982 if (has_msr_star) {
1983 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1984 }
1985 if (has_msr_hsave_pa) {
1986 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1987 }
1988 if (has_msr_tsc_aux) {
1989 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1990 }
1991 if (has_msr_tsc_adjust) {
1992 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
1993 }
1994 if (has_msr_tsc_deadline) {
1995 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
1996 }
1997 if (has_msr_misc_enable) {
1998 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
1999 }
2000 if (has_msr_smbase) {
2001 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2002 }
2003 if (has_msr_feature_control) {
2004 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2005 }
2006 if (has_msr_bndcfgs) {
2007 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2008 }
2009 if (has_msr_xss) {
2010 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2011 }
2012
2013
2014 if (!env->tsc_valid) {
2015 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2016 env->tsc_valid = !runstate_is_running();
2017 }
2018
2019 #ifdef TARGET_X86_64
2020 if (lm_capable_kernel) {
2021 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2022 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2023 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2024 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2025 }
2026 #endif
2027 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2028 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2029 if (has_msr_async_pf_en) {
2030 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2031 }
2032 if (has_msr_pv_eoi_en) {
2033 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2034 }
2035 if (has_msr_kvm_steal_time) {
2036 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2037 }
2038 if (has_msr_architectural_pmu) {
2039 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2040 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2041 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2042 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2043 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2044 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2045 }
2046 for (i = 0; i < num_architectural_pmu_counters; i++) {
2047 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2048 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2049 }
2050 }
2051
2052 if (env->mcg_cap) {
2053 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2054 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2055 if (has_msr_mcg_ext_ctl) {
2056 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2057 }
2058 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2059 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2060 }
2061 }
2062
2063 if (has_msr_hv_hypercall) {
2064 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2065 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2066 }
2067 if (has_msr_hv_vapic) {
2068 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2069 }
2070 if (has_msr_hv_tsc) {
2071 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2072 }
2073 if (has_msr_hv_crash) {
2074 int j;
2075
2076 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2077 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2078 }
2079 }
2080 if (has_msr_hv_runtime) {
2081 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2082 }
2083 if (cpu->hyperv_synic) {
2084 uint32_t msr;
2085
2086 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2087 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2088 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2089 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2090 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2091 kvm_msr_entry_add(cpu, msr, 0);
2092 }
2093 }
2094 if (has_msr_hv_stimer) {
2095 uint32_t msr;
2096
2097 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2098 msr++) {
2099 kvm_msr_entry_add(cpu, msr, 0);
2100 }
2101 }
2102 if (has_msr_mtrr) {
2103 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2104 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2105 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2106 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2107 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2108 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2109 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2110 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2111 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2112 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2113 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2114 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2115 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2116 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2117 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2118 }
2119 }
2120
2121 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2122 if (ret < 0) {
2123 return ret;
2124 }
2125
2126 assert(ret == cpu->kvm_msr_buf->nmsrs);
2127 for (i = 0; i < ret; i++) {
2128 uint32_t index = msrs[i].index;
2129 switch (index) {
2130 case MSR_IA32_SYSENTER_CS:
2131 env->sysenter_cs = msrs[i].data;
2132 break;
2133 case MSR_IA32_SYSENTER_ESP:
2134 env->sysenter_esp = msrs[i].data;
2135 break;
2136 case MSR_IA32_SYSENTER_EIP:
2137 env->sysenter_eip = msrs[i].data;
2138 break;
2139 case MSR_PAT:
2140 env->pat = msrs[i].data;
2141 break;
2142 case MSR_STAR:
2143 env->star = msrs[i].data;
2144 break;
2145 #ifdef TARGET_X86_64
2146 case MSR_CSTAR:
2147 env->cstar = msrs[i].data;
2148 break;
2149 case MSR_KERNELGSBASE:
2150 env->kernelgsbase = msrs[i].data;
2151 break;
2152 case MSR_FMASK:
2153 env->fmask = msrs[i].data;
2154 break;
2155 case MSR_LSTAR:
2156 env->lstar = msrs[i].data;
2157 break;
2158 #endif
2159 case MSR_IA32_TSC:
2160 env->tsc = msrs[i].data;
2161 break;
2162 case MSR_TSC_AUX:
2163 env->tsc_aux = msrs[i].data;
2164 break;
2165 case MSR_TSC_ADJUST:
2166 env->tsc_adjust = msrs[i].data;
2167 break;
2168 case MSR_IA32_TSCDEADLINE:
2169 env->tsc_deadline = msrs[i].data;
2170 break;
2171 case MSR_VM_HSAVE_PA:
2172 env->vm_hsave = msrs[i].data;
2173 break;
2174 case MSR_KVM_SYSTEM_TIME:
2175 env->system_time_msr = msrs[i].data;
2176 break;
2177 case MSR_KVM_WALL_CLOCK:
2178 env->wall_clock_msr = msrs[i].data;
2179 break;
2180 case MSR_MCG_STATUS:
2181 env->mcg_status = msrs[i].data;
2182 break;
2183 case MSR_MCG_CTL:
2184 env->mcg_ctl = msrs[i].data;
2185 break;
2186 case MSR_MCG_EXT_CTL:
2187 env->mcg_ext_ctl = msrs[i].data;
2188 break;
2189 case MSR_IA32_MISC_ENABLE:
2190 env->msr_ia32_misc_enable = msrs[i].data;
2191 break;
2192 case MSR_IA32_SMBASE:
2193 env->smbase = msrs[i].data;
2194 break;
2195 case MSR_IA32_FEATURE_CONTROL:
2196 env->msr_ia32_feature_control = msrs[i].data;
2197 break;
2198 case MSR_IA32_BNDCFGS:
2199 env->msr_bndcfgs = msrs[i].data;
2200 break;
2201 case MSR_IA32_XSS:
2202 env->xss = msrs[i].data;
2203 break;
2204 default:
2205 if (msrs[i].index >= MSR_MC0_CTL &&
2206 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2207 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2208 }
2209 break;
2210 case MSR_KVM_ASYNC_PF_EN:
2211 env->async_pf_en_msr = msrs[i].data;
2212 break;
2213 case MSR_KVM_PV_EOI_EN:
2214 env->pv_eoi_en_msr = msrs[i].data;
2215 break;
2216 case MSR_KVM_STEAL_TIME:
2217 env->steal_time_msr = msrs[i].data;
2218 break;
2219 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2220 env->msr_fixed_ctr_ctrl = msrs[i].data;
2221 break;
2222 case MSR_CORE_PERF_GLOBAL_CTRL:
2223 env->msr_global_ctrl = msrs[i].data;
2224 break;
2225 case MSR_CORE_PERF_GLOBAL_STATUS:
2226 env->msr_global_status = msrs[i].data;
2227 break;
2228 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2229 env->msr_global_ovf_ctrl = msrs[i].data;
2230 break;
2231 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2232 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2233 break;
2234 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2235 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2236 break;
2237 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2238 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2239 break;
2240 case HV_X64_MSR_HYPERCALL:
2241 env->msr_hv_hypercall = msrs[i].data;
2242 break;
2243 case HV_X64_MSR_GUEST_OS_ID:
2244 env->msr_hv_guest_os_id = msrs[i].data;
2245 break;
2246 case HV_X64_MSR_APIC_ASSIST_PAGE:
2247 env->msr_hv_vapic = msrs[i].data;
2248 break;
2249 case HV_X64_MSR_REFERENCE_TSC:
2250 env->msr_hv_tsc = msrs[i].data;
2251 break;
2252 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2253 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2254 break;
2255 case HV_X64_MSR_VP_RUNTIME:
2256 env->msr_hv_runtime = msrs[i].data;
2257 break;
2258 case HV_X64_MSR_SCONTROL:
2259 env->msr_hv_synic_control = msrs[i].data;
2260 break;
2261 case HV_X64_MSR_SVERSION:
2262 env->msr_hv_synic_version = msrs[i].data;
2263 break;
2264 case HV_X64_MSR_SIEFP:
2265 env->msr_hv_synic_evt_page = msrs[i].data;
2266 break;
2267 case HV_X64_MSR_SIMP:
2268 env->msr_hv_synic_msg_page = msrs[i].data;
2269 break;
2270 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2271 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2272 break;
2273 case HV_X64_MSR_STIMER0_CONFIG:
2274 case HV_X64_MSR_STIMER1_CONFIG:
2275 case HV_X64_MSR_STIMER2_CONFIG:
2276 case HV_X64_MSR_STIMER3_CONFIG:
2277 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2278 msrs[i].data;
2279 break;
2280 case HV_X64_MSR_STIMER0_COUNT:
2281 case HV_X64_MSR_STIMER1_COUNT:
2282 case HV_X64_MSR_STIMER2_COUNT:
2283 case HV_X64_MSR_STIMER3_COUNT:
2284 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2285 msrs[i].data;
2286 break;
2287 case MSR_MTRRdefType:
2288 env->mtrr_deftype = msrs[i].data;
2289 break;
2290 case MSR_MTRRfix64K_00000:
2291 env->mtrr_fixed[0] = msrs[i].data;
2292 break;
2293 case MSR_MTRRfix16K_80000:
2294 env->mtrr_fixed[1] = msrs[i].data;
2295 break;
2296 case MSR_MTRRfix16K_A0000:
2297 env->mtrr_fixed[2] = msrs[i].data;
2298 break;
2299 case MSR_MTRRfix4K_C0000:
2300 env->mtrr_fixed[3] = msrs[i].data;
2301 break;
2302 case MSR_MTRRfix4K_C8000:
2303 env->mtrr_fixed[4] = msrs[i].data;
2304 break;
2305 case MSR_MTRRfix4K_D0000:
2306 env->mtrr_fixed[5] = msrs[i].data;
2307 break;
2308 case MSR_MTRRfix4K_D8000:
2309 env->mtrr_fixed[6] = msrs[i].data;
2310 break;
2311 case MSR_MTRRfix4K_E0000:
2312 env->mtrr_fixed[7] = msrs[i].data;
2313 break;
2314 case MSR_MTRRfix4K_E8000:
2315 env->mtrr_fixed[8] = msrs[i].data;
2316 break;
2317 case MSR_MTRRfix4K_F0000:
2318 env->mtrr_fixed[9] = msrs[i].data;
2319 break;
2320 case MSR_MTRRfix4K_F8000:
2321 env->mtrr_fixed[10] = msrs[i].data;
2322 break;
2323 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2324 if (index & 1) {
2325 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2326 } else {
2327 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2328 }
2329 break;
2330 }
2331 }
2332
2333 return 0;
2334 }
2335
2336 static int kvm_put_mp_state(X86CPU *cpu)
2337 {
2338 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2339
2340 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2341 }
2342
2343 static int kvm_get_mp_state(X86CPU *cpu)
2344 {
2345 CPUState *cs = CPU(cpu);
2346 CPUX86State *env = &cpu->env;
2347 struct kvm_mp_state mp_state;
2348 int ret;
2349
2350 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2351 if (ret < 0) {
2352 return ret;
2353 }
2354 env->mp_state = mp_state.mp_state;
2355 if (kvm_irqchip_in_kernel()) {
2356 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2357 }
2358 return 0;
2359 }
2360
2361 static int kvm_get_apic(X86CPU *cpu)
2362 {
2363 DeviceState *apic = cpu->apic_state;
2364 struct kvm_lapic_state kapic;
2365 int ret;
2366
2367 if (apic && kvm_irqchip_in_kernel()) {
2368 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2369 if (ret < 0) {
2370 return ret;
2371 }
2372
2373 kvm_get_apic_state(apic, &kapic);
2374 }
2375 return 0;
2376 }
2377
2378 static int kvm_put_apic(X86CPU *cpu)
2379 {
2380 DeviceState *apic = cpu->apic_state;
2381 struct kvm_lapic_state kapic;
2382
2383 if (apic && kvm_irqchip_in_kernel()) {
2384 kvm_put_apic_state(apic, &kapic);
2385
2386 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2387 }
2388 return 0;
2389 }
2390
2391 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2392 {
2393 CPUState *cs = CPU(cpu);
2394 CPUX86State *env = &cpu->env;
2395 struct kvm_vcpu_events events = {};
2396
2397 if (!kvm_has_vcpu_events()) {
2398 return 0;
2399 }
2400
2401 events.exception.injected = (env->exception_injected >= 0);
2402 events.exception.nr = env->exception_injected;
2403 events.exception.has_error_code = env->has_error_code;
2404 events.exception.error_code = env->error_code;
2405 events.exception.pad = 0;
2406
2407 events.interrupt.injected = (env->interrupt_injected >= 0);
2408 events.interrupt.nr = env->interrupt_injected;
2409 events.interrupt.soft = env->soft_interrupt;
2410
2411 events.nmi.injected = env->nmi_injected;
2412 events.nmi.pending = env->nmi_pending;
2413 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2414 events.nmi.pad = 0;
2415
2416 events.sipi_vector = env->sipi_vector;
2417
2418 if (has_msr_smbase) {
2419 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2420 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2421 if (kvm_irqchip_in_kernel()) {
2422 /* As soon as these are moved to the kernel, remove them
2423 * from cs->interrupt_request.
2424 */
2425 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2426 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2427 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2428 } else {
2429 /* Keep these in cs->interrupt_request. */
2430 events.smi.pending = 0;
2431 events.smi.latched_init = 0;
2432 }
2433 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2434 }
2435
2436 events.flags = 0;
2437 if (level >= KVM_PUT_RESET_STATE) {
2438 events.flags |=
2439 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2440 }
2441
2442 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2443 }
2444
2445 static int kvm_get_vcpu_events(X86CPU *cpu)
2446 {
2447 CPUX86State *env = &cpu->env;
2448 struct kvm_vcpu_events events;
2449 int ret;
2450
2451 if (!kvm_has_vcpu_events()) {
2452 return 0;
2453 }
2454
2455 memset(&events, 0, sizeof(events));
2456 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2457 if (ret < 0) {
2458 return ret;
2459 }
2460 env->exception_injected =
2461 events.exception.injected ? events.exception.nr : -1;
2462 env->has_error_code = events.exception.has_error_code;
2463 env->error_code = events.exception.error_code;
2464
2465 env->interrupt_injected =
2466 events.interrupt.injected ? events.interrupt.nr : -1;
2467 env->soft_interrupt = events.interrupt.soft;
2468
2469 env->nmi_injected = events.nmi.injected;
2470 env->nmi_pending = events.nmi.pending;
2471 if (events.nmi.masked) {
2472 env->hflags2 |= HF2_NMI_MASK;
2473 } else {
2474 env->hflags2 &= ~HF2_NMI_MASK;
2475 }
2476
2477 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2478 if (events.smi.smm) {
2479 env->hflags |= HF_SMM_MASK;
2480 } else {
2481 env->hflags &= ~HF_SMM_MASK;
2482 }
2483 if (events.smi.pending) {
2484 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2485 } else {
2486 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2487 }
2488 if (events.smi.smm_inside_nmi) {
2489 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2490 } else {
2491 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2492 }
2493 if (events.smi.latched_init) {
2494 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2495 } else {
2496 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2497 }
2498 }
2499
2500 env->sipi_vector = events.sipi_vector;
2501
2502 return 0;
2503 }
2504
2505 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2506 {
2507 CPUState *cs = CPU(cpu);
2508 CPUX86State *env = &cpu->env;
2509 int ret = 0;
2510 unsigned long reinject_trap = 0;
2511
2512 if (!kvm_has_vcpu_events()) {
2513 if (env->exception_injected == 1) {
2514 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2515 } else if (env->exception_injected == 3) {
2516 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2517 }
2518 env->exception_injected = -1;
2519 }
2520
2521 /*
2522 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2523 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2524 * by updating the debug state once again if single-stepping is on.
2525 * Another reason to call kvm_update_guest_debug here is a pending debug
2526 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2527 * reinject them via SET_GUEST_DEBUG.
2528 */
2529 if (reinject_trap ||
2530 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2531 ret = kvm_update_guest_debug(cs, reinject_trap);
2532 }
2533 return ret;
2534 }
2535
2536 static int kvm_put_debugregs(X86CPU *cpu)
2537 {
2538 CPUX86State *env = &cpu->env;
2539 struct kvm_debugregs dbgregs;
2540 int i;
2541
2542 if (!kvm_has_debugregs()) {
2543 return 0;
2544 }
2545
2546 for (i = 0; i < 4; i++) {
2547 dbgregs.db[i] = env->dr[i];
2548 }
2549 dbgregs.dr6 = env->dr[6];
2550 dbgregs.dr7 = env->dr[7];
2551 dbgregs.flags = 0;
2552
2553 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2554 }
2555
2556 static int kvm_get_debugregs(X86CPU *cpu)
2557 {
2558 CPUX86State *env = &cpu->env;
2559 struct kvm_debugregs dbgregs;
2560 int i, ret;
2561
2562 if (!kvm_has_debugregs()) {
2563 return 0;
2564 }
2565
2566 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2567 if (ret < 0) {
2568 return ret;
2569 }
2570 for (i = 0; i < 4; i++) {
2571 env->dr[i] = dbgregs.db[i];
2572 }
2573 env->dr[4] = env->dr[6] = dbgregs.dr6;
2574 env->dr[5] = env->dr[7] = dbgregs.dr7;
2575
2576 return 0;
2577 }
2578
2579 int kvm_arch_put_registers(CPUState *cpu, int level)
2580 {
2581 X86CPU *x86_cpu = X86_CPU(cpu);
2582 int ret;
2583
2584 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2585
2586 if (level >= KVM_PUT_RESET_STATE) {
2587 ret = kvm_put_msr_feature_control(x86_cpu);
2588 if (ret < 0) {
2589 return ret;
2590 }
2591 }
2592
2593 if (level == KVM_PUT_FULL_STATE) {
2594 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2595 * because TSC frequency mismatch shouldn't abort migration,
2596 * unless the user explicitly asked for a more strict TSC
2597 * setting (e.g. using an explicit "tsc-freq" option).
2598 */
2599 kvm_arch_set_tsc_khz(cpu);
2600 }
2601
2602 ret = kvm_getput_regs(x86_cpu, 1);
2603 if (ret < 0) {
2604 return ret;
2605 }
2606 ret = kvm_put_xsave(x86_cpu);
2607 if (ret < 0) {
2608 return ret;
2609 }
2610 ret = kvm_put_xcrs(x86_cpu);
2611 if (ret < 0) {
2612 return ret;
2613 }
2614 ret = kvm_put_sregs(x86_cpu);
2615 if (ret < 0) {
2616 return ret;
2617 }
2618 /* must be before kvm_put_msrs */
2619 ret = kvm_inject_mce_oldstyle(x86_cpu);
2620 if (ret < 0) {
2621 return ret;
2622 }
2623 ret = kvm_put_msrs(x86_cpu, level);
2624 if (ret < 0) {
2625 return ret;
2626 }
2627 if (level >= KVM_PUT_RESET_STATE) {
2628 ret = kvm_put_mp_state(x86_cpu);
2629 if (ret < 0) {
2630 return ret;
2631 }
2632 ret = kvm_put_apic(x86_cpu);
2633 if (ret < 0) {
2634 return ret;
2635 }
2636 }
2637
2638 ret = kvm_put_tscdeadline_msr(x86_cpu);
2639 if (ret < 0) {
2640 return ret;
2641 }
2642
2643 ret = kvm_put_vcpu_events(x86_cpu, level);
2644 if (ret < 0) {
2645 return ret;
2646 }
2647 ret = kvm_put_debugregs(x86_cpu);
2648 if (ret < 0) {
2649 return ret;
2650 }
2651 /* must be last */
2652 ret = kvm_guest_debug_workarounds(x86_cpu);
2653 if (ret < 0) {
2654 return ret;
2655 }
2656 return 0;
2657 }
2658
2659 int kvm_arch_get_registers(CPUState *cs)
2660 {
2661 X86CPU *cpu = X86_CPU(cs);
2662 int ret;
2663
2664 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2665
2666 ret = kvm_getput_regs(cpu, 0);
2667 if (ret < 0) {
2668 goto out;
2669 }
2670 ret = kvm_get_xsave(cpu);
2671 if (ret < 0) {
2672 goto out;
2673 }
2674 ret = kvm_get_xcrs(cpu);
2675 if (ret < 0) {
2676 goto out;
2677 }
2678 ret = kvm_get_sregs(cpu);
2679 if (ret < 0) {
2680 goto out;
2681 }
2682 ret = kvm_get_msrs(cpu);
2683 if (ret < 0) {
2684 goto out;
2685 }
2686 ret = kvm_get_mp_state(cpu);
2687 if (ret < 0) {
2688 goto out;
2689 }
2690 ret = kvm_get_apic(cpu);
2691 if (ret < 0) {
2692 goto out;
2693 }
2694 ret = kvm_get_vcpu_events(cpu);
2695 if (ret < 0) {
2696 goto out;
2697 }
2698 ret = kvm_get_debugregs(cpu);
2699 if (ret < 0) {
2700 goto out;
2701 }
2702 ret = 0;
2703 out:
2704 cpu_sync_bndcs_hflags(&cpu->env);
2705 return ret;
2706 }
2707
2708 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2709 {
2710 X86CPU *x86_cpu = X86_CPU(cpu);
2711 CPUX86State *env = &x86_cpu->env;
2712 int ret;
2713
2714 /* Inject NMI */
2715 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2716 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2717 qemu_mutex_lock_iothread();
2718 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2719 qemu_mutex_unlock_iothread();
2720 DPRINTF("injected NMI\n");
2721 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2722 if (ret < 0) {
2723 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2724 strerror(-ret));
2725 }
2726 }
2727 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2728 qemu_mutex_lock_iothread();
2729 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2730 qemu_mutex_unlock_iothread();
2731 DPRINTF("injected SMI\n");
2732 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2733 if (ret < 0) {
2734 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2735 strerror(-ret));
2736 }
2737 }
2738 }
2739
2740 if (!kvm_pic_in_kernel()) {
2741 qemu_mutex_lock_iothread();
2742 }
2743
2744 /* Force the VCPU out of its inner loop to process any INIT requests
2745 * or (for userspace APIC, but it is cheap to combine the checks here)
2746 * pending TPR access reports.
2747 */
2748 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2749 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2750 !(env->hflags & HF_SMM_MASK)) {
2751 cpu->exit_request = 1;
2752 }
2753 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2754 cpu->exit_request = 1;
2755 }
2756 }
2757
2758 if (!kvm_pic_in_kernel()) {
2759 /* Try to inject an interrupt if the guest can accept it */
2760 if (run->ready_for_interrupt_injection &&
2761 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2762 (env->eflags & IF_MASK)) {
2763 int irq;
2764
2765 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2766 irq = cpu_get_pic_interrupt(env);
2767 if (irq >= 0) {
2768 struct kvm_interrupt intr;
2769
2770 intr.irq = irq;
2771 DPRINTF("injected interrupt %d\n", irq);
2772 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2773 if (ret < 0) {
2774 fprintf(stderr,
2775 "KVM: injection failed, interrupt lost (%s)\n",
2776 strerror(-ret));
2777 }
2778 }
2779 }
2780
2781 /* If we have an interrupt but the guest is not ready to receive an
2782 * interrupt, request an interrupt window exit. This will
2783 * cause a return to userspace as soon as the guest is ready to
2784 * receive interrupts. */
2785 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2786 run->request_interrupt_window = 1;
2787 } else {
2788 run->request_interrupt_window = 0;
2789 }
2790
2791 DPRINTF("setting tpr\n");
2792 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2793
2794 qemu_mutex_unlock_iothread();
2795 }
2796 }
2797
2798 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2799 {
2800 X86CPU *x86_cpu = X86_CPU(cpu);
2801 CPUX86State *env = &x86_cpu->env;
2802
2803 if (run->flags & KVM_RUN_X86_SMM) {
2804 env->hflags |= HF_SMM_MASK;
2805 } else {
2806 env->hflags &= HF_SMM_MASK;
2807 }
2808 if (run->if_flag) {
2809 env->eflags |= IF_MASK;
2810 } else {
2811 env->eflags &= ~IF_MASK;
2812 }
2813
2814 /* We need to protect the apic state against concurrent accesses from
2815 * different threads in case the userspace irqchip is used. */
2816 if (!kvm_irqchip_in_kernel()) {
2817 qemu_mutex_lock_iothread();
2818 }
2819 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2820 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2821 if (!kvm_irqchip_in_kernel()) {
2822 qemu_mutex_unlock_iothread();
2823 }
2824 return cpu_get_mem_attrs(env);
2825 }
2826
2827 int kvm_arch_process_async_events(CPUState *cs)
2828 {
2829 X86CPU *cpu = X86_CPU(cs);
2830 CPUX86State *env = &cpu->env;
2831
2832 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2833 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2834 assert(env->mcg_cap);
2835
2836 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2837
2838 kvm_cpu_synchronize_state(cs);
2839
2840 if (env->exception_injected == EXCP08_DBLE) {
2841 /* this means triple fault */
2842 qemu_system_reset_request();
2843 cs->exit_request = 1;
2844 return 0;
2845 }
2846 env->exception_injected = EXCP12_MCHK;
2847 env->has_error_code = 0;
2848
2849 cs->halted = 0;
2850 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2851 env->mp_state = KVM_MP_STATE_RUNNABLE;
2852 }
2853 }
2854
2855 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2856 !(env->hflags & HF_SMM_MASK)) {
2857 kvm_cpu_synchronize_state(cs);
2858 do_cpu_init(cpu);
2859 }
2860
2861 if (kvm_irqchip_in_kernel()) {
2862 return 0;
2863 }
2864
2865 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2866 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2867 apic_poll_irq(cpu->apic_state);
2868 }
2869 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2870 (env->eflags & IF_MASK)) ||
2871 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2872 cs->halted = 0;
2873 }
2874 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2875 kvm_cpu_synchronize_state(cs);
2876 do_cpu_sipi(cpu);
2877 }
2878 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2879 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2880 kvm_cpu_synchronize_state(cs);
2881 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2882 env->tpr_access_type);
2883 }
2884
2885 return cs->halted;
2886 }
2887
2888 static int kvm_handle_halt(X86CPU *cpu)
2889 {
2890 CPUState *cs = CPU(cpu);
2891 CPUX86State *env = &cpu->env;
2892
2893 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2894 (env->eflags & IF_MASK)) &&
2895 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2896 cs->halted = 1;
2897 return EXCP_HLT;
2898 }
2899
2900 return 0;
2901 }
2902
2903 static int kvm_handle_tpr_access(X86CPU *cpu)
2904 {
2905 CPUState *cs = CPU(cpu);
2906 struct kvm_run *run = cs->kvm_run;
2907
2908 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2909 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2910 : TPR_ACCESS_READ);
2911 return 1;
2912 }
2913
2914 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2915 {
2916 static const uint8_t int3 = 0xcc;
2917
2918 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2919 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2920 return -EINVAL;
2921 }
2922 return 0;
2923 }
2924
2925 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2926 {
2927 uint8_t int3;
2928
2929 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2930 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2931 return -EINVAL;
2932 }
2933 return 0;
2934 }
2935
2936 static struct {
2937 target_ulong addr;
2938 int len;
2939 int type;
2940 } hw_breakpoint[4];
2941
2942 static int nb_hw_breakpoint;
2943
2944 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2945 {
2946 int n;
2947
2948 for (n = 0; n < nb_hw_breakpoint; n++) {
2949 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2950 (hw_breakpoint[n].len == len || len == -1)) {
2951 return n;
2952 }
2953 }
2954 return -1;
2955 }
2956
2957 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2958 target_ulong len, int type)
2959 {
2960 switch (type) {
2961 case GDB_BREAKPOINT_HW:
2962 len = 1;
2963 break;
2964 case GDB_WATCHPOINT_WRITE:
2965 case GDB_WATCHPOINT_ACCESS:
2966 switch (len) {
2967 case 1:
2968 break;
2969 case 2:
2970 case 4:
2971 case 8:
2972 if (addr & (len - 1)) {
2973 return -EINVAL;
2974 }
2975 break;
2976 default:
2977 return -EINVAL;
2978 }
2979 break;
2980 default:
2981 return -ENOSYS;
2982 }
2983
2984 if (nb_hw_breakpoint == 4) {
2985 return -ENOBUFS;
2986 }
2987 if (find_hw_breakpoint(addr, len, type) >= 0) {
2988 return -EEXIST;
2989 }
2990 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2991 hw_breakpoint[nb_hw_breakpoint].len = len;
2992 hw_breakpoint[nb_hw_breakpoint].type = type;
2993 nb_hw_breakpoint++;
2994
2995 return 0;
2996 }
2997
2998 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2999 target_ulong len, int type)
3000 {
3001 int n;
3002
3003 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3004 if (n < 0) {
3005 return -ENOENT;
3006 }
3007 nb_hw_breakpoint--;
3008 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3009
3010 return 0;
3011 }
3012
3013 void kvm_arch_remove_all_hw_breakpoints(void)
3014 {
3015 nb_hw_breakpoint = 0;
3016 }
3017
3018 static CPUWatchpoint hw_watchpoint;
3019
3020 static int kvm_handle_debug(X86CPU *cpu,
3021 struct kvm_debug_exit_arch *arch_info)
3022 {
3023 CPUState *cs = CPU(cpu);
3024 CPUX86State *env = &cpu->env;
3025 int ret = 0;
3026 int n;
3027
3028 if (arch_info->exception == 1) {
3029 if (arch_info->dr6 & (1 << 14)) {
3030 if (cs->singlestep_enabled) {
3031 ret = EXCP_DEBUG;
3032 }
3033 } else {
3034 for (n = 0; n < 4; n++) {
3035 if (arch_info->dr6 & (1 << n)) {
3036 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3037 case 0x0:
3038 ret = EXCP_DEBUG;
3039 break;
3040 case 0x1:
3041 ret = EXCP_DEBUG;
3042 cs->watchpoint_hit = &hw_watchpoint;
3043 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3044 hw_watchpoint.flags = BP_MEM_WRITE;
3045 break;
3046 case 0x3:
3047 ret = EXCP_DEBUG;
3048 cs->watchpoint_hit = &hw_watchpoint;
3049 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3050 hw_watchpoint.flags = BP_MEM_ACCESS;
3051 break;
3052 }
3053 }
3054 }
3055 }
3056 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3057 ret = EXCP_DEBUG;
3058 }
3059 if (ret == 0) {
3060 cpu_synchronize_state(cs);
3061 assert(env->exception_injected == -1);
3062
3063 /* pass to guest */
3064 env->exception_injected = arch_info->exception;
3065 env->has_error_code = 0;
3066 }
3067
3068 return ret;
3069 }
3070
3071 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3072 {
3073 const uint8_t type_code[] = {
3074 [GDB_BREAKPOINT_HW] = 0x0,
3075 [GDB_WATCHPOINT_WRITE] = 0x1,
3076 [GDB_WATCHPOINT_ACCESS] = 0x3
3077 };
3078 const uint8_t len_code[] = {
3079 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3080 };
3081 int n;
3082
3083 if (kvm_sw_breakpoints_active(cpu)) {
3084 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3085 }
3086 if (nb_hw_breakpoint > 0) {
3087 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3088 dbg->arch.debugreg[7] = 0x0600;
3089 for (n = 0; n < nb_hw_breakpoint; n++) {
3090 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3091 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3092 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3093 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3094 }
3095 }
3096 }
3097
3098 static bool host_supports_vmx(void)
3099 {
3100 uint32_t ecx, unused;
3101
3102 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3103 return ecx & CPUID_EXT_VMX;
3104 }
3105
3106 #define VMX_INVALID_GUEST_STATE 0x80000021
3107
3108 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3109 {
3110 X86CPU *cpu = X86_CPU(cs);
3111 uint64_t code;
3112 int ret;
3113
3114 switch (run->exit_reason) {
3115 case KVM_EXIT_HLT:
3116 DPRINTF("handle_hlt\n");
3117 qemu_mutex_lock_iothread();
3118 ret = kvm_handle_halt(cpu);
3119 qemu_mutex_unlock_iothread();
3120 break;
3121 case KVM_EXIT_SET_TPR:
3122 ret = 0;
3123 break;
3124 case KVM_EXIT_TPR_ACCESS:
3125 qemu_mutex_lock_iothread();
3126 ret = kvm_handle_tpr_access(cpu);
3127 qemu_mutex_unlock_iothread();
3128 break;
3129 case KVM_EXIT_FAIL_ENTRY:
3130 code = run->fail_entry.hardware_entry_failure_reason;
3131 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3132 code);
3133 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3134 fprintf(stderr,
3135 "\nIf you're running a guest on an Intel machine without "
3136 "unrestricted mode\n"
3137 "support, the failure can be most likely due to the guest "
3138 "entering an invalid\n"
3139 "state for Intel VT. For example, the guest maybe running "
3140 "in big real mode\n"
3141 "which is not supported on less recent Intel processors."
3142 "\n\n");
3143 }
3144 ret = -1;
3145 break;
3146 case KVM_EXIT_EXCEPTION:
3147 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3148 run->ex.exception, run->ex.error_code);
3149 ret = -1;
3150 break;
3151 case KVM_EXIT_DEBUG:
3152 DPRINTF("kvm_exit_debug\n");
3153 qemu_mutex_lock_iothread();
3154 ret = kvm_handle_debug(cpu, &run->debug.arch);
3155 qemu_mutex_unlock_iothread();
3156 break;
3157 case KVM_EXIT_HYPERV:
3158 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3159 break;
3160 case KVM_EXIT_IOAPIC_EOI:
3161 ioapic_eoi_broadcast(run->eoi.vector);
3162 ret = 0;
3163 break;
3164 default:
3165 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3166 ret = -1;
3167 break;
3168 }
3169
3170 return ret;
3171 }
3172
3173 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3174 {
3175 X86CPU *cpu = X86_CPU(cs);
3176 CPUX86State *env = &cpu->env;
3177
3178 kvm_cpu_synchronize_state(cs);
3179 return !(env->cr[0] & CR0_PE_MASK) ||
3180 ((env->segs[R_CS].selector & 3) != 3);
3181 }
3182
3183 void kvm_arch_init_irq_routing(KVMState *s)
3184 {
3185 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3186 /* If kernel can't do irq routing, interrupt source
3187 * override 0->2 cannot be set up as required by HPET.
3188 * So we have to disable it.
3189 */
3190 no_hpet = 1;
3191 }
3192 /* We know at this point that we're using the in-kernel
3193 * irqchip, so we can use irqfds, and on x86 we know
3194 * we can use msi via irqfd and GSI routing.
3195 */
3196 kvm_msi_via_irqfd_allowed = true;
3197 kvm_gsi_routing_allowed = true;
3198
3199 if (kvm_irqchip_is_split()) {
3200 int i;
3201
3202 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3203 MSI routes for signaling interrupts to the local apics. */
3204 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3205 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3206 error_report("Could not enable split IRQ mode.");
3207 exit(1);
3208 }
3209 }
3210 }
3211 }
3212
3213 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3214 {
3215 int ret;
3216 if (machine_kernel_irqchip_split(ms)) {
3217 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3218 if (ret) {
3219 error_report("Could not enable split irqchip mode: %s\n",
3220 strerror(-ret));
3221 exit(1);
3222 } else {
3223 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3224 kvm_split_irqchip = true;
3225 return 1;
3226 }
3227 } else {
3228 return 0;
3229 }
3230 }
3231
3232 /* Classic KVM device assignment interface. Will remain x86 only. */
3233 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3234 uint32_t flags, uint32_t *dev_id)
3235 {
3236 struct kvm_assigned_pci_dev dev_data = {
3237 .segnr = dev_addr->domain,
3238 .busnr = dev_addr->bus,
3239 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3240 .flags = flags,
3241 };
3242 int ret;
3243
3244 dev_data.assigned_dev_id =
3245 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3246
3247 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3248 if (ret < 0) {
3249 return ret;
3250 }
3251
3252 *dev_id = dev_data.assigned_dev_id;
3253
3254 return 0;
3255 }
3256
3257 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3258 {
3259 struct kvm_assigned_pci_dev dev_data = {
3260 .assigned_dev_id = dev_id,
3261 };
3262
3263 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3264 }
3265
3266 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3267 uint32_t irq_type, uint32_t guest_irq)
3268 {
3269 struct kvm_assigned_irq assigned_irq = {
3270 .assigned_dev_id = dev_id,
3271 .guest_irq = guest_irq,
3272 .flags = irq_type,
3273 };
3274
3275 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3276 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3277 } else {
3278 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3279 }
3280 }
3281
3282 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3283 uint32_t guest_irq)
3284 {
3285 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3286 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3287
3288 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3289 }
3290
3291 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3292 {
3293 struct kvm_assigned_pci_dev dev_data = {
3294 .assigned_dev_id = dev_id,
3295 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3296 };
3297
3298 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3299 }
3300
3301 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3302 uint32_t type)
3303 {
3304 struct kvm_assigned_irq assigned_irq = {
3305 .assigned_dev_id = dev_id,
3306 .flags = type,
3307 };
3308
3309 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3310 }
3311
3312 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3313 {
3314 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3315 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3316 }
3317
3318 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3319 {
3320 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3321 KVM_DEV_IRQ_GUEST_MSI, virq);
3322 }
3323
3324 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3325 {
3326 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3327 KVM_DEV_IRQ_HOST_MSI);
3328 }
3329
3330 bool kvm_device_msix_supported(KVMState *s)
3331 {
3332 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3333 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3334 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3335 }
3336
3337 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3338 uint32_t nr_vectors)
3339 {
3340 struct kvm_assigned_msix_nr msix_nr = {
3341 .assigned_dev_id = dev_id,
3342 .entry_nr = nr_vectors,
3343 };
3344
3345 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3346 }
3347
3348 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3349 int virq)
3350 {
3351 struct kvm_assigned_msix_entry msix_entry = {
3352 .assigned_dev_id = dev_id,
3353 .gsi = virq,
3354 .entry = vector,
3355 };
3356
3357 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3358 }
3359
3360 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3361 {
3362 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3363 KVM_DEV_IRQ_GUEST_MSIX, 0);
3364 }
3365
3366 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3367 {
3368 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3369 KVM_DEV_IRQ_HOST_MSIX);
3370 }
3371
3372 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3373 uint64_t address, uint32_t data, PCIDevice *dev)
3374 {
3375 X86IOMMUState *iommu = x86_iommu_get_default();
3376
3377 if (iommu) {
3378 int ret;
3379 MSIMessage src, dst;
3380 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3381
3382 src.address = route->u.msi.address_hi;
3383 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3384 src.address |= route->u.msi.address_lo;
3385 src.data = route->u.msi.data;
3386
3387 ret = class->int_remap(iommu, &src, &dst, dev ? \
3388 pci_requester_id(dev) : \
3389 X86_IOMMU_SID_INVALID);
3390 if (ret) {
3391 trace_kvm_x86_fixup_msi_error(route->gsi);
3392 return 1;
3393 }
3394
3395 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3396 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3397 route->u.msi.data = dst.data;
3398 }
3399
3400 return 0;
3401 }
3402
3403 typedef struct MSIRouteEntry MSIRouteEntry;
3404
3405 struct MSIRouteEntry {
3406 PCIDevice *dev; /* Device pointer */
3407 int vector; /* MSI/MSIX vector index */
3408 int virq; /* Virtual IRQ index */
3409 QLIST_ENTRY(MSIRouteEntry) list;
3410 };
3411
3412 /* List of used GSI routes */
3413 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3414 QLIST_HEAD_INITIALIZER(msi_route_list);
3415
3416 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3417 int vector, PCIDevice *dev)
3418 {
3419 MSIRouteEntry *entry;
3420
3421 if (!dev) {
3422 /* These are (possibly) IOAPIC routes only used for split
3423 * kernel irqchip mode, while what we are housekeeping are
3424 * PCI devices only. */
3425 return 0;
3426 }
3427
3428 entry = g_new0(MSIRouteEntry, 1);
3429 entry->dev = dev;
3430 entry->vector = vector;
3431 entry->virq = route->gsi;
3432 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3433
3434 trace_kvm_x86_add_msi_route(route->gsi);
3435 return 0;
3436 }
3437
3438 int kvm_arch_release_virq_post(int virq)
3439 {
3440 MSIRouteEntry *entry, *next;
3441 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3442 if (entry->virq == virq) {
3443 trace_kvm_x86_remove_msi_route(virq);
3444 QLIST_REMOVE(entry, list);
3445 break;
3446 }
3447 }
3448 return 0;
3449 }
3450
3451 int kvm_arch_msi_data_to_gsi(uint32_t data)
3452 {
3453 abort();
3454 }
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