4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38 #include "hw/i386/intel_iommu.h"
39 #include "hw/i386/x86-iommu.h"
41 #include "exec/ioport.h"
42 #include "standard-headers/asm-x86/hyperv.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "migration/migration.h"
46 #include "exec/memattrs.h"
52 #define DPRINTF(fmt, ...) \
53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #define DPRINTF(fmt, ...) \
59 #define MSR_KVM_WALL_CLOCK 0x11
60 #define MSR_KVM_SYSTEM_TIME 0x12
62 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64 #define MSR_BUF_SIZE 4096
67 #define BUS_MCEERR_AR 4
70 #define BUS_MCEERR_AO 5
73 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR
),
75 KVM_CAP_INFO(EXT_CPUID
),
76 KVM_CAP_INFO(MP_STATE
),
80 static bool has_msr_star
;
81 static bool has_msr_hsave_pa
;
82 static bool has_msr_tsc_aux
;
83 static bool has_msr_tsc_adjust
;
84 static bool has_msr_tsc_deadline
;
85 static bool has_msr_feature_control
;
86 static bool has_msr_async_pf_en
;
87 static bool has_msr_pv_eoi_en
;
88 static bool has_msr_misc_enable
;
89 static bool has_msr_smbase
;
90 static bool has_msr_bndcfgs
;
91 static bool has_msr_kvm_steal_time
;
92 static int lm_capable_kernel
;
93 static bool has_msr_hv_hypercall
;
94 static bool has_msr_hv_vapic
;
95 static bool has_msr_hv_tsc
;
96 static bool has_msr_hv_crash
;
97 static bool has_msr_hv_reset
;
98 static bool has_msr_hv_vpindex
;
99 static bool has_msr_hv_runtime
;
100 static bool has_msr_hv_synic
;
101 static bool has_msr_hv_stimer
;
102 static bool has_msr_mtrr
;
103 static bool has_msr_xss
;
105 static bool has_msr_architectural_pmu
;
106 static uint32_t num_architectural_pmu_counters
;
108 static int has_xsave
;
110 static int has_pit_state2
;
112 static bool has_msr_mcg_ext_ctl
;
114 static struct kvm_cpuid2
*cpuid_cache
;
116 int kvm_has_pit_state2(void)
118 return has_pit_state2
;
121 bool kvm_has_smm(void)
123 return kvm_check_extension(kvm_state
, KVM_CAP_X86_SMM
);
126 bool kvm_allows_irq0_override(void)
128 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
131 static int kvm_get_tsc(CPUState
*cs
)
133 X86CPU
*cpu
= X86_CPU(cs
);
134 CPUX86State
*env
= &cpu
->env
;
136 struct kvm_msrs info
;
137 struct kvm_msr_entry entries
[1];
141 if (env
->tsc_valid
) {
145 msr_data
.info
.nmsrs
= 1;
146 msr_data
.entries
[0].index
= MSR_IA32_TSC
;
147 env
->tsc_valid
= !runstate_is_running();
149 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
155 env
->tsc
= msr_data
.entries
[0].data
;
159 static inline void do_kvm_synchronize_tsc(void *arg
)
166 void kvm_synchronize_all_tsc(void)
172 run_on_cpu(cpu
, do_kvm_synchronize_tsc
, cpu
);
177 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
179 struct kvm_cpuid2
*cpuid
;
182 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
183 cpuid
= g_malloc0(size
);
185 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
186 if (r
== 0 && cpuid
->nent
>= max
) {
194 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
202 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
205 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
207 struct kvm_cpuid2
*cpuid
;
210 if (cpuid_cache
!= NULL
) {
213 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
220 static const struct kvm_para_features
{
223 } para_features
[] = {
224 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
225 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
226 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
227 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
230 static int get_para_features(KVMState
*s
)
234 for (i
= 0; i
< ARRAY_SIZE(para_features
); i
++) {
235 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
236 features
|= (1 << para_features
[i
].feature
);
244 /* Returns the value for a specific register on the cpuid entry
246 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
266 /* Find matching entry for function/index on kvm_cpuid2 struct
268 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
273 for (i
= 0; i
< cpuid
->nent
; ++i
) {
274 if (cpuid
->entries
[i
].function
== function
&&
275 cpuid
->entries
[i
].index
== index
) {
276 return &cpuid
->entries
[i
];
283 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
284 uint32_t index
, int reg
)
286 struct kvm_cpuid2
*cpuid
;
288 uint32_t cpuid_1_edx
;
291 cpuid
= get_supported_cpuid(s
);
293 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
296 ret
= cpuid_entry_get_reg(entry
, reg
);
299 /* Fixups for the data returned by KVM, below */
301 if (function
== 1 && reg
== R_EDX
) {
302 /* KVM before 2.6.30 misreports the following features */
303 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
304 } else if (function
== 1 && reg
== R_ECX
) {
305 /* We can set the hypervisor flag, even if KVM does not return it on
306 * GET_SUPPORTED_CPUID
308 ret
|= CPUID_EXT_HYPERVISOR
;
309 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
310 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
311 * and the irqchip is in the kernel.
313 if (kvm_irqchip_in_kernel() &&
314 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
315 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
318 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
319 * without the in-kernel irqchip
321 if (!kvm_irqchip_in_kernel()) {
322 ret
&= ~CPUID_EXT_X2APIC
;
324 } else if (function
== 6 && reg
== R_EAX
) {
325 ret
|= CPUID_6_EAX_ARAT
; /* safe to allow because of emulated APIC */
326 } else if (function
== 0x80000001 && reg
== R_EDX
) {
327 /* On Intel, kvm returns cpuid according to the Intel spec,
328 * so add missing bits according to the AMD spec:
330 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
331 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
334 /* fallback for older kernels */
335 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
336 ret
= get_para_features(s
);
342 typedef struct HWPoisonPage
{
344 QLIST_ENTRY(HWPoisonPage
) list
;
347 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
348 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
350 static void kvm_unpoison_all(void *param
)
352 HWPoisonPage
*page
, *next_page
;
354 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
355 QLIST_REMOVE(page
, list
);
356 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
361 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
365 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
366 if (page
->ram_addr
== ram_addr
) {
370 page
= g_new(HWPoisonPage
, 1);
371 page
->ram_addr
= ram_addr
;
372 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
375 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
380 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
383 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
388 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
390 CPUState
*cs
= CPU(cpu
);
391 CPUX86State
*env
= &cpu
->env
;
392 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
393 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
394 uint64_t mcg_status
= MCG_STATUS_MCIP
;
397 if (code
== BUS_MCEERR_AR
) {
398 status
|= MCI_STATUS_AR
| 0x134;
399 mcg_status
|= MCG_STATUS_EIPV
;
402 mcg_status
|= MCG_STATUS_RIPV
;
405 flags
= cpu_x86_support_mca_broadcast(env
) ? MCE_INJECT_BROADCAST
: 0;
406 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
407 * guest kernel back into env->mcg_ext_ctl.
409 cpu_synchronize_state(cs
);
410 if (env
->mcg_ext_ctl
& MCG_EXT_CTL_LMCE_EN
) {
411 mcg_status
|= MCG_STATUS_LMCE
;
415 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
416 (MCM_ADDR_PHYS
<< 6) | 0xc, flags
);
419 static void hardware_memory_error(void)
421 fprintf(stderr
, "Hardware memory error!\n");
425 int kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
427 X86CPU
*cpu
= X86_CPU(c
);
428 CPUX86State
*env
= &cpu
->env
;
432 if ((env
->mcg_cap
& MCG_SER_P
) && addr
433 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
434 ram_addr
= qemu_ram_addr_from_host(addr
);
435 if (ram_addr
== RAM_ADDR_INVALID
||
436 !kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
437 fprintf(stderr
, "Hardware memory error for memory used by "
438 "QEMU itself instead of guest system!\n");
439 /* Hope we are lucky for AO MCE */
440 if (code
== BUS_MCEERR_AO
) {
443 hardware_memory_error();
446 kvm_hwpoison_page_add(ram_addr
);
447 kvm_mce_inject(cpu
, paddr
, code
);
449 if (code
== BUS_MCEERR_AO
) {
451 } else if (code
== BUS_MCEERR_AR
) {
452 hardware_memory_error();
460 int kvm_arch_on_sigbus(int code
, void *addr
)
462 X86CPU
*cpu
= X86_CPU(first_cpu
);
464 if ((cpu
->env
.mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
468 /* Hope we are lucky for AO MCE */
469 ram_addr
= qemu_ram_addr_from_host(addr
);
470 if (ram_addr
== RAM_ADDR_INVALID
||
471 !kvm_physical_memory_addr_from_host(first_cpu
->kvm_state
,
473 fprintf(stderr
, "Hardware memory error for memory used by "
474 "QEMU itself instead of guest system!: %p\n", addr
);
477 kvm_hwpoison_page_add(ram_addr
);
478 kvm_mce_inject(X86_CPU(first_cpu
), paddr
, code
);
480 if (code
== BUS_MCEERR_AO
) {
482 } else if (code
== BUS_MCEERR_AR
) {
483 hardware_memory_error();
491 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
493 CPUX86State
*env
= &cpu
->env
;
495 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
496 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
497 struct kvm_x86_mce mce
;
499 env
->exception_injected
= -1;
502 * There must be at least one bank in use if an MCE is pending.
503 * Find it and use its values for the event injection.
505 for (bank
= 0; bank
< bank_num
; bank
++) {
506 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
510 assert(bank
< bank_num
);
513 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
514 mce
.mcg_status
= env
->mcg_status
;
515 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
516 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
518 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
523 static void cpu_update_state(void *opaque
, int running
, RunState state
)
525 CPUX86State
*env
= opaque
;
528 env
->tsc_valid
= false;
532 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
534 X86CPU
*cpu
= X86_CPU(cs
);
538 #ifndef KVM_CPUID_SIGNATURE_NEXT
539 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
542 static bool hyperv_hypercall_available(X86CPU
*cpu
)
544 return cpu
->hyperv_vapic
||
545 (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
);
548 static bool hyperv_enabled(X86CPU
*cpu
)
550 CPUState
*cs
= CPU(cpu
);
551 return kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0 &&
552 (hyperv_hypercall_available(cpu
) ||
554 cpu
->hyperv_relaxed_timing
||
557 cpu
->hyperv_vpindex
||
558 cpu
->hyperv_runtime
||
563 static int kvm_arch_set_tsc_khz(CPUState
*cs
)
565 X86CPU
*cpu
= X86_CPU(cs
);
566 CPUX86State
*env
= &cpu
->env
;
573 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
) ?
574 kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
) :
577 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
578 * TSC frequency doesn't match the one we want.
580 int cur_freq
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
581 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
583 if (cur_freq
<= 0 || cur_freq
!= env
->tsc_khz
) {
584 error_report("warning: TSC frequency mismatch between "
585 "VM (%" PRId64
" kHz) and host (%d kHz), "
586 "and TSC scaling unavailable",
587 env
->tsc_khz
, cur_freq
);
595 static int hyperv_handle_properties(CPUState
*cs
)
597 X86CPU
*cpu
= X86_CPU(cs
);
598 CPUX86State
*env
= &cpu
->env
;
600 if (cpu
->hyperv_relaxed_timing
) {
601 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_HYPERCALL_AVAILABLE
;
603 if (cpu
->hyperv_vapic
) {
604 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_HYPERCALL_AVAILABLE
;
605 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE
;
606 has_msr_hv_vapic
= true;
608 if (cpu
->hyperv_time
&&
609 kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_TIME
) > 0) {
610 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_HYPERCALL_AVAILABLE
;
611 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE
;
612 env
->features
[FEAT_HYPERV_EAX
] |= 0x200;
613 has_msr_hv_tsc
= true;
615 if (cpu
->hyperv_crash
&& has_msr_hv_crash
) {
616 env
->features
[FEAT_HYPERV_EDX
] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE
;
618 env
->features
[FEAT_HYPERV_EDX
] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
619 if (cpu
->hyperv_reset
&& has_msr_hv_reset
) {
620 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_RESET_AVAILABLE
;
622 if (cpu
->hyperv_vpindex
&& has_msr_hv_vpindex
) {
623 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_VP_INDEX_AVAILABLE
;
625 if (cpu
->hyperv_runtime
&& has_msr_hv_runtime
) {
626 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE
;
628 if (cpu
->hyperv_synic
) {
631 if (!has_msr_hv_synic
||
632 kvm_vcpu_enable_cap(cs
, KVM_CAP_HYPERV_SYNIC
, 0)) {
633 fprintf(stderr
, "Hyper-V SynIC is not supported by kernel\n");
637 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_SYNIC_AVAILABLE
;
638 env
->msr_hv_synic_version
= HV_SYNIC_VERSION_1
;
639 for (sint
= 0; sint
< ARRAY_SIZE(env
->msr_hv_synic_sint
); sint
++) {
640 env
->msr_hv_synic_sint
[sint
] = HV_SYNIC_SINT_MASKED
;
643 if (cpu
->hyperv_stimer
) {
644 if (!has_msr_hv_stimer
) {
645 fprintf(stderr
, "Hyper-V timers aren't supported by kernel\n");
648 env
->features
[FEAT_HYPERV_EAX
] |= HV_X64_MSR_SYNTIMER_AVAILABLE
;
653 static Error
*invtsc_mig_blocker
;
655 #define KVM_MAX_CPUID_ENTRIES 100
657 int kvm_arch_init_vcpu(CPUState
*cs
)
660 struct kvm_cpuid2 cpuid
;
661 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
662 } QEMU_PACKED cpuid_data
;
663 X86CPU
*cpu
= X86_CPU(cs
);
664 CPUX86State
*env
= &cpu
->env
;
665 uint32_t limit
, i
, j
, cpuid_i
;
667 struct kvm_cpuid_entry2
*c
;
668 uint32_t signature
[3];
669 int kvm_base
= KVM_CPUID_SIGNATURE
;
672 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
676 /* Paravirtualization CPUIDs */
677 if (hyperv_enabled(cpu
)) {
678 c
= &cpuid_data
.entries
[cpuid_i
++];
679 c
->function
= HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS
;
680 if (!cpu
->hyperv_vendor_id
) {
681 memcpy(signature
, "Microsoft Hv", 12);
683 size_t len
= strlen(cpu
->hyperv_vendor_id
);
686 error_report("hv-vendor-id truncated to 12 characters");
689 memset(signature
, 0, 12);
690 memcpy(signature
, cpu
->hyperv_vendor_id
, len
);
692 c
->eax
= HYPERV_CPUID_MIN
;
693 c
->ebx
= signature
[0];
694 c
->ecx
= signature
[1];
695 c
->edx
= signature
[2];
697 c
= &cpuid_data
.entries
[cpuid_i
++];
698 c
->function
= HYPERV_CPUID_INTERFACE
;
699 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
700 c
->eax
= signature
[0];
705 c
= &cpuid_data
.entries
[cpuid_i
++];
706 c
->function
= HYPERV_CPUID_VERSION
;
710 c
= &cpuid_data
.entries
[cpuid_i
++];
711 c
->function
= HYPERV_CPUID_FEATURES
;
712 r
= hyperv_handle_properties(cs
);
716 c
->eax
= env
->features
[FEAT_HYPERV_EAX
];
717 c
->ebx
= env
->features
[FEAT_HYPERV_EBX
];
718 c
->edx
= env
->features
[FEAT_HYPERV_EDX
];
720 c
= &cpuid_data
.entries
[cpuid_i
++];
721 c
->function
= HYPERV_CPUID_ENLIGHTMENT_INFO
;
722 if (cpu
->hyperv_relaxed_timing
) {
723 c
->eax
|= HV_X64_RELAXED_TIMING_RECOMMENDED
;
725 if (has_msr_hv_vapic
) {
726 c
->eax
|= HV_X64_APIC_ACCESS_RECOMMENDED
;
728 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
730 c
= &cpuid_data
.entries
[cpuid_i
++];
731 c
->function
= HYPERV_CPUID_IMPLEMENT_LIMITS
;
735 kvm_base
= KVM_CPUID_SIGNATURE_NEXT
;
736 has_msr_hv_hypercall
= true;
739 if (cpu
->expose_kvm
) {
740 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
741 c
= &cpuid_data
.entries
[cpuid_i
++];
742 c
->function
= KVM_CPUID_SIGNATURE
| kvm_base
;
743 c
->eax
= KVM_CPUID_FEATURES
| kvm_base
;
744 c
->ebx
= signature
[0];
745 c
->ecx
= signature
[1];
746 c
->edx
= signature
[2];
748 c
= &cpuid_data
.entries
[cpuid_i
++];
749 c
->function
= KVM_CPUID_FEATURES
| kvm_base
;
750 c
->eax
= env
->features
[FEAT_KVM
];
752 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
754 has_msr_pv_eoi_en
= c
->eax
& (1 << KVM_FEATURE_PV_EOI
);
756 has_msr_kvm_steal_time
= c
->eax
& (1 << KVM_FEATURE_STEAL_TIME
);
759 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
761 for (i
= 0; i
<= limit
; i
++) {
762 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
763 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
766 c
= &cpuid_data
.entries
[cpuid_i
++];
770 /* Keep reading function 2 till all the input is received */
774 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
775 KVM_CPUID_FLAG_STATE_READ_NEXT
;
776 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
777 times
= c
->eax
& 0xff;
779 for (j
= 1; j
< times
; ++j
) {
780 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
781 fprintf(stderr
, "cpuid_data is full, no space for "
782 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
785 c
= &cpuid_data
.entries
[cpuid_i
++];
787 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
788 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
796 if (i
== 0xd && j
== 64) {
800 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
802 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
804 if (i
== 4 && c
->eax
== 0) {
807 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
810 if (i
== 0xd && c
->eax
== 0) {
813 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
814 fprintf(stderr
, "cpuid_data is full, no space for "
815 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
818 c
= &cpuid_data
.entries
[cpuid_i
++];
824 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
832 cpu_x86_cpuid(env
, 0x0a, 0, &ver
, &unused
, &unused
, &unused
);
833 if ((ver
& 0xff) > 0) {
834 has_msr_architectural_pmu
= true;
835 num_architectural_pmu_counters
= (ver
& 0xff00) >> 8;
837 /* Shouldn't be more than 32, since that's the number of bits
838 * available in EBX to tell us _which_ counters are available.
841 if (num_architectural_pmu_counters
> MAX_GP_COUNTERS
) {
842 num_architectural_pmu_counters
= MAX_GP_COUNTERS
;
847 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
849 for (i
= 0x80000000; i
<= limit
; i
++) {
850 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
851 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
854 c
= &cpuid_data
.entries
[cpuid_i
++];
858 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
861 /* Call Centaur's CPUID instructions they are supported. */
862 if (env
->cpuid_xlevel2
> 0) {
863 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
865 for (i
= 0xC0000000; i
<= limit
; i
++) {
866 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
867 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
870 c
= &cpuid_data
.entries
[cpuid_i
++];
874 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
878 cpuid_data
.cpuid
.nent
= cpuid_i
;
880 if (((env
->cpuid_version
>> 8)&0xF) >= 6
881 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
882 (CPUID_MCE
| CPUID_MCA
)
883 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
884 uint64_t mcg_cap
, unsupported_caps
;
888 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
890 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
894 if (banks
< (env
->mcg_cap
& MCG_CAP_BANKS_MASK
)) {
895 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
896 (int)(env
->mcg_cap
& MCG_CAP_BANKS_MASK
), banks
);
900 unsupported_caps
= env
->mcg_cap
& ~(mcg_cap
| MCG_CAP_BANKS_MASK
);
901 if (unsupported_caps
) {
902 if (unsupported_caps
& MCG_LMCE_P
) {
903 error_report("kvm: LMCE not supported");
906 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64
,
910 env
->mcg_cap
&= mcg_cap
| MCG_CAP_BANKS_MASK
;
911 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &env
->mcg_cap
);
913 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
918 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
920 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
922 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
923 !!(c
->ecx
& CPUID_EXT_SMX
);
926 if (env
->mcg_cap
& MCG_LMCE_P
) {
927 has_msr_mcg_ext_ctl
= has_msr_feature_control
= true;
930 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 0x80000007, 0);
931 if (c
&& (c
->edx
& 1<<8) && invtsc_mig_blocker
== NULL
) {
933 error_setg(&invtsc_mig_blocker
,
934 "State blocked by non-migratable CPU device"
936 migrate_add_blocker(invtsc_mig_blocker
);
938 vmstate_x86_cpu
.unmigratable
= 1;
941 cpuid_data
.cpuid
.padding
= 0;
942 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
947 r
= kvm_arch_set_tsc_khz(cs
);
952 /* vcpu's TSC frequency is either specified by user, or following
953 * the value used by KVM if the former is not present. In the
954 * latter case, we query it from KVM and record in env->tsc_khz,
955 * so that vcpu's TSC frequency can be migrated later via this field.
958 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
959 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
967 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
969 cpu
->kvm_msr_buf
= g_malloc0(MSR_BUF_SIZE
);
971 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
974 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_RDTSCP
)) {
975 has_msr_tsc_aux
= false;
981 void kvm_arch_reset_vcpu(X86CPU
*cpu
)
983 CPUX86State
*env
= &cpu
->env
;
985 env
->exception_injected
= -1;
986 env
->interrupt_injected
= -1;
988 if (kvm_irqchip_in_kernel()) {
989 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
990 KVM_MP_STATE_UNINITIALIZED
;
992 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
996 void kvm_arch_do_init_vcpu(X86CPU
*cpu
)
998 CPUX86State
*env
= &cpu
->env
;
1000 /* APs get directly into wait-for-SIPI state. */
1001 if (env
->mp_state
== KVM_MP_STATE_UNINITIALIZED
) {
1002 env
->mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1006 static int kvm_get_supported_msrs(KVMState
*s
)
1008 static int kvm_supported_msrs
;
1012 if (kvm_supported_msrs
== 0) {
1013 struct kvm_msr_list msr_list
, *kvm_msr_list
;
1015 kvm_supported_msrs
= -1;
1017 /* Obtain MSR list from KVM. These are the MSRs that we must
1020 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
1021 if (ret
< 0 && ret
!= -E2BIG
) {
1024 /* Old kernel modules had a bug and could write beyond the provided
1025 memory. Allocate at least a safe amount of 1K. */
1026 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
1028 sizeof(msr_list
.indices
[0])));
1030 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
1031 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
1035 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
1036 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
1037 has_msr_star
= true;
1040 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
1041 has_msr_hsave_pa
= true;
1044 if (kvm_msr_list
->indices
[i
] == MSR_TSC_AUX
) {
1045 has_msr_tsc_aux
= true;
1048 if (kvm_msr_list
->indices
[i
] == MSR_TSC_ADJUST
) {
1049 has_msr_tsc_adjust
= true;
1052 if (kvm_msr_list
->indices
[i
] == MSR_IA32_TSCDEADLINE
) {
1053 has_msr_tsc_deadline
= true;
1056 if (kvm_msr_list
->indices
[i
] == MSR_IA32_SMBASE
) {
1057 has_msr_smbase
= true;
1060 if (kvm_msr_list
->indices
[i
] == MSR_IA32_MISC_ENABLE
) {
1061 has_msr_misc_enable
= true;
1064 if (kvm_msr_list
->indices
[i
] == MSR_IA32_BNDCFGS
) {
1065 has_msr_bndcfgs
= true;
1068 if (kvm_msr_list
->indices
[i
] == MSR_IA32_XSS
) {
1072 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_CRASH_CTL
) {
1073 has_msr_hv_crash
= true;
1076 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_RESET
) {
1077 has_msr_hv_reset
= true;
1080 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_VP_INDEX
) {
1081 has_msr_hv_vpindex
= true;
1084 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_VP_RUNTIME
) {
1085 has_msr_hv_runtime
= true;
1088 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_SCONTROL
) {
1089 has_msr_hv_synic
= true;
1092 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_STIMER0_CONFIG
) {
1093 has_msr_hv_stimer
= true;
1099 g_free(kvm_msr_list
);
1105 static Notifier smram_machine_done
;
1106 static KVMMemoryListener smram_listener
;
1107 static AddressSpace smram_address_space
;
1108 static MemoryRegion smram_as_root
;
1109 static MemoryRegion smram_as_mem
;
1111 static void register_smram_listener(Notifier
*n
, void *unused
)
1113 MemoryRegion
*smram
=
1114 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
1116 /* Outer container... */
1117 memory_region_init(&smram_as_root
, OBJECT(kvm_state
), "mem-container-smram", ~0ull);
1118 memory_region_set_enabled(&smram_as_root
, true);
1120 /* ... with two regions inside: normal system memory with low
1123 memory_region_init_alias(&smram_as_mem
, OBJECT(kvm_state
), "mem-smram",
1124 get_system_memory(), 0, ~0ull);
1125 memory_region_add_subregion_overlap(&smram_as_root
, 0, &smram_as_mem
, 0);
1126 memory_region_set_enabled(&smram_as_mem
, true);
1129 /* ... SMRAM with higher priority */
1130 memory_region_add_subregion_overlap(&smram_as_root
, 0, smram
, 10);
1131 memory_region_set_enabled(smram
, true);
1134 address_space_init(&smram_address_space
, &smram_as_root
, "KVM-SMRAM");
1135 kvm_memory_listener_register(kvm_state
, &smram_listener
,
1136 &smram_address_space
, 1);
1139 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
1141 uint64_t identity_base
= 0xfffbc000;
1142 uint64_t shadow_mem
;
1144 struct utsname utsname
;
1146 #ifdef KVM_CAP_XSAVE
1147 has_xsave
= kvm_check_extension(s
, KVM_CAP_XSAVE
);
1151 has_xcrs
= kvm_check_extension(s
, KVM_CAP_XCRS
);
1154 #ifdef KVM_CAP_PIT_STATE2
1155 has_pit_state2
= kvm_check_extension(s
, KVM_CAP_PIT_STATE2
);
1158 ret
= kvm_get_supported_msrs(s
);
1164 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
1167 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1168 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1169 * Since these must be part of guest physical memory, we need to allocate
1170 * them, both by setting their start addresses in the kernel and by
1171 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1173 * Older KVM versions may not support setting the identity map base. In
1174 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1177 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
1178 /* Allows up to 16M BIOSes. */
1179 identity_base
= 0xfeffc000;
1181 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
1187 /* Set TSS base one page after EPT identity map. */
1188 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
1193 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1194 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
1196 fprintf(stderr
, "e820_add_entry() table is full\n");
1199 qemu_register_reset(kvm_unpoison_all
, NULL
);
1201 shadow_mem
= machine_kvm_shadow_mem(ms
);
1202 if (shadow_mem
!= -1) {
1204 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
1210 if (kvm_check_extension(s
, KVM_CAP_X86_SMM
)) {
1211 smram_machine_done
.notify
= register_smram_listener
;
1212 qemu_add_machine_init_done_notifier(&smram_machine_done
);
1217 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
1219 lhs
->selector
= rhs
->selector
;
1220 lhs
->base
= rhs
->base
;
1221 lhs
->limit
= rhs
->limit
;
1233 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
1235 unsigned flags
= rhs
->flags
;
1236 lhs
->selector
= rhs
->selector
;
1237 lhs
->base
= rhs
->base
;
1238 lhs
->limit
= rhs
->limit
;
1239 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
1240 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
1241 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
1242 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
1243 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
1244 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
1245 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
1246 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
1247 lhs
->unusable
= !lhs
->present
;
1251 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
1253 lhs
->selector
= rhs
->selector
;
1254 lhs
->base
= rhs
->base
;
1255 lhs
->limit
= rhs
->limit
;
1256 if (rhs
->unusable
) {
1259 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
1260 (rhs
->present
* DESC_P_MASK
) |
1261 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
1262 (rhs
->db
<< DESC_B_SHIFT
) |
1263 (rhs
->s
* DESC_S_MASK
) |
1264 (rhs
->l
<< DESC_L_SHIFT
) |
1265 (rhs
->g
* DESC_G_MASK
) |
1266 (rhs
->avl
* DESC_AVL_MASK
);
1270 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
1273 *kvm_reg
= *qemu_reg
;
1275 *qemu_reg
= *kvm_reg
;
1279 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
1281 CPUX86State
*env
= &cpu
->env
;
1282 struct kvm_regs regs
;
1286 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
1292 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
1293 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
1294 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
1295 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
1296 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
1297 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
1298 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
1299 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
1300 #ifdef TARGET_X86_64
1301 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
1302 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
1303 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
1304 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
1305 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
1306 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
1307 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
1308 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
1311 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
1312 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
1315 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
1321 static int kvm_put_fpu(X86CPU
*cpu
)
1323 CPUX86State
*env
= &cpu
->env
;
1327 memset(&fpu
, 0, sizeof fpu
);
1328 fpu
.fsw
= env
->fpus
& ~(7 << 11);
1329 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
1330 fpu
.fcw
= env
->fpuc
;
1331 fpu
.last_opcode
= env
->fpop
;
1332 fpu
.last_ip
= env
->fpip
;
1333 fpu
.last_dp
= env
->fpdp
;
1334 for (i
= 0; i
< 8; ++i
) {
1335 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
1337 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
1338 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1339 stq_p(&fpu
.xmm
[i
][0], env
->xmm_regs
[i
].ZMM_Q(0));
1340 stq_p(&fpu
.xmm
[i
][8], env
->xmm_regs
[i
].ZMM_Q(1));
1342 fpu
.mxcsr
= env
->mxcsr
;
1344 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
1347 #define XSAVE_FCW_FSW 0
1348 #define XSAVE_FTW_FOP 1
1349 #define XSAVE_CWD_RIP 2
1350 #define XSAVE_CWD_RDP 4
1351 #define XSAVE_MXCSR 6
1352 #define XSAVE_ST_SPACE 8
1353 #define XSAVE_XMM_SPACE 40
1354 #define XSAVE_XSTATE_BV 128
1355 #define XSAVE_YMMH_SPACE 144
1356 #define XSAVE_BNDREGS 240
1357 #define XSAVE_BNDCSR 256
1358 #define XSAVE_OPMASK 272
1359 #define XSAVE_ZMM_Hi256 288
1360 #define XSAVE_Hi16_ZMM 416
1361 #define XSAVE_PKRU 672
1363 #define XSAVE_BYTE_OFFSET(word_offset) \
1364 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1366 #define ASSERT_OFFSET(word_offset, field) \
1367 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1368 offsetof(X86XSaveArea, field))
1370 ASSERT_OFFSET(XSAVE_FCW_FSW
, legacy
.fcw
);
1371 ASSERT_OFFSET(XSAVE_FTW_FOP
, legacy
.ftw
);
1372 ASSERT_OFFSET(XSAVE_CWD_RIP
, legacy
.fpip
);
1373 ASSERT_OFFSET(XSAVE_CWD_RDP
, legacy
.fpdp
);
1374 ASSERT_OFFSET(XSAVE_MXCSR
, legacy
.mxcsr
);
1375 ASSERT_OFFSET(XSAVE_ST_SPACE
, legacy
.fpregs
);
1376 ASSERT_OFFSET(XSAVE_XMM_SPACE
, legacy
.xmm_regs
);
1377 ASSERT_OFFSET(XSAVE_XSTATE_BV
, header
.xstate_bv
);
1378 ASSERT_OFFSET(XSAVE_YMMH_SPACE
, avx_state
);
1379 ASSERT_OFFSET(XSAVE_BNDREGS
, bndreg_state
);
1380 ASSERT_OFFSET(XSAVE_BNDCSR
, bndcsr_state
);
1381 ASSERT_OFFSET(XSAVE_OPMASK
, opmask_state
);
1382 ASSERT_OFFSET(XSAVE_ZMM_Hi256
, zmm_hi256_state
);
1383 ASSERT_OFFSET(XSAVE_Hi16_ZMM
, hi16_zmm_state
);
1384 ASSERT_OFFSET(XSAVE_PKRU
, pkru_state
);
1386 static int kvm_put_xsave(X86CPU
*cpu
)
1388 CPUX86State
*env
= &cpu
->env
;
1389 X86XSaveArea
*xsave
= env
->kvm_xsave_buf
;
1390 uint16_t cwd
, swd
, twd
;
1394 return kvm_put_fpu(cpu
);
1397 memset(xsave
, 0, sizeof(struct kvm_xsave
));
1399 swd
= env
->fpus
& ~(7 << 11);
1400 swd
|= (env
->fpstt
& 7) << 11;
1402 for (i
= 0; i
< 8; ++i
) {
1403 twd
|= (!env
->fptags
[i
]) << i
;
1405 xsave
->legacy
.fcw
= cwd
;
1406 xsave
->legacy
.fsw
= swd
;
1407 xsave
->legacy
.ftw
= twd
;
1408 xsave
->legacy
.fpop
= env
->fpop
;
1409 xsave
->legacy
.fpip
= env
->fpip
;
1410 xsave
->legacy
.fpdp
= env
->fpdp
;
1411 memcpy(&xsave
->legacy
.fpregs
, env
->fpregs
,
1412 sizeof env
->fpregs
);
1413 xsave
->legacy
.mxcsr
= env
->mxcsr
;
1414 xsave
->header
.xstate_bv
= env
->xstate_bv
;
1415 memcpy(&xsave
->bndreg_state
.bnd_regs
, env
->bnd_regs
,
1416 sizeof env
->bnd_regs
);
1417 xsave
->bndcsr_state
.bndcsr
= env
->bndcs_regs
;
1418 memcpy(&xsave
->opmask_state
.opmask_regs
, env
->opmask_regs
,
1419 sizeof env
->opmask_regs
);
1421 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1422 uint8_t *xmm
= xsave
->legacy
.xmm_regs
[i
];
1423 uint8_t *ymmh
= xsave
->avx_state
.ymmh
[i
];
1424 uint8_t *zmmh
= xsave
->zmm_hi256_state
.zmm_hi256
[i
];
1425 stq_p(xmm
, env
->xmm_regs
[i
].ZMM_Q(0));
1426 stq_p(xmm
+8, env
->xmm_regs
[i
].ZMM_Q(1));
1427 stq_p(ymmh
, env
->xmm_regs
[i
].ZMM_Q(2));
1428 stq_p(ymmh
+8, env
->xmm_regs
[i
].ZMM_Q(3));
1429 stq_p(zmmh
, env
->xmm_regs
[i
].ZMM_Q(4));
1430 stq_p(zmmh
+8, env
->xmm_regs
[i
].ZMM_Q(5));
1431 stq_p(zmmh
+16, env
->xmm_regs
[i
].ZMM_Q(6));
1432 stq_p(zmmh
+24, env
->xmm_regs
[i
].ZMM_Q(7));
1435 #ifdef TARGET_X86_64
1436 memcpy(&xsave
->hi16_zmm_state
.hi16_zmm
, &env
->xmm_regs
[16],
1437 16 * sizeof env
->xmm_regs
[16]);
1438 memcpy(&xsave
->pkru_state
, &env
->pkru
, sizeof env
->pkru
);
1440 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
1443 static int kvm_put_xcrs(X86CPU
*cpu
)
1445 CPUX86State
*env
= &cpu
->env
;
1446 struct kvm_xcrs xcrs
= {};
1454 xcrs
.xcrs
[0].xcr
= 0;
1455 xcrs
.xcrs
[0].value
= env
->xcr0
;
1456 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
1459 static int kvm_put_sregs(X86CPU
*cpu
)
1461 CPUX86State
*env
= &cpu
->env
;
1462 struct kvm_sregs sregs
;
1464 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
1465 if (env
->interrupt_injected
>= 0) {
1466 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
1467 (uint64_t)1 << (env
->interrupt_injected
% 64);
1470 if ((env
->eflags
& VM_MASK
)) {
1471 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1472 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1473 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1474 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1475 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1476 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1478 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1479 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1480 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1481 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1482 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1483 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1486 set_seg(&sregs
.tr
, &env
->tr
);
1487 set_seg(&sregs
.ldt
, &env
->ldt
);
1489 sregs
.idt
.limit
= env
->idt
.limit
;
1490 sregs
.idt
.base
= env
->idt
.base
;
1491 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
1492 sregs
.gdt
.limit
= env
->gdt
.limit
;
1493 sregs
.gdt
.base
= env
->gdt
.base
;
1494 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
1496 sregs
.cr0
= env
->cr
[0];
1497 sregs
.cr2
= env
->cr
[2];
1498 sregs
.cr3
= env
->cr
[3];
1499 sregs
.cr4
= env
->cr
[4];
1501 sregs
.cr8
= cpu_get_apic_tpr(cpu
->apic_state
);
1502 sregs
.apic_base
= cpu_get_apic_base(cpu
->apic_state
);
1504 sregs
.efer
= env
->efer
;
1506 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
1509 static void kvm_msr_buf_reset(X86CPU
*cpu
)
1511 memset(cpu
->kvm_msr_buf
, 0, MSR_BUF_SIZE
);
1514 static void kvm_msr_entry_add(X86CPU
*cpu
, uint32_t index
, uint64_t value
)
1516 struct kvm_msrs
*msrs
= cpu
->kvm_msr_buf
;
1517 void *limit
= ((void *)msrs
) + MSR_BUF_SIZE
;
1518 struct kvm_msr_entry
*entry
= &msrs
->entries
[msrs
->nmsrs
];
1520 assert((void *)(entry
+ 1) <= limit
);
1522 entry
->index
= index
;
1523 entry
->reserved
= 0;
1524 entry
->data
= value
;
1528 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
1530 CPUX86State
*env
= &cpu
->env
;
1533 if (!has_msr_tsc_deadline
) {
1537 kvm_msr_buf_reset(cpu
);
1538 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1540 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1550 * Provide a separate write service for the feature control MSR in order to
1551 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1552 * before writing any other state because forcibly leaving nested mode
1553 * invalidates the VCPU state.
1555 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
1559 if (!has_msr_feature_control
) {
1563 kvm_msr_buf_reset(cpu
);
1564 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
,
1565 cpu
->env
.msr_ia32_feature_control
);
1567 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1576 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
1578 CPUX86State
*env
= &cpu
->env
;
1582 kvm_msr_buf_reset(cpu
);
1584 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1585 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1586 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1587 kvm_msr_entry_add(cpu
, MSR_PAT
, env
->pat
);
1589 kvm_msr_entry_add(cpu
, MSR_STAR
, env
->star
);
1591 if (has_msr_hsave_pa
) {
1592 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1594 if (has_msr_tsc_aux
) {
1595 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, env
->tsc_aux
);
1597 if (has_msr_tsc_adjust
) {
1598 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, env
->tsc_adjust
);
1600 if (has_msr_misc_enable
) {
1601 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
,
1602 env
->msr_ia32_misc_enable
);
1604 if (has_msr_smbase
) {
1605 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, env
->smbase
);
1607 if (has_msr_bndcfgs
) {
1608 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
1611 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, env
->xss
);
1613 #ifdef TARGET_X86_64
1614 if (lm_capable_kernel
) {
1615 kvm_msr_entry_add(cpu
, MSR_CSTAR
, env
->cstar
);
1616 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, env
->kernelgsbase
);
1617 kvm_msr_entry_add(cpu
, MSR_FMASK
, env
->fmask
);
1618 kvm_msr_entry_add(cpu
, MSR_LSTAR
, env
->lstar
);
1622 * The following MSRs have side effects on the guest or are too heavy
1623 * for normal writeback. Limit them to reset or full state updates.
1625 if (level
>= KVM_PUT_RESET_STATE
) {
1626 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, env
->tsc
);
1627 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
1628 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1629 if (has_msr_async_pf_en
) {
1630 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
1632 if (has_msr_pv_eoi_en
) {
1633 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, env
->pv_eoi_en_msr
);
1635 if (has_msr_kvm_steal_time
) {
1636 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, env
->steal_time_msr
);
1638 if (has_msr_architectural_pmu
) {
1639 /* Stop the counter. */
1640 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
1641 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1643 /* Set the counter values. */
1644 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
1645 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
,
1646 env
->msr_fixed_counters
[i
]);
1648 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
1649 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
,
1650 env
->msr_gp_counters
[i
]);
1651 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
,
1652 env
->msr_gp_evtsel
[i
]);
1654 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
,
1655 env
->msr_global_status
);
1656 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
1657 env
->msr_global_ovf_ctrl
);
1659 /* Now start the PMU. */
1660 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
,
1661 env
->msr_fixed_ctr_ctrl
);
1662 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
,
1663 env
->msr_global_ctrl
);
1665 if (has_msr_hv_hypercall
) {
1666 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
,
1667 env
->msr_hv_guest_os_id
);
1668 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
,
1669 env
->msr_hv_hypercall
);
1671 if (has_msr_hv_vapic
) {
1672 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
,
1675 if (has_msr_hv_tsc
) {
1676 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, env
->msr_hv_tsc
);
1678 if (has_msr_hv_crash
) {
1681 for (j
= 0; j
< HV_X64_MSR_CRASH_PARAMS
; j
++)
1682 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
,
1683 env
->msr_hv_crash_params
[j
]);
1685 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_CTL
,
1686 HV_X64_MSR_CRASH_CTL_NOTIFY
);
1688 if (has_msr_hv_runtime
) {
1689 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, env
->msr_hv_runtime
);
1691 if (cpu
->hyperv_synic
) {
1694 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
,
1695 env
->msr_hv_synic_control
);
1696 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
,
1697 env
->msr_hv_synic_version
);
1698 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
,
1699 env
->msr_hv_synic_evt_page
);
1700 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
,
1701 env
->msr_hv_synic_msg_page
);
1703 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_synic_sint
); j
++) {
1704 kvm_msr_entry_add(cpu
, HV_X64_MSR_SINT0
+ j
,
1705 env
->msr_hv_synic_sint
[j
]);
1708 if (has_msr_hv_stimer
) {
1711 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_config
); j
++) {
1712 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_CONFIG
+ j
* 2,
1713 env
->msr_hv_stimer_config
[j
]);
1716 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_count
); j
++) {
1717 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_COUNT
+ j
* 2,
1718 env
->msr_hv_stimer_count
[j
]);
1722 uint64_t phys_mask
= MAKE_64BIT_MASK(0, cpu
->phys_bits
);
1724 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, env
->mtrr_deftype
);
1725 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, env
->mtrr_fixed
[0]);
1726 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, env
->mtrr_fixed
[1]);
1727 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, env
->mtrr_fixed
[2]);
1728 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, env
->mtrr_fixed
[3]);
1729 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, env
->mtrr_fixed
[4]);
1730 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, env
->mtrr_fixed
[5]);
1731 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, env
->mtrr_fixed
[6]);
1732 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, env
->mtrr_fixed
[7]);
1733 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, env
->mtrr_fixed
[8]);
1734 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, env
->mtrr_fixed
[9]);
1735 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, env
->mtrr_fixed
[10]);
1736 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
1737 /* The CPU GPs if we write to a bit above the physical limit of
1738 * the host CPU (and KVM emulates that)
1740 uint64_t mask
= env
->mtrr_var
[i
].mask
;
1743 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
),
1744 env
->mtrr_var
[i
].base
);
1745 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), mask
);
1749 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1750 * kvm_put_msr_feature_control. */
1755 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, env
->mcg_status
);
1756 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, env
->mcg_ctl
);
1757 if (has_msr_mcg_ext_ctl
) {
1758 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, env
->mcg_ext_ctl
);
1760 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1761 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
1765 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1770 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
1775 static int kvm_get_fpu(X86CPU
*cpu
)
1777 CPUX86State
*env
= &cpu
->env
;
1781 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
1786 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1787 env
->fpus
= fpu
.fsw
;
1788 env
->fpuc
= fpu
.fcw
;
1789 env
->fpop
= fpu
.last_opcode
;
1790 env
->fpip
= fpu
.last_ip
;
1791 env
->fpdp
= fpu
.last_dp
;
1792 for (i
= 0; i
< 8; ++i
) {
1793 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1795 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1796 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1797 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(&fpu
.xmm
[i
][0]);
1798 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(&fpu
.xmm
[i
][8]);
1800 env
->mxcsr
= fpu
.mxcsr
;
1805 static int kvm_get_xsave(X86CPU
*cpu
)
1807 CPUX86State
*env
= &cpu
->env
;
1808 X86XSaveArea
*xsave
= env
->kvm_xsave_buf
;
1810 uint16_t cwd
, swd
, twd
;
1813 return kvm_get_fpu(cpu
);
1816 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
1821 cwd
= xsave
->legacy
.fcw
;
1822 swd
= xsave
->legacy
.fsw
;
1823 twd
= xsave
->legacy
.ftw
;
1824 env
->fpop
= xsave
->legacy
.fpop
;
1825 env
->fpstt
= (swd
>> 11) & 7;
1828 for (i
= 0; i
< 8; ++i
) {
1829 env
->fptags
[i
] = !((twd
>> i
) & 1);
1831 env
->fpip
= xsave
->legacy
.fpip
;
1832 env
->fpdp
= xsave
->legacy
.fpdp
;
1833 env
->mxcsr
= xsave
->legacy
.mxcsr
;
1834 memcpy(env
->fpregs
, &xsave
->legacy
.fpregs
,
1835 sizeof env
->fpregs
);
1836 env
->xstate_bv
= xsave
->header
.xstate_bv
;
1837 memcpy(env
->bnd_regs
, &xsave
->bndreg_state
.bnd_regs
,
1838 sizeof env
->bnd_regs
);
1839 env
->bndcs_regs
= xsave
->bndcsr_state
.bndcsr
;
1840 memcpy(env
->opmask_regs
, &xsave
->opmask_state
.opmask_regs
,
1841 sizeof env
->opmask_regs
);
1843 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1844 uint8_t *xmm
= xsave
->legacy
.xmm_regs
[i
];
1845 uint8_t *ymmh
= xsave
->avx_state
.ymmh
[i
];
1846 uint8_t *zmmh
= xsave
->zmm_hi256_state
.zmm_hi256
[i
];
1847 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(xmm
);
1848 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(xmm
+8);
1849 env
->xmm_regs
[i
].ZMM_Q(2) = ldq_p(ymmh
);
1850 env
->xmm_regs
[i
].ZMM_Q(3) = ldq_p(ymmh
+8);
1851 env
->xmm_regs
[i
].ZMM_Q(4) = ldq_p(zmmh
);
1852 env
->xmm_regs
[i
].ZMM_Q(5) = ldq_p(zmmh
+8);
1853 env
->xmm_regs
[i
].ZMM_Q(6) = ldq_p(zmmh
+16);
1854 env
->xmm_regs
[i
].ZMM_Q(7) = ldq_p(zmmh
+24);
1857 #ifdef TARGET_X86_64
1858 memcpy(&env
->xmm_regs
[16], &xsave
->hi16_zmm_state
.hi16_zmm
,
1859 16 * sizeof env
->xmm_regs
[16]);
1860 memcpy(&env
->pkru
, &xsave
->pkru_state
, sizeof env
->pkru
);
1865 static int kvm_get_xcrs(X86CPU
*cpu
)
1867 CPUX86State
*env
= &cpu
->env
;
1869 struct kvm_xcrs xcrs
;
1875 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
1880 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1881 /* Only support xcr0 now */
1882 if (xcrs
.xcrs
[i
].xcr
== 0) {
1883 env
->xcr0
= xcrs
.xcrs
[i
].value
;
1890 static int kvm_get_sregs(X86CPU
*cpu
)
1892 CPUX86State
*env
= &cpu
->env
;
1893 struct kvm_sregs sregs
;
1897 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1902 /* There can only be one pending IRQ set in the bitmap at a time, so try
1903 to find it and save its number instead (-1 for none). */
1904 env
->interrupt_injected
= -1;
1905 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1906 if (sregs
.interrupt_bitmap
[i
]) {
1907 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1908 env
->interrupt_injected
= i
* 64 + bit
;
1913 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1914 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1915 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1916 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1917 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1918 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1920 get_seg(&env
->tr
, &sregs
.tr
);
1921 get_seg(&env
->ldt
, &sregs
.ldt
);
1923 env
->idt
.limit
= sregs
.idt
.limit
;
1924 env
->idt
.base
= sregs
.idt
.base
;
1925 env
->gdt
.limit
= sregs
.gdt
.limit
;
1926 env
->gdt
.base
= sregs
.gdt
.base
;
1928 env
->cr
[0] = sregs
.cr0
;
1929 env
->cr
[2] = sregs
.cr2
;
1930 env
->cr
[3] = sregs
.cr3
;
1931 env
->cr
[4] = sregs
.cr4
;
1933 env
->efer
= sregs
.efer
;
1935 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1937 #define HFLAG_COPY_MASK \
1938 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1939 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1940 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1941 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1943 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
1944 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1945 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1946 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1947 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1948 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1950 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
1951 hflags
|= HF_OSFXSR_MASK
;
1954 if (env
->efer
& MSR_EFER_LMA
) {
1955 hflags
|= HF_LMA_MASK
;
1958 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1959 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1961 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1962 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1963 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1964 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1965 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1966 !(hflags
& HF_CS32_MASK
)) {
1967 hflags
|= HF_ADDSEG_MASK
;
1969 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1970 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1973 env
->hflags
= hflags
;
1978 static int kvm_get_msrs(X86CPU
*cpu
)
1980 CPUX86State
*env
= &cpu
->env
;
1981 struct kvm_msr_entry
*msrs
= cpu
->kvm_msr_buf
->entries
;
1983 uint64_t mtrr_top_bits
;
1985 kvm_msr_buf_reset(cpu
);
1987 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, 0);
1988 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, 0);
1989 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, 0);
1990 kvm_msr_entry_add(cpu
, MSR_PAT
, 0);
1992 kvm_msr_entry_add(cpu
, MSR_STAR
, 0);
1994 if (has_msr_hsave_pa
) {
1995 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, 0);
1997 if (has_msr_tsc_aux
) {
1998 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, 0);
2000 if (has_msr_tsc_adjust
) {
2001 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, 0);
2003 if (has_msr_tsc_deadline
) {
2004 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, 0);
2006 if (has_msr_misc_enable
) {
2007 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
, 0);
2009 if (has_msr_smbase
) {
2010 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, 0);
2012 if (has_msr_feature_control
) {
2013 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
, 0);
2015 if (has_msr_bndcfgs
) {
2016 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, 0);
2019 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, 0);
2023 if (!env
->tsc_valid
) {
2024 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, 0);
2025 env
->tsc_valid
= !runstate_is_running();
2028 #ifdef TARGET_X86_64
2029 if (lm_capable_kernel
) {
2030 kvm_msr_entry_add(cpu
, MSR_CSTAR
, 0);
2031 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, 0);
2032 kvm_msr_entry_add(cpu
, MSR_FMASK
, 0);
2033 kvm_msr_entry_add(cpu
, MSR_LSTAR
, 0);
2036 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, 0);
2037 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, 0);
2038 if (has_msr_async_pf_en
) {
2039 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, 0);
2041 if (has_msr_pv_eoi_en
) {
2042 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, 0);
2044 if (has_msr_kvm_steal_time
) {
2045 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, 0);
2047 if (has_msr_architectural_pmu
) {
2048 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
2049 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
2050 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
, 0);
2051 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
, 0);
2052 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
2053 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
, 0);
2055 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
2056 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
, 0);
2057 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
, 0);
2062 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, 0);
2063 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, 0);
2064 if (has_msr_mcg_ext_ctl
) {
2065 kvm_msr_entry_add(cpu
, MSR_MCG_EXT_CTL
, 0);
2067 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
2068 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, 0);
2072 if (has_msr_hv_hypercall
) {
2073 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
, 0);
2074 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
, 0);
2076 if (has_msr_hv_vapic
) {
2077 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
2079 if (has_msr_hv_tsc
) {
2080 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, 0);
2082 if (has_msr_hv_crash
) {
2085 for (j
= 0; j
< HV_X64_MSR_CRASH_PARAMS
; j
++) {
2086 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
, 0);
2089 if (has_msr_hv_runtime
) {
2090 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, 0);
2092 if (cpu
->hyperv_synic
) {
2095 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
, 0);
2096 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
, 0);
2097 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
, 0);
2098 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
, 0);
2099 for (msr
= HV_X64_MSR_SINT0
; msr
<= HV_X64_MSR_SINT15
; msr
++) {
2100 kvm_msr_entry_add(cpu
, msr
, 0);
2103 if (has_msr_hv_stimer
) {
2106 for (msr
= HV_X64_MSR_STIMER0_CONFIG
; msr
<= HV_X64_MSR_STIMER3_COUNT
;
2108 kvm_msr_entry_add(cpu
, msr
, 0);
2112 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, 0);
2113 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, 0);
2114 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, 0);
2115 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, 0);
2116 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, 0);
2117 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, 0);
2118 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, 0);
2119 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, 0);
2120 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, 0);
2121 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, 0);
2122 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, 0);
2123 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, 0);
2124 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
2125 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
), 0);
2126 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), 0);
2130 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, cpu
->kvm_msr_buf
);
2135 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
2137 * MTRR masks: Each mask consists of 5 parts
2138 * a 10..0: must be zero
2140 * c n-1.12: actual mask bits
2141 * d 51..n: reserved must be zero
2142 * e 63.52: reserved must be zero
2144 * 'n' is the number of physical bits supported by the CPU and is
2145 * apparently always <= 52. We know our 'n' but don't know what
2146 * the destinations 'n' is; it might be smaller, in which case
2147 * it masks (c) on loading. It might be larger, in which case
2148 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2149 * we're migrating to.
2152 if (cpu
->fill_mtrr_mask
) {
2153 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS
> 52);
2154 assert(cpu
->phys_bits
<= TARGET_PHYS_ADDR_SPACE_BITS
);
2155 mtrr_top_bits
= MAKE_64BIT_MASK(cpu
->phys_bits
, 52 - cpu
->phys_bits
);
2160 for (i
= 0; i
< ret
; i
++) {
2161 uint32_t index
= msrs
[i
].index
;
2163 case MSR_IA32_SYSENTER_CS
:
2164 env
->sysenter_cs
= msrs
[i
].data
;
2166 case MSR_IA32_SYSENTER_ESP
:
2167 env
->sysenter_esp
= msrs
[i
].data
;
2169 case MSR_IA32_SYSENTER_EIP
:
2170 env
->sysenter_eip
= msrs
[i
].data
;
2173 env
->pat
= msrs
[i
].data
;
2176 env
->star
= msrs
[i
].data
;
2178 #ifdef TARGET_X86_64
2180 env
->cstar
= msrs
[i
].data
;
2182 case MSR_KERNELGSBASE
:
2183 env
->kernelgsbase
= msrs
[i
].data
;
2186 env
->fmask
= msrs
[i
].data
;
2189 env
->lstar
= msrs
[i
].data
;
2193 env
->tsc
= msrs
[i
].data
;
2196 env
->tsc_aux
= msrs
[i
].data
;
2198 case MSR_TSC_ADJUST
:
2199 env
->tsc_adjust
= msrs
[i
].data
;
2201 case MSR_IA32_TSCDEADLINE
:
2202 env
->tsc_deadline
= msrs
[i
].data
;
2204 case MSR_VM_HSAVE_PA
:
2205 env
->vm_hsave
= msrs
[i
].data
;
2207 case MSR_KVM_SYSTEM_TIME
:
2208 env
->system_time_msr
= msrs
[i
].data
;
2210 case MSR_KVM_WALL_CLOCK
:
2211 env
->wall_clock_msr
= msrs
[i
].data
;
2213 case MSR_MCG_STATUS
:
2214 env
->mcg_status
= msrs
[i
].data
;
2217 env
->mcg_ctl
= msrs
[i
].data
;
2219 case MSR_MCG_EXT_CTL
:
2220 env
->mcg_ext_ctl
= msrs
[i
].data
;
2222 case MSR_IA32_MISC_ENABLE
:
2223 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
2225 case MSR_IA32_SMBASE
:
2226 env
->smbase
= msrs
[i
].data
;
2228 case MSR_IA32_FEATURE_CONTROL
:
2229 env
->msr_ia32_feature_control
= msrs
[i
].data
;
2231 case MSR_IA32_BNDCFGS
:
2232 env
->msr_bndcfgs
= msrs
[i
].data
;
2235 env
->xss
= msrs
[i
].data
;
2238 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
2239 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
2240 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
2243 case MSR_KVM_ASYNC_PF_EN
:
2244 env
->async_pf_en_msr
= msrs
[i
].data
;
2246 case MSR_KVM_PV_EOI_EN
:
2247 env
->pv_eoi_en_msr
= msrs
[i
].data
;
2249 case MSR_KVM_STEAL_TIME
:
2250 env
->steal_time_msr
= msrs
[i
].data
;
2252 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
2253 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
2255 case MSR_CORE_PERF_GLOBAL_CTRL
:
2256 env
->msr_global_ctrl
= msrs
[i
].data
;
2258 case MSR_CORE_PERF_GLOBAL_STATUS
:
2259 env
->msr_global_status
= msrs
[i
].data
;
2261 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
2262 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
2264 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
2265 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
2267 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
2268 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
2270 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
2271 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
2273 case HV_X64_MSR_HYPERCALL
:
2274 env
->msr_hv_hypercall
= msrs
[i
].data
;
2276 case HV_X64_MSR_GUEST_OS_ID
:
2277 env
->msr_hv_guest_os_id
= msrs
[i
].data
;
2279 case HV_X64_MSR_APIC_ASSIST_PAGE
:
2280 env
->msr_hv_vapic
= msrs
[i
].data
;
2282 case HV_X64_MSR_REFERENCE_TSC
:
2283 env
->msr_hv_tsc
= msrs
[i
].data
;
2285 case HV_X64_MSR_CRASH_P0
... HV_X64_MSR_CRASH_P4
:
2286 env
->msr_hv_crash_params
[index
- HV_X64_MSR_CRASH_P0
] = msrs
[i
].data
;
2288 case HV_X64_MSR_VP_RUNTIME
:
2289 env
->msr_hv_runtime
= msrs
[i
].data
;
2291 case HV_X64_MSR_SCONTROL
:
2292 env
->msr_hv_synic_control
= msrs
[i
].data
;
2294 case HV_X64_MSR_SVERSION
:
2295 env
->msr_hv_synic_version
= msrs
[i
].data
;
2297 case HV_X64_MSR_SIEFP
:
2298 env
->msr_hv_synic_evt_page
= msrs
[i
].data
;
2300 case HV_X64_MSR_SIMP
:
2301 env
->msr_hv_synic_msg_page
= msrs
[i
].data
;
2303 case HV_X64_MSR_SINT0
... HV_X64_MSR_SINT15
:
2304 env
->msr_hv_synic_sint
[index
- HV_X64_MSR_SINT0
] = msrs
[i
].data
;
2306 case HV_X64_MSR_STIMER0_CONFIG
:
2307 case HV_X64_MSR_STIMER1_CONFIG
:
2308 case HV_X64_MSR_STIMER2_CONFIG
:
2309 case HV_X64_MSR_STIMER3_CONFIG
:
2310 env
->msr_hv_stimer_config
[(index
- HV_X64_MSR_STIMER0_CONFIG
)/2] =
2313 case HV_X64_MSR_STIMER0_COUNT
:
2314 case HV_X64_MSR_STIMER1_COUNT
:
2315 case HV_X64_MSR_STIMER2_COUNT
:
2316 case HV_X64_MSR_STIMER3_COUNT
:
2317 env
->msr_hv_stimer_count
[(index
- HV_X64_MSR_STIMER0_COUNT
)/2] =
2320 case MSR_MTRRdefType
:
2321 env
->mtrr_deftype
= msrs
[i
].data
;
2323 case MSR_MTRRfix64K_00000
:
2324 env
->mtrr_fixed
[0] = msrs
[i
].data
;
2326 case MSR_MTRRfix16K_80000
:
2327 env
->mtrr_fixed
[1] = msrs
[i
].data
;
2329 case MSR_MTRRfix16K_A0000
:
2330 env
->mtrr_fixed
[2] = msrs
[i
].data
;
2332 case MSR_MTRRfix4K_C0000
:
2333 env
->mtrr_fixed
[3] = msrs
[i
].data
;
2335 case MSR_MTRRfix4K_C8000
:
2336 env
->mtrr_fixed
[4] = msrs
[i
].data
;
2338 case MSR_MTRRfix4K_D0000
:
2339 env
->mtrr_fixed
[5] = msrs
[i
].data
;
2341 case MSR_MTRRfix4K_D8000
:
2342 env
->mtrr_fixed
[6] = msrs
[i
].data
;
2344 case MSR_MTRRfix4K_E0000
:
2345 env
->mtrr_fixed
[7] = msrs
[i
].data
;
2347 case MSR_MTRRfix4K_E8000
:
2348 env
->mtrr_fixed
[8] = msrs
[i
].data
;
2350 case MSR_MTRRfix4K_F0000
:
2351 env
->mtrr_fixed
[9] = msrs
[i
].data
;
2353 case MSR_MTRRfix4K_F8000
:
2354 env
->mtrr_fixed
[10] = msrs
[i
].data
;
2356 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT
- 1):
2358 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].mask
= msrs
[i
].data
|
2361 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].base
= msrs
[i
].data
;
2370 static int kvm_put_mp_state(X86CPU
*cpu
)
2372 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
2374 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
2377 static int kvm_get_mp_state(X86CPU
*cpu
)
2379 CPUState
*cs
= CPU(cpu
);
2380 CPUX86State
*env
= &cpu
->env
;
2381 struct kvm_mp_state mp_state
;
2384 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
2388 env
->mp_state
= mp_state
.mp_state
;
2389 if (kvm_irqchip_in_kernel()) {
2390 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
2395 static int kvm_get_apic(X86CPU
*cpu
)
2397 DeviceState
*apic
= cpu
->apic_state
;
2398 struct kvm_lapic_state kapic
;
2401 if (apic
&& kvm_irqchip_in_kernel()) {
2402 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
2407 kvm_get_apic_state(apic
, &kapic
);
2412 static int kvm_put_apic(X86CPU
*cpu
)
2414 DeviceState
*apic
= cpu
->apic_state
;
2415 struct kvm_lapic_state kapic
;
2417 if (apic
&& kvm_irqchip_in_kernel()) {
2418 kvm_put_apic_state(apic
, &kapic
);
2420 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_LAPIC
, &kapic
);
2425 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
2427 CPUState
*cs
= CPU(cpu
);
2428 CPUX86State
*env
= &cpu
->env
;
2429 struct kvm_vcpu_events events
= {};
2431 if (!kvm_has_vcpu_events()) {
2435 events
.exception
.injected
= (env
->exception_injected
>= 0);
2436 events
.exception
.nr
= env
->exception_injected
;
2437 events
.exception
.has_error_code
= env
->has_error_code
;
2438 events
.exception
.error_code
= env
->error_code
;
2439 events
.exception
.pad
= 0;
2441 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
2442 events
.interrupt
.nr
= env
->interrupt_injected
;
2443 events
.interrupt
.soft
= env
->soft_interrupt
;
2445 events
.nmi
.injected
= env
->nmi_injected
;
2446 events
.nmi
.pending
= env
->nmi_pending
;
2447 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
2450 events
.sipi_vector
= env
->sipi_vector
;
2452 if (has_msr_smbase
) {
2453 events
.smi
.smm
= !!(env
->hflags
& HF_SMM_MASK
);
2454 events
.smi
.smm_inside_nmi
= !!(env
->hflags2
& HF2_SMM_INSIDE_NMI_MASK
);
2455 if (kvm_irqchip_in_kernel()) {
2456 /* As soon as these are moved to the kernel, remove them
2457 * from cs->interrupt_request.
2459 events
.smi
.pending
= cs
->interrupt_request
& CPU_INTERRUPT_SMI
;
2460 events
.smi
.latched_init
= cs
->interrupt_request
& CPU_INTERRUPT_INIT
;
2461 cs
->interrupt_request
&= ~(CPU_INTERRUPT_INIT
| CPU_INTERRUPT_SMI
);
2463 /* Keep these in cs->interrupt_request. */
2464 events
.smi
.pending
= 0;
2465 events
.smi
.latched_init
= 0;
2467 events
.flags
|= KVM_VCPUEVENT_VALID_SMM
;
2471 if (level
>= KVM_PUT_RESET_STATE
) {
2473 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
2476 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
2479 static int kvm_get_vcpu_events(X86CPU
*cpu
)
2481 CPUX86State
*env
= &cpu
->env
;
2482 struct kvm_vcpu_events events
;
2485 if (!kvm_has_vcpu_events()) {
2489 memset(&events
, 0, sizeof(events
));
2490 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
2494 env
->exception_injected
=
2495 events
.exception
.injected
? events
.exception
.nr
: -1;
2496 env
->has_error_code
= events
.exception
.has_error_code
;
2497 env
->error_code
= events
.exception
.error_code
;
2499 env
->interrupt_injected
=
2500 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
2501 env
->soft_interrupt
= events
.interrupt
.soft
;
2503 env
->nmi_injected
= events
.nmi
.injected
;
2504 env
->nmi_pending
= events
.nmi
.pending
;
2505 if (events
.nmi
.masked
) {
2506 env
->hflags2
|= HF2_NMI_MASK
;
2508 env
->hflags2
&= ~HF2_NMI_MASK
;
2511 if (events
.flags
& KVM_VCPUEVENT_VALID_SMM
) {
2512 if (events
.smi
.smm
) {
2513 env
->hflags
|= HF_SMM_MASK
;
2515 env
->hflags
&= ~HF_SMM_MASK
;
2517 if (events
.smi
.pending
) {
2518 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
2520 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
2522 if (events
.smi
.smm_inside_nmi
) {
2523 env
->hflags2
|= HF2_SMM_INSIDE_NMI_MASK
;
2525 env
->hflags2
&= ~HF2_SMM_INSIDE_NMI_MASK
;
2527 if (events
.smi
.latched_init
) {
2528 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
2530 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
2534 env
->sipi_vector
= events
.sipi_vector
;
2539 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
2541 CPUState
*cs
= CPU(cpu
);
2542 CPUX86State
*env
= &cpu
->env
;
2544 unsigned long reinject_trap
= 0;
2546 if (!kvm_has_vcpu_events()) {
2547 if (env
->exception_injected
== 1) {
2548 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
2549 } else if (env
->exception_injected
== 3) {
2550 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
2552 env
->exception_injected
= -1;
2556 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2557 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2558 * by updating the debug state once again if single-stepping is on.
2559 * Another reason to call kvm_update_guest_debug here is a pending debug
2560 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2561 * reinject them via SET_GUEST_DEBUG.
2563 if (reinject_trap
||
2564 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
2565 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
2570 static int kvm_put_debugregs(X86CPU
*cpu
)
2572 CPUX86State
*env
= &cpu
->env
;
2573 struct kvm_debugregs dbgregs
;
2576 if (!kvm_has_debugregs()) {
2580 for (i
= 0; i
< 4; i
++) {
2581 dbgregs
.db
[i
] = env
->dr
[i
];
2583 dbgregs
.dr6
= env
->dr
[6];
2584 dbgregs
.dr7
= env
->dr
[7];
2587 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
2590 static int kvm_get_debugregs(X86CPU
*cpu
)
2592 CPUX86State
*env
= &cpu
->env
;
2593 struct kvm_debugregs dbgregs
;
2596 if (!kvm_has_debugregs()) {
2600 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
2604 for (i
= 0; i
< 4; i
++) {
2605 env
->dr
[i
] = dbgregs
.db
[i
];
2607 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
2608 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
2613 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
2615 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2618 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
2620 if (level
>= KVM_PUT_RESET_STATE
) {
2621 ret
= kvm_put_msr_feature_control(x86_cpu
);
2627 if (level
== KVM_PUT_FULL_STATE
) {
2628 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2629 * because TSC frequency mismatch shouldn't abort migration,
2630 * unless the user explicitly asked for a more strict TSC
2631 * setting (e.g. using an explicit "tsc-freq" option).
2633 kvm_arch_set_tsc_khz(cpu
);
2636 ret
= kvm_getput_regs(x86_cpu
, 1);
2640 ret
= kvm_put_xsave(x86_cpu
);
2644 ret
= kvm_put_xcrs(x86_cpu
);
2648 ret
= kvm_put_sregs(x86_cpu
);
2652 /* must be before kvm_put_msrs */
2653 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
2657 ret
= kvm_put_msrs(x86_cpu
, level
);
2661 if (level
>= KVM_PUT_RESET_STATE
) {
2662 ret
= kvm_put_mp_state(x86_cpu
);
2666 ret
= kvm_put_apic(x86_cpu
);
2672 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
2677 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
2681 ret
= kvm_put_debugregs(x86_cpu
);
2686 ret
= kvm_guest_debug_workarounds(x86_cpu
);
2693 int kvm_arch_get_registers(CPUState
*cs
)
2695 X86CPU
*cpu
= X86_CPU(cs
);
2698 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
2700 ret
= kvm_getput_regs(cpu
, 0);
2704 ret
= kvm_get_xsave(cpu
);
2708 ret
= kvm_get_xcrs(cpu
);
2712 ret
= kvm_get_sregs(cpu
);
2716 ret
= kvm_get_msrs(cpu
);
2720 ret
= kvm_get_mp_state(cpu
);
2724 ret
= kvm_get_apic(cpu
);
2728 ret
= kvm_get_vcpu_events(cpu
);
2732 ret
= kvm_get_debugregs(cpu
);
2738 cpu_sync_bndcs_hflags(&cpu
->env
);
2742 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
2744 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2745 CPUX86State
*env
= &x86_cpu
->env
;
2749 if (cpu
->interrupt_request
& (CPU_INTERRUPT_NMI
| CPU_INTERRUPT_SMI
)) {
2750 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
2751 qemu_mutex_lock_iothread();
2752 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
2753 qemu_mutex_unlock_iothread();
2754 DPRINTF("injected NMI\n");
2755 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
2757 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
2761 if (cpu
->interrupt_request
& CPU_INTERRUPT_SMI
) {
2762 qemu_mutex_lock_iothread();
2763 cpu
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
2764 qemu_mutex_unlock_iothread();
2765 DPRINTF("injected SMI\n");
2766 ret
= kvm_vcpu_ioctl(cpu
, KVM_SMI
);
2768 fprintf(stderr
, "KVM: injection failed, SMI lost (%s)\n",
2774 if (!kvm_pic_in_kernel()) {
2775 qemu_mutex_lock_iothread();
2778 /* Force the VCPU out of its inner loop to process any INIT requests
2779 * or (for userspace APIC, but it is cheap to combine the checks here)
2780 * pending TPR access reports.
2782 if (cpu
->interrupt_request
& (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
2783 if ((cpu
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
2784 !(env
->hflags
& HF_SMM_MASK
)) {
2785 cpu
->exit_request
= 1;
2787 if (cpu
->interrupt_request
& CPU_INTERRUPT_TPR
) {
2788 cpu
->exit_request
= 1;
2792 if (!kvm_pic_in_kernel()) {
2793 /* Try to inject an interrupt if the guest can accept it */
2794 if (run
->ready_for_interrupt_injection
&&
2795 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2796 (env
->eflags
& IF_MASK
)) {
2799 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
2800 irq
= cpu_get_pic_interrupt(env
);
2802 struct kvm_interrupt intr
;
2805 DPRINTF("injected interrupt %d\n", irq
);
2806 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
2809 "KVM: injection failed, interrupt lost (%s)\n",
2815 /* If we have an interrupt but the guest is not ready to receive an
2816 * interrupt, request an interrupt window exit. This will
2817 * cause a return to userspace as soon as the guest is ready to
2818 * receive interrupts. */
2819 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
2820 run
->request_interrupt_window
= 1;
2822 run
->request_interrupt_window
= 0;
2825 DPRINTF("setting tpr\n");
2826 run
->cr8
= cpu_get_apic_tpr(x86_cpu
->apic_state
);
2828 qemu_mutex_unlock_iothread();
2832 MemTxAttrs
kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
2834 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2835 CPUX86State
*env
= &x86_cpu
->env
;
2837 if (run
->flags
& KVM_RUN_X86_SMM
) {
2838 env
->hflags
|= HF_SMM_MASK
;
2840 env
->hflags
&= HF_SMM_MASK
;
2843 env
->eflags
|= IF_MASK
;
2845 env
->eflags
&= ~IF_MASK
;
2848 /* We need to protect the apic state against concurrent accesses from
2849 * different threads in case the userspace irqchip is used. */
2850 if (!kvm_irqchip_in_kernel()) {
2851 qemu_mutex_lock_iothread();
2853 cpu_set_apic_tpr(x86_cpu
->apic_state
, run
->cr8
);
2854 cpu_set_apic_base(x86_cpu
->apic_state
, run
->apic_base
);
2855 if (!kvm_irqchip_in_kernel()) {
2856 qemu_mutex_unlock_iothread();
2858 return cpu_get_mem_attrs(env
);
2861 int kvm_arch_process_async_events(CPUState
*cs
)
2863 X86CPU
*cpu
= X86_CPU(cs
);
2864 CPUX86State
*env
= &cpu
->env
;
2866 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
2867 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2868 assert(env
->mcg_cap
);
2870 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
2872 kvm_cpu_synchronize_state(cs
);
2874 if (env
->exception_injected
== EXCP08_DBLE
) {
2875 /* this means triple fault */
2876 qemu_system_reset_request();
2877 cs
->exit_request
= 1;
2880 env
->exception_injected
= EXCP12_MCHK
;
2881 env
->has_error_code
= 0;
2884 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
2885 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
2889 if ((cs
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
2890 !(env
->hflags
& HF_SMM_MASK
)) {
2891 kvm_cpu_synchronize_state(cs
);
2895 if (kvm_irqchip_in_kernel()) {
2899 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
2900 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
2901 apic_poll_irq(cpu
->apic_state
);
2903 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2904 (env
->eflags
& IF_MASK
)) ||
2905 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2908 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
2909 kvm_cpu_synchronize_state(cs
);
2912 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
2913 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
2914 kvm_cpu_synchronize_state(cs
);
2915 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
,
2916 env
->tpr_access_type
);
2922 static int kvm_handle_halt(X86CPU
*cpu
)
2924 CPUState
*cs
= CPU(cpu
);
2925 CPUX86State
*env
= &cpu
->env
;
2927 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2928 (env
->eflags
& IF_MASK
)) &&
2929 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2937 static int kvm_handle_tpr_access(X86CPU
*cpu
)
2939 CPUState
*cs
= CPU(cpu
);
2940 struct kvm_run
*run
= cs
->kvm_run
;
2942 apic_handle_tpr_access_report(cpu
->apic_state
, run
->tpr_access
.rip
,
2943 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
2948 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2950 static const uint8_t int3
= 0xcc;
2952 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
2953 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
2959 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2963 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
2964 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
2976 static int nb_hw_breakpoint
;
2978 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
2982 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2983 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
2984 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
2991 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
2992 target_ulong len
, int type
)
2995 case GDB_BREAKPOINT_HW
:
2998 case GDB_WATCHPOINT_WRITE
:
2999 case GDB_WATCHPOINT_ACCESS
:
3006 if (addr
& (len
- 1)) {
3018 if (nb_hw_breakpoint
== 4) {
3021 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
3024 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
3025 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
3026 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
3032 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
3033 target_ulong len
, int type
)
3037 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
3042 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
3047 void kvm_arch_remove_all_hw_breakpoints(void)
3049 nb_hw_breakpoint
= 0;
3052 static CPUWatchpoint hw_watchpoint
;
3054 static int kvm_handle_debug(X86CPU
*cpu
,
3055 struct kvm_debug_exit_arch
*arch_info
)
3057 CPUState
*cs
= CPU(cpu
);
3058 CPUX86State
*env
= &cpu
->env
;
3062 if (arch_info
->exception
== 1) {
3063 if (arch_info
->dr6
& (1 << 14)) {
3064 if (cs
->singlestep_enabled
) {
3068 for (n
= 0; n
< 4; n
++) {
3069 if (arch_info
->dr6
& (1 << n
)) {
3070 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
3076 cs
->watchpoint_hit
= &hw_watchpoint
;
3077 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
3078 hw_watchpoint
.flags
= BP_MEM_WRITE
;
3082 cs
->watchpoint_hit
= &hw_watchpoint
;
3083 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
3084 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
3090 } else if (kvm_find_sw_breakpoint(cs
, arch_info
->pc
)) {
3094 cpu_synchronize_state(cs
);
3095 assert(env
->exception_injected
== -1);
3098 env
->exception_injected
= arch_info
->exception
;
3099 env
->has_error_code
= 0;
3105 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
3107 const uint8_t type_code
[] = {
3108 [GDB_BREAKPOINT_HW
] = 0x0,
3109 [GDB_WATCHPOINT_WRITE
] = 0x1,
3110 [GDB_WATCHPOINT_ACCESS
] = 0x3
3112 const uint8_t len_code
[] = {
3113 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3117 if (kvm_sw_breakpoints_active(cpu
)) {
3118 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
3120 if (nb_hw_breakpoint
> 0) {
3121 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
3122 dbg
->arch
.debugreg
[7] = 0x0600;
3123 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
3124 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
3125 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
3126 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
3127 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
3132 static bool host_supports_vmx(void)
3134 uint32_t ecx
, unused
;
3136 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
3137 return ecx
& CPUID_EXT_VMX
;
3140 #define VMX_INVALID_GUEST_STATE 0x80000021
3142 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
3144 X86CPU
*cpu
= X86_CPU(cs
);
3148 switch (run
->exit_reason
) {
3150 DPRINTF("handle_hlt\n");
3151 qemu_mutex_lock_iothread();
3152 ret
= kvm_handle_halt(cpu
);
3153 qemu_mutex_unlock_iothread();
3155 case KVM_EXIT_SET_TPR
:
3158 case KVM_EXIT_TPR_ACCESS
:
3159 qemu_mutex_lock_iothread();
3160 ret
= kvm_handle_tpr_access(cpu
);
3161 qemu_mutex_unlock_iothread();
3163 case KVM_EXIT_FAIL_ENTRY
:
3164 code
= run
->fail_entry
.hardware_entry_failure_reason
;
3165 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
3167 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
3169 "\nIf you're running a guest on an Intel machine without "
3170 "unrestricted mode\n"
3171 "support, the failure can be most likely due to the guest "
3172 "entering an invalid\n"
3173 "state for Intel VT. For example, the guest maybe running "
3174 "in big real mode\n"
3175 "which is not supported on less recent Intel processors."
3180 case KVM_EXIT_EXCEPTION
:
3181 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
3182 run
->ex
.exception
, run
->ex
.error_code
);
3185 case KVM_EXIT_DEBUG
:
3186 DPRINTF("kvm_exit_debug\n");
3187 qemu_mutex_lock_iothread();
3188 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
3189 qemu_mutex_unlock_iothread();
3191 case KVM_EXIT_HYPERV
:
3192 ret
= kvm_hv_handle_exit(cpu
, &run
->hyperv
);
3194 case KVM_EXIT_IOAPIC_EOI
:
3195 ioapic_eoi_broadcast(run
->eoi
.vector
);
3199 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
3207 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
3209 X86CPU
*cpu
= X86_CPU(cs
);
3210 CPUX86State
*env
= &cpu
->env
;
3212 kvm_cpu_synchronize_state(cs
);
3213 return !(env
->cr
[0] & CR0_PE_MASK
) ||
3214 ((env
->segs
[R_CS
].selector
& 3) != 3);
3217 void kvm_arch_init_irq_routing(KVMState
*s
)
3219 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
3220 /* If kernel can't do irq routing, interrupt source
3221 * override 0->2 cannot be set up as required by HPET.
3222 * So we have to disable it.
3226 /* We know at this point that we're using the in-kernel
3227 * irqchip, so we can use irqfds, and on x86 we know
3228 * we can use msi via irqfd and GSI routing.
3230 kvm_msi_via_irqfd_allowed
= true;
3231 kvm_gsi_routing_allowed
= true;
3233 if (kvm_irqchip_is_split()) {
3236 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3237 MSI routes for signaling interrupts to the local apics. */
3238 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
3239 if (kvm_irqchip_add_msi_route(s
, 0, NULL
) < 0) {
3240 error_report("Could not enable split IRQ mode.");
3247 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
3250 if (machine_kernel_irqchip_split(ms
)) {
3251 ret
= kvm_vm_enable_cap(s
, KVM_CAP_SPLIT_IRQCHIP
, 0, 24);
3253 error_report("Could not enable split irqchip mode: %s\n",
3257 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3258 kvm_split_irqchip
= true;
3266 /* Classic KVM device assignment interface. Will remain x86 only. */
3267 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
3268 uint32_t flags
, uint32_t *dev_id
)
3270 struct kvm_assigned_pci_dev dev_data
= {
3271 .segnr
= dev_addr
->domain
,
3272 .busnr
= dev_addr
->bus
,
3273 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
3278 dev_data
.assigned_dev_id
=
3279 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
3281 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
3286 *dev_id
= dev_data
.assigned_dev_id
;
3291 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
3293 struct kvm_assigned_pci_dev dev_data
= {
3294 .assigned_dev_id
= dev_id
,
3297 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
3300 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
3301 uint32_t irq_type
, uint32_t guest_irq
)
3303 struct kvm_assigned_irq assigned_irq
= {
3304 .assigned_dev_id
= dev_id
,
3305 .guest_irq
= guest_irq
,
3309 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
3310 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
3312 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
3316 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
3319 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
3320 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
3322 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
3325 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
3327 struct kvm_assigned_pci_dev dev_data
= {
3328 .assigned_dev_id
= dev_id
,
3329 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
3332 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
3335 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
3338 struct kvm_assigned_irq assigned_irq
= {
3339 .assigned_dev_id
= dev_id
,
3343 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
3346 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
3348 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
3349 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
3352 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
3354 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
3355 KVM_DEV_IRQ_GUEST_MSI
, virq
);
3358 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
3360 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
3361 KVM_DEV_IRQ_HOST_MSI
);
3364 bool kvm_device_msix_supported(KVMState
*s
)
3366 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3367 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3368 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
3371 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
3372 uint32_t nr_vectors
)
3374 struct kvm_assigned_msix_nr msix_nr
= {
3375 .assigned_dev_id
= dev_id
,
3376 .entry_nr
= nr_vectors
,
3379 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
3382 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
3385 struct kvm_assigned_msix_entry msix_entry
= {
3386 .assigned_dev_id
= dev_id
,
3391 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
3394 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
3396 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
3397 KVM_DEV_IRQ_GUEST_MSIX
, 0);
3400 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
3402 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
3403 KVM_DEV_IRQ_HOST_MSIX
);
3406 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
3407 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
3409 X86IOMMUState
*iommu
= x86_iommu_get_default();
3413 MSIMessage src
, dst
;
3414 X86IOMMUClass
*class = X86_IOMMU_GET_CLASS(iommu
);
3416 src
.address
= route
->u
.msi
.address_hi
;
3417 src
.address
<<= VTD_MSI_ADDR_HI_SHIFT
;
3418 src
.address
|= route
->u
.msi
.address_lo
;
3419 src
.data
= route
->u
.msi
.data
;
3421 ret
= class->int_remap(iommu
, &src
, &dst
, dev
? \
3422 pci_requester_id(dev
) : \
3423 X86_IOMMU_SID_INVALID
);
3425 trace_kvm_x86_fixup_msi_error(route
->gsi
);
3429 route
->u
.msi
.address_hi
= dst
.address
>> VTD_MSI_ADDR_HI_SHIFT
;
3430 route
->u
.msi
.address_lo
= dst
.address
& VTD_MSI_ADDR_LO_MASK
;
3431 route
->u
.msi
.data
= dst
.data
;
3437 typedef struct MSIRouteEntry MSIRouteEntry
;
3439 struct MSIRouteEntry
{
3440 PCIDevice
*dev
; /* Device pointer */
3441 int vector
; /* MSI/MSIX vector index */
3442 int virq
; /* Virtual IRQ index */
3443 QLIST_ENTRY(MSIRouteEntry
) list
;
3446 /* List of used GSI routes */
3447 static QLIST_HEAD(, MSIRouteEntry
) msi_route_list
= \
3448 QLIST_HEAD_INITIALIZER(msi_route_list
);
3450 static void kvm_update_msi_routes_all(void *private, bool global
,
3451 uint32_t index
, uint32_t mask
)
3454 MSIRouteEntry
*entry
;
3456 /* TODO: explicit route update */
3457 QLIST_FOREACH(entry
, &msi_route_list
, list
) {
3459 msg
= pci_get_msi_message(entry
->dev
, entry
->vector
);
3460 kvm_irqchip_update_msi_route(kvm_state
, entry
->virq
,
3463 kvm_irqchip_commit_routes(kvm_state
);
3464 trace_kvm_x86_update_msi_routes(cnt
);
3467 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
3468 int vector
, PCIDevice
*dev
)
3470 static bool notify_list_inited
= false;
3471 MSIRouteEntry
*entry
;
3474 /* These are (possibly) IOAPIC routes only used for split
3475 * kernel irqchip mode, while what we are housekeeping are
3476 * PCI devices only. */
3480 entry
= g_new0(MSIRouteEntry
, 1);
3482 entry
->vector
= vector
;
3483 entry
->virq
= route
->gsi
;
3484 QLIST_INSERT_HEAD(&msi_route_list
, entry
, list
);
3486 trace_kvm_x86_add_msi_route(route
->gsi
);
3488 if (!notify_list_inited
) {
3489 /* For the first time we do add route, add ourselves into
3490 * IOMMU's IEC notify list if needed. */
3491 X86IOMMUState
*iommu
= x86_iommu_get_default();
3493 x86_iommu_iec_register_notifier(iommu
,
3494 kvm_update_msi_routes_all
,
3497 notify_list_inited
= true;
3502 int kvm_arch_release_virq_post(int virq
)
3504 MSIRouteEntry
*entry
, *next
;
3505 QLIST_FOREACH_SAFE(entry
, &msi_route_list
, list
, next
) {
3506 if (entry
->virq
== virq
) {
3507 trace_kvm_x86_remove_msi_route(virq
);
3508 QLIST_REMOVE(entry
, list
);
3515 int kvm_arch_msi_data_to_gsi(uint32_t data
)