4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
22 #include "qemu-common.h"
27 #include "host-utils.h"
33 #ifdef CONFIG_KVM_PARA
34 #include <linux/kvm_para.h>
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
43 #define DPRINTF(fmt, ...) \
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
51 #define BUS_MCEERR_AR 4
54 #define BUS_MCEERR_AO 5
57 static int lm_capable_kernel
;
59 #ifdef KVM_CAP_EXT_CPUID
61 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
63 struct kvm_cpuid2
*cpuid
;
66 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
67 cpuid
= (struct kvm_cpuid2
*)qemu_mallocz(size
);
69 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
70 if (r
== 0 && cpuid
->nent
>= max
) {
78 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
86 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
87 uint32_t index
, int reg
)
89 struct kvm_cpuid2
*cpuid
;
94 if (!kvm_check_extension(env
->kvm_state
, KVM_CAP_EXT_CPUID
)) {
99 while ((cpuid
= try_get_cpuid(env
->kvm_state
, max
)) == NULL
) {
103 for (i
= 0; i
< cpuid
->nent
; ++i
) {
104 if (cpuid
->entries
[i
].function
== function
&&
105 cpuid
->entries
[i
].index
== index
) {
108 ret
= cpuid
->entries
[i
].eax
;
111 ret
= cpuid
->entries
[i
].ebx
;
114 ret
= cpuid
->entries
[i
].ecx
;
117 ret
= cpuid
->entries
[i
].edx
;
120 /* KVM before 2.6.30 misreports the following features */
121 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
124 /* On Intel, kvm returns cpuid according to the Intel spec,
125 * so add missing bits according to the AMD spec:
127 cpuid_1_edx
= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
128 ret
|= cpuid_1_edx
& 0x183f7ff;
143 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
144 uint32_t index
, int reg
)
151 #ifdef CONFIG_KVM_PARA
152 struct kvm_para_features
{
155 } para_features
[] = {
156 #ifdef KVM_CAP_CLOCKSOURCE
157 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
159 #ifdef KVM_CAP_NOP_IO_DELAY
160 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
162 #ifdef KVM_CAP_PV_MMU
163 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
165 #ifdef KVM_CAP_ASYNC_PF
166 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
171 static int get_para_features(CPUState
*env
)
175 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
176 if (kvm_check_extension(env
->kvm_state
, para_features
[i
].cap
))
177 features
|= (1 << para_features
[i
].feature
);
185 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
190 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
193 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
198 static int kvm_setup_mce(CPUState
*env
, uint64_t *mcg_cap
)
200 return kvm_vcpu_ioctl(env
, KVM_X86_SETUP_MCE
, mcg_cap
);
203 static int kvm_set_mce(CPUState
*env
, struct kvm_x86_mce
*m
)
205 return kvm_vcpu_ioctl(env
, KVM_X86_SET_MCE
, m
);
208 static int kvm_get_msr(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
210 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
214 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
215 r
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, kmsrs
);
216 memcpy(msrs
, kmsrs
->entries
, n
* sizeof *msrs
);
221 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
222 static int kvm_mce_in_exception(CPUState
*env
)
224 struct kvm_msr_entry msr_mcg_status
= {
225 .index
= MSR_MCG_STATUS
,
229 r
= kvm_get_msr(env
, &msr_mcg_status
, 1);
230 if (r
== -1 || r
== 0) {
233 return !!(msr_mcg_status
.data
& MCG_STATUS_MCIP
);
236 struct kvm_x86_mce_data
239 struct kvm_x86_mce
*mce
;
243 static void kvm_do_inject_x86_mce(void *_data
)
245 struct kvm_x86_mce_data
*data
= _data
;
248 /* If there is an MCE exception being processed, ignore this SRAO MCE */
249 if ((data
->env
->mcg_cap
& MCG_SER_P
) &&
250 !(data
->mce
->status
& MCI_STATUS_AR
)) {
251 r
= kvm_mce_in_exception(data
->env
);
253 fprintf(stderr
, "Failed to get MCE status\n");
259 r
= kvm_set_mce(data
->env
, data
->mce
);
261 perror("kvm_set_mce FAILED");
262 if (data
->abort_on_error
) {
268 static void kvm_mce_broadcast_rest(CPUState
*env
);
271 void kvm_inject_x86_mce(CPUState
*cenv
, int bank
, uint64_t status
,
272 uint64_t mcg_status
, uint64_t addr
, uint64_t misc
,
276 struct kvm_x86_mce mce
= {
279 .mcg_status
= mcg_status
,
283 struct kvm_x86_mce_data data
= {
288 if (!cenv
->mcg_cap
) {
289 fprintf(stderr
, "MCE support is not enabled!\n");
293 if (flag
& MCE_BROADCAST
) {
294 kvm_mce_broadcast_rest(cenv
);
297 run_on_cpu(cenv
, kvm_do_inject_x86_mce
, &data
);
299 if (flag
& ABORT_ON_ERROR
) {
305 int kvm_arch_init_vcpu(CPUState
*env
)
308 struct kvm_cpuid2 cpuid
;
309 struct kvm_cpuid_entry2 entries
[100];
310 } __attribute__((packed
)) cpuid_data
;
311 uint32_t limit
, i
, j
, cpuid_i
;
313 struct kvm_cpuid_entry2
*c
;
314 #ifdef KVM_CPUID_SIGNATURE
315 uint32_t signature
[3];
318 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
320 env
->cpuid_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
322 i
= env
->cpuid_ext_features
& CPUID_EXT_HYPERVISOR
;
323 env
->cpuid_ext_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_ECX
);
324 env
->cpuid_ext_features
|= i
;
326 env
->cpuid_ext2_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
328 env
->cpuid_ext3_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
330 env
->cpuid_svm_features
&= kvm_arch_get_supported_cpuid(env
, 0x8000000A,
336 #ifdef CONFIG_KVM_PARA
337 /* Paravirtualization CPUIDs */
338 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
339 c
= &cpuid_data
.entries
[cpuid_i
++];
340 memset(c
, 0, sizeof(*c
));
341 c
->function
= KVM_CPUID_SIGNATURE
;
343 c
->ebx
= signature
[0];
344 c
->ecx
= signature
[1];
345 c
->edx
= signature
[2];
347 c
= &cpuid_data
.entries
[cpuid_i
++];
348 memset(c
, 0, sizeof(*c
));
349 c
->function
= KVM_CPUID_FEATURES
;
350 c
->eax
= env
->cpuid_kvm_features
& get_para_features(env
);
353 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
355 for (i
= 0; i
<= limit
; i
++) {
356 c
= &cpuid_data
.entries
[cpuid_i
++];
360 /* Keep reading function 2 till all the input is received */
364 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
365 KVM_CPUID_FLAG_STATE_READ_NEXT
;
366 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
367 times
= c
->eax
& 0xff;
369 for (j
= 1; j
< times
; ++j
) {
370 c
= &cpuid_data
.entries
[cpuid_i
++];
372 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
373 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
382 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
384 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
386 if (i
== 4 && c
->eax
== 0)
388 if (i
== 0xb && !(c
->ecx
& 0xff00))
390 if (i
== 0xd && c
->eax
== 0)
393 c
= &cpuid_data
.entries
[cpuid_i
++];
399 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
403 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
405 for (i
= 0x80000000; i
<= limit
; i
++) {
406 c
= &cpuid_data
.entries
[cpuid_i
++];
410 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
413 cpuid_data
.cpuid
.nent
= cpuid_i
;
416 if (((env
->cpuid_version
>> 8)&0xF) >= 6
417 && (env
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
418 && kvm_check_extension(env
->kvm_state
, KVM_CAP_MCE
) > 0) {
422 if (kvm_get_mce_cap_supported(env
->kvm_state
, &mcg_cap
, &banks
))
423 perror("kvm_get_mce_cap_supported FAILED");
425 if (banks
> MCE_BANKS_DEF
)
426 banks
= MCE_BANKS_DEF
;
427 mcg_cap
&= MCE_CAP_DEF
;
429 if (kvm_setup_mce(env
, &mcg_cap
))
430 perror("kvm_setup_mce FAILED");
432 env
->mcg_cap
= mcg_cap
;
437 return kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, &cpuid_data
);
440 void kvm_arch_reset_vcpu(CPUState
*env
)
442 env
->exception_injected
= -1;
443 env
->interrupt_injected
= -1;
444 env
->nmi_injected
= 0;
445 env
->nmi_pending
= 0;
446 if (kvm_irqchip_in_kernel()) {
447 env
->mp_state
= cpu_is_bsp(env
) ? KVM_MP_STATE_RUNNABLE
:
448 KVM_MP_STATE_UNINITIALIZED
;
450 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
455 int has_msr_hsave_pa
;
457 static void kvm_supported_msrs(CPUState
*env
)
459 static int kvm_supported_msrs
;
463 if (kvm_supported_msrs
== 0) {
464 struct kvm_msr_list msr_list
, *kvm_msr_list
;
466 kvm_supported_msrs
= -1;
468 /* Obtain MSR list from KVM. These are the MSRs that we must
471 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
472 if (ret
< 0 && ret
!= -E2BIG
) {
475 /* Old kernel modules had a bug and could write beyond the provided
476 memory. Allocate at least a safe amount of 1K. */
477 kvm_msr_list
= qemu_mallocz(MAX(1024, sizeof(msr_list
) +
479 sizeof(msr_list
.indices
[0])));
481 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
482 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
486 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
487 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
491 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
492 has_msr_hsave_pa
= 1;
504 static int kvm_has_msr_hsave_pa(CPUState
*env
)
506 kvm_supported_msrs(env
);
507 return has_msr_hsave_pa
;
510 static int kvm_has_msr_star(CPUState
*env
)
512 kvm_supported_msrs(env
);
516 static int kvm_init_identity_map_page(KVMState
*s
)
518 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
520 uint64_t addr
= 0xfffbc000;
522 if (!kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
526 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &addr
);
528 fprintf(stderr
, "kvm_set_identity_map_addr: %s\n", strerror(ret
));
535 int kvm_arch_init(KVMState
*s
, int smp_cpus
)
539 struct utsname utsname
;
542 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
544 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
545 * directly. In order to use vm86 mode, a TSS is needed. Since this
546 * must be part of guest physical memory, we need to allocate it. Older
547 * versions of KVM just assumed that it would be at the end of physical
548 * memory but that doesn't work with more than 4GB of memory. We simply
549 * refuse to work with those older versions of KVM. */
550 ret
= kvm_check_extension(s
, KVM_CAP_SET_TSS_ADDR
);
552 fprintf(stderr
, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
556 /* this address is 3 pages before the bios, and the bios should present
557 * as unavaible memory. FIXME, need to ensure the e820 map deals with
561 * Tell fw_cfg to notify the BIOS to reserve the range.
563 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED
) < 0) {
564 perror("e820_add_entry() table is full");
567 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, 0xfffbd000);
572 return kvm_init_identity_map_page(s
);
575 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
577 lhs
->selector
= rhs
->selector
;
578 lhs
->base
= rhs
->base
;
579 lhs
->limit
= rhs
->limit
;
591 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
593 unsigned flags
= rhs
->flags
;
594 lhs
->selector
= rhs
->selector
;
595 lhs
->base
= rhs
->base
;
596 lhs
->limit
= rhs
->limit
;
597 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
598 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
599 lhs
->dpl
= rhs
->selector
& 3;
600 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
601 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
602 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
603 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
604 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
608 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
610 lhs
->selector
= rhs
->selector
;
611 lhs
->base
= rhs
->base
;
612 lhs
->limit
= rhs
->limit
;
614 (rhs
->type
<< DESC_TYPE_SHIFT
)
615 | (rhs
->present
* DESC_P_MASK
)
616 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
617 | (rhs
->db
<< DESC_B_SHIFT
)
618 | (rhs
->s
* DESC_S_MASK
)
619 | (rhs
->l
<< DESC_L_SHIFT
)
620 | (rhs
->g
* DESC_G_MASK
)
621 | (rhs
->avl
* DESC_AVL_MASK
);
624 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
627 *kvm_reg
= *qemu_reg
;
629 *qemu_reg
= *kvm_reg
;
632 static int kvm_getput_regs(CPUState
*env
, int set
)
634 struct kvm_regs regs
;
638 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
643 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
644 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
645 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
646 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
647 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
648 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
649 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
650 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
652 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
653 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
654 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
655 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
656 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
657 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
658 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
659 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
662 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
663 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
666 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
671 static int kvm_put_fpu(CPUState
*env
)
676 memset(&fpu
, 0, sizeof fpu
);
677 fpu
.fsw
= env
->fpus
& ~(7 << 11);
678 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
680 for (i
= 0; i
< 8; ++i
)
681 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
682 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
683 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
684 fpu
.mxcsr
= env
->mxcsr
;
686 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
690 #define XSAVE_CWD_RIP 2
691 #define XSAVE_CWD_RDP 4
692 #define XSAVE_MXCSR 6
693 #define XSAVE_ST_SPACE 8
694 #define XSAVE_XMM_SPACE 40
695 #define XSAVE_XSTATE_BV 128
696 #define XSAVE_YMMH_SPACE 144
699 static int kvm_put_xsave(CPUState
*env
)
703 struct kvm_xsave
* xsave
;
704 uint16_t cwd
, swd
, twd
, fop
;
706 if (!kvm_has_xsave())
707 return kvm_put_fpu(env
);
709 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
710 memset(xsave
, 0, sizeof(struct kvm_xsave
));
711 cwd
= swd
= twd
= fop
= 0;
712 swd
= env
->fpus
& ~(7 << 11);
713 swd
|= (env
->fpstt
& 7) << 11;
715 for (i
= 0; i
< 8; ++i
)
716 twd
|= (!env
->fptags
[i
]) << i
;
717 xsave
->region
[0] = (uint32_t)(swd
<< 16) + cwd
;
718 xsave
->region
[1] = (uint32_t)(fop
<< 16) + twd
;
719 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
721 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
722 sizeof env
->xmm_regs
);
723 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
724 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
725 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
726 sizeof env
->ymmh_regs
);
727 r
= kvm_vcpu_ioctl(env
, KVM_SET_XSAVE
, xsave
);
731 return kvm_put_fpu(env
);
735 static int kvm_put_xcrs(CPUState
*env
)
738 struct kvm_xcrs xcrs
;
745 xcrs
.xcrs
[0].xcr
= 0;
746 xcrs
.xcrs
[0].value
= env
->xcr0
;
747 return kvm_vcpu_ioctl(env
, KVM_SET_XCRS
, &xcrs
);
753 static int kvm_put_sregs(CPUState
*env
)
755 struct kvm_sregs sregs
;
757 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
758 if (env
->interrupt_injected
>= 0) {
759 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
760 (uint64_t)1 << (env
->interrupt_injected
% 64);
763 if ((env
->eflags
& VM_MASK
)) {
764 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
765 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
766 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
767 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
768 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
769 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
771 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
772 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
773 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
774 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
775 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
776 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
778 if (env
->cr
[0] & CR0_PE_MASK
) {
779 /* force ss cpl to cs cpl */
780 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
781 (sregs
.cs
.selector
& 3);
782 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
786 set_seg(&sregs
.tr
, &env
->tr
);
787 set_seg(&sregs
.ldt
, &env
->ldt
);
789 sregs
.idt
.limit
= env
->idt
.limit
;
790 sregs
.idt
.base
= env
->idt
.base
;
791 sregs
.gdt
.limit
= env
->gdt
.limit
;
792 sregs
.gdt
.base
= env
->gdt
.base
;
794 sregs
.cr0
= env
->cr
[0];
795 sregs
.cr2
= env
->cr
[2];
796 sregs
.cr3
= env
->cr
[3];
797 sregs
.cr4
= env
->cr
[4];
799 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
800 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
802 sregs
.efer
= env
->efer
;
804 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
807 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
808 uint32_t index
, uint64_t value
)
810 entry
->index
= index
;
814 static int kvm_put_msrs(CPUState
*env
, int level
)
817 struct kvm_msrs info
;
818 struct kvm_msr_entry entries
[100];
820 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
823 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
824 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
825 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
826 if (kvm_has_msr_star(env
))
827 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
828 if (kvm_has_msr_hsave_pa(env
))
829 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
831 if (lm_capable_kernel
) {
832 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
833 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
834 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
835 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
838 if (level
== KVM_PUT_FULL_STATE
) {
840 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
841 * writeback. Until this is fixed, we only write the offset to SMP
842 * guests after migration, desynchronizing the VCPUs, but avoiding
843 * huge jump-backs that would occur without any writeback at all.
845 if (smp_cpus
== 1 || env
->tsc
!= 0) {
846 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
848 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
849 env
->system_time_msr
);
850 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
851 #ifdef KVM_CAP_ASYNC_PF
852 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
858 if (level
== KVM_PUT_RESET_STATE
)
859 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
860 else if (level
== KVM_PUT_FULL_STATE
) {
861 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
862 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
863 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++)
864 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
869 msr_data
.info
.nmsrs
= n
;
871 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
876 static int kvm_get_fpu(CPUState
*env
)
881 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
885 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
888 for (i
= 0; i
< 8; ++i
)
889 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
890 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
891 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
892 env
->mxcsr
= fpu
.mxcsr
;
897 static int kvm_get_xsave(CPUState
*env
)
900 struct kvm_xsave
* xsave
;
902 uint16_t cwd
, swd
, twd
, fop
;
904 if (!kvm_has_xsave())
905 return kvm_get_fpu(env
);
907 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
908 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XSAVE
, xsave
);
914 cwd
= (uint16_t)xsave
->region
[0];
915 swd
= (uint16_t)(xsave
->region
[0] >> 16);
916 twd
= (uint16_t)xsave
->region
[1];
917 fop
= (uint16_t)(xsave
->region
[1] >> 16);
918 env
->fpstt
= (swd
>> 11) & 7;
921 for (i
= 0; i
< 8; ++i
)
922 env
->fptags
[i
] = !((twd
>> i
) & 1);
923 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
924 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
926 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
927 sizeof env
->xmm_regs
);
928 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
929 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
930 sizeof env
->ymmh_regs
);
934 return kvm_get_fpu(env
);
938 static int kvm_get_xcrs(CPUState
*env
)
942 struct kvm_xcrs xcrs
;
947 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XCRS
, &xcrs
);
951 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++)
952 /* Only support xcr0 now */
953 if (xcrs
.xcrs
[0].xcr
== 0) {
954 env
->xcr0
= xcrs
.xcrs
[0].value
;
963 static int kvm_get_sregs(CPUState
*env
)
965 struct kvm_sregs sregs
;
969 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
973 /* There can only be one pending IRQ set in the bitmap at a time, so try
974 to find it and save its number instead (-1 for none). */
975 env
->interrupt_injected
= -1;
976 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
977 if (sregs
.interrupt_bitmap
[i
]) {
978 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
979 env
->interrupt_injected
= i
* 64 + bit
;
984 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
985 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
986 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
987 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
988 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
989 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
991 get_seg(&env
->tr
, &sregs
.tr
);
992 get_seg(&env
->ldt
, &sregs
.ldt
);
994 env
->idt
.limit
= sregs
.idt
.limit
;
995 env
->idt
.base
= sregs
.idt
.base
;
996 env
->gdt
.limit
= sregs
.gdt
.limit
;
997 env
->gdt
.base
= sregs
.gdt
.base
;
999 env
->cr
[0] = sregs
.cr0
;
1000 env
->cr
[2] = sregs
.cr2
;
1001 env
->cr
[3] = sregs
.cr3
;
1002 env
->cr
[4] = sregs
.cr4
;
1004 cpu_set_apic_base(env
->apic_state
, sregs
.apic_base
);
1006 env
->efer
= sregs
.efer
;
1007 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1009 #define HFLAG_COPY_MASK ~( \
1010 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1011 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1012 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1013 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1017 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1018 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1019 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1020 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1021 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1022 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1023 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1025 if (env
->efer
& MSR_EFER_LMA
) {
1026 hflags
|= HF_LMA_MASK
;
1029 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1030 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1032 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1033 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1034 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1035 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1036 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
1037 (env
->eflags
& VM_MASK
) ||
1038 !(hflags
& HF_CS32_MASK
)) {
1039 hflags
|= HF_ADDSEG_MASK
;
1041 hflags
|= ((env
->segs
[R_DS
].base
|
1042 env
->segs
[R_ES
].base
|
1043 env
->segs
[R_SS
].base
) != 0) <<
1047 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1052 static int kvm_get_msrs(CPUState
*env
)
1055 struct kvm_msrs info
;
1056 struct kvm_msr_entry entries
[100];
1058 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1062 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1063 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1064 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1065 if (kvm_has_msr_star(env
))
1066 msrs
[n
++].index
= MSR_STAR
;
1067 if (kvm_has_msr_hsave_pa(env
))
1068 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1069 msrs
[n
++].index
= MSR_IA32_TSC
;
1070 #ifdef TARGET_X86_64
1071 if (lm_capable_kernel
) {
1072 msrs
[n
++].index
= MSR_CSTAR
;
1073 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1074 msrs
[n
++].index
= MSR_FMASK
;
1075 msrs
[n
++].index
= MSR_LSTAR
;
1078 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1079 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1080 #ifdef KVM_CAP_ASYNC_PF
1081 msrs
[n
++].index
= MSR_KVM_ASYNC_PF_EN
;
1086 msrs
[n
++].index
= MSR_MCG_STATUS
;
1087 msrs
[n
++].index
= MSR_MCG_CTL
;
1088 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++)
1089 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1093 msr_data
.info
.nmsrs
= n
;
1094 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
1098 for (i
= 0; i
< ret
; i
++) {
1099 switch (msrs
[i
].index
) {
1100 case MSR_IA32_SYSENTER_CS
:
1101 env
->sysenter_cs
= msrs
[i
].data
;
1103 case MSR_IA32_SYSENTER_ESP
:
1104 env
->sysenter_esp
= msrs
[i
].data
;
1106 case MSR_IA32_SYSENTER_EIP
:
1107 env
->sysenter_eip
= msrs
[i
].data
;
1110 env
->star
= msrs
[i
].data
;
1112 #ifdef TARGET_X86_64
1114 env
->cstar
= msrs
[i
].data
;
1116 case MSR_KERNELGSBASE
:
1117 env
->kernelgsbase
= msrs
[i
].data
;
1120 env
->fmask
= msrs
[i
].data
;
1123 env
->lstar
= msrs
[i
].data
;
1127 env
->tsc
= msrs
[i
].data
;
1129 case MSR_VM_HSAVE_PA
:
1130 env
->vm_hsave
= msrs
[i
].data
;
1132 case MSR_KVM_SYSTEM_TIME
:
1133 env
->system_time_msr
= msrs
[i
].data
;
1135 case MSR_KVM_WALL_CLOCK
:
1136 env
->wall_clock_msr
= msrs
[i
].data
;
1139 case MSR_MCG_STATUS
:
1140 env
->mcg_status
= msrs
[i
].data
;
1143 env
->mcg_ctl
= msrs
[i
].data
;
1148 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1149 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1150 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1154 #ifdef KVM_CAP_ASYNC_PF
1155 case MSR_KVM_ASYNC_PF_EN
:
1156 env
->async_pf_en_msr
= msrs
[i
].data
;
1165 static int kvm_put_mp_state(CPUState
*env
)
1167 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
1169 return kvm_vcpu_ioctl(env
, KVM_SET_MP_STATE
, &mp_state
);
1172 static int kvm_get_mp_state(CPUState
*env
)
1174 struct kvm_mp_state mp_state
;
1177 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MP_STATE
, &mp_state
);
1181 env
->mp_state
= mp_state
.mp_state
;
1185 static int kvm_put_vcpu_events(CPUState
*env
, int level
)
1187 #ifdef KVM_CAP_VCPU_EVENTS
1188 struct kvm_vcpu_events events
;
1190 if (!kvm_has_vcpu_events()) {
1194 events
.exception
.injected
= (env
->exception_injected
>= 0);
1195 events
.exception
.nr
= env
->exception_injected
;
1196 events
.exception
.has_error_code
= env
->has_error_code
;
1197 events
.exception
.error_code
= env
->error_code
;
1199 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1200 events
.interrupt
.nr
= env
->interrupt_injected
;
1201 events
.interrupt
.soft
= env
->soft_interrupt
;
1203 events
.nmi
.injected
= env
->nmi_injected
;
1204 events
.nmi
.pending
= env
->nmi_pending
;
1205 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1207 events
.sipi_vector
= env
->sipi_vector
;
1210 if (level
>= KVM_PUT_RESET_STATE
) {
1212 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1215 return kvm_vcpu_ioctl(env
, KVM_SET_VCPU_EVENTS
, &events
);
1221 static int kvm_get_vcpu_events(CPUState
*env
)
1223 #ifdef KVM_CAP_VCPU_EVENTS
1224 struct kvm_vcpu_events events
;
1227 if (!kvm_has_vcpu_events()) {
1231 ret
= kvm_vcpu_ioctl(env
, KVM_GET_VCPU_EVENTS
, &events
);
1235 env
->exception_injected
=
1236 events
.exception
.injected
? events
.exception
.nr
: -1;
1237 env
->has_error_code
= events
.exception
.has_error_code
;
1238 env
->error_code
= events
.exception
.error_code
;
1240 env
->interrupt_injected
=
1241 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1242 env
->soft_interrupt
= events
.interrupt
.soft
;
1244 env
->nmi_injected
= events
.nmi
.injected
;
1245 env
->nmi_pending
= events
.nmi
.pending
;
1246 if (events
.nmi
.masked
) {
1247 env
->hflags2
|= HF2_NMI_MASK
;
1249 env
->hflags2
&= ~HF2_NMI_MASK
;
1252 env
->sipi_vector
= events
.sipi_vector
;
1258 static int kvm_guest_debug_workarounds(CPUState
*env
)
1261 #ifdef KVM_CAP_SET_GUEST_DEBUG
1262 unsigned long reinject_trap
= 0;
1264 if (!kvm_has_vcpu_events()) {
1265 if (env
->exception_injected
== 1) {
1266 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1267 } else if (env
->exception_injected
== 3) {
1268 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1270 env
->exception_injected
= -1;
1274 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1275 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1276 * by updating the debug state once again if single-stepping is on.
1277 * Another reason to call kvm_update_guest_debug here is a pending debug
1278 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1279 * reinject them via SET_GUEST_DEBUG.
1281 if (reinject_trap
||
1282 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
1283 ret
= kvm_update_guest_debug(env
, reinject_trap
);
1285 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1289 static int kvm_put_debugregs(CPUState
*env
)
1291 #ifdef KVM_CAP_DEBUGREGS
1292 struct kvm_debugregs dbgregs
;
1295 if (!kvm_has_debugregs()) {
1299 for (i
= 0; i
< 4; i
++) {
1300 dbgregs
.db
[i
] = env
->dr
[i
];
1302 dbgregs
.dr6
= env
->dr
[6];
1303 dbgregs
.dr7
= env
->dr
[7];
1306 return kvm_vcpu_ioctl(env
, KVM_SET_DEBUGREGS
, &dbgregs
);
1312 static int kvm_get_debugregs(CPUState
*env
)
1314 #ifdef KVM_CAP_DEBUGREGS
1315 struct kvm_debugregs dbgregs
;
1318 if (!kvm_has_debugregs()) {
1322 ret
= kvm_vcpu_ioctl(env
, KVM_GET_DEBUGREGS
, &dbgregs
);
1326 for (i
= 0; i
< 4; i
++) {
1327 env
->dr
[i
] = dbgregs
.db
[i
];
1329 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1330 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1336 int kvm_arch_put_registers(CPUState
*env
, int level
)
1340 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1342 ret
= kvm_getput_regs(env
, 1);
1346 ret
= kvm_put_xsave(env
);
1350 ret
= kvm_put_xcrs(env
);
1354 ret
= kvm_put_sregs(env
);
1358 ret
= kvm_put_msrs(env
, level
);
1362 if (level
>= KVM_PUT_RESET_STATE
) {
1363 ret
= kvm_put_mp_state(env
);
1368 ret
= kvm_put_vcpu_events(env
, level
);
1373 ret
= kvm_guest_debug_workarounds(env
);
1377 ret
= kvm_put_debugregs(env
);
1384 int kvm_arch_get_registers(CPUState
*env
)
1388 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1390 ret
= kvm_getput_regs(env
, 0);
1394 ret
= kvm_get_xsave(env
);
1398 ret
= kvm_get_xcrs(env
);
1402 ret
= kvm_get_sregs(env
);
1406 ret
= kvm_get_msrs(env
);
1410 ret
= kvm_get_mp_state(env
);
1414 ret
= kvm_get_vcpu_events(env
);
1418 ret
= kvm_get_debugregs(env
);
1425 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1428 if (env
->interrupt_request
& CPU_INTERRUPT_NMI
) {
1429 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1430 DPRINTF("injected NMI\n");
1431 kvm_vcpu_ioctl(env
, KVM_NMI
);
1434 /* Try to inject an interrupt if the guest can accept it */
1435 if (run
->ready_for_interrupt_injection
&&
1436 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1437 (env
->eflags
& IF_MASK
)) {
1440 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1441 irq
= cpu_get_pic_interrupt(env
);
1443 struct kvm_interrupt intr
;
1446 DPRINTF("injected interrupt %d\n", irq
);
1447 kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
1451 /* If we have an interrupt but the guest is not ready to receive an
1452 * interrupt, request an interrupt window exit. This will
1453 * cause a return to userspace as soon as the guest is ready to
1454 * receive interrupts. */
1455 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
))
1456 run
->request_interrupt_window
= 1;
1458 run
->request_interrupt_window
= 0;
1460 DPRINTF("setting tpr\n");
1461 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1466 int kvm_arch_post_run(CPUState
*env
, struct kvm_run
*run
)
1469 env
->eflags
|= IF_MASK
;
1471 env
->eflags
&= ~IF_MASK
;
1473 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1474 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1479 int kvm_arch_process_irqchip_events(CPUState
*env
)
1481 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1482 kvm_cpu_synchronize_state(env
);
1484 env
->exception_index
= EXCP_HALTED
;
1487 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1488 kvm_cpu_synchronize_state(env
);
1495 static int kvm_handle_halt(CPUState
*env
)
1497 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1498 (env
->eflags
& IF_MASK
)) &&
1499 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1501 env
->exception_index
= EXCP_HLT
;
1508 int kvm_arch_handle_exit(CPUState
*env
, struct kvm_run
*run
)
1512 switch (run
->exit_reason
) {
1514 DPRINTF("handle_hlt\n");
1515 ret
= kvm_handle_halt(env
);
1522 #ifdef KVM_CAP_SET_GUEST_DEBUG
1523 int kvm_arch_insert_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1525 static const uint8_t int3
= 0xcc;
1527 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1528 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1))
1533 int kvm_arch_remove_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1537 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1538 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1))
1549 static int nb_hw_breakpoint
;
1551 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1555 for (n
= 0; n
< nb_hw_breakpoint
; n
++)
1556 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1557 (hw_breakpoint
[n
].len
== len
|| len
== -1))
1562 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1563 target_ulong len
, int type
)
1566 case GDB_BREAKPOINT_HW
:
1569 case GDB_WATCHPOINT_WRITE
:
1570 case GDB_WATCHPOINT_ACCESS
:
1577 if (addr
& (len
- 1))
1588 if (nb_hw_breakpoint
== 4)
1591 if (find_hw_breakpoint(addr
, len
, type
) >= 0)
1594 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1595 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1596 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1602 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1603 target_ulong len
, int type
)
1607 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1612 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1617 void kvm_arch_remove_all_hw_breakpoints(void)
1619 nb_hw_breakpoint
= 0;
1622 static CPUWatchpoint hw_watchpoint
;
1624 int kvm_arch_debug(struct kvm_debug_exit_arch
*arch_info
)
1629 if (arch_info
->exception
== 1) {
1630 if (arch_info
->dr6
& (1 << 14)) {
1631 if (cpu_single_env
->singlestep_enabled
)
1634 for (n
= 0; n
< 4; n
++)
1635 if (arch_info
->dr6
& (1 << n
))
1636 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1642 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1643 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1644 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1648 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1649 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1650 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1654 } else if (kvm_find_sw_breakpoint(cpu_single_env
, arch_info
->pc
))
1658 cpu_synchronize_state(cpu_single_env
);
1659 assert(cpu_single_env
->exception_injected
== -1);
1661 cpu_single_env
->exception_injected
= arch_info
->exception
;
1662 cpu_single_env
->has_error_code
= 0;
1668 void kvm_arch_update_guest_debug(CPUState
*env
, struct kvm_guest_debug
*dbg
)
1670 const uint8_t type_code
[] = {
1671 [GDB_BREAKPOINT_HW
] = 0x0,
1672 [GDB_WATCHPOINT_WRITE
] = 0x1,
1673 [GDB_WATCHPOINT_ACCESS
] = 0x3
1675 const uint8_t len_code
[] = {
1676 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1680 if (kvm_sw_breakpoints_active(env
))
1681 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1683 if (nb_hw_breakpoint
> 0) {
1684 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1685 dbg
->arch
.debugreg
[7] = 0x0600;
1686 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1687 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
1688 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
1689 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
1690 (len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
1693 /* Legal xcr0 for loading */
1696 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1698 bool kvm_arch_stop_on_emulation_error(CPUState
*env
)
1700 return !(env
->cr
[0] & CR0_PE_MASK
) ||
1701 ((env
->segs
[R_CS
].selector
& 3) != 3);
1704 static void hardware_memory_error(void)
1706 fprintf(stderr
, "Hardware memory error!\n");
1711 static void kvm_mce_broadcast_rest(CPUState
*env
)
1715 /* Broadcast MCA signal for processor version 06H_EH and above */
1716 if (cpu_x86_support_mca_broadcast(env
)) {
1717 for (cenv
= first_cpu
; cenv
!= NULL
; cenv
= cenv
->next_cpu
) {
1721 kvm_inject_x86_mce(cenv
, 1, MCI_STATUS_VAL
| MCI_STATUS_UC
,
1722 MCG_STATUS_MCIP
| MCG_STATUS_RIPV
, 0, 0,
1729 int kvm_on_sigbus_vcpu(CPUState
*env
, int code
, void *addr
)
1731 #if defined(KVM_CAP_MCE)
1732 struct kvm_x86_mce mce
= {
1736 ram_addr_t ram_addr
;
1737 target_phys_addr_t paddr
;
1740 if ((env
->mcg_cap
& MCG_SER_P
) && addr
1741 && (code
== BUS_MCEERR_AR
1742 || code
== BUS_MCEERR_AO
)) {
1743 if (code
== BUS_MCEERR_AR
) {
1744 /* Fake an Intel architectural Data Load SRAR UCR */
1745 mce
.status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1746 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1747 | MCI_STATUS_AR
| 0x134;
1748 mce
.misc
= (MCM_ADDR_PHYS
<< 6) | 0xc;
1749 mce
.mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_EIPV
;
1752 * If there is an MCE excpetion being processed, ignore
1755 r
= kvm_mce_in_exception(env
);
1757 fprintf(stderr
, "Failed to get MCE status\n");
1761 /* Fake an Intel architectural Memory scrubbing UCR */
1762 mce
.status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1763 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1765 mce
.misc
= (MCM_ADDR_PHYS
<< 6) | 0xc;
1766 mce
.mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_RIPV
;
1768 vaddr
= (void *)addr
;
1769 if (qemu_ram_addr_from_host(vaddr
, &ram_addr
) ||
1770 !kvm_physical_memory_addr_from_ram(env
->kvm_state
, ram_addr
, &paddr
)) {
1771 fprintf(stderr
, "Hardware memory error for memory used by "
1772 "QEMU itself instead of guest system!\n");
1773 /* Hope we are lucky for AO MCE */
1774 if (code
== BUS_MCEERR_AO
) {
1777 hardware_memory_error();
1781 r
= kvm_set_mce(env
, &mce
);
1783 fprintf(stderr
, "kvm_set_mce: %s\n", strerror(errno
));
1786 kvm_mce_broadcast_rest(env
);
1790 if (code
== BUS_MCEERR_AO
) {
1792 } else if (code
== BUS_MCEERR_AR
) {
1793 hardware_memory_error();
1801 int kvm_on_sigbus(int code
, void *addr
)
1803 #if defined(KVM_CAP_MCE)
1804 if ((first_cpu
->mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
1807 ram_addr_t ram_addr
;
1808 target_phys_addr_t paddr
;
1810 /* Hope we are lucky for AO MCE */
1812 if (qemu_ram_addr_from_host(vaddr
, &ram_addr
) ||
1813 !kvm_physical_memory_addr_from_ram(first_cpu
->kvm_state
, ram_addr
, &paddr
)) {
1814 fprintf(stderr
, "Hardware memory error for memory used by "
1815 "QEMU itself instead of guest system!: %p\n", addr
);
1818 status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1819 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1821 kvm_inject_x86_mce(first_cpu
, 9, status
,
1822 MCG_STATUS_MCIP
| MCG_STATUS_RIPV
, paddr
,
1823 (MCM_ADDR_PHYS
<< 6) | 0xc, ABORT_ON_ERROR
);
1824 kvm_mce_broadcast_rest(first_cpu
);
1828 if (code
== BUS_MCEERR_AO
) {
1830 } else if (code
== BUS_MCEERR_AR
) {
1831 hardware_memory_error();