target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31 #include "kvm_x86.h"
  32
  33 #ifdef CONFIG_KVM_PARA
  34 #include <linux/kvm_para.h>
  35 #endif
  36 //
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 static int lm_capable_kernel;
  58
  59 #ifdef KVM_CAP_EXT_CPUID
  60
  61 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  62 {
  63     struct kvm_cpuid2 *cpuid;
  64     int r, size;
  65
  66     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  67     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  68     cpuid->nent = max;
  69     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  70     if (r == 0 && cpuid->nent >= max) {
  71         r = -E2BIG;
  72     }
  73     if (r < 0) {
  74         if (r == -E2BIG) {
  75             qemu_free(cpuid);
  76             return NULL;
  77         } else {
  78             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  79                     strerror(-r));
  80             exit(1);
  81         }
  82     }
  83     return cpuid;
  84 }
  85
  86 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  87                                       uint32_t index, int reg)
  88 {
  89     struct kvm_cpuid2 *cpuid;
  90     int i, max;
  91     uint32_t ret = 0;
  92     uint32_t cpuid_1_edx;
  93
  94     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  95         return -1U;
  96     }
  97
  98     max = 1;
  99     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 100         max *= 2;
 101     }
 102
 103     for (i = 0; i < cpuid->nent; ++i) {
 104         if (cpuid->entries[i].function == function &&
 105             cpuid->entries[i].index == index) {
 106             switch (reg) {
 107             case R_EAX:
 108                 ret = cpuid->entries[i].eax;
 109                 break;
 110             case R_EBX:
 111                 ret = cpuid->entries[i].ebx;
 112                 break;
 113             case R_ECX:
 114                 ret = cpuid->entries[i].ecx;
 115                 break;
 116             case R_EDX:
 117                 ret = cpuid->entries[i].edx;
 118                 switch (function) {
 119                 case 1:
 120                     /* KVM before 2.6.30 misreports the following features */
 121                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 122                     break;
 123                 case 0x80000001:
 124                     /* On Intel, kvm returns cpuid according to the Intel spec,
 125                      * so add missing bits according to the AMD spec:
 126                      */
 127                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 128                     ret |= cpuid_1_edx & 0x183f7ff;
 129                     break;
 130                 }
 131                 break;
 132             }
 133         }
 134     }
 135
 136     qemu_free(cpuid);
 137
 138     return ret;
 139 }
 140
 141 #else
 142
 143 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 144                                       uint32_t index, int reg)
 145 {
 146     return -1U;
 147 }
 148
 149 #endif
 150
 151 #ifdef CONFIG_KVM_PARA
 152 struct kvm_para_features {
 153     int cap;
 154     int feature;
 155 } para_features[] = {
 156 #ifdef KVM_CAP_CLOCKSOURCE
 157     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 158 #endif
 159 #ifdef KVM_CAP_NOP_IO_DELAY
 160     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 161 #endif
 162 #ifdef KVM_CAP_PV_MMU
 163     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 164 #endif
 165 #ifdef KVM_CAP_ASYNC_PF
 166     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 167 #endif
 168     { -1, -1 }
 169 };
 170
 171 static int get_para_features(CPUState *env)
 172 {
 173     int i, features = 0;
 174
 175     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 176         if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
 177             features |= (1 << para_features[i].feature);
 178         }
 179     }
 180     return features;
 181 }
 182 #endif
 183
 184 #ifdef KVM_CAP_MCE
 185 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 186                                      int *max_banks)
 187 {
 188     int r;
 189
 190     r = kvm_check_extension(s, KVM_CAP_MCE);
 191     if (r > 0) {
 192         *max_banks = r;
 193         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 194     }
 195     return -ENOSYS;
 196 }
 197
 198 static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
 199 {
 200     return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
 201 }
 202
 203 static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
 204 {
 205     return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
 206 }
 207
 208 static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
 209 {
 210     struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
 211     int r;
 212
 213     kmsrs->nmsrs = n;
 214     memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
 215     r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
 216     memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
 217     free(kmsrs);
 218     return r;
 219 }
 220
 221 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
 222 static int kvm_mce_in_progress(CPUState *env)
 223 {
 224     struct kvm_msr_entry msr_mcg_status = {
 225         .index = MSR_MCG_STATUS,
 226     };
 227     int r;
 228
 229     r = kvm_get_msr(env, &msr_mcg_status, 1);
 230     if (r == -1 || r == 0) {
 231         fprintf(stderr, "Failed to get MCE status\n");
 232         return 0;
 233     }
 234     return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
 235 }
 236
 237 struct kvm_x86_mce_data
 238 {
 239     CPUState *env;
 240     struct kvm_x86_mce *mce;
 241     int abort_on_error;
 242 };
 243
 244 static void kvm_do_inject_x86_mce(void *_data)
 245 {
 246     struct kvm_x86_mce_data *data = _data;
 247     int r;
 248
 249     /* If there is an MCE exception being processed, ignore this SRAO MCE */
 250     if ((data->env->mcg_cap & MCG_SER_P) &&
 251         !(data->mce->status & MCI_STATUS_AR)) {
 252         if (kvm_mce_in_progress(data->env)) {
 253             return;
 254         }
 255     }
 256
 257     r = kvm_set_mce(data->env, data->mce);
 258     if (r < 0) {
 259         perror("kvm_set_mce FAILED");
 260         if (data->abort_on_error) {
 261             abort();
 262         }
 263     }
 264 }
 265
 266 static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce,
 267                                   int flag)
 268 {
 269     struct kvm_x86_mce_data data = {
 270         .env = env,
 271         .mce = mce,
 272         .abort_on_error = (flag & ABORT_ON_ERROR),
 273     };
 274
 275     if (!env->mcg_cap) {
 276         fprintf(stderr, "MCE support is not enabled!\n");
 277         return;
 278     }
 279
 280     run_on_cpu(env, kvm_do_inject_x86_mce, &data);
 281 }
 282
 283 static void kvm_mce_broadcast_rest(CPUState *env);
 284 #endif
 285
 286 void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
 287                         uint64_t mcg_status, uint64_t addr, uint64_t misc,
 288                         int flag)
 289 {
 290 #ifdef KVM_CAP_MCE
 291     struct kvm_x86_mce mce = {
 292         .bank = bank,
 293         .status = status,
 294         .mcg_status = mcg_status,
 295         .addr = addr,
 296         .misc = misc,
 297     };
 298
 299     if (flag & MCE_BROADCAST) {
 300         kvm_mce_broadcast_rest(cenv);
 301     }
 302
 303     kvm_inject_x86_mce_on(cenv, &mce, flag);
 304 #else
 305     if (flag & ABORT_ON_ERROR) {
 306         abort();
 307     }
 308 #endif
 309 }
 310
 311 int kvm_arch_init_vcpu(CPUState *env)
 312 {
 313     struct {
 314         struct kvm_cpuid2 cpuid;
 315         struct kvm_cpuid_entry2 entries[100];
 316     } __attribute__((packed)) cpuid_data;
 317     uint32_t limit, i, j, cpuid_i;
 318     uint32_t unused;
 319     struct kvm_cpuid_entry2 *c;
 320 #ifdef KVM_CPUID_SIGNATURE
 321     uint32_t signature[3];
 322 #endif
 323
 324     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 325
 326     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 327     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 328     env->cpuid_ext_features |= i;
 329
 330     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 331                                                              0, R_EDX);
 332     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 333                                                              0, R_ECX);
 334     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 335                                                              0, R_EDX);
 336
 337
 338     cpuid_i = 0;
 339
 340 #ifdef CONFIG_KVM_PARA
 341     /* Paravirtualization CPUIDs */
 342     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 343     c = &cpuid_data.entries[cpuid_i++];
 344     memset(c, 0, sizeof(*c));
 345     c->function = KVM_CPUID_SIGNATURE;
 346     c->eax = 0;
 347     c->ebx = signature[0];
 348     c->ecx = signature[1];
 349     c->edx = signature[2];
 350
 351     c = &cpuid_data.entries[cpuid_i++];
 352     memset(c, 0, sizeof(*c));
 353     c->function = KVM_CPUID_FEATURES;
 354     c->eax = env->cpuid_kvm_features & get_para_features(env);
 355 #endif
 356
 357     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 358
 359     for (i = 0; i <= limit; i++) {
 360         c = &cpuid_data.entries[cpuid_i++];
 361
 362         switch (i) {
 363         case 2: {
 364             /* Keep reading function 2 till all the input is received */
 365             int times;
 366
 367             c->function = i;
 368             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 369                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 370             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 371             times = c->eax & 0xff;
 372
 373             for (j = 1; j < times; ++j) {
 374                 c = &cpuid_data.entries[cpuid_i++];
 375                 c->function = i;
 376                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 377                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 378             }
 379             break;
 380         }
 381         case 4:
 382         case 0xb:
 383         case 0xd:
 384             for (j = 0; ; j++) {
 385                 c->function = i;
 386                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 387                 c->index = j;
 388                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 389
 390                 if (i == 4 && c->eax == 0) {
 391                     break;
 392                 }
 393                 if (i == 0xb && !(c->ecx & 0xff00)) {
 394                     break;
 395                 }
 396                 if (i == 0xd && c->eax == 0) {
 397                     break;
 398                 }
 399                 c = &cpuid_data.entries[cpuid_i++];
 400             }
 401             break;
 402         default:
 403             c->function = i;
 404             c->flags = 0;
 405             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 406             break;
 407         }
 408     }
 409     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 410
 411     for (i = 0x80000000; i <= limit; i++) {
 412         c = &cpuid_data.entries[cpuid_i++];
 413
 414         c->function = i;
 415         c->flags = 0;
 416         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 417     }
 418
 419     cpuid_data.cpuid.nent = cpuid_i;
 420
 421 #ifdef KVM_CAP_MCE
 422     if (((env->cpuid_version >> 8)&0xF) >= 6
 423         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 424         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 425         uint64_t mcg_cap;
 426         int banks;
 427
 428         if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) {
 429             perror("kvm_get_mce_cap_supported FAILED");
 430         } else {
 431             if (banks > MCE_BANKS_DEF)
 432                 banks = MCE_BANKS_DEF;
 433             mcg_cap &= MCE_CAP_DEF;
 434             mcg_cap |= banks;
 435             if (kvm_setup_mce(env, &mcg_cap)) {
 436                 perror("kvm_setup_mce FAILED");
 437             } else {
 438                 env->mcg_cap = mcg_cap;
 439             }
 440         }
 441     }
 442 #endif
 443
 444     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 445 }
 446
 447 void kvm_arch_reset_vcpu(CPUState *env)
 448 {
 449     env->exception_injected = -1;
 450     env->interrupt_injected = -1;
 451     env->nmi_injected = 0;
 452     env->nmi_pending = 0;
 453     if (kvm_irqchip_in_kernel()) {
 454         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 455                                           KVM_MP_STATE_UNINITIALIZED;
 456     } else {
 457         env->mp_state = KVM_MP_STATE_RUNNABLE;
 458     }
 459 }
 460
 461 int has_msr_star;
 462 int has_msr_hsave_pa;
 463
 464 static void kvm_supported_msrs(CPUState *env)
 465 {
 466     static int kvm_supported_msrs;
 467     int ret;
 468
 469     /* first time */
 470     if (kvm_supported_msrs == 0) {
 471         struct kvm_msr_list msr_list, *kvm_msr_list;
 472
 473         kvm_supported_msrs = -1;
 474
 475         /* Obtain MSR list from KVM.  These are the MSRs that we must
 476          * save/restore */
 477         msr_list.nmsrs = 0;
 478         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 479         if (ret < 0 && ret != -E2BIG) {
 480             return;
 481         }
 482         /* Old kernel modules had a bug and could write beyond the provided
 483            memory. Allocate at least a safe amount of 1K. */
 484         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 485                                               msr_list.nmsrs *
 486                                               sizeof(msr_list.indices[0])));
 487
 488         kvm_msr_list->nmsrs = msr_list.nmsrs;
 489         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 490         if (ret >= 0) {
 491             int i;
 492
 493             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 494                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 495                     has_msr_star = 1;
 496                     continue;
 497                 }
 498                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 499                     has_msr_hsave_pa = 1;
 500                     continue;
 501                 }
 502             }
 503         }
 504
 505         free(kvm_msr_list);
 506     }
 507
 508     return;
 509 }
 510
 511 static int kvm_has_msr_hsave_pa(CPUState *env)
 512 {
 513     kvm_supported_msrs(env);
 514     return has_msr_hsave_pa;
 515 }
 516
 517 static int kvm_has_msr_star(CPUState *env)
 518 {
 519     kvm_supported_msrs(env);
 520     return has_msr_star;
 521 }
 522
 523 static int kvm_init_identity_map_page(KVMState *s)
 524 {
 525 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 526     int ret;
 527     uint64_t addr = 0xfffbc000;
 528
 529     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 530         return 0;
 531     }
 532
 533     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 534     if (ret < 0) {
 535         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 536         return ret;
 537     }
 538 #endif
 539     return 0;
 540 }
 541
 542 int kvm_arch_init(KVMState *s, int smp_cpus)
 543 {
 544     int ret;
 545
 546     struct utsname utsname;
 547
 548     uname(&utsname);
 549     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 550
 551     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 552      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 553      * must be part of guest physical memory, we need to allocate it.  Older
 554      * versions of KVM just assumed that it would be at the end of physical
 555      * memory but that doesn't work with more than 4GB of memory.  We simply
 556      * refuse to work with those older versions of KVM. */
 557     ret = kvm_check_extension(s, KVM_CAP_SET_TSS_ADDR);
 558     if (ret <= 0) {
 559         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 560         return ret;
 561     }
 562
 563     /* this address is 3 pages before the bios, and the bios should present
 564      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 565      * this?
 566      */
 567     /*
 568      * Tell fw_cfg to notify the BIOS to reserve the range.
 569      */
 570     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 571         perror("e820_add_entry() table is full");
 572         exit(1);
 573     }
 574     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 575     if (ret < 0) {
 576         return ret;
 577     }
 578
 579     return kvm_init_identity_map_page(s);
 580 }
 581
 582 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 583 {
 584     lhs->selector = rhs->selector;
 585     lhs->base = rhs->base;
 586     lhs->limit = rhs->limit;
 587     lhs->type = 3;
 588     lhs->present = 1;
 589     lhs->dpl = 3;
 590     lhs->db = 0;
 591     lhs->s = 1;
 592     lhs->l = 0;
 593     lhs->g = 0;
 594     lhs->avl = 0;
 595     lhs->unusable = 0;
 596 }
 597
 598 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 599 {
 600     unsigned flags = rhs->flags;
 601     lhs->selector = rhs->selector;
 602     lhs->base = rhs->base;
 603     lhs->limit = rhs->limit;
 604     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 605     lhs->present = (flags & DESC_P_MASK) != 0;
 606     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 607     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 608     lhs->s = (flags & DESC_S_MASK) != 0;
 609     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 610     lhs->g = (flags & DESC_G_MASK) != 0;
 611     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 612     lhs->unusable = 0;
 613 }
 614
 615 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 616 {
 617     lhs->selector = rhs->selector;
 618     lhs->base = rhs->base;
 619     lhs->limit = rhs->limit;
 620     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 621                  (rhs->present * DESC_P_MASK) |
 622                  (rhs->dpl << DESC_DPL_SHIFT) |
 623                  (rhs->db << DESC_B_SHIFT) |
 624                  (rhs->s * DESC_S_MASK) |
 625                  (rhs->l << DESC_L_SHIFT) |
 626                  (rhs->g * DESC_G_MASK) |
 627                  (rhs->avl * DESC_AVL_MASK);
 628 }
 629
 630 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 631 {
 632     if (set) {
 633         *kvm_reg = *qemu_reg;
 634     } else {
 635         *qemu_reg = *kvm_reg;
 636     }
 637 }
 638
 639 static int kvm_getput_regs(CPUState *env, int set)
 640 {
 641     struct kvm_regs regs;
 642     int ret = 0;
 643
 644     if (!set) {
 645         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 646         if (ret < 0) {
 647             return ret;
 648         }
 649     }
 650
 651     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 652     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 653     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 654     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 655     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 656     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 657     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 658     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 659 #ifdef TARGET_X86_64
 660     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 661     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 662     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 663     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 664     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 665     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 666     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 667     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 668 #endif
 669
 670     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 671     kvm_getput_reg(&regs.rip, &env->eip, set);
 672
 673     if (set) {
 674         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 675     }
 676
 677     return ret;
 678 }
 679
 680 static int kvm_put_fpu(CPUState *env)
 681 {
 682     struct kvm_fpu fpu;
 683     int i;
 684
 685     memset(&fpu, 0, sizeof fpu);
 686     fpu.fsw = env->fpus & ~(7 << 11);
 687     fpu.fsw |= (env->fpstt & 7) << 11;
 688     fpu.fcw = env->fpuc;
 689     for (i = 0; i < 8; ++i) {
 690         fpu.ftwx |= (!env->fptags[i]) << i;
 691     }
 692     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 693     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 694     fpu.mxcsr = env->mxcsr;
 695
 696     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 697 }
 698
 699 #ifdef KVM_CAP_XSAVE
 700 #define XSAVE_CWD_RIP     2
 701 #define XSAVE_CWD_RDP     4
 702 #define XSAVE_MXCSR       6
 703 #define XSAVE_ST_SPACE    8
 704 #define XSAVE_XMM_SPACE   40
 705 #define XSAVE_XSTATE_BV   128
 706 #define XSAVE_YMMH_SPACE  144
 707 #endif
 708
 709 static int kvm_put_xsave(CPUState *env)
 710 {
 711 #ifdef KVM_CAP_XSAVE
 712     int i, r;
 713     struct kvm_xsave* xsave;
 714     uint16_t cwd, swd, twd, fop;
 715
 716     if (!kvm_has_xsave()) {
 717         return kvm_put_fpu(env);
 718     }
 719
 720     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 721     memset(xsave, 0, sizeof(struct kvm_xsave));
 722     cwd = swd = twd = fop = 0;
 723     swd = env->fpus & ~(7 << 11);
 724     swd |= (env->fpstt & 7) << 11;
 725     cwd = env->fpuc;
 726     for (i = 0; i < 8; ++i) {
 727         twd |= (!env->fptags[i]) << i;
 728     }
 729     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 730     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 731     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 732             sizeof env->fpregs);
 733     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 734             sizeof env->xmm_regs);
 735     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 736     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 737     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 738             sizeof env->ymmh_regs);
 739     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 740     qemu_free(xsave);
 741     return r;
 742 #else
 743     return kvm_put_fpu(env);
 744 #endif
 745 }
 746
 747 static int kvm_put_xcrs(CPUState *env)
 748 {
 749 #ifdef KVM_CAP_XCRS
 750     struct kvm_xcrs xcrs;
 751
 752     if (!kvm_has_xcrs()) {
 753         return 0;
 754     }
 755
 756     xcrs.nr_xcrs = 1;
 757     xcrs.flags = 0;
 758     xcrs.xcrs[0].xcr = 0;
 759     xcrs.xcrs[0].value = env->xcr0;
 760     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 761 #else
 762     return 0;
 763 #endif
 764 }
 765
 766 static int kvm_put_sregs(CPUState *env)
 767 {
 768     struct kvm_sregs sregs;
 769
 770     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 771     if (env->interrupt_injected >= 0) {
 772         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 773                 (uint64_t)1 << (env->interrupt_injected % 64);
 774     }
 775
 776     if ((env->eflags & VM_MASK)) {
 777         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 778         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 779         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 780         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 781         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 782         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 783     } else {
 784         set_seg(&sregs.cs, &env->segs[R_CS]);
 785         set_seg(&sregs.ds, &env->segs[R_DS]);
 786         set_seg(&sregs.es, &env->segs[R_ES]);
 787         set_seg(&sregs.fs, &env->segs[R_FS]);
 788         set_seg(&sregs.gs, &env->segs[R_GS]);
 789         set_seg(&sregs.ss, &env->segs[R_SS]);
 790     }
 791
 792     set_seg(&sregs.tr, &env->tr);
 793     set_seg(&sregs.ldt, &env->ldt);
 794
 795     sregs.idt.limit = env->idt.limit;
 796     sregs.idt.base = env->idt.base;
 797     sregs.gdt.limit = env->gdt.limit;
 798     sregs.gdt.base = env->gdt.base;
 799
 800     sregs.cr0 = env->cr[0];
 801     sregs.cr2 = env->cr[2];
 802     sregs.cr3 = env->cr[3];
 803     sregs.cr4 = env->cr[4];
 804
 805     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 806     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 807
 808     sregs.efer = env->efer;
 809
 810     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 811 }
 812
 813 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 814                               uint32_t index, uint64_t value)
 815 {
 816     entry->index = index;
 817     entry->data = value;
 818 }
 819
 820 static int kvm_put_msrs(CPUState *env, int level)
 821 {
 822     struct {
 823         struct kvm_msrs info;
 824         struct kvm_msr_entry entries[100];
 825     } msr_data;
 826     struct kvm_msr_entry *msrs = msr_data.entries;
 827     int n = 0;
 828
 829     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 830     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 831     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 832     if (kvm_has_msr_star(env)) {
 833         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 834     }
 835     if (kvm_has_msr_hsave_pa(env)) {
 836         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 837     }
 838 #ifdef TARGET_X86_64
 839     if (lm_capable_kernel) {
 840         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 841         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 842         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 843         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 844     }
 845 #endif
 846     if (level == KVM_PUT_FULL_STATE) {
 847         /*
 848          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 849          * writeback. Until this is fixed, we only write the offset to SMP
 850          * guests after migration, desynchronizing the VCPUs, but avoiding
 851          * huge jump-backs that would occur without any writeback at all.
 852          */
 853         if (smp_cpus == 1 || env->tsc != 0) {
 854             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 855         }
 856         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 857                           env->system_time_msr);
 858         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 859 #ifdef KVM_CAP_ASYNC_PF
 860         kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
 861 #endif
 862     }
 863 #ifdef KVM_CAP_MCE
 864     if (env->mcg_cap) {
 865         int i;
 866
 867         if (level == KVM_PUT_RESET_STATE) {
 868             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 869         } else if (level == KVM_PUT_FULL_STATE) {
 870             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 871             kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 872             for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 873                 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 874             }
 875         }
 876     }
 877 #endif
 878
 879     msr_data.info.nmsrs = n;
 880
 881     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 882
 883 }
 884
 885
 886 static int kvm_get_fpu(CPUState *env)
 887 {
 888     struct kvm_fpu fpu;
 889     int i, ret;
 890
 891     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 892     if (ret < 0) {
 893         return ret;
 894     }
 895
 896     env->fpstt = (fpu.fsw >> 11) & 7;
 897     env->fpus = fpu.fsw;
 898     env->fpuc = fpu.fcw;
 899     for (i = 0; i < 8; ++i) {
 900         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 901     }
 902     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 903     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 904     env->mxcsr = fpu.mxcsr;
 905
 906     return 0;
 907 }
 908
 909 static int kvm_get_xsave(CPUState *env)
 910 {
 911 #ifdef KVM_CAP_XSAVE
 912     struct kvm_xsave* xsave;
 913     int ret, i;
 914     uint16_t cwd, swd, twd, fop;
 915
 916     if (!kvm_has_xsave()) {
 917         return kvm_get_fpu(env);
 918     }
 919
 920     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 921     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 922     if (ret < 0) {
 923         qemu_free(xsave);
 924         return ret;
 925     }
 926
 927     cwd = (uint16_t)xsave->region[0];
 928     swd = (uint16_t)(xsave->region[0] >> 16);
 929     twd = (uint16_t)xsave->region[1];
 930     fop = (uint16_t)(xsave->region[1] >> 16);
 931     env->fpstt = (swd >> 11) & 7;
 932     env->fpus = swd;
 933     env->fpuc = cwd;
 934     for (i = 0; i < 8; ++i) {
 935         env->fptags[i] = !((twd >> i) & 1);
 936     }
 937     env->mxcsr = xsave->region[XSAVE_MXCSR];
 938     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 939             sizeof env->fpregs);
 940     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 941             sizeof env->xmm_regs);
 942     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 943     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 944             sizeof env->ymmh_regs);
 945     qemu_free(xsave);
 946     return 0;
 947 #else
 948     return kvm_get_fpu(env);
 949 #endif
 950 }
 951
 952 static int kvm_get_xcrs(CPUState *env)
 953 {
 954 #ifdef KVM_CAP_XCRS
 955     int i, ret;
 956     struct kvm_xcrs xcrs;
 957
 958     if (!kvm_has_xcrs()) {
 959         return 0;
 960     }
 961
 962     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 963     if (ret < 0) {
 964         return ret;
 965     }
 966
 967     for (i = 0; i < xcrs.nr_xcrs; i++) {
 968         /* Only support xcr0 now */
 969         if (xcrs.xcrs[0].xcr == 0) {
 970             env->xcr0 = xcrs.xcrs[0].value;
 971             break;
 972         }
 973     }
 974     return 0;
 975 #else
 976     return 0;
 977 #endif
 978 }
 979
 980 static int kvm_get_sregs(CPUState *env)
 981 {
 982     struct kvm_sregs sregs;
 983     uint32_t hflags;
 984     int bit, i, ret;
 985
 986     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 987     if (ret < 0) {
 988         return ret;
 989     }
 990
 991     /* There can only be one pending IRQ set in the bitmap at a time, so try
 992        to find it and save its number instead (-1 for none). */
 993     env->interrupt_injected = -1;
 994     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 995         if (sregs.interrupt_bitmap[i]) {
 996             bit = ctz64(sregs.interrupt_bitmap[i]);
 997             env->interrupt_injected = i * 64 + bit;
 998             break;
 999         }
1000     }
1001
1002     get_seg(&env->segs[R_CS], &sregs.cs);
1003     get_seg(&env->segs[R_DS], &sregs.ds);
1004     get_seg(&env->segs[R_ES], &sregs.es);
1005     get_seg(&env->segs[R_FS], &sregs.fs);
1006     get_seg(&env->segs[R_GS], &sregs.gs);
1007     get_seg(&env->segs[R_SS], &sregs.ss);
1008
1009     get_seg(&env->tr, &sregs.tr);
1010     get_seg(&env->ldt, &sregs.ldt);
1011
1012     env->idt.limit = sregs.idt.limit;
1013     env->idt.base = sregs.idt.base;
1014     env->gdt.limit = sregs.gdt.limit;
1015     env->gdt.base = sregs.gdt.base;
1016
1017     env->cr[0] = sregs.cr0;
1018     env->cr[2] = sregs.cr2;
1019     env->cr[3] = sregs.cr3;
1020     env->cr[4] = sregs.cr4;
1021
1022     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1023
1024     env->efer = sregs.efer;
1025     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1026
1027 #define HFLAG_COPY_MASK \
1028     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1029        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1030        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1031        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1032
1033     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1034     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1035     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1036                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1037     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1038     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1039                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1040
1041     if (env->efer & MSR_EFER_LMA) {
1042         hflags |= HF_LMA_MASK;
1043     }
1044
1045     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1046         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1047     } else {
1048         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1049                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1050         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1051                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1052         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1053             !(hflags & HF_CS32_MASK)) {
1054             hflags |= HF_ADDSEG_MASK;
1055         } else {
1056             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1057                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1058         }
1059     }
1060     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1061
1062     return 0;
1063 }
1064
1065 static int kvm_get_msrs(CPUState *env)
1066 {
1067     struct {
1068         struct kvm_msrs info;
1069         struct kvm_msr_entry entries[100];
1070     } msr_data;
1071     struct kvm_msr_entry *msrs = msr_data.entries;
1072     int ret, i, n;
1073
1074     n = 0;
1075     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1076     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1077     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1078     if (kvm_has_msr_star(env)) {
1079         msrs[n++].index = MSR_STAR;
1080     }
1081     if (kvm_has_msr_hsave_pa(env)) {
1082         msrs[n++].index = MSR_VM_HSAVE_PA;
1083     }
1084     msrs[n++].index = MSR_IA32_TSC;
1085 #ifdef TARGET_X86_64
1086     if (lm_capable_kernel) {
1087         msrs[n++].index = MSR_CSTAR;
1088         msrs[n++].index = MSR_KERNELGSBASE;
1089         msrs[n++].index = MSR_FMASK;
1090         msrs[n++].index = MSR_LSTAR;
1091     }
1092 #endif
1093     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1094     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1095 #ifdef KVM_CAP_ASYNC_PF
1096     msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1097 #endif
1098
1099 #ifdef KVM_CAP_MCE
1100     if (env->mcg_cap) {
1101         msrs[n++].index = MSR_MCG_STATUS;
1102         msrs[n++].index = MSR_MCG_CTL;
1103         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1104             msrs[n++].index = MSR_MC0_CTL + i;
1105         }
1106     }
1107 #endif
1108
1109     msr_data.info.nmsrs = n;
1110     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1111     if (ret < 0) {
1112         return ret;
1113     }
1114
1115     for (i = 0; i < ret; i++) {
1116         switch (msrs[i].index) {
1117         case MSR_IA32_SYSENTER_CS:
1118             env->sysenter_cs = msrs[i].data;
1119             break;
1120         case MSR_IA32_SYSENTER_ESP:
1121             env->sysenter_esp = msrs[i].data;
1122             break;
1123         case MSR_IA32_SYSENTER_EIP:
1124             env->sysenter_eip = msrs[i].data;
1125             break;
1126         case MSR_STAR:
1127             env->star = msrs[i].data;
1128             break;
1129 #ifdef TARGET_X86_64
1130         case MSR_CSTAR:
1131             env->cstar = msrs[i].data;
1132             break;
1133         case MSR_KERNELGSBASE:
1134             env->kernelgsbase = msrs[i].data;
1135             break;
1136         case MSR_FMASK:
1137             env->fmask = msrs[i].data;
1138             break;
1139         case MSR_LSTAR:
1140             env->lstar = msrs[i].data;
1141             break;
1142 #endif
1143         case MSR_IA32_TSC:
1144             env->tsc = msrs[i].data;
1145             break;
1146         case MSR_VM_HSAVE_PA:
1147             env->vm_hsave = msrs[i].data;
1148             break;
1149         case MSR_KVM_SYSTEM_TIME:
1150             env->system_time_msr = msrs[i].data;
1151             break;
1152         case MSR_KVM_WALL_CLOCK:
1153             env->wall_clock_msr = msrs[i].data;
1154             break;
1155 #ifdef KVM_CAP_MCE
1156         case MSR_MCG_STATUS:
1157             env->mcg_status = msrs[i].data;
1158             break;
1159         case MSR_MCG_CTL:
1160             env->mcg_ctl = msrs[i].data;
1161             break;
1162 #endif
1163         default:
1164 #ifdef KVM_CAP_MCE
1165             if (msrs[i].index >= MSR_MC0_CTL &&
1166                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1167                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1168             }
1169 #endif
1170             break;
1171 #ifdef KVM_CAP_ASYNC_PF
1172         case MSR_KVM_ASYNC_PF_EN:
1173             env->async_pf_en_msr = msrs[i].data;
1174             break;
1175 #endif
1176         }
1177     }
1178
1179     return 0;
1180 }
1181
1182 static int kvm_put_mp_state(CPUState *env)
1183 {
1184     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1185
1186     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1187 }
1188
1189 static int kvm_get_mp_state(CPUState *env)
1190 {
1191     struct kvm_mp_state mp_state;
1192     int ret;
1193
1194     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1195     if (ret < 0) {
1196         return ret;
1197     }
1198     env->mp_state = mp_state.mp_state;
1199     if (kvm_irqchip_in_kernel()) {
1200         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1201     }
1202     return 0;
1203 }
1204
1205 static int kvm_put_vcpu_events(CPUState *env, int level)
1206 {
1207 #ifdef KVM_CAP_VCPU_EVENTS
1208     struct kvm_vcpu_events events;
1209
1210     if (!kvm_has_vcpu_events()) {
1211         return 0;
1212     }
1213
1214     events.exception.injected = (env->exception_injected >= 0);
1215     events.exception.nr = env->exception_injected;
1216     events.exception.has_error_code = env->has_error_code;
1217     events.exception.error_code = env->error_code;
1218
1219     events.interrupt.injected = (env->interrupt_injected >= 0);
1220     events.interrupt.nr = env->interrupt_injected;
1221     events.interrupt.soft = env->soft_interrupt;
1222
1223     events.nmi.injected = env->nmi_injected;
1224     events.nmi.pending = env->nmi_pending;
1225     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1226
1227     events.sipi_vector = env->sipi_vector;
1228
1229     events.flags = 0;
1230     if (level >= KVM_PUT_RESET_STATE) {
1231         events.flags |=
1232             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1233     }
1234
1235     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1236 #else
1237     return 0;
1238 #endif
1239 }
1240
1241 static int kvm_get_vcpu_events(CPUState *env)
1242 {
1243 #ifdef KVM_CAP_VCPU_EVENTS
1244     struct kvm_vcpu_events events;
1245     int ret;
1246
1247     if (!kvm_has_vcpu_events()) {
1248         return 0;
1249     }
1250
1251     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1252     if (ret < 0) {
1253        return ret;
1254     }
1255     env->exception_injected =
1256        events.exception.injected ? events.exception.nr : -1;
1257     env->has_error_code = events.exception.has_error_code;
1258     env->error_code = events.exception.error_code;
1259
1260     env->interrupt_injected =
1261         events.interrupt.injected ? events.interrupt.nr : -1;
1262     env->soft_interrupt = events.interrupt.soft;
1263
1264     env->nmi_injected = events.nmi.injected;
1265     env->nmi_pending = events.nmi.pending;
1266     if (events.nmi.masked) {
1267         env->hflags2 |= HF2_NMI_MASK;
1268     } else {
1269         env->hflags2 &= ~HF2_NMI_MASK;
1270     }
1271
1272     env->sipi_vector = events.sipi_vector;
1273 #endif
1274
1275     return 0;
1276 }
1277
1278 static int kvm_guest_debug_workarounds(CPUState *env)
1279 {
1280     int ret = 0;
1281 #ifdef KVM_CAP_SET_GUEST_DEBUG
1282     unsigned long reinject_trap = 0;
1283
1284     if (!kvm_has_vcpu_events()) {
1285         if (env->exception_injected == 1) {
1286             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1287         } else if (env->exception_injected == 3) {
1288             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1289         }
1290         env->exception_injected = -1;
1291     }
1292
1293     /*
1294      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1295      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1296      * by updating the debug state once again if single-stepping is on.
1297      * Another reason to call kvm_update_guest_debug here is a pending debug
1298      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1299      * reinject them via SET_GUEST_DEBUG.
1300      */
1301     if (reinject_trap ||
1302         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1303         ret = kvm_update_guest_debug(env, reinject_trap);
1304     }
1305 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1306     return ret;
1307 }
1308
1309 static int kvm_put_debugregs(CPUState *env)
1310 {
1311 #ifdef KVM_CAP_DEBUGREGS
1312     struct kvm_debugregs dbgregs;
1313     int i;
1314
1315     if (!kvm_has_debugregs()) {
1316         return 0;
1317     }
1318
1319     for (i = 0; i < 4; i++) {
1320         dbgregs.db[i] = env->dr[i];
1321     }
1322     dbgregs.dr6 = env->dr[6];
1323     dbgregs.dr7 = env->dr[7];
1324     dbgregs.flags = 0;
1325
1326     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1327 #else
1328     return 0;
1329 #endif
1330 }
1331
1332 static int kvm_get_debugregs(CPUState *env)
1333 {
1334 #ifdef KVM_CAP_DEBUGREGS
1335     struct kvm_debugregs dbgregs;
1336     int i, ret;
1337
1338     if (!kvm_has_debugregs()) {
1339         return 0;
1340     }
1341
1342     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1343     if (ret < 0) {
1344         return ret;
1345     }
1346     for (i = 0; i < 4; i++) {
1347         env->dr[i] = dbgregs.db[i];
1348     }
1349     env->dr[4] = env->dr[6] = dbgregs.dr6;
1350     env->dr[5] = env->dr[7] = dbgregs.dr7;
1351 #endif
1352
1353     return 0;
1354 }
1355
1356 int kvm_arch_put_registers(CPUState *env, int level)
1357 {
1358     int ret;
1359
1360     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1361
1362     ret = kvm_getput_regs(env, 1);
1363     if (ret < 0) {
1364         return ret;
1365     }
1366     ret = kvm_put_xsave(env);
1367     if (ret < 0) {
1368         return ret;
1369     }
1370     ret = kvm_put_xcrs(env);
1371     if (ret < 0) {
1372         return ret;
1373     }
1374     ret = kvm_put_sregs(env);
1375     if (ret < 0) {
1376         return ret;
1377     }
1378     ret = kvm_put_msrs(env, level);
1379     if (ret < 0) {
1380         return ret;
1381     }
1382     if (level >= KVM_PUT_RESET_STATE) {
1383         ret = kvm_put_mp_state(env);
1384         if (ret < 0) {
1385             return ret;
1386         }
1387     }
1388     ret = kvm_put_vcpu_events(env, level);
1389     if (ret < 0) {
1390         return ret;
1391     }
1392     ret = kvm_put_debugregs(env);
1393     if (ret < 0) {
1394         return ret;
1395     }
1396     /* must be last */
1397     ret = kvm_guest_debug_workarounds(env);
1398     if (ret < 0) {
1399         return ret;
1400     }
1401     return 0;
1402 }
1403
1404 int kvm_arch_get_registers(CPUState *env)
1405 {
1406     int ret;
1407
1408     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1409
1410     ret = kvm_getput_regs(env, 0);
1411     if (ret < 0) {
1412         return ret;
1413     }
1414     ret = kvm_get_xsave(env);
1415     if (ret < 0) {
1416         return ret;
1417     }
1418     ret = kvm_get_xcrs(env);
1419     if (ret < 0) {
1420         return ret;
1421     }
1422     ret = kvm_get_sregs(env);
1423     if (ret < 0) {
1424         return ret;
1425     }
1426     ret = kvm_get_msrs(env);
1427     if (ret < 0) {
1428         return ret;
1429     }
1430     ret = kvm_get_mp_state(env);
1431     if (ret < 0) {
1432         return ret;
1433     }
1434     ret = kvm_get_vcpu_events(env);
1435     if (ret < 0) {
1436         return ret;
1437     }
1438     ret = kvm_get_debugregs(env);
1439     if (ret < 0) {
1440         return ret;
1441     }
1442     return 0;
1443 }
1444
1445 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1446 {
1447     /* Inject NMI */
1448     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1449         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1450         DPRINTF("injected NMI\n");
1451         kvm_vcpu_ioctl(env, KVM_NMI);
1452     }
1453
1454     /* Try to inject an interrupt if the guest can accept it */
1455     if (run->ready_for_interrupt_injection &&
1456         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1457         (env->eflags & IF_MASK)) {
1458         int irq;
1459
1460         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1461         irq = cpu_get_pic_interrupt(env);
1462         if (irq >= 0) {
1463             struct kvm_interrupt intr;
1464             intr.irq = irq;
1465             /* FIXME: errors */
1466             DPRINTF("injected interrupt %d\n", irq);
1467             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1468         }
1469     }
1470
1471     /* If we have an interrupt but the guest is not ready to receive an
1472      * interrupt, request an interrupt window exit.  This will
1473      * cause a return to userspace as soon as the guest is ready to
1474      * receive interrupts. */
1475     if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1476         run->request_interrupt_window = 1;
1477     } else {
1478         run->request_interrupt_window = 0;
1479     }
1480
1481     DPRINTF("setting tpr\n");
1482     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1483
1484     return 0;
1485 }
1486
1487 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1488 {
1489     if (run->if_flag) {
1490         env->eflags |= IF_MASK;
1491     } else {
1492         env->eflags &= ~IF_MASK;
1493     }
1494     cpu_set_apic_tpr(env->apic_state, run->cr8);
1495     cpu_set_apic_base(env->apic_state, run->apic_base);
1496
1497     return 0;
1498 }
1499
1500 int kvm_arch_process_irqchip_events(CPUState *env)
1501 {
1502     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1503         kvm_cpu_synchronize_state(env);
1504         do_cpu_init(env);
1505         env->exception_index = EXCP_HALTED;
1506     }
1507
1508     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1509         kvm_cpu_synchronize_state(env);
1510         do_cpu_sipi(env);
1511     }
1512
1513     return env->halted;
1514 }
1515
1516 static int kvm_handle_halt(CPUState *env)
1517 {
1518     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1519           (env->eflags & IF_MASK)) &&
1520         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1521         env->halted = 1;
1522         env->exception_index = EXCP_HLT;
1523         return 0;
1524     }
1525
1526     return 1;
1527 }
1528
1529 static bool host_supports_vmx(void)
1530 {
1531     uint32_t ecx, unused;
1532
1533     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1534     return ecx & CPUID_EXT_VMX;
1535 }
1536
1537 #define VMX_INVALID_GUEST_STATE 0x80000021
1538
1539 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1540 {
1541     uint64_t code;
1542     int ret = 0;
1543
1544     switch (run->exit_reason) {
1545     case KVM_EXIT_HLT:
1546         DPRINTF("handle_hlt\n");
1547         ret = kvm_handle_halt(env);
1548         break;
1549     case KVM_EXIT_SET_TPR:
1550         ret = 1;
1551         break;
1552     case KVM_EXIT_FAIL_ENTRY:
1553         code = run->fail_entry.hardware_entry_failure_reason;
1554         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1555                 code);
1556         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1557             fprintf(stderr,
1558                     "\nIf you're runnning a guest on an Intel machine without "
1559                         "unrestricted mode\n"
1560                     "support, the failure can be most likely due to the guest "
1561                         "entering an invalid\n"
1562                     "state for Intel VT. For example, the guest maybe running "
1563                         "in big real mode\n"
1564                     "which is not supported on less recent Intel processors."
1565                         "\n\n");
1566         }
1567         ret = -1;
1568         break;
1569     case KVM_EXIT_EXCEPTION:
1570         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1571                 run->ex.exception, run->ex.error_code);
1572         ret = -1;
1573         break;
1574     default:
1575         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1576         ret = -1;
1577         break;
1578     }
1579
1580     return ret;
1581 }
1582
1583 #ifdef KVM_CAP_SET_GUEST_DEBUG
1584 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1585 {
1586     static const uint8_t int3 = 0xcc;
1587
1588     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1589         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1590         return -EINVAL;
1591     }
1592     return 0;
1593 }
1594
1595 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1596 {
1597     uint8_t int3;
1598
1599     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1600         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1601         return -EINVAL;
1602     }
1603     return 0;
1604 }
1605
1606 static struct {
1607     target_ulong addr;
1608     int len;
1609     int type;
1610 } hw_breakpoint[4];
1611
1612 static int nb_hw_breakpoint;
1613
1614 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1615 {
1616     int n;
1617
1618     for (n = 0; n < nb_hw_breakpoint; n++) {
1619         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1620             (hw_breakpoint[n].len == len || len == -1)) {
1621             return n;
1622         }
1623     }
1624     return -1;
1625 }
1626
1627 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1628                                   target_ulong len, int type)
1629 {
1630     switch (type) {
1631     case GDB_BREAKPOINT_HW:
1632         len = 1;
1633         break;
1634     case GDB_WATCHPOINT_WRITE:
1635     case GDB_WATCHPOINT_ACCESS:
1636         switch (len) {
1637         case 1:
1638             break;
1639         case 2:
1640         case 4:
1641         case 8:
1642             if (addr & (len - 1)) {
1643                 return -EINVAL;
1644             }
1645             break;
1646         default:
1647             return -EINVAL;
1648         }
1649         break;
1650     default:
1651         return -ENOSYS;
1652     }
1653
1654     if (nb_hw_breakpoint == 4) {
1655         return -ENOBUFS;
1656     }
1657     if (find_hw_breakpoint(addr, len, type) >= 0) {
1658         return -EEXIST;
1659     }
1660     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1661     hw_breakpoint[nb_hw_breakpoint].len = len;
1662     hw_breakpoint[nb_hw_breakpoint].type = type;
1663     nb_hw_breakpoint++;
1664
1665     return 0;
1666 }
1667
1668 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1669                                   target_ulong len, int type)
1670 {
1671     int n;
1672
1673     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1674     if (n < 0) {
1675         return -ENOENT;
1676     }
1677     nb_hw_breakpoint--;
1678     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1679
1680     return 0;
1681 }
1682
1683 void kvm_arch_remove_all_hw_breakpoints(void)
1684 {
1685     nb_hw_breakpoint = 0;
1686 }
1687
1688 static CPUWatchpoint hw_watchpoint;
1689
1690 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1691 {
1692     int handle = 0;
1693     int n;
1694
1695     if (arch_info->exception == 1) {
1696         if (arch_info->dr6 & (1 << 14)) {
1697             if (cpu_single_env->singlestep_enabled) {
1698                 handle = 1;
1699             }
1700         } else {
1701             for (n = 0; n < 4; n++) {
1702                 if (arch_info->dr6 & (1 << n)) {
1703                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1704                     case 0x0:
1705                         handle = 1;
1706                         break;
1707                     case 0x1:
1708                         handle = 1;
1709                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1710                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1711                         hw_watchpoint.flags = BP_MEM_WRITE;
1712                         break;
1713                     case 0x3:
1714                         handle = 1;
1715                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1716                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1717                         hw_watchpoint.flags = BP_MEM_ACCESS;
1718                         break;
1719                     }
1720                 }
1721             }
1722         }
1723     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1724         handle = 1;
1725     }
1726     if (!handle) {
1727         cpu_synchronize_state(cpu_single_env);
1728         assert(cpu_single_env->exception_injected == -1);
1729
1730         cpu_single_env->exception_injected = arch_info->exception;
1731         cpu_single_env->has_error_code = 0;
1732     }
1733
1734     return handle;
1735 }
1736
1737 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1738 {
1739     const uint8_t type_code[] = {
1740         [GDB_BREAKPOINT_HW] = 0x0,
1741         [GDB_WATCHPOINT_WRITE] = 0x1,
1742         [GDB_WATCHPOINT_ACCESS] = 0x3
1743     };
1744     const uint8_t len_code[] = {
1745         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1746     };
1747     int n;
1748
1749     if (kvm_sw_breakpoints_active(env)) {
1750         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1751     }
1752     if (nb_hw_breakpoint > 0) {
1753         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1754         dbg->arch.debugreg[7] = 0x0600;
1755         for (n = 0; n < nb_hw_breakpoint; n++) {
1756             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1757             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1758                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1759                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1760         }
1761     }
1762     /* Legal xcr0 for loading */
1763     env->xcr0 = 1;
1764 }
1765 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1766
1767 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1768 {
1769     return !(env->cr[0] & CR0_PE_MASK) ||
1770            ((env->segs[R_CS].selector  & 3) != 3);
1771 }
1772
1773 static void hardware_memory_error(void)
1774 {
1775     fprintf(stderr, "Hardware memory error!\n");
1776     exit(1);
1777 }
1778
1779 #ifdef KVM_CAP_MCE
1780 static void kvm_mce_broadcast_rest(CPUState *env)
1781 {
1782     struct kvm_x86_mce mce = {
1783         .bank = 1,
1784         .status = MCI_STATUS_VAL | MCI_STATUS_UC,
1785         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1786         .addr = 0,
1787         .misc = 0,
1788     };
1789     CPUState *cenv;
1790
1791     /* Broadcast MCA signal for processor version 06H_EH and above */
1792     if (cpu_x86_support_mca_broadcast(env)) {
1793         for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1794             if (cenv == env) {
1795                 continue;
1796             }
1797             kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR);
1798         }
1799     }
1800 }
1801
1802 static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr)
1803 {
1804     struct kvm_x86_mce mce = {
1805         .bank = 9,
1806         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1807                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1808                   | MCI_STATUS_AR | 0x134,
1809         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV,
1810         .addr = paddr,
1811         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1812     };
1813     int r;
1814
1815     r = kvm_set_mce(env, &mce);
1816     if (r < 0) {
1817         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1818         abort();
1819     }
1820     kvm_mce_broadcast_rest(env);
1821 }
1822
1823 static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr)
1824 {
1825     struct kvm_x86_mce mce = {
1826         .bank = 9,
1827         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1828                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1829                   | 0xc0,
1830         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1831         .addr = paddr,
1832         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1833     };
1834     int r;
1835
1836     r = kvm_set_mce(env, &mce);
1837     if (r < 0) {
1838         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1839         abort();
1840     }
1841     kvm_mce_broadcast_rest(env);
1842 }
1843
1844 static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr)
1845 {
1846     struct kvm_x86_mce mce = {
1847         .bank = 9,
1848         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1849                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1850                   | 0xc0,
1851         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1852         .addr = paddr,
1853         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1854     };
1855
1856     kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR);
1857     kvm_mce_broadcast_rest(env);
1858 }
1859
1860 #endif
1861
1862 int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1863 {
1864 #if defined(KVM_CAP_MCE)
1865     void *vaddr;
1866     ram_addr_t ram_addr;
1867     target_phys_addr_t paddr;
1868
1869     if ((env->mcg_cap & MCG_SER_P) && addr
1870         && (code == BUS_MCEERR_AR
1871             || code == BUS_MCEERR_AO)) {
1872         vaddr = (void *)addr;
1873         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1874             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1875             fprintf(stderr, "Hardware memory error for memory used by "
1876                     "QEMU itself instead of guest system!\n");
1877             /* Hope we are lucky for AO MCE */
1878             if (code == BUS_MCEERR_AO) {
1879                 return 0;
1880             } else {
1881                 hardware_memory_error();
1882             }
1883         }
1884
1885         if (code == BUS_MCEERR_AR) {
1886             /* Fake an Intel architectural Data Load SRAR UCR */
1887             kvm_mce_inj_srar_dataload(env, paddr);
1888         } else {
1889             /*
1890              * If there is an MCE excpetion being processed, ignore
1891              * this SRAO MCE
1892              */
1893             if (!kvm_mce_in_progress(env)) {
1894                 /* Fake an Intel architectural Memory scrubbing UCR */
1895                 kvm_mce_inj_srao_memscrub(env, paddr);
1896             }
1897         }
1898     } else
1899 #endif
1900     {
1901         if (code == BUS_MCEERR_AO) {
1902             return 0;
1903         } else if (code == BUS_MCEERR_AR) {
1904             hardware_memory_error();
1905         } else {
1906             return 1;
1907         }
1908     }
1909     return 0;
1910 }
1911
1912 int kvm_on_sigbus(int code, void *addr)
1913 {
1914 #if defined(KVM_CAP_MCE)
1915     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1916         void *vaddr;
1917         ram_addr_t ram_addr;
1918         target_phys_addr_t paddr;
1919
1920         /* Hope we are lucky for AO MCE */
1921         vaddr = addr;
1922         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1923             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1924             fprintf(stderr, "Hardware memory error for memory used by "
1925                     "QEMU itself instead of guest system!: %p\n", addr);
1926             return 0;
1927         }
1928         kvm_mce_inj_srao_memscrub2(first_cpu, paddr);
1929     } else
1930 #endif
1931     {
1932         if (code == BUS_MCEERR_AO) {
1933             return 0;
1934         } else if (code == BUS_MCEERR_AR) {
1935             hardware_memory_error();
1936         } else {
1937             return 1;
1938         }
1939     }
1940     return 0;
1941 }