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kvm: make hyperv vapic assist page migratable
[mirror_qemu.git] / target-i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "exec/ioport.h"
34 #include <asm/hyperv.h>
35 #include "hw/pci/pci.h"
36
37 //#define DEBUG_KVM
38
39 #ifdef DEBUG_KVM
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42 #else
43 #define DPRINTF(fmt, ...) \
44 do { } while (0)
45 #endif
46
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
49
50 #ifndef BUS_MCEERR_AR
51 #define BUS_MCEERR_AR 4
52 #endif
53 #ifndef BUS_MCEERR_AO
54 #define BUS_MCEERR_AO 5
55 #endif
56
57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
58 KVM_CAP_INFO(SET_TSS_ADDR),
59 KVM_CAP_INFO(EXT_CPUID),
60 KVM_CAP_INFO(MP_STATE),
61 KVM_CAP_LAST_INFO
62 };
63
64 static bool has_msr_star;
65 static bool has_msr_hsave_pa;
66 static bool has_msr_tsc_adjust;
67 static bool has_msr_tsc_deadline;
68 static bool has_msr_feature_control;
69 static bool has_msr_async_pf_en;
70 static bool has_msr_pv_eoi_en;
71 static bool has_msr_misc_enable;
72 static bool has_msr_bndcfgs;
73 static bool has_msr_kvm_steal_time;
74 static int lm_capable_kernel;
75 static bool has_msr_hv_hypercall;
76 static bool has_msr_hv_vapic;
77
78 static bool has_msr_architectural_pmu;
79 static uint32_t num_architectural_pmu_counters;
80
81 bool kvm_allows_irq0_override(void)
82 {
83 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
84 }
85
86 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
87 {
88 struct kvm_cpuid2 *cpuid;
89 int r, size;
90
91 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
92 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
93 cpuid->nent = max;
94 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
95 if (r == 0 && cpuid->nent >= max) {
96 r = -E2BIG;
97 }
98 if (r < 0) {
99 if (r == -E2BIG) {
100 g_free(cpuid);
101 return NULL;
102 } else {
103 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
104 strerror(-r));
105 exit(1);
106 }
107 }
108 return cpuid;
109 }
110
111 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
112 * for all entries.
113 */
114 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
115 {
116 struct kvm_cpuid2 *cpuid;
117 int max = 1;
118 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
119 max *= 2;
120 }
121 return cpuid;
122 }
123
124 struct kvm_para_features {
125 int cap;
126 int feature;
127 } para_features[] = {
128 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
129 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
130 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
131 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
132 { -1, -1 }
133 };
134
135 static int get_para_features(KVMState *s)
136 {
137 int i, features = 0;
138
139 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
140 if (kvm_check_extension(s, para_features[i].cap)) {
141 features |= (1 << para_features[i].feature);
142 }
143 }
144
145 return features;
146 }
147
148
149 /* Returns the value for a specific register on the cpuid entry
150 */
151 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
152 {
153 uint32_t ret = 0;
154 switch (reg) {
155 case R_EAX:
156 ret = entry->eax;
157 break;
158 case R_EBX:
159 ret = entry->ebx;
160 break;
161 case R_ECX:
162 ret = entry->ecx;
163 break;
164 case R_EDX:
165 ret = entry->edx;
166 break;
167 }
168 return ret;
169 }
170
171 /* Find matching entry for function/index on kvm_cpuid2 struct
172 */
173 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
174 uint32_t function,
175 uint32_t index)
176 {
177 int i;
178 for (i = 0; i < cpuid->nent; ++i) {
179 if (cpuid->entries[i].function == function &&
180 cpuid->entries[i].index == index) {
181 return &cpuid->entries[i];
182 }
183 }
184 /* not found: */
185 return NULL;
186 }
187
188 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
189 uint32_t index, int reg)
190 {
191 struct kvm_cpuid2 *cpuid;
192 uint32_t ret = 0;
193 uint32_t cpuid_1_edx;
194 bool found = false;
195
196 cpuid = get_supported_cpuid(s);
197
198 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
199 if (entry) {
200 found = true;
201 ret = cpuid_entry_get_reg(entry, reg);
202 }
203
204 /* Fixups for the data returned by KVM, below */
205
206 if (function == 1 && reg == R_EDX) {
207 /* KVM before 2.6.30 misreports the following features */
208 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
209 } else if (function == 1 && reg == R_ECX) {
210 /* We can set the hypervisor flag, even if KVM does not return it on
211 * GET_SUPPORTED_CPUID
212 */
213 ret |= CPUID_EXT_HYPERVISOR;
214 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
215 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
216 * and the irqchip is in the kernel.
217 */
218 if (kvm_irqchip_in_kernel() &&
219 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
220 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
221 }
222
223 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
224 * without the in-kernel irqchip
225 */
226 if (!kvm_irqchip_in_kernel()) {
227 ret &= ~CPUID_EXT_X2APIC;
228 }
229 } else if (function == 0x80000001 && reg == R_EDX) {
230 /* On Intel, kvm returns cpuid according to the Intel spec,
231 * so add missing bits according to the AMD spec:
232 */
233 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
234 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
235 }
236
237 g_free(cpuid);
238
239 /* fallback for older kernels */
240 if ((function == KVM_CPUID_FEATURES) && !found) {
241 ret = get_para_features(s);
242 }
243
244 return ret;
245 }
246
247 typedef struct HWPoisonPage {
248 ram_addr_t ram_addr;
249 QLIST_ENTRY(HWPoisonPage) list;
250 } HWPoisonPage;
251
252 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
253 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
254
255 static void kvm_unpoison_all(void *param)
256 {
257 HWPoisonPage *page, *next_page;
258
259 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
260 QLIST_REMOVE(page, list);
261 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
262 g_free(page);
263 }
264 }
265
266 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
267 {
268 HWPoisonPage *page;
269
270 QLIST_FOREACH(page, &hwpoison_page_list, list) {
271 if (page->ram_addr == ram_addr) {
272 return;
273 }
274 }
275 page = g_malloc(sizeof(HWPoisonPage));
276 page->ram_addr = ram_addr;
277 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
278 }
279
280 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
281 int *max_banks)
282 {
283 int r;
284
285 r = kvm_check_extension(s, KVM_CAP_MCE);
286 if (r > 0) {
287 *max_banks = r;
288 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
289 }
290 return -ENOSYS;
291 }
292
293 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
294 {
295 CPUX86State *env = &cpu->env;
296 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
297 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
298 uint64_t mcg_status = MCG_STATUS_MCIP;
299
300 if (code == BUS_MCEERR_AR) {
301 status |= MCI_STATUS_AR | 0x134;
302 mcg_status |= MCG_STATUS_EIPV;
303 } else {
304 status |= 0xc0;
305 mcg_status |= MCG_STATUS_RIPV;
306 }
307 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
308 (MCM_ADDR_PHYS << 6) | 0xc,
309 cpu_x86_support_mca_broadcast(env) ?
310 MCE_INJECT_BROADCAST : 0);
311 }
312
313 static void hardware_memory_error(void)
314 {
315 fprintf(stderr, "Hardware memory error!\n");
316 exit(1);
317 }
318
319 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
320 {
321 X86CPU *cpu = X86_CPU(c);
322 CPUX86State *env = &cpu->env;
323 ram_addr_t ram_addr;
324 hwaddr paddr;
325
326 if ((env->mcg_cap & MCG_SER_P) && addr
327 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
328 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
329 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
330 fprintf(stderr, "Hardware memory error for memory used by "
331 "QEMU itself instead of guest system!\n");
332 /* Hope we are lucky for AO MCE */
333 if (code == BUS_MCEERR_AO) {
334 return 0;
335 } else {
336 hardware_memory_error();
337 }
338 }
339 kvm_hwpoison_page_add(ram_addr);
340 kvm_mce_inject(cpu, paddr, code);
341 } else {
342 if (code == BUS_MCEERR_AO) {
343 return 0;
344 } else if (code == BUS_MCEERR_AR) {
345 hardware_memory_error();
346 } else {
347 return 1;
348 }
349 }
350 return 0;
351 }
352
353 int kvm_arch_on_sigbus(int code, void *addr)
354 {
355 X86CPU *cpu = X86_CPU(first_cpu);
356
357 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
358 ram_addr_t ram_addr;
359 hwaddr paddr;
360
361 /* Hope we are lucky for AO MCE */
362 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
363 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
364 addr, &paddr)) {
365 fprintf(stderr, "Hardware memory error for memory used by "
366 "QEMU itself instead of guest system!: %p\n", addr);
367 return 0;
368 }
369 kvm_hwpoison_page_add(ram_addr);
370 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
371 } else {
372 if (code == BUS_MCEERR_AO) {
373 return 0;
374 } else if (code == BUS_MCEERR_AR) {
375 hardware_memory_error();
376 } else {
377 return 1;
378 }
379 }
380 return 0;
381 }
382
383 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
384 {
385 CPUX86State *env = &cpu->env;
386
387 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
388 unsigned int bank, bank_num = env->mcg_cap & 0xff;
389 struct kvm_x86_mce mce;
390
391 env->exception_injected = -1;
392
393 /*
394 * There must be at least one bank in use if an MCE is pending.
395 * Find it and use its values for the event injection.
396 */
397 for (bank = 0; bank < bank_num; bank++) {
398 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
399 break;
400 }
401 }
402 assert(bank < bank_num);
403
404 mce.bank = bank;
405 mce.status = env->mce_banks[bank * 4 + 1];
406 mce.mcg_status = env->mcg_status;
407 mce.addr = env->mce_banks[bank * 4 + 2];
408 mce.misc = env->mce_banks[bank * 4 + 3];
409
410 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
411 }
412 return 0;
413 }
414
415 static void cpu_update_state(void *opaque, int running, RunState state)
416 {
417 CPUX86State *env = opaque;
418
419 if (running) {
420 env->tsc_valid = false;
421 }
422 }
423
424 unsigned long kvm_arch_vcpu_id(CPUState *cs)
425 {
426 X86CPU *cpu = X86_CPU(cs);
427 return cpu->env.cpuid_apic_id;
428 }
429
430 #ifndef KVM_CPUID_SIGNATURE_NEXT
431 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
432 #endif
433
434 static bool hyperv_hypercall_available(X86CPU *cpu)
435 {
436 return cpu->hyperv_vapic ||
437 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
438 }
439
440 static bool hyperv_enabled(X86CPU *cpu)
441 {
442 CPUState *cs = CPU(cpu);
443 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
444 (hyperv_hypercall_available(cpu) ||
445 cpu->hyperv_relaxed_timing);
446 }
447
448 #define KVM_MAX_CPUID_ENTRIES 100
449
450 int kvm_arch_init_vcpu(CPUState *cs)
451 {
452 struct {
453 struct kvm_cpuid2 cpuid;
454 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
455 } QEMU_PACKED cpuid_data;
456 X86CPU *cpu = X86_CPU(cs);
457 CPUX86State *env = &cpu->env;
458 uint32_t limit, i, j, cpuid_i;
459 uint32_t unused;
460 struct kvm_cpuid_entry2 *c;
461 uint32_t signature[3];
462 int kvm_base = KVM_CPUID_SIGNATURE;
463 int r;
464
465 memset(&cpuid_data, 0, sizeof(cpuid_data));
466
467 cpuid_i = 0;
468
469 /* Paravirtualization CPUIDs */
470 if (hyperv_enabled(cpu)) {
471 c = &cpuid_data.entries[cpuid_i++];
472 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
473 memcpy(signature, "Microsoft Hv", 12);
474 c->eax = HYPERV_CPUID_MIN;
475 c->ebx = signature[0];
476 c->ecx = signature[1];
477 c->edx = signature[2];
478
479 c = &cpuid_data.entries[cpuid_i++];
480 c->function = HYPERV_CPUID_INTERFACE;
481 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
482 c->eax = signature[0];
483 c->ebx = 0;
484 c->ecx = 0;
485 c->edx = 0;
486
487 c = &cpuid_data.entries[cpuid_i++];
488 c->function = HYPERV_CPUID_VERSION;
489 c->eax = 0x00001bbc;
490 c->ebx = 0x00060001;
491
492 c = &cpuid_data.entries[cpuid_i++];
493 c->function = HYPERV_CPUID_FEATURES;
494 if (cpu->hyperv_relaxed_timing) {
495 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
496 }
497 if (cpu->hyperv_vapic) {
498 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
499 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
500 has_msr_hv_vapic = true;
501 }
502
503 c = &cpuid_data.entries[cpuid_i++];
504 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
505 if (cpu->hyperv_relaxed_timing) {
506 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
507 }
508 if (has_msr_hv_vapic) {
509 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
510 }
511 c->ebx = cpu->hyperv_spinlock_attempts;
512
513 c = &cpuid_data.entries[cpuid_i++];
514 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
515 c->eax = 0x40;
516 c->ebx = 0x40;
517
518 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
519 has_msr_hv_hypercall = true;
520 }
521
522 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
523 c = &cpuid_data.entries[cpuid_i++];
524 c->function = KVM_CPUID_SIGNATURE | kvm_base;
525 c->eax = 0;
526 c->ebx = signature[0];
527 c->ecx = signature[1];
528 c->edx = signature[2];
529
530 c = &cpuid_data.entries[cpuid_i++];
531 c->function = KVM_CPUID_FEATURES | kvm_base;
532 c->eax = env->features[FEAT_KVM];
533
534 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
535
536 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
537
538 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
539
540 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
541
542 for (i = 0; i <= limit; i++) {
543 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
544 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
545 abort();
546 }
547 c = &cpuid_data.entries[cpuid_i++];
548
549 switch (i) {
550 case 2: {
551 /* Keep reading function 2 till all the input is received */
552 int times;
553
554 c->function = i;
555 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
556 KVM_CPUID_FLAG_STATE_READ_NEXT;
557 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
558 times = c->eax & 0xff;
559
560 for (j = 1; j < times; ++j) {
561 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
562 fprintf(stderr, "cpuid_data is full, no space for "
563 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
564 abort();
565 }
566 c = &cpuid_data.entries[cpuid_i++];
567 c->function = i;
568 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
569 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
570 }
571 break;
572 }
573 case 4:
574 case 0xb:
575 case 0xd:
576 for (j = 0; ; j++) {
577 if (i == 0xd && j == 64) {
578 break;
579 }
580 c->function = i;
581 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
582 c->index = j;
583 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
584
585 if (i == 4 && c->eax == 0) {
586 break;
587 }
588 if (i == 0xb && !(c->ecx & 0xff00)) {
589 break;
590 }
591 if (i == 0xd && c->eax == 0) {
592 continue;
593 }
594 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
595 fprintf(stderr, "cpuid_data is full, no space for "
596 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
597 abort();
598 }
599 c = &cpuid_data.entries[cpuid_i++];
600 }
601 break;
602 default:
603 c->function = i;
604 c->flags = 0;
605 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
606 break;
607 }
608 }
609
610 if (limit >= 0x0a) {
611 uint32_t ver;
612
613 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
614 if ((ver & 0xff) > 0) {
615 has_msr_architectural_pmu = true;
616 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
617
618 /* Shouldn't be more than 32, since that's the number of bits
619 * available in EBX to tell us _which_ counters are available.
620 * Play it safe.
621 */
622 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
623 num_architectural_pmu_counters = MAX_GP_COUNTERS;
624 }
625 }
626 }
627
628 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
629
630 for (i = 0x80000000; i <= limit; i++) {
631 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
632 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
633 abort();
634 }
635 c = &cpuid_data.entries[cpuid_i++];
636
637 c->function = i;
638 c->flags = 0;
639 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
640 }
641
642 /* Call Centaur's CPUID instructions they are supported. */
643 if (env->cpuid_xlevel2 > 0) {
644 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
645
646 for (i = 0xC0000000; i <= limit; i++) {
647 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
648 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
649 abort();
650 }
651 c = &cpuid_data.entries[cpuid_i++];
652
653 c->function = i;
654 c->flags = 0;
655 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
656 }
657 }
658
659 cpuid_data.cpuid.nent = cpuid_i;
660
661 if (((env->cpuid_version >> 8)&0xF) >= 6
662 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
663 (CPUID_MCE | CPUID_MCA)
664 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
665 uint64_t mcg_cap;
666 int banks;
667 int ret;
668
669 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
670 if (ret < 0) {
671 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
672 return ret;
673 }
674
675 if (banks > MCE_BANKS_DEF) {
676 banks = MCE_BANKS_DEF;
677 }
678 mcg_cap &= MCE_CAP_DEF;
679 mcg_cap |= banks;
680 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
681 if (ret < 0) {
682 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
683 return ret;
684 }
685
686 env->mcg_cap = mcg_cap;
687 }
688
689 qemu_add_vm_change_state_handler(cpu_update_state, env);
690
691 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
692 if (c) {
693 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
694 !!(c->ecx & CPUID_EXT_SMX);
695 }
696
697 cpuid_data.cpuid.padding = 0;
698 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
699 if (r) {
700 return r;
701 }
702
703 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
704 if (r && env->tsc_khz) {
705 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
706 if (r < 0) {
707 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
708 return r;
709 }
710 }
711
712 if (kvm_has_xsave()) {
713 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
714 }
715
716 return 0;
717 }
718
719 void kvm_arch_reset_vcpu(CPUState *cs)
720 {
721 X86CPU *cpu = X86_CPU(cs);
722 CPUX86State *env = &cpu->env;
723
724 env->exception_injected = -1;
725 env->interrupt_injected = -1;
726 env->xcr0 = 1;
727 if (kvm_irqchip_in_kernel()) {
728 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
729 KVM_MP_STATE_UNINITIALIZED;
730 } else {
731 env->mp_state = KVM_MP_STATE_RUNNABLE;
732 }
733 }
734
735 static int kvm_get_supported_msrs(KVMState *s)
736 {
737 static int kvm_supported_msrs;
738 int ret = 0;
739
740 /* first time */
741 if (kvm_supported_msrs == 0) {
742 struct kvm_msr_list msr_list, *kvm_msr_list;
743
744 kvm_supported_msrs = -1;
745
746 /* Obtain MSR list from KVM. These are the MSRs that we must
747 * save/restore */
748 msr_list.nmsrs = 0;
749 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
750 if (ret < 0 && ret != -E2BIG) {
751 return ret;
752 }
753 /* Old kernel modules had a bug and could write beyond the provided
754 memory. Allocate at least a safe amount of 1K. */
755 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
756 msr_list.nmsrs *
757 sizeof(msr_list.indices[0])));
758
759 kvm_msr_list->nmsrs = msr_list.nmsrs;
760 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
761 if (ret >= 0) {
762 int i;
763
764 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
765 if (kvm_msr_list->indices[i] == MSR_STAR) {
766 has_msr_star = true;
767 continue;
768 }
769 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
770 has_msr_hsave_pa = true;
771 continue;
772 }
773 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
774 has_msr_tsc_adjust = true;
775 continue;
776 }
777 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
778 has_msr_tsc_deadline = true;
779 continue;
780 }
781 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
782 has_msr_misc_enable = true;
783 continue;
784 }
785 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
786 has_msr_bndcfgs = true;
787 continue;
788 }
789 }
790 }
791
792 g_free(kvm_msr_list);
793 }
794
795 return ret;
796 }
797
798 int kvm_arch_init(KVMState *s)
799 {
800 uint64_t identity_base = 0xfffbc000;
801 uint64_t shadow_mem;
802 int ret;
803 struct utsname utsname;
804
805 ret = kvm_get_supported_msrs(s);
806 if (ret < 0) {
807 return ret;
808 }
809
810 uname(&utsname);
811 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
812
813 /*
814 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
815 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
816 * Since these must be part of guest physical memory, we need to allocate
817 * them, both by setting their start addresses in the kernel and by
818 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
819 *
820 * Older KVM versions may not support setting the identity map base. In
821 * that case we need to stick with the default, i.e. a 256K maximum BIOS
822 * size.
823 */
824 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
825 /* Allows up to 16M BIOSes. */
826 identity_base = 0xfeffc000;
827
828 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
829 if (ret < 0) {
830 return ret;
831 }
832 }
833
834 /* Set TSS base one page after EPT identity map. */
835 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
836 if (ret < 0) {
837 return ret;
838 }
839
840 /* Tell fw_cfg to notify the BIOS to reserve the range. */
841 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
842 if (ret < 0) {
843 fprintf(stderr, "e820_add_entry() table is full\n");
844 return ret;
845 }
846 qemu_register_reset(kvm_unpoison_all, NULL);
847
848 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
849 "kvm_shadow_mem", -1);
850 if (shadow_mem != -1) {
851 shadow_mem /= 4096;
852 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
853 if (ret < 0) {
854 return ret;
855 }
856 }
857 return 0;
858 }
859
860 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
861 {
862 lhs->selector = rhs->selector;
863 lhs->base = rhs->base;
864 lhs->limit = rhs->limit;
865 lhs->type = 3;
866 lhs->present = 1;
867 lhs->dpl = 3;
868 lhs->db = 0;
869 lhs->s = 1;
870 lhs->l = 0;
871 lhs->g = 0;
872 lhs->avl = 0;
873 lhs->unusable = 0;
874 }
875
876 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
877 {
878 unsigned flags = rhs->flags;
879 lhs->selector = rhs->selector;
880 lhs->base = rhs->base;
881 lhs->limit = rhs->limit;
882 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
883 lhs->present = (flags & DESC_P_MASK) != 0;
884 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
885 lhs->db = (flags >> DESC_B_SHIFT) & 1;
886 lhs->s = (flags & DESC_S_MASK) != 0;
887 lhs->l = (flags >> DESC_L_SHIFT) & 1;
888 lhs->g = (flags & DESC_G_MASK) != 0;
889 lhs->avl = (flags & DESC_AVL_MASK) != 0;
890 lhs->unusable = 0;
891 lhs->padding = 0;
892 }
893
894 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
895 {
896 lhs->selector = rhs->selector;
897 lhs->base = rhs->base;
898 lhs->limit = rhs->limit;
899 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
900 (rhs->present * DESC_P_MASK) |
901 (rhs->dpl << DESC_DPL_SHIFT) |
902 (rhs->db << DESC_B_SHIFT) |
903 (rhs->s * DESC_S_MASK) |
904 (rhs->l << DESC_L_SHIFT) |
905 (rhs->g * DESC_G_MASK) |
906 (rhs->avl * DESC_AVL_MASK);
907 }
908
909 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
910 {
911 if (set) {
912 *kvm_reg = *qemu_reg;
913 } else {
914 *qemu_reg = *kvm_reg;
915 }
916 }
917
918 static int kvm_getput_regs(X86CPU *cpu, int set)
919 {
920 CPUX86State *env = &cpu->env;
921 struct kvm_regs regs;
922 int ret = 0;
923
924 if (!set) {
925 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
926 if (ret < 0) {
927 return ret;
928 }
929 }
930
931 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
932 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
933 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
934 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
935 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
936 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
937 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
938 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
939 #ifdef TARGET_X86_64
940 kvm_getput_reg(&regs.r8, &env->regs[8], set);
941 kvm_getput_reg(&regs.r9, &env->regs[9], set);
942 kvm_getput_reg(&regs.r10, &env->regs[10], set);
943 kvm_getput_reg(&regs.r11, &env->regs[11], set);
944 kvm_getput_reg(&regs.r12, &env->regs[12], set);
945 kvm_getput_reg(&regs.r13, &env->regs[13], set);
946 kvm_getput_reg(&regs.r14, &env->regs[14], set);
947 kvm_getput_reg(&regs.r15, &env->regs[15], set);
948 #endif
949
950 kvm_getput_reg(&regs.rflags, &env->eflags, set);
951 kvm_getput_reg(&regs.rip, &env->eip, set);
952
953 if (set) {
954 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
955 }
956
957 return ret;
958 }
959
960 static int kvm_put_fpu(X86CPU *cpu)
961 {
962 CPUX86State *env = &cpu->env;
963 struct kvm_fpu fpu;
964 int i;
965
966 memset(&fpu, 0, sizeof fpu);
967 fpu.fsw = env->fpus & ~(7 << 11);
968 fpu.fsw |= (env->fpstt & 7) << 11;
969 fpu.fcw = env->fpuc;
970 fpu.last_opcode = env->fpop;
971 fpu.last_ip = env->fpip;
972 fpu.last_dp = env->fpdp;
973 for (i = 0; i < 8; ++i) {
974 fpu.ftwx |= (!env->fptags[i]) << i;
975 }
976 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
977 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
978 fpu.mxcsr = env->mxcsr;
979
980 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
981 }
982
983 #define XSAVE_FCW_FSW 0
984 #define XSAVE_FTW_FOP 1
985 #define XSAVE_CWD_RIP 2
986 #define XSAVE_CWD_RDP 4
987 #define XSAVE_MXCSR 6
988 #define XSAVE_ST_SPACE 8
989 #define XSAVE_XMM_SPACE 40
990 #define XSAVE_XSTATE_BV 128
991 #define XSAVE_YMMH_SPACE 144
992 #define XSAVE_BNDREGS 240
993 #define XSAVE_BNDCSR 256
994
995 static int kvm_put_xsave(X86CPU *cpu)
996 {
997 CPUX86State *env = &cpu->env;
998 struct kvm_xsave* xsave = env->kvm_xsave_buf;
999 uint16_t cwd, swd, twd;
1000 int i, r;
1001
1002 if (!kvm_has_xsave()) {
1003 return kvm_put_fpu(cpu);
1004 }
1005
1006 memset(xsave, 0, sizeof(struct kvm_xsave));
1007 twd = 0;
1008 swd = env->fpus & ~(7 << 11);
1009 swd |= (env->fpstt & 7) << 11;
1010 cwd = env->fpuc;
1011 for (i = 0; i < 8; ++i) {
1012 twd |= (!env->fptags[i]) << i;
1013 }
1014 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1015 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1016 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1017 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1018 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1019 sizeof env->fpregs);
1020 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1021 sizeof env->xmm_regs);
1022 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1023 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1024 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1025 sizeof env->ymmh_regs);
1026 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1027 sizeof env->bnd_regs);
1028 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1029 sizeof(env->bndcs_regs));
1030 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1031 return r;
1032 }
1033
1034 static int kvm_put_xcrs(X86CPU *cpu)
1035 {
1036 CPUX86State *env = &cpu->env;
1037 struct kvm_xcrs xcrs;
1038
1039 if (!kvm_has_xcrs()) {
1040 return 0;
1041 }
1042
1043 xcrs.nr_xcrs = 1;
1044 xcrs.flags = 0;
1045 xcrs.xcrs[0].xcr = 0;
1046 xcrs.xcrs[0].value = env->xcr0;
1047 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1048 }
1049
1050 static int kvm_put_sregs(X86CPU *cpu)
1051 {
1052 CPUX86State *env = &cpu->env;
1053 struct kvm_sregs sregs;
1054
1055 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1056 if (env->interrupt_injected >= 0) {
1057 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1058 (uint64_t)1 << (env->interrupt_injected % 64);
1059 }
1060
1061 if ((env->eflags & VM_MASK)) {
1062 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1063 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1064 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1065 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1066 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1067 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1068 } else {
1069 set_seg(&sregs.cs, &env->segs[R_CS]);
1070 set_seg(&sregs.ds, &env->segs[R_DS]);
1071 set_seg(&sregs.es, &env->segs[R_ES]);
1072 set_seg(&sregs.fs, &env->segs[R_FS]);
1073 set_seg(&sregs.gs, &env->segs[R_GS]);
1074 set_seg(&sregs.ss, &env->segs[R_SS]);
1075 }
1076
1077 set_seg(&sregs.tr, &env->tr);
1078 set_seg(&sregs.ldt, &env->ldt);
1079
1080 sregs.idt.limit = env->idt.limit;
1081 sregs.idt.base = env->idt.base;
1082 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1083 sregs.gdt.limit = env->gdt.limit;
1084 sregs.gdt.base = env->gdt.base;
1085 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1086
1087 sregs.cr0 = env->cr[0];
1088 sregs.cr2 = env->cr[2];
1089 sregs.cr3 = env->cr[3];
1090 sregs.cr4 = env->cr[4];
1091
1092 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1093 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1094
1095 sregs.efer = env->efer;
1096
1097 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1098 }
1099
1100 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1101 uint32_t index, uint64_t value)
1102 {
1103 entry->index = index;
1104 entry->data = value;
1105 }
1106
1107 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1108 {
1109 CPUX86State *env = &cpu->env;
1110 struct {
1111 struct kvm_msrs info;
1112 struct kvm_msr_entry entries[1];
1113 } msr_data;
1114 struct kvm_msr_entry *msrs = msr_data.entries;
1115
1116 if (!has_msr_tsc_deadline) {
1117 return 0;
1118 }
1119
1120 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1121
1122 msr_data.info.nmsrs = 1;
1123
1124 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1125 }
1126
1127 /*
1128 * Provide a separate write service for the feature control MSR in order to
1129 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1130 * before writing any other state because forcibly leaving nested mode
1131 * invalidates the VCPU state.
1132 */
1133 static int kvm_put_msr_feature_control(X86CPU *cpu)
1134 {
1135 struct {
1136 struct kvm_msrs info;
1137 struct kvm_msr_entry entry;
1138 } msr_data;
1139
1140 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1141 cpu->env.msr_ia32_feature_control);
1142 msr_data.info.nmsrs = 1;
1143 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1144 }
1145
1146 static int kvm_put_msrs(X86CPU *cpu, int level)
1147 {
1148 CPUX86State *env = &cpu->env;
1149 struct {
1150 struct kvm_msrs info;
1151 struct kvm_msr_entry entries[100];
1152 } msr_data;
1153 struct kvm_msr_entry *msrs = msr_data.entries;
1154 int n = 0, i;
1155
1156 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1157 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1158 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1159 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1160 if (has_msr_star) {
1161 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1162 }
1163 if (has_msr_hsave_pa) {
1164 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1165 }
1166 if (has_msr_tsc_adjust) {
1167 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1168 }
1169 if (has_msr_misc_enable) {
1170 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1171 env->msr_ia32_misc_enable);
1172 }
1173 if (has_msr_bndcfgs) {
1174 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1175 }
1176 #ifdef TARGET_X86_64
1177 if (lm_capable_kernel) {
1178 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1179 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1180 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1181 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1182 }
1183 #endif
1184 /*
1185 * The following MSRs have side effects on the guest or are too heavy
1186 * for normal writeback. Limit them to reset or full state updates.
1187 */
1188 if (level >= KVM_PUT_RESET_STATE) {
1189 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1190 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1191 env->system_time_msr);
1192 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1193 if (has_msr_async_pf_en) {
1194 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1195 env->async_pf_en_msr);
1196 }
1197 if (has_msr_pv_eoi_en) {
1198 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1199 env->pv_eoi_en_msr);
1200 }
1201 if (has_msr_kvm_steal_time) {
1202 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1203 env->steal_time_msr);
1204 }
1205 if (has_msr_architectural_pmu) {
1206 /* Stop the counter. */
1207 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1208 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1209
1210 /* Set the counter values. */
1211 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1212 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1213 env->msr_fixed_counters[i]);
1214 }
1215 for (i = 0; i < num_architectural_pmu_counters; i++) {
1216 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1217 env->msr_gp_counters[i]);
1218 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1219 env->msr_gp_evtsel[i]);
1220 }
1221 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1222 env->msr_global_status);
1223 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1224 env->msr_global_ovf_ctrl);
1225
1226 /* Now start the PMU. */
1227 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1228 env->msr_fixed_ctr_ctrl);
1229 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1230 env->msr_global_ctrl);
1231 }
1232 if (has_msr_hv_hypercall) {
1233 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1234 env->msr_hv_guest_os_id);
1235 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1236 env->msr_hv_hypercall);
1237 }
1238 if (has_msr_hv_vapic) {
1239 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1240 env->msr_hv_vapic);
1241 }
1242
1243 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1244 * kvm_put_msr_feature_control. */
1245 }
1246 if (env->mcg_cap) {
1247 int i;
1248
1249 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1250 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1251 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1252 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1253 }
1254 }
1255
1256 msr_data.info.nmsrs = n;
1257
1258 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1259
1260 }
1261
1262
1263 static int kvm_get_fpu(X86CPU *cpu)
1264 {
1265 CPUX86State *env = &cpu->env;
1266 struct kvm_fpu fpu;
1267 int i, ret;
1268
1269 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1270 if (ret < 0) {
1271 return ret;
1272 }
1273
1274 env->fpstt = (fpu.fsw >> 11) & 7;
1275 env->fpus = fpu.fsw;
1276 env->fpuc = fpu.fcw;
1277 env->fpop = fpu.last_opcode;
1278 env->fpip = fpu.last_ip;
1279 env->fpdp = fpu.last_dp;
1280 for (i = 0; i < 8; ++i) {
1281 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1282 }
1283 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1284 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1285 env->mxcsr = fpu.mxcsr;
1286
1287 return 0;
1288 }
1289
1290 static int kvm_get_xsave(X86CPU *cpu)
1291 {
1292 CPUX86State *env = &cpu->env;
1293 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1294 int ret, i;
1295 uint16_t cwd, swd, twd;
1296
1297 if (!kvm_has_xsave()) {
1298 return kvm_get_fpu(cpu);
1299 }
1300
1301 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1302 if (ret < 0) {
1303 return ret;
1304 }
1305
1306 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1307 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1308 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1309 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1310 env->fpstt = (swd >> 11) & 7;
1311 env->fpus = swd;
1312 env->fpuc = cwd;
1313 for (i = 0; i < 8; ++i) {
1314 env->fptags[i] = !((twd >> i) & 1);
1315 }
1316 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1317 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1318 env->mxcsr = xsave->region[XSAVE_MXCSR];
1319 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1320 sizeof env->fpregs);
1321 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1322 sizeof env->xmm_regs);
1323 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1324 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1325 sizeof env->ymmh_regs);
1326 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1327 sizeof env->bnd_regs);
1328 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1329 sizeof(env->bndcs_regs));
1330 return 0;
1331 }
1332
1333 static int kvm_get_xcrs(X86CPU *cpu)
1334 {
1335 CPUX86State *env = &cpu->env;
1336 int i, ret;
1337 struct kvm_xcrs xcrs;
1338
1339 if (!kvm_has_xcrs()) {
1340 return 0;
1341 }
1342
1343 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1344 if (ret < 0) {
1345 return ret;
1346 }
1347
1348 for (i = 0; i < xcrs.nr_xcrs; i++) {
1349 /* Only support xcr0 now */
1350 if (xcrs.xcrs[i].xcr == 0) {
1351 env->xcr0 = xcrs.xcrs[i].value;
1352 break;
1353 }
1354 }
1355 return 0;
1356 }
1357
1358 static int kvm_get_sregs(X86CPU *cpu)
1359 {
1360 CPUX86State *env = &cpu->env;
1361 struct kvm_sregs sregs;
1362 uint32_t hflags;
1363 int bit, i, ret;
1364
1365 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1366 if (ret < 0) {
1367 return ret;
1368 }
1369
1370 /* There can only be one pending IRQ set in the bitmap at a time, so try
1371 to find it and save its number instead (-1 for none). */
1372 env->interrupt_injected = -1;
1373 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1374 if (sregs.interrupt_bitmap[i]) {
1375 bit = ctz64(sregs.interrupt_bitmap[i]);
1376 env->interrupt_injected = i * 64 + bit;
1377 break;
1378 }
1379 }
1380
1381 get_seg(&env->segs[R_CS], &sregs.cs);
1382 get_seg(&env->segs[R_DS], &sregs.ds);
1383 get_seg(&env->segs[R_ES], &sregs.es);
1384 get_seg(&env->segs[R_FS], &sregs.fs);
1385 get_seg(&env->segs[R_GS], &sregs.gs);
1386 get_seg(&env->segs[R_SS], &sregs.ss);
1387
1388 get_seg(&env->tr, &sregs.tr);
1389 get_seg(&env->ldt, &sregs.ldt);
1390
1391 env->idt.limit = sregs.idt.limit;
1392 env->idt.base = sregs.idt.base;
1393 env->gdt.limit = sregs.gdt.limit;
1394 env->gdt.base = sregs.gdt.base;
1395
1396 env->cr[0] = sregs.cr0;
1397 env->cr[2] = sregs.cr2;
1398 env->cr[3] = sregs.cr3;
1399 env->cr[4] = sregs.cr4;
1400
1401 env->efer = sregs.efer;
1402
1403 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1404
1405 #define HFLAG_COPY_MASK \
1406 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1407 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1408 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1409 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1410
1411 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1412 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1413 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1414 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1415 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1416 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1417 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1418
1419 if (env->efer & MSR_EFER_LMA) {
1420 hflags |= HF_LMA_MASK;
1421 }
1422
1423 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1424 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1425 } else {
1426 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1427 (DESC_B_SHIFT - HF_CS32_SHIFT);
1428 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1429 (DESC_B_SHIFT - HF_SS32_SHIFT);
1430 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1431 !(hflags & HF_CS32_MASK)) {
1432 hflags |= HF_ADDSEG_MASK;
1433 } else {
1434 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1435 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1436 }
1437 }
1438 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1439
1440 return 0;
1441 }
1442
1443 static int kvm_get_msrs(X86CPU *cpu)
1444 {
1445 CPUX86State *env = &cpu->env;
1446 struct {
1447 struct kvm_msrs info;
1448 struct kvm_msr_entry entries[100];
1449 } msr_data;
1450 struct kvm_msr_entry *msrs = msr_data.entries;
1451 int ret, i, n;
1452
1453 n = 0;
1454 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1455 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1456 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1457 msrs[n++].index = MSR_PAT;
1458 if (has_msr_star) {
1459 msrs[n++].index = MSR_STAR;
1460 }
1461 if (has_msr_hsave_pa) {
1462 msrs[n++].index = MSR_VM_HSAVE_PA;
1463 }
1464 if (has_msr_tsc_adjust) {
1465 msrs[n++].index = MSR_TSC_ADJUST;
1466 }
1467 if (has_msr_tsc_deadline) {
1468 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1469 }
1470 if (has_msr_misc_enable) {
1471 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1472 }
1473 if (has_msr_feature_control) {
1474 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1475 }
1476 if (has_msr_bndcfgs) {
1477 msrs[n++].index = MSR_IA32_BNDCFGS;
1478 }
1479
1480 if (!env->tsc_valid) {
1481 msrs[n++].index = MSR_IA32_TSC;
1482 env->tsc_valid = !runstate_is_running();
1483 }
1484
1485 #ifdef TARGET_X86_64
1486 if (lm_capable_kernel) {
1487 msrs[n++].index = MSR_CSTAR;
1488 msrs[n++].index = MSR_KERNELGSBASE;
1489 msrs[n++].index = MSR_FMASK;
1490 msrs[n++].index = MSR_LSTAR;
1491 }
1492 #endif
1493 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1494 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1495 if (has_msr_async_pf_en) {
1496 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1497 }
1498 if (has_msr_pv_eoi_en) {
1499 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1500 }
1501 if (has_msr_kvm_steal_time) {
1502 msrs[n++].index = MSR_KVM_STEAL_TIME;
1503 }
1504 if (has_msr_architectural_pmu) {
1505 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1506 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1507 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1508 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1509 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1510 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1511 }
1512 for (i = 0; i < num_architectural_pmu_counters; i++) {
1513 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1514 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1515 }
1516 }
1517
1518 if (env->mcg_cap) {
1519 msrs[n++].index = MSR_MCG_STATUS;
1520 msrs[n++].index = MSR_MCG_CTL;
1521 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1522 msrs[n++].index = MSR_MC0_CTL + i;
1523 }
1524 }
1525
1526 if (has_msr_hv_hypercall) {
1527 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1528 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1529 }
1530 if (has_msr_hv_vapic) {
1531 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1532 }
1533
1534 msr_data.info.nmsrs = n;
1535 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1536 if (ret < 0) {
1537 return ret;
1538 }
1539
1540 for (i = 0; i < ret; i++) {
1541 uint32_t index = msrs[i].index;
1542 switch (index) {
1543 case MSR_IA32_SYSENTER_CS:
1544 env->sysenter_cs = msrs[i].data;
1545 break;
1546 case MSR_IA32_SYSENTER_ESP:
1547 env->sysenter_esp = msrs[i].data;
1548 break;
1549 case MSR_IA32_SYSENTER_EIP:
1550 env->sysenter_eip = msrs[i].data;
1551 break;
1552 case MSR_PAT:
1553 env->pat = msrs[i].data;
1554 break;
1555 case MSR_STAR:
1556 env->star = msrs[i].data;
1557 break;
1558 #ifdef TARGET_X86_64
1559 case MSR_CSTAR:
1560 env->cstar = msrs[i].data;
1561 break;
1562 case MSR_KERNELGSBASE:
1563 env->kernelgsbase = msrs[i].data;
1564 break;
1565 case MSR_FMASK:
1566 env->fmask = msrs[i].data;
1567 break;
1568 case MSR_LSTAR:
1569 env->lstar = msrs[i].data;
1570 break;
1571 #endif
1572 case MSR_IA32_TSC:
1573 env->tsc = msrs[i].data;
1574 break;
1575 case MSR_TSC_ADJUST:
1576 env->tsc_adjust = msrs[i].data;
1577 break;
1578 case MSR_IA32_TSCDEADLINE:
1579 env->tsc_deadline = msrs[i].data;
1580 break;
1581 case MSR_VM_HSAVE_PA:
1582 env->vm_hsave = msrs[i].data;
1583 break;
1584 case MSR_KVM_SYSTEM_TIME:
1585 env->system_time_msr = msrs[i].data;
1586 break;
1587 case MSR_KVM_WALL_CLOCK:
1588 env->wall_clock_msr = msrs[i].data;
1589 break;
1590 case MSR_MCG_STATUS:
1591 env->mcg_status = msrs[i].data;
1592 break;
1593 case MSR_MCG_CTL:
1594 env->mcg_ctl = msrs[i].data;
1595 break;
1596 case MSR_IA32_MISC_ENABLE:
1597 env->msr_ia32_misc_enable = msrs[i].data;
1598 break;
1599 case MSR_IA32_FEATURE_CONTROL:
1600 env->msr_ia32_feature_control = msrs[i].data;
1601 break;
1602 case MSR_IA32_BNDCFGS:
1603 env->msr_bndcfgs = msrs[i].data;
1604 break;
1605 default:
1606 if (msrs[i].index >= MSR_MC0_CTL &&
1607 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1608 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1609 }
1610 break;
1611 case MSR_KVM_ASYNC_PF_EN:
1612 env->async_pf_en_msr = msrs[i].data;
1613 break;
1614 case MSR_KVM_PV_EOI_EN:
1615 env->pv_eoi_en_msr = msrs[i].data;
1616 break;
1617 case MSR_KVM_STEAL_TIME:
1618 env->steal_time_msr = msrs[i].data;
1619 break;
1620 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1621 env->msr_fixed_ctr_ctrl = msrs[i].data;
1622 break;
1623 case MSR_CORE_PERF_GLOBAL_CTRL:
1624 env->msr_global_ctrl = msrs[i].data;
1625 break;
1626 case MSR_CORE_PERF_GLOBAL_STATUS:
1627 env->msr_global_status = msrs[i].data;
1628 break;
1629 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1630 env->msr_global_ovf_ctrl = msrs[i].data;
1631 break;
1632 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1633 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1634 break;
1635 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1636 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1637 break;
1638 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1639 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1640 break;
1641 case HV_X64_MSR_HYPERCALL:
1642 env->msr_hv_hypercall = msrs[i].data;
1643 break;
1644 case HV_X64_MSR_GUEST_OS_ID:
1645 env->msr_hv_guest_os_id = msrs[i].data;
1646 break;
1647 case HV_X64_MSR_APIC_ASSIST_PAGE:
1648 env->msr_hv_vapic = msrs[i].data;
1649 break;
1650 }
1651 }
1652
1653 return 0;
1654 }
1655
1656 static int kvm_put_mp_state(X86CPU *cpu)
1657 {
1658 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1659
1660 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1661 }
1662
1663 static int kvm_get_mp_state(X86CPU *cpu)
1664 {
1665 CPUState *cs = CPU(cpu);
1666 CPUX86State *env = &cpu->env;
1667 struct kvm_mp_state mp_state;
1668 int ret;
1669
1670 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1671 if (ret < 0) {
1672 return ret;
1673 }
1674 env->mp_state = mp_state.mp_state;
1675 if (kvm_irqchip_in_kernel()) {
1676 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1677 }
1678 return 0;
1679 }
1680
1681 static int kvm_get_apic(X86CPU *cpu)
1682 {
1683 DeviceState *apic = cpu->apic_state;
1684 struct kvm_lapic_state kapic;
1685 int ret;
1686
1687 if (apic && kvm_irqchip_in_kernel()) {
1688 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1689 if (ret < 0) {
1690 return ret;
1691 }
1692
1693 kvm_get_apic_state(apic, &kapic);
1694 }
1695 return 0;
1696 }
1697
1698 static int kvm_put_apic(X86CPU *cpu)
1699 {
1700 DeviceState *apic = cpu->apic_state;
1701 struct kvm_lapic_state kapic;
1702
1703 if (apic && kvm_irqchip_in_kernel()) {
1704 kvm_put_apic_state(apic, &kapic);
1705
1706 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1707 }
1708 return 0;
1709 }
1710
1711 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1712 {
1713 CPUX86State *env = &cpu->env;
1714 struct kvm_vcpu_events events;
1715
1716 if (!kvm_has_vcpu_events()) {
1717 return 0;
1718 }
1719
1720 events.exception.injected = (env->exception_injected >= 0);
1721 events.exception.nr = env->exception_injected;
1722 events.exception.has_error_code = env->has_error_code;
1723 events.exception.error_code = env->error_code;
1724 events.exception.pad = 0;
1725
1726 events.interrupt.injected = (env->interrupt_injected >= 0);
1727 events.interrupt.nr = env->interrupt_injected;
1728 events.interrupt.soft = env->soft_interrupt;
1729
1730 events.nmi.injected = env->nmi_injected;
1731 events.nmi.pending = env->nmi_pending;
1732 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1733 events.nmi.pad = 0;
1734
1735 events.sipi_vector = env->sipi_vector;
1736
1737 events.flags = 0;
1738 if (level >= KVM_PUT_RESET_STATE) {
1739 events.flags |=
1740 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1741 }
1742
1743 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1744 }
1745
1746 static int kvm_get_vcpu_events(X86CPU *cpu)
1747 {
1748 CPUX86State *env = &cpu->env;
1749 struct kvm_vcpu_events events;
1750 int ret;
1751
1752 if (!kvm_has_vcpu_events()) {
1753 return 0;
1754 }
1755
1756 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1757 if (ret < 0) {
1758 return ret;
1759 }
1760 env->exception_injected =
1761 events.exception.injected ? events.exception.nr : -1;
1762 env->has_error_code = events.exception.has_error_code;
1763 env->error_code = events.exception.error_code;
1764
1765 env->interrupt_injected =
1766 events.interrupt.injected ? events.interrupt.nr : -1;
1767 env->soft_interrupt = events.interrupt.soft;
1768
1769 env->nmi_injected = events.nmi.injected;
1770 env->nmi_pending = events.nmi.pending;
1771 if (events.nmi.masked) {
1772 env->hflags2 |= HF2_NMI_MASK;
1773 } else {
1774 env->hflags2 &= ~HF2_NMI_MASK;
1775 }
1776
1777 env->sipi_vector = events.sipi_vector;
1778
1779 return 0;
1780 }
1781
1782 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1783 {
1784 CPUState *cs = CPU(cpu);
1785 CPUX86State *env = &cpu->env;
1786 int ret = 0;
1787 unsigned long reinject_trap = 0;
1788
1789 if (!kvm_has_vcpu_events()) {
1790 if (env->exception_injected == 1) {
1791 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1792 } else if (env->exception_injected == 3) {
1793 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1794 }
1795 env->exception_injected = -1;
1796 }
1797
1798 /*
1799 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1800 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1801 * by updating the debug state once again if single-stepping is on.
1802 * Another reason to call kvm_update_guest_debug here is a pending debug
1803 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1804 * reinject them via SET_GUEST_DEBUG.
1805 */
1806 if (reinject_trap ||
1807 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1808 ret = kvm_update_guest_debug(cs, reinject_trap);
1809 }
1810 return ret;
1811 }
1812
1813 static int kvm_put_debugregs(X86CPU *cpu)
1814 {
1815 CPUX86State *env = &cpu->env;
1816 struct kvm_debugregs dbgregs;
1817 int i;
1818
1819 if (!kvm_has_debugregs()) {
1820 return 0;
1821 }
1822
1823 for (i = 0; i < 4; i++) {
1824 dbgregs.db[i] = env->dr[i];
1825 }
1826 dbgregs.dr6 = env->dr[6];
1827 dbgregs.dr7 = env->dr[7];
1828 dbgregs.flags = 0;
1829
1830 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1831 }
1832
1833 static int kvm_get_debugregs(X86CPU *cpu)
1834 {
1835 CPUX86State *env = &cpu->env;
1836 struct kvm_debugregs dbgregs;
1837 int i, ret;
1838
1839 if (!kvm_has_debugregs()) {
1840 return 0;
1841 }
1842
1843 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1844 if (ret < 0) {
1845 return ret;
1846 }
1847 for (i = 0; i < 4; i++) {
1848 env->dr[i] = dbgregs.db[i];
1849 }
1850 env->dr[4] = env->dr[6] = dbgregs.dr6;
1851 env->dr[5] = env->dr[7] = dbgregs.dr7;
1852
1853 return 0;
1854 }
1855
1856 int kvm_arch_put_registers(CPUState *cpu, int level)
1857 {
1858 X86CPU *x86_cpu = X86_CPU(cpu);
1859 int ret;
1860
1861 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1862
1863 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
1864 ret = kvm_put_msr_feature_control(x86_cpu);
1865 if (ret < 0) {
1866 return ret;
1867 }
1868 }
1869
1870 ret = kvm_getput_regs(x86_cpu, 1);
1871 if (ret < 0) {
1872 return ret;
1873 }
1874 ret = kvm_put_xsave(x86_cpu);
1875 if (ret < 0) {
1876 return ret;
1877 }
1878 ret = kvm_put_xcrs(x86_cpu);
1879 if (ret < 0) {
1880 return ret;
1881 }
1882 ret = kvm_put_sregs(x86_cpu);
1883 if (ret < 0) {
1884 return ret;
1885 }
1886 /* must be before kvm_put_msrs */
1887 ret = kvm_inject_mce_oldstyle(x86_cpu);
1888 if (ret < 0) {
1889 return ret;
1890 }
1891 ret = kvm_put_msrs(x86_cpu, level);
1892 if (ret < 0) {
1893 return ret;
1894 }
1895 if (level >= KVM_PUT_RESET_STATE) {
1896 ret = kvm_put_mp_state(x86_cpu);
1897 if (ret < 0) {
1898 return ret;
1899 }
1900 ret = kvm_put_apic(x86_cpu);
1901 if (ret < 0) {
1902 return ret;
1903 }
1904 }
1905
1906 ret = kvm_put_tscdeadline_msr(x86_cpu);
1907 if (ret < 0) {
1908 return ret;
1909 }
1910
1911 ret = kvm_put_vcpu_events(x86_cpu, level);
1912 if (ret < 0) {
1913 return ret;
1914 }
1915 ret = kvm_put_debugregs(x86_cpu);
1916 if (ret < 0) {
1917 return ret;
1918 }
1919 /* must be last */
1920 ret = kvm_guest_debug_workarounds(x86_cpu);
1921 if (ret < 0) {
1922 return ret;
1923 }
1924 return 0;
1925 }
1926
1927 int kvm_arch_get_registers(CPUState *cs)
1928 {
1929 X86CPU *cpu = X86_CPU(cs);
1930 int ret;
1931
1932 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1933
1934 ret = kvm_getput_regs(cpu, 0);
1935 if (ret < 0) {
1936 return ret;
1937 }
1938 ret = kvm_get_xsave(cpu);
1939 if (ret < 0) {
1940 return ret;
1941 }
1942 ret = kvm_get_xcrs(cpu);
1943 if (ret < 0) {
1944 return ret;
1945 }
1946 ret = kvm_get_sregs(cpu);
1947 if (ret < 0) {
1948 return ret;
1949 }
1950 ret = kvm_get_msrs(cpu);
1951 if (ret < 0) {
1952 return ret;
1953 }
1954 ret = kvm_get_mp_state(cpu);
1955 if (ret < 0) {
1956 return ret;
1957 }
1958 ret = kvm_get_apic(cpu);
1959 if (ret < 0) {
1960 return ret;
1961 }
1962 ret = kvm_get_vcpu_events(cpu);
1963 if (ret < 0) {
1964 return ret;
1965 }
1966 ret = kvm_get_debugregs(cpu);
1967 if (ret < 0) {
1968 return ret;
1969 }
1970 return 0;
1971 }
1972
1973 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1974 {
1975 X86CPU *x86_cpu = X86_CPU(cpu);
1976 CPUX86State *env = &x86_cpu->env;
1977 int ret;
1978
1979 /* Inject NMI */
1980 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
1981 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
1982 DPRINTF("injected NMI\n");
1983 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1984 if (ret < 0) {
1985 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1986 strerror(-ret));
1987 }
1988 }
1989
1990 if (!kvm_irqchip_in_kernel()) {
1991 /* Force the VCPU out of its inner loop to process any INIT requests
1992 * or pending TPR access reports. */
1993 if (cpu->interrupt_request &
1994 (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1995 cpu->exit_request = 1;
1996 }
1997
1998 /* Try to inject an interrupt if the guest can accept it */
1999 if (run->ready_for_interrupt_injection &&
2000 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2001 (env->eflags & IF_MASK)) {
2002 int irq;
2003
2004 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2005 irq = cpu_get_pic_interrupt(env);
2006 if (irq >= 0) {
2007 struct kvm_interrupt intr;
2008
2009 intr.irq = irq;
2010 DPRINTF("injected interrupt %d\n", irq);
2011 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2012 if (ret < 0) {
2013 fprintf(stderr,
2014 "KVM: injection failed, interrupt lost (%s)\n",
2015 strerror(-ret));
2016 }
2017 }
2018 }
2019
2020 /* If we have an interrupt but the guest is not ready to receive an
2021 * interrupt, request an interrupt window exit. This will
2022 * cause a return to userspace as soon as the guest is ready to
2023 * receive interrupts. */
2024 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2025 run->request_interrupt_window = 1;
2026 } else {
2027 run->request_interrupt_window = 0;
2028 }
2029
2030 DPRINTF("setting tpr\n");
2031 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2032 }
2033 }
2034
2035 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2036 {
2037 X86CPU *x86_cpu = X86_CPU(cpu);
2038 CPUX86State *env = &x86_cpu->env;
2039
2040 if (run->if_flag) {
2041 env->eflags |= IF_MASK;
2042 } else {
2043 env->eflags &= ~IF_MASK;
2044 }
2045 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2046 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2047 }
2048
2049 int kvm_arch_process_async_events(CPUState *cs)
2050 {
2051 X86CPU *cpu = X86_CPU(cs);
2052 CPUX86State *env = &cpu->env;
2053
2054 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2055 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2056 assert(env->mcg_cap);
2057
2058 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2059
2060 kvm_cpu_synchronize_state(cs);
2061
2062 if (env->exception_injected == EXCP08_DBLE) {
2063 /* this means triple fault */
2064 qemu_system_reset_request();
2065 cs->exit_request = 1;
2066 return 0;
2067 }
2068 env->exception_injected = EXCP12_MCHK;
2069 env->has_error_code = 0;
2070
2071 cs->halted = 0;
2072 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2073 env->mp_state = KVM_MP_STATE_RUNNABLE;
2074 }
2075 }
2076
2077 if (kvm_irqchip_in_kernel()) {
2078 return 0;
2079 }
2080
2081 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2082 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2083 apic_poll_irq(cpu->apic_state);
2084 }
2085 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2086 (env->eflags & IF_MASK)) ||
2087 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2088 cs->halted = 0;
2089 }
2090 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2091 kvm_cpu_synchronize_state(cs);
2092 do_cpu_init(cpu);
2093 }
2094 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2095 kvm_cpu_synchronize_state(cs);
2096 do_cpu_sipi(cpu);
2097 }
2098 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2099 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2100 kvm_cpu_synchronize_state(cs);
2101 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2102 env->tpr_access_type);
2103 }
2104
2105 return cs->halted;
2106 }
2107
2108 static int kvm_handle_halt(X86CPU *cpu)
2109 {
2110 CPUState *cs = CPU(cpu);
2111 CPUX86State *env = &cpu->env;
2112
2113 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2114 (env->eflags & IF_MASK)) &&
2115 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2116 cs->halted = 1;
2117 return EXCP_HLT;
2118 }
2119
2120 return 0;
2121 }
2122
2123 static int kvm_handle_tpr_access(X86CPU *cpu)
2124 {
2125 CPUState *cs = CPU(cpu);
2126 struct kvm_run *run = cs->kvm_run;
2127
2128 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2129 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2130 : TPR_ACCESS_READ);
2131 return 1;
2132 }
2133
2134 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2135 {
2136 static const uint8_t int3 = 0xcc;
2137
2138 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2139 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2140 return -EINVAL;
2141 }
2142 return 0;
2143 }
2144
2145 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2146 {
2147 uint8_t int3;
2148
2149 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2150 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2151 return -EINVAL;
2152 }
2153 return 0;
2154 }
2155
2156 static struct {
2157 target_ulong addr;
2158 int len;
2159 int type;
2160 } hw_breakpoint[4];
2161
2162 static int nb_hw_breakpoint;
2163
2164 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2165 {
2166 int n;
2167
2168 for (n = 0; n < nb_hw_breakpoint; n++) {
2169 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2170 (hw_breakpoint[n].len == len || len == -1)) {
2171 return n;
2172 }
2173 }
2174 return -1;
2175 }
2176
2177 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2178 target_ulong len, int type)
2179 {
2180 switch (type) {
2181 case GDB_BREAKPOINT_HW:
2182 len = 1;
2183 break;
2184 case GDB_WATCHPOINT_WRITE:
2185 case GDB_WATCHPOINT_ACCESS:
2186 switch (len) {
2187 case 1:
2188 break;
2189 case 2:
2190 case 4:
2191 case 8:
2192 if (addr & (len - 1)) {
2193 return -EINVAL;
2194 }
2195 break;
2196 default:
2197 return -EINVAL;
2198 }
2199 break;
2200 default:
2201 return -ENOSYS;
2202 }
2203
2204 if (nb_hw_breakpoint == 4) {
2205 return -ENOBUFS;
2206 }
2207 if (find_hw_breakpoint(addr, len, type) >= 0) {
2208 return -EEXIST;
2209 }
2210 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2211 hw_breakpoint[nb_hw_breakpoint].len = len;
2212 hw_breakpoint[nb_hw_breakpoint].type = type;
2213 nb_hw_breakpoint++;
2214
2215 return 0;
2216 }
2217
2218 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2219 target_ulong len, int type)
2220 {
2221 int n;
2222
2223 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2224 if (n < 0) {
2225 return -ENOENT;
2226 }
2227 nb_hw_breakpoint--;
2228 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2229
2230 return 0;
2231 }
2232
2233 void kvm_arch_remove_all_hw_breakpoints(void)
2234 {
2235 nb_hw_breakpoint = 0;
2236 }
2237
2238 static CPUWatchpoint hw_watchpoint;
2239
2240 static int kvm_handle_debug(X86CPU *cpu,
2241 struct kvm_debug_exit_arch *arch_info)
2242 {
2243 CPUState *cs = CPU(cpu);
2244 CPUX86State *env = &cpu->env;
2245 int ret = 0;
2246 int n;
2247
2248 if (arch_info->exception == 1) {
2249 if (arch_info->dr6 & (1 << 14)) {
2250 if (cs->singlestep_enabled) {
2251 ret = EXCP_DEBUG;
2252 }
2253 } else {
2254 for (n = 0; n < 4; n++) {
2255 if (arch_info->dr6 & (1 << n)) {
2256 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2257 case 0x0:
2258 ret = EXCP_DEBUG;
2259 break;
2260 case 0x1:
2261 ret = EXCP_DEBUG;
2262 env->watchpoint_hit = &hw_watchpoint;
2263 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2264 hw_watchpoint.flags = BP_MEM_WRITE;
2265 break;
2266 case 0x3:
2267 ret = EXCP_DEBUG;
2268 env->watchpoint_hit = &hw_watchpoint;
2269 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2270 hw_watchpoint.flags = BP_MEM_ACCESS;
2271 break;
2272 }
2273 }
2274 }
2275 }
2276 } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2277 ret = EXCP_DEBUG;
2278 }
2279 if (ret == 0) {
2280 cpu_synchronize_state(CPU(cpu));
2281 assert(env->exception_injected == -1);
2282
2283 /* pass to guest */
2284 env->exception_injected = arch_info->exception;
2285 env->has_error_code = 0;
2286 }
2287
2288 return ret;
2289 }
2290
2291 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2292 {
2293 const uint8_t type_code[] = {
2294 [GDB_BREAKPOINT_HW] = 0x0,
2295 [GDB_WATCHPOINT_WRITE] = 0x1,
2296 [GDB_WATCHPOINT_ACCESS] = 0x3
2297 };
2298 const uint8_t len_code[] = {
2299 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2300 };
2301 int n;
2302
2303 if (kvm_sw_breakpoints_active(cpu)) {
2304 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2305 }
2306 if (nb_hw_breakpoint > 0) {
2307 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2308 dbg->arch.debugreg[7] = 0x0600;
2309 for (n = 0; n < nb_hw_breakpoint; n++) {
2310 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2311 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2312 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2313 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2314 }
2315 }
2316 }
2317
2318 static bool host_supports_vmx(void)
2319 {
2320 uint32_t ecx, unused;
2321
2322 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2323 return ecx & CPUID_EXT_VMX;
2324 }
2325
2326 #define VMX_INVALID_GUEST_STATE 0x80000021
2327
2328 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2329 {
2330 X86CPU *cpu = X86_CPU(cs);
2331 uint64_t code;
2332 int ret;
2333
2334 switch (run->exit_reason) {
2335 case KVM_EXIT_HLT:
2336 DPRINTF("handle_hlt\n");
2337 ret = kvm_handle_halt(cpu);
2338 break;
2339 case KVM_EXIT_SET_TPR:
2340 ret = 0;
2341 break;
2342 case KVM_EXIT_TPR_ACCESS:
2343 ret = kvm_handle_tpr_access(cpu);
2344 break;
2345 case KVM_EXIT_FAIL_ENTRY:
2346 code = run->fail_entry.hardware_entry_failure_reason;
2347 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2348 code);
2349 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2350 fprintf(stderr,
2351 "\nIf you're running a guest on an Intel machine without "
2352 "unrestricted mode\n"
2353 "support, the failure can be most likely due to the guest "
2354 "entering an invalid\n"
2355 "state for Intel VT. For example, the guest maybe running "
2356 "in big real mode\n"
2357 "which is not supported on less recent Intel processors."
2358 "\n\n");
2359 }
2360 ret = -1;
2361 break;
2362 case KVM_EXIT_EXCEPTION:
2363 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2364 run->ex.exception, run->ex.error_code);
2365 ret = -1;
2366 break;
2367 case KVM_EXIT_DEBUG:
2368 DPRINTF("kvm_exit_debug\n");
2369 ret = kvm_handle_debug(cpu, &run->debug.arch);
2370 break;
2371 default:
2372 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2373 ret = -1;
2374 break;
2375 }
2376
2377 return ret;
2378 }
2379
2380 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2381 {
2382 X86CPU *cpu = X86_CPU(cs);
2383 CPUX86State *env = &cpu->env;
2384
2385 kvm_cpu_synchronize_state(cs);
2386 return !(env->cr[0] & CR0_PE_MASK) ||
2387 ((env->segs[R_CS].selector & 3) != 3);
2388 }
2389
2390 void kvm_arch_init_irq_routing(KVMState *s)
2391 {
2392 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2393 /* If kernel can't do irq routing, interrupt source
2394 * override 0->2 cannot be set up as required by HPET.
2395 * So we have to disable it.
2396 */
2397 no_hpet = 1;
2398 }
2399 /* We know at this point that we're using the in-kernel
2400 * irqchip, so we can use irqfds, and on x86 we know
2401 * we can use msi via irqfd and GSI routing.
2402 */
2403 kvm_irqfds_allowed = true;
2404 kvm_msi_via_irqfd_allowed = true;
2405 kvm_gsi_routing_allowed = true;
2406 }
2407
2408 /* Classic KVM device assignment interface. Will remain x86 only. */
2409 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2410 uint32_t flags, uint32_t *dev_id)
2411 {
2412 struct kvm_assigned_pci_dev dev_data = {
2413 .segnr = dev_addr->domain,
2414 .busnr = dev_addr->bus,
2415 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2416 .flags = flags,
2417 };
2418 int ret;
2419
2420 dev_data.assigned_dev_id =
2421 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2422
2423 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2424 if (ret < 0) {
2425 return ret;
2426 }
2427
2428 *dev_id = dev_data.assigned_dev_id;
2429
2430 return 0;
2431 }
2432
2433 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2434 {
2435 struct kvm_assigned_pci_dev dev_data = {
2436 .assigned_dev_id = dev_id,
2437 };
2438
2439 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2440 }
2441
2442 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2443 uint32_t irq_type, uint32_t guest_irq)
2444 {
2445 struct kvm_assigned_irq assigned_irq = {
2446 .assigned_dev_id = dev_id,
2447 .guest_irq = guest_irq,
2448 .flags = irq_type,
2449 };
2450
2451 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2452 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2453 } else {
2454 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2455 }
2456 }
2457
2458 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2459 uint32_t guest_irq)
2460 {
2461 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2462 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2463
2464 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2465 }
2466
2467 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2468 {
2469 struct kvm_assigned_pci_dev dev_data = {
2470 .assigned_dev_id = dev_id,
2471 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2472 };
2473
2474 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2475 }
2476
2477 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2478 uint32_t type)
2479 {
2480 struct kvm_assigned_irq assigned_irq = {
2481 .assigned_dev_id = dev_id,
2482 .flags = type,
2483 };
2484
2485 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2486 }
2487
2488 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2489 {
2490 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2491 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2492 }
2493
2494 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2495 {
2496 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2497 KVM_DEV_IRQ_GUEST_MSI, virq);
2498 }
2499
2500 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2501 {
2502 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2503 KVM_DEV_IRQ_HOST_MSI);
2504 }
2505
2506 bool kvm_device_msix_supported(KVMState *s)
2507 {
2508 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2509 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2510 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2511 }
2512
2513 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2514 uint32_t nr_vectors)
2515 {
2516 struct kvm_assigned_msix_nr msix_nr = {
2517 .assigned_dev_id = dev_id,
2518 .entry_nr = nr_vectors,
2519 };
2520
2521 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2522 }
2523
2524 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2525 int virq)
2526 {
2527 struct kvm_assigned_msix_entry msix_entry = {
2528 .assigned_dev_id = dev_id,
2529 .gsi = virq,
2530 .entry = vector,
2531 };
2532
2533 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2534 }
2535
2536 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2537 {
2538 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2539 KVM_DEV_IRQ_GUEST_MSIX, 0);
2540 }
2541
2542 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2543 {
2544 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2545 KVM_DEV_IRQ_HOST_MSIX);
2546 }
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