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Merge remote-tracking branch 'remotes/bonzini/scsi-next' into staging
[mirror_qemu.git] / target-i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38
39 //#define DEBUG_KVM
40
41 #ifdef DEBUG_KVM
42 #define DPRINTF(fmt, ...) \
43 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
44 #else
45 #define DPRINTF(fmt, ...) \
46 do { } while (0)
47 #endif
48
49 #define MSR_KVM_WALL_CLOCK 0x11
50 #define MSR_KVM_SYSTEM_TIME 0x12
51
52 #ifndef BUS_MCEERR_AR
53 #define BUS_MCEERR_AR 4
54 #endif
55 #ifndef BUS_MCEERR_AO
56 #define BUS_MCEERR_AO 5
57 #endif
58
59 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
60 KVM_CAP_INFO(SET_TSS_ADDR),
61 KVM_CAP_INFO(EXT_CPUID),
62 KVM_CAP_INFO(MP_STATE),
63 KVM_CAP_LAST_INFO
64 };
65
66 static bool has_msr_star;
67 static bool has_msr_hsave_pa;
68 static bool has_msr_tsc_adjust;
69 static bool has_msr_tsc_deadline;
70 static bool has_msr_feature_control;
71 static bool has_msr_async_pf_en;
72 static bool has_msr_pv_eoi_en;
73 static bool has_msr_misc_enable;
74 static bool has_msr_bndcfgs;
75 static bool has_msr_kvm_steal_time;
76 static int lm_capable_kernel;
77 static bool has_msr_hv_hypercall;
78 static bool has_msr_hv_vapic;
79 static bool has_msr_hv_tsc;
80
81 static bool has_msr_architectural_pmu;
82 static uint32_t num_architectural_pmu_counters;
83
84 bool kvm_allows_irq0_override(void)
85 {
86 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
87 }
88
89 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
90 {
91 struct kvm_cpuid2 *cpuid;
92 int r, size;
93
94 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
95 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
96 cpuid->nent = max;
97 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
98 if (r == 0 && cpuid->nent >= max) {
99 r = -E2BIG;
100 }
101 if (r < 0) {
102 if (r == -E2BIG) {
103 g_free(cpuid);
104 return NULL;
105 } else {
106 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
107 strerror(-r));
108 exit(1);
109 }
110 }
111 return cpuid;
112 }
113
114 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
115 * for all entries.
116 */
117 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
118 {
119 struct kvm_cpuid2 *cpuid;
120 int max = 1;
121 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
122 max *= 2;
123 }
124 return cpuid;
125 }
126
127 static const struct kvm_para_features {
128 int cap;
129 int feature;
130 } para_features[] = {
131 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
132 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
133 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
134 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
135 };
136
137 static int get_para_features(KVMState *s)
138 {
139 int i, features = 0;
140
141 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
142 if (kvm_check_extension(s, para_features[i].cap)) {
143 features |= (1 << para_features[i].feature);
144 }
145 }
146
147 return features;
148 }
149
150
151 /* Returns the value for a specific register on the cpuid entry
152 */
153 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
154 {
155 uint32_t ret = 0;
156 switch (reg) {
157 case R_EAX:
158 ret = entry->eax;
159 break;
160 case R_EBX:
161 ret = entry->ebx;
162 break;
163 case R_ECX:
164 ret = entry->ecx;
165 break;
166 case R_EDX:
167 ret = entry->edx;
168 break;
169 }
170 return ret;
171 }
172
173 /* Find matching entry for function/index on kvm_cpuid2 struct
174 */
175 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
176 uint32_t function,
177 uint32_t index)
178 {
179 int i;
180 for (i = 0; i < cpuid->nent; ++i) {
181 if (cpuid->entries[i].function == function &&
182 cpuid->entries[i].index == index) {
183 return &cpuid->entries[i];
184 }
185 }
186 /* not found: */
187 return NULL;
188 }
189
190 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
191 uint32_t index, int reg)
192 {
193 struct kvm_cpuid2 *cpuid;
194 uint32_t ret = 0;
195 uint32_t cpuid_1_edx;
196 bool found = false;
197
198 cpuid = get_supported_cpuid(s);
199
200 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
201 if (entry) {
202 found = true;
203 ret = cpuid_entry_get_reg(entry, reg);
204 }
205
206 /* Fixups for the data returned by KVM, below */
207
208 if (function == 1 && reg == R_EDX) {
209 /* KVM before 2.6.30 misreports the following features */
210 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
211 } else if (function == 1 && reg == R_ECX) {
212 /* We can set the hypervisor flag, even if KVM does not return it on
213 * GET_SUPPORTED_CPUID
214 */
215 ret |= CPUID_EXT_HYPERVISOR;
216 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
217 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
218 * and the irqchip is in the kernel.
219 */
220 if (kvm_irqchip_in_kernel() &&
221 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
222 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
223 }
224
225 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
226 * without the in-kernel irqchip
227 */
228 if (!kvm_irqchip_in_kernel()) {
229 ret &= ~CPUID_EXT_X2APIC;
230 }
231 } else if (function == 0x80000001 && reg == R_EDX) {
232 /* On Intel, kvm returns cpuid according to the Intel spec,
233 * so add missing bits according to the AMD spec:
234 */
235 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
236 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
237 }
238
239 g_free(cpuid);
240
241 /* fallback for older kernels */
242 if ((function == KVM_CPUID_FEATURES) && !found) {
243 ret = get_para_features(s);
244 }
245
246 return ret;
247 }
248
249 typedef struct HWPoisonPage {
250 ram_addr_t ram_addr;
251 QLIST_ENTRY(HWPoisonPage) list;
252 } HWPoisonPage;
253
254 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
255 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
256
257 static void kvm_unpoison_all(void *param)
258 {
259 HWPoisonPage *page, *next_page;
260
261 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
262 QLIST_REMOVE(page, list);
263 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
264 g_free(page);
265 }
266 }
267
268 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
269 {
270 HWPoisonPage *page;
271
272 QLIST_FOREACH(page, &hwpoison_page_list, list) {
273 if (page->ram_addr == ram_addr) {
274 return;
275 }
276 }
277 page = g_malloc(sizeof(HWPoisonPage));
278 page->ram_addr = ram_addr;
279 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
280 }
281
282 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
283 int *max_banks)
284 {
285 int r;
286
287 r = kvm_check_extension(s, KVM_CAP_MCE);
288 if (r > 0) {
289 *max_banks = r;
290 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
291 }
292 return -ENOSYS;
293 }
294
295 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
296 {
297 CPUX86State *env = &cpu->env;
298 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
299 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
300 uint64_t mcg_status = MCG_STATUS_MCIP;
301
302 if (code == BUS_MCEERR_AR) {
303 status |= MCI_STATUS_AR | 0x134;
304 mcg_status |= MCG_STATUS_EIPV;
305 } else {
306 status |= 0xc0;
307 mcg_status |= MCG_STATUS_RIPV;
308 }
309 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
310 (MCM_ADDR_PHYS << 6) | 0xc,
311 cpu_x86_support_mca_broadcast(env) ?
312 MCE_INJECT_BROADCAST : 0);
313 }
314
315 static void hardware_memory_error(void)
316 {
317 fprintf(stderr, "Hardware memory error!\n");
318 exit(1);
319 }
320
321 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
322 {
323 X86CPU *cpu = X86_CPU(c);
324 CPUX86State *env = &cpu->env;
325 ram_addr_t ram_addr;
326 hwaddr paddr;
327
328 if ((env->mcg_cap & MCG_SER_P) && addr
329 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
330 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
331 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
332 fprintf(stderr, "Hardware memory error for memory used by "
333 "QEMU itself instead of guest system!\n");
334 /* Hope we are lucky for AO MCE */
335 if (code == BUS_MCEERR_AO) {
336 return 0;
337 } else {
338 hardware_memory_error();
339 }
340 }
341 kvm_hwpoison_page_add(ram_addr);
342 kvm_mce_inject(cpu, paddr, code);
343 } else {
344 if (code == BUS_MCEERR_AO) {
345 return 0;
346 } else if (code == BUS_MCEERR_AR) {
347 hardware_memory_error();
348 } else {
349 return 1;
350 }
351 }
352 return 0;
353 }
354
355 int kvm_arch_on_sigbus(int code, void *addr)
356 {
357 X86CPU *cpu = X86_CPU(first_cpu);
358
359 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
360 ram_addr_t ram_addr;
361 hwaddr paddr;
362
363 /* Hope we are lucky for AO MCE */
364 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
365 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
366 addr, &paddr)) {
367 fprintf(stderr, "Hardware memory error for memory used by "
368 "QEMU itself instead of guest system!: %p\n", addr);
369 return 0;
370 }
371 kvm_hwpoison_page_add(ram_addr);
372 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
373 } else {
374 if (code == BUS_MCEERR_AO) {
375 return 0;
376 } else if (code == BUS_MCEERR_AR) {
377 hardware_memory_error();
378 } else {
379 return 1;
380 }
381 }
382 return 0;
383 }
384
385 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
386 {
387 CPUX86State *env = &cpu->env;
388
389 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
390 unsigned int bank, bank_num = env->mcg_cap & 0xff;
391 struct kvm_x86_mce mce;
392
393 env->exception_injected = -1;
394
395 /*
396 * There must be at least one bank in use if an MCE is pending.
397 * Find it and use its values for the event injection.
398 */
399 for (bank = 0; bank < bank_num; bank++) {
400 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
401 break;
402 }
403 }
404 assert(bank < bank_num);
405
406 mce.bank = bank;
407 mce.status = env->mce_banks[bank * 4 + 1];
408 mce.mcg_status = env->mcg_status;
409 mce.addr = env->mce_banks[bank * 4 + 2];
410 mce.misc = env->mce_banks[bank * 4 + 3];
411
412 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
413 }
414 return 0;
415 }
416
417 static void cpu_update_state(void *opaque, int running, RunState state)
418 {
419 CPUX86State *env = opaque;
420
421 if (running) {
422 env->tsc_valid = false;
423 }
424 }
425
426 unsigned long kvm_arch_vcpu_id(CPUState *cs)
427 {
428 X86CPU *cpu = X86_CPU(cs);
429 return cpu->env.cpuid_apic_id;
430 }
431
432 #ifndef KVM_CPUID_SIGNATURE_NEXT
433 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
434 #endif
435
436 static bool hyperv_hypercall_available(X86CPU *cpu)
437 {
438 return cpu->hyperv_vapic ||
439 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
440 }
441
442 static bool hyperv_enabled(X86CPU *cpu)
443 {
444 CPUState *cs = CPU(cpu);
445 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
446 (hyperv_hypercall_available(cpu) ||
447 cpu->hyperv_time ||
448 cpu->hyperv_relaxed_timing);
449 }
450
451 #define KVM_MAX_CPUID_ENTRIES 100
452
453 int kvm_arch_init_vcpu(CPUState *cs)
454 {
455 struct {
456 struct kvm_cpuid2 cpuid;
457 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
458 } QEMU_PACKED cpuid_data;
459 X86CPU *cpu = X86_CPU(cs);
460 CPUX86State *env = &cpu->env;
461 uint32_t limit, i, j, cpuid_i;
462 uint32_t unused;
463 struct kvm_cpuid_entry2 *c;
464 uint32_t signature[3];
465 int kvm_base = KVM_CPUID_SIGNATURE;
466 int r;
467
468 memset(&cpuid_data, 0, sizeof(cpuid_data));
469
470 cpuid_i = 0;
471
472 /* Paravirtualization CPUIDs */
473 if (hyperv_enabled(cpu)) {
474 c = &cpuid_data.entries[cpuid_i++];
475 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
476 memcpy(signature, "Microsoft Hv", 12);
477 c->eax = HYPERV_CPUID_MIN;
478 c->ebx = signature[0];
479 c->ecx = signature[1];
480 c->edx = signature[2];
481
482 c = &cpuid_data.entries[cpuid_i++];
483 c->function = HYPERV_CPUID_INTERFACE;
484 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
485 c->eax = signature[0];
486 c->ebx = 0;
487 c->ecx = 0;
488 c->edx = 0;
489
490 c = &cpuid_data.entries[cpuid_i++];
491 c->function = HYPERV_CPUID_VERSION;
492 c->eax = 0x00001bbc;
493 c->ebx = 0x00060001;
494
495 c = &cpuid_data.entries[cpuid_i++];
496 c->function = HYPERV_CPUID_FEATURES;
497 if (cpu->hyperv_relaxed_timing) {
498 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
499 }
500 if (cpu->hyperv_vapic) {
501 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
502 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
503 has_msr_hv_vapic = true;
504 }
505 if (cpu->hyperv_time &&
506 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
507 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
508 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
509 c->eax |= 0x200;
510 has_msr_hv_tsc = true;
511 }
512 c = &cpuid_data.entries[cpuid_i++];
513 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
514 if (cpu->hyperv_relaxed_timing) {
515 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
516 }
517 if (has_msr_hv_vapic) {
518 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
519 }
520 c->ebx = cpu->hyperv_spinlock_attempts;
521
522 c = &cpuid_data.entries[cpuid_i++];
523 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
524 c->eax = 0x40;
525 c->ebx = 0x40;
526
527 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
528 has_msr_hv_hypercall = true;
529 }
530
531 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
532 c = &cpuid_data.entries[cpuid_i++];
533 c->function = KVM_CPUID_SIGNATURE | kvm_base;
534 c->eax = 0;
535 c->ebx = signature[0];
536 c->ecx = signature[1];
537 c->edx = signature[2];
538
539 c = &cpuid_data.entries[cpuid_i++];
540 c->function = KVM_CPUID_FEATURES | kvm_base;
541 c->eax = env->features[FEAT_KVM];
542
543 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
544
545 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
546
547 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
548
549 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
550
551 for (i = 0; i <= limit; i++) {
552 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
553 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
554 abort();
555 }
556 c = &cpuid_data.entries[cpuid_i++];
557
558 switch (i) {
559 case 2: {
560 /* Keep reading function 2 till all the input is received */
561 int times;
562
563 c->function = i;
564 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
565 KVM_CPUID_FLAG_STATE_READ_NEXT;
566 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
567 times = c->eax & 0xff;
568
569 for (j = 1; j < times; ++j) {
570 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
571 fprintf(stderr, "cpuid_data is full, no space for "
572 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
573 abort();
574 }
575 c = &cpuid_data.entries[cpuid_i++];
576 c->function = i;
577 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
578 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
579 }
580 break;
581 }
582 case 4:
583 case 0xb:
584 case 0xd:
585 for (j = 0; ; j++) {
586 if (i == 0xd && j == 64) {
587 break;
588 }
589 c->function = i;
590 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
591 c->index = j;
592 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
593
594 if (i == 4 && c->eax == 0) {
595 break;
596 }
597 if (i == 0xb && !(c->ecx & 0xff00)) {
598 break;
599 }
600 if (i == 0xd && c->eax == 0) {
601 continue;
602 }
603 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
604 fprintf(stderr, "cpuid_data is full, no space for "
605 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
606 abort();
607 }
608 c = &cpuid_data.entries[cpuid_i++];
609 }
610 break;
611 default:
612 c->function = i;
613 c->flags = 0;
614 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
615 break;
616 }
617 }
618
619 if (limit >= 0x0a) {
620 uint32_t ver;
621
622 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
623 if ((ver & 0xff) > 0) {
624 has_msr_architectural_pmu = true;
625 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
626
627 /* Shouldn't be more than 32, since that's the number of bits
628 * available in EBX to tell us _which_ counters are available.
629 * Play it safe.
630 */
631 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
632 num_architectural_pmu_counters = MAX_GP_COUNTERS;
633 }
634 }
635 }
636
637 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
638
639 for (i = 0x80000000; i <= limit; i++) {
640 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
641 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
642 abort();
643 }
644 c = &cpuid_data.entries[cpuid_i++];
645
646 c->function = i;
647 c->flags = 0;
648 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
649 }
650
651 /* Call Centaur's CPUID instructions they are supported. */
652 if (env->cpuid_xlevel2 > 0) {
653 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
654
655 for (i = 0xC0000000; i <= limit; i++) {
656 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
657 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
658 abort();
659 }
660 c = &cpuid_data.entries[cpuid_i++];
661
662 c->function = i;
663 c->flags = 0;
664 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
665 }
666 }
667
668 cpuid_data.cpuid.nent = cpuid_i;
669
670 if (((env->cpuid_version >> 8)&0xF) >= 6
671 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
672 (CPUID_MCE | CPUID_MCA)
673 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
674 uint64_t mcg_cap;
675 int banks;
676 int ret;
677
678 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
679 if (ret < 0) {
680 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
681 return ret;
682 }
683
684 if (banks > MCE_BANKS_DEF) {
685 banks = MCE_BANKS_DEF;
686 }
687 mcg_cap &= MCE_CAP_DEF;
688 mcg_cap |= banks;
689 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
690 if (ret < 0) {
691 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
692 return ret;
693 }
694
695 env->mcg_cap = mcg_cap;
696 }
697
698 qemu_add_vm_change_state_handler(cpu_update_state, env);
699
700 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
701 if (c) {
702 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
703 !!(c->ecx & CPUID_EXT_SMX);
704 }
705
706 cpuid_data.cpuid.padding = 0;
707 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
708 if (r) {
709 return r;
710 }
711
712 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
713 if (r && env->tsc_khz) {
714 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
715 if (r < 0) {
716 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
717 return r;
718 }
719 }
720
721 if (kvm_has_xsave()) {
722 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
723 }
724
725 return 0;
726 }
727
728 void kvm_arch_reset_vcpu(X86CPU *cpu)
729 {
730 CPUX86State *env = &cpu->env;
731
732 env->exception_injected = -1;
733 env->interrupt_injected = -1;
734 env->xcr0 = 1;
735 if (kvm_irqchip_in_kernel()) {
736 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
737 KVM_MP_STATE_UNINITIALIZED;
738 } else {
739 env->mp_state = KVM_MP_STATE_RUNNABLE;
740 }
741 }
742
743 void kvm_arch_do_init_vcpu(X86CPU *cpu)
744 {
745 CPUX86State *env = &cpu->env;
746
747 /* APs get directly into wait-for-SIPI state. */
748 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
749 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
750 }
751 }
752
753 static int kvm_get_supported_msrs(KVMState *s)
754 {
755 static int kvm_supported_msrs;
756 int ret = 0;
757
758 /* first time */
759 if (kvm_supported_msrs == 0) {
760 struct kvm_msr_list msr_list, *kvm_msr_list;
761
762 kvm_supported_msrs = -1;
763
764 /* Obtain MSR list from KVM. These are the MSRs that we must
765 * save/restore */
766 msr_list.nmsrs = 0;
767 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
768 if (ret < 0 && ret != -E2BIG) {
769 return ret;
770 }
771 /* Old kernel modules had a bug and could write beyond the provided
772 memory. Allocate at least a safe amount of 1K. */
773 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
774 msr_list.nmsrs *
775 sizeof(msr_list.indices[0])));
776
777 kvm_msr_list->nmsrs = msr_list.nmsrs;
778 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
779 if (ret >= 0) {
780 int i;
781
782 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
783 if (kvm_msr_list->indices[i] == MSR_STAR) {
784 has_msr_star = true;
785 continue;
786 }
787 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
788 has_msr_hsave_pa = true;
789 continue;
790 }
791 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
792 has_msr_tsc_adjust = true;
793 continue;
794 }
795 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
796 has_msr_tsc_deadline = true;
797 continue;
798 }
799 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
800 has_msr_misc_enable = true;
801 continue;
802 }
803 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
804 has_msr_bndcfgs = true;
805 continue;
806 }
807 }
808 }
809
810 g_free(kvm_msr_list);
811 }
812
813 return ret;
814 }
815
816 int kvm_arch_init(KVMState *s)
817 {
818 uint64_t identity_base = 0xfffbc000;
819 uint64_t shadow_mem;
820 int ret;
821 struct utsname utsname;
822
823 ret = kvm_get_supported_msrs(s);
824 if (ret < 0) {
825 return ret;
826 }
827
828 uname(&utsname);
829 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
830
831 /*
832 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
833 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
834 * Since these must be part of guest physical memory, we need to allocate
835 * them, both by setting their start addresses in the kernel and by
836 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
837 *
838 * Older KVM versions may not support setting the identity map base. In
839 * that case we need to stick with the default, i.e. a 256K maximum BIOS
840 * size.
841 */
842 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
843 /* Allows up to 16M BIOSes. */
844 identity_base = 0xfeffc000;
845
846 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
847 if (ret < 0) {
848 return ret;
849 }
850 }
851
852 /* Set TSS base one page after EPT identity map. */
853 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
854 if (ret < 0) {
855 return ret;
856 }
857
858 /* Tell fw_cfg to notify the BIOS to reserve the range. */
859 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
860 if (ret < 0) {
861 fprintf(stderr, "e820_add_entry() table is full\n");
862 return ret;
863 }
864 qemu_register_reset(kvm_unpoison_all, NULL);
865
866 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
867 "kvm_shadow_mem", -1);
868 if (shadow_mem != -1) {
869 shadow_mem /= 4096;
870 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
871 if (ret < 0) {
872 return ret;
873 }
874 }
875 return 0;
876 }
877
878 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
879 {
880 lhs->selector = rhs->selector;
881 lhs->base = rhs->base;
882 lhs->limit = rhs->limit;
883 lhs->type = 3;
884 lhs->present = 1;
885 lhs->dpl = 3;
886 lhs->db = 0;
887 lhs->s = 1;
888 lhs->l = 0;
889 lhs->g = 0;
890 lhs->avl = 0;
891 lhs->unusable = 0;
892 }
893
894 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
895 {
896 unsigned flags = rhs->flags;
897 lhs->selector = rhs->selector;
898 lhs->base = rhs->base;
899 lhs->limit = rhs->limit;
900 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
901 lhs->present = (flags & DESC_P_MASK) != 0;
902 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
903 lhs->db = (flags >> DESC_B_SHIFT) & 1;
904 lhs->s = (flags & DESC_S_MASK) != 0;
905 lhs->l = (flags >> DESC_L_SHIFT) & 1;
906 lhs->g = (flags & DESC_G_MASK) != 0;
907 lhs->avl = (flags & DESC_AVL_MASK) != 0;
908 lhs->unusable = 0;
909 lhs->padding = 0;
910 }
911
912 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
913 {
914 lhs->selector = rhs->selector;
915 lhs->base = rhs->base;
916 lhs->limit = rhs->limit;
917 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
918 (rhs->present * DESC_P_MASK) |
919 (rhs->dpl << DESC_DPL_SHIFT) |
920 (rhs->db << DESC_B_SHIFT) |
921 (rhs->s * DESC_S_MASK) |
922 (rhs->l << DESC_L_SHIFT) |
923 (rhs->g * DESC_G_MASK) |
924 (rhs->avl * DESC_AVL_MASK);
925 }
926
927 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
928 {
929 if (set) {
930 *kvm_reg = *qemu_reg;
931 } else {
932 *qemu_reg = *kvm_reg;
933 }
934 }
935
936 static int kvm_getput_regs(X86CPU *cpu, int set)
937 {
938 CPUX86State *env = &cpu->env;
939 struct kvm_regs regs;
940 int ret = 0;
941
942 if (!set) {
943 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
944 if (ret < 0) {
945 return ret;
946 }
947 }
948
949 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
950 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
951 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
952 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
953 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
954 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
955 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
956 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
957 #ifdef TARGET_X86_64
958 kvm_getput_reg(&regs.r8, &env->regs[8], set);
959 kvm_getput_reg(&regs.r9, &env->regs[9], set);
960 kvm_getput_reg(&regs.r10, &env->regs[10], set);
961 kvm_getput_reg(&regs.r11, &env->regs[11], set);
962 kvm_getput_reg(&regs.r12, &env->regs[12], set);
963 kvm_getput_reg(&regs.r13, &env->regs[13], set);
964 kvm_getput_reg(&regs.r14, &env->regs[14], set);
965 kvm_getput_reg(&regs.r15, &env->regs[15], set);
966 #endif
967
968 kvm_getput_reg(&regs.rflags, &env->eflags, set);
969 kvm_getput_reg(&regs.rip, &env->eip, set);
970
971 if (set) {
972 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
973 }
974
975 return ret;
976 }
977
978 static int kvm_put_fpu(X86CPU *cpu)
979 {
980 CPUX86State *env = &cpu->env;
981 struct kvm_fpu fpu;
982 int i;
983
984 memset(&fpu, 0, sizeof fpu);
985 fpu.fsw = env->fpus & ~(7 << 11);
986 fpu.fsw |= (env->fpstt & 7) << 11;
987 fpu.fcw = env->fpuc;
988 fpu.last_opcode = env->fpop;
989 fpu.last_ip = env->fpip;
990 fpu.last_dp = env->fpdp;
991 for (i = 0; i < 8; ++i) {
992 fpu.ftwx |= (!env->fptags[i]) << i;
993 }
994 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
995 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
996 fpu.mxcsr = env->mxcsr;
997
998 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
999 }
1000
1001 #define XSAVE_FCW_FSW 0
1002 #define XSAVE_FTW_FOP 1
1003 #define XSAVE_CWD_RIP 2
1004 #define XSAVE_CWD_RDP 4
1005 #define XSAVE_MXCSR 6
1006 #define XSAVE_ST_SPACE 8
1007 #define XSAVE_XMM_SPACE 40
1008 #define XSAVE_XSTATE_BV 128
1009 #define XSAVE_YMMH_SPACE 144
1010 #define XSAVE_BNDREGS 240
1011 #define XSAVE_BNDCSR 256
1012
1013 static int kvm_put_xsave(X86CPU *cpu)
1014 {
1015 CPUX86State *env = &cpu->env;
1016 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1017 uint16_t cwd, swd, twd;
1018 int i, r;
1019
1020 if (!kvm_has_xsave()) {
1021 return kvm_put_fpu(cpu);
1022 }
1023
1024 memset(xsave, 0, sizeof(struct kvm_xsave));
1025 twd = 0;
1026 swd = env->fpus & ~(7 << 11);
1027 swd |= (env->fpstt & 7) << 11;
1028 cwd = env->fpuc;
1029 for (i = 0; i < 8; ++i) {
1030 twd |= (!env->fptags[i]) << i;
1031 }
1032 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1033 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1034 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1035 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1036 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1037 sizeof env->fpregs);
1038 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1039 sizeof env->xmm_regs);
1040 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1041 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1042 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1043 sizeof env->ymmh_regs);
1044 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1045 sizeof env->bnd_regs);
1046 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1047 sizeof(env->bndcs_regs));
1048 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1049 return r;
1050 }
1051
1052 static int kvm_put_xcrs(X86CPU *cpu)
1053 {
1054 CPUX86State *env = &cpu->env;
1055 struct kvm_xcrs xcrs;
1056
1057 if (!kvm_has_xcrs()) {
1058 return 0;
1059 }
1060
1061 xcrs.nr_xcrs = 1;
1062 xcrs.flags = 0;
1063 xcrs.xcrs[0].xcr = 0;
1064 xcrs.xcrs[0].value = env->xcr0;
1065 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1066 }
1067
1068 static int kvm_put_sregs(X86CPU *cpu)
1069 {
1070 CPUX86State *env = &cpu->env;
1071 struct kvm_sregs sregs;
1072
1073 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1074 if (env->interrupt_injected >= 0) {
1075 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1076 (uint64_t)1 << (env->interrupt_injected % 64);
1077 }
1078
1079 if ((env->eflags & VM_MASK)) {
1080 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1081 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1082 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1083 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1084 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1085 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1086 } else {
1087 set_seg(&sregs.cs, &env->segs[R_CS]);
1088 set_seg(&sregs.ds, &env->segs[R_DS]);
1089 set_seg(&sregs.es, &env->segs[R_ES]);
1090 set_seg(&sregs.fs, &env->segs[R_FS]);
1091 set_seg(&sregs.gs, &env->segs[R_GS]);
1092 set_seg(&sregs.ss, &env->segs[R_SS]);
1093 }
1094
1095 set_seg(&sregs.tr, &env->tr);
1096 set_seg(&sregs.ldt, &env->ldt);
1097
1098 sregs.idt.limit = env->idt.limit;
1099 sregs.idt.base = env->idt.base;
1100 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1101 sregs.gdt.limit = env->gdt.limit;
1102 sregs.gdt.base = env->gdt.base;
1103 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1104
1105 sregs.cr0 = env->cr[0];
1106 sregs.cr2 = env->cr[2];
1107 sregs.cr3 = env->cr[3];
1108 sregs.cr4 = env->cr[4];
1109
1110 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1111 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1112
1113 sregs.efer = env->efer;
1114
1115 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1116 }
1117
1118 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1119 uint32_t index, uint64_t value)
1120 {
1121 entry->index = index;
1122 entry->data = value;
1123 }
1124
1125 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1126 {
1127 CPUX86State *env = &cpu->env;
1128 struct {
1129 struct kvm_msrs info;
1130 struct kvm_msr_entry entries[1];
1131 } msr_data;
1132 struct kvm_msr_entry *msrs = msr_data.entries;
1133
1134 if (!has_msr_tsc_deadline) {
1135 return 0;
1136 }
1137
1138 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1139
1140 msr_data.info.nmsrs = 1;
1141
1142 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1143 }
1144
1145 /*
1146 * Provide a separate write service for the feature control MSR in order to
1147 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1148 * before writing any other state because forcibly leaving nested mode
1149 * invalidates the VCPU state.
1150 */
1151 static int kvm_put_msr_feature_control(X86CPU *cpu)
1152 {
1153 struct {
1154 struct kvm_msrs info;
1155 struct kvm_msr_entry entry;
1156 } msr_data;
1157
1158 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1159 cpu->env.msr_ia32_feature_control);
1160 msr_data.info.nmsrs = 1;
1161 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1162 }
1163
1164 static int kvm_put_msrs(X86CPU *cpu, int level)
1165 {
1166 CPUX86State *env = &cpu->env;
1167 struct {
1168 struct kvm_msrs info;
1169 struct kvm_msr_entry entries[100];
1170 } msr_data;
1171 struct kvm_msr_entry *msrs = msr_data.entries;
1172 int n = 0, i;
1173
1174 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1175 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1176 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1177 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1178 if (has_msr_star) {
1179 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1180 }
1181 if (has_msr_hsave_pa) {
1182 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1183 }
1184 if (has_msr_tsc_adjust) {
1185 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1186 }
1187 if (has_msr_misc_enable) {
1188 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1189 env->msr_ia32_misc_enable);
1190 }
1191 if (has_msr_bndcfgs) {
1192 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1193 }
1194 #ifdef TARGET_X86_64
1195 if (lm_capable_kernel) {
1196 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1197 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1198 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1199 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1200 }
1201 #endif
1202 /*
1203 * The following MSRs have side effects on the guest or are too heavy
1204 * for normal writeback. Limit them to reset or full state updates.
1205 */
1206 if (level >= KVM_PUT_RESET_STATE) {
1207 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1208 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1209 env->system_time_msr);
1210 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1211 if (has_msr_async_pf_en) {
1212 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1213 env->async_pf_en_msr);
1214 }
1215 if (has_msr_pv_eoi_en) {
1216 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1217 env->pv_eoi_en_msr);
1218 }
1219 if (has_msr_kvm_steal_time) {
1220 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1221 env->steal_time_msr);
1222 }
1223 if (has_msr_architectural_pmu) {
1224 /* Stop the counter. */
1225 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1226 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1227
1228 /* Set the counter values. */
1229 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1230 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1231 env->msr_fixed_counters[i]);
1232 }
1233 for (i = 0; i < num_architectural_pmu_counters; i++) {
1234 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1235 env->msr_gp_counters[i]);
1236 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1237 env->msr_gp_evtsel[i]);
1238 }
1239 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1240 env->msr_global_status);
1241 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1242 env->msr_global_ovf_ctrl);
1243
1244 /* Now start the PMU. */
1245 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1246 env->msr_fixed_ctr_ctrl);
1247 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1248 env->msr_global_ctrl);
1249 }
1250 if (has_msr_hv_hypercall) {
1251 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1252 env->msr_hv_guest_os_id);
1253 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1254 env->msr_hv_hypercall);
1255 }
1256 if (has_msr_hv_vapic) {
1257 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1258 env->msr_hv_vapic);
1259 }
1260 if (has_msr_hv_tsc) {
1261 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1262 env->msr_hv_tsc);
1263 }
1264
1265 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1266 * kvm_put_msr_feature_control. */
1267 }
1268 if (env->mcg_cap) {
1269 int i;
1270
1271 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1272 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1273 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1274 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1275 }
1276 }
1277
1278 msr_data.info.nmsrs = n;
1279
1280 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1281
1282 }
1283
1284
1285 static int kvm_get_fpu(X86CPU *cpu)
1286 {
1287 CPUX86State *env = &cpu->env;
1288 struct kvm_fpu fpu;
1289 int i, ret;
1290
1291 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1292 if (ret < 0) {
1293 return ret;
1294 }
1295
1296 env->fpstt = (fpu.fsw >> 11) & 7;
1297 env->fpus = fpu.fsw;
1298 env->fpuc = fpu.fcw;
1299 env->fpop = fpu.last_opcode;
1300 env->fpip = fpu.last_ip;
1301 env->fpdp = fpu.last_dp;
1302 for (i = 0; i < 8; ++i) {
1303 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1304 }
1305 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1306 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1307 env->mxcsr = fpu.mxcsr;
1308
1309 return 0;
1310 }
1311
1312 static int kvm_get_xsave(X86CPU *cpu)
1313 {
1314 CPUX86State *env = &cpu->env;
1315 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1316 int ret, i;
1317 uint16_t cwd, swd, twd;
1318
1319 if (!kvm_has_xsave()) {
1320 return kvm_get_fpu(cpu);
1321 }
1322
1323 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1324 if (ret < 0) {
1325 return ret;
1326 }
1327
1328 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1329 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1330 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1331 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1332 env->fpstt = (swd >> 11) & 7;
1333 env->fpus = swd;
1334 env->fpuc = cwd;
1335 for (i = 0; i < 8; ++i) {
1336 env->fptags[i] = !((twd >> i) & 1);
1337 }
1338 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1339 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1340 env->mxcsr = xsave->region[XSAVE_MXCSR];
1341 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1342 sizeof env->fpregs);
1343 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1344 sizeof env->xmm_regs);
1345 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1346 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1347 sizeof env->ymmh_regs);
1348 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1349 sizeof env->bnd_regs);
1350 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1351 sizeof(env->bndcs_regs));
1352 return 0;
1353 }
1354
1355 static int kvm_get_xcrs(X86CPU *cpu)
1356 {
1357 CPUX86State *env = &cpu->env;
1358 int i, ret;
1359 struct kvm_xcrs xcrs;
1360
1361 if (!kvm_has_xcrs()) {
1362 return 0;
1363 }
1364
1365 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1366 if (ret < 0) {
1367 return ret;
1368 }
1369
1370 for (i = 0; i < xcrs.nr_xcrs; i++) {
1371 /* Only support xcr0 now */
1372 if (xcrs.xcrs[i].xcr == 0) {
1373 env->xcr0 = xcrs.xcrs[i].value;
1374 break;
1375 }
1376 }
1377 return 0;
1378 }
1379
1380 static int kvm_get_sregs(X86CPU *cpu)
1381 {
1382 CPUX86State *env = &cpu->env;
1383 struct kvm_sregs sregs;
1384 uint32_t hflags;
1385 int bit, i, ret;
1386
1387 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1388 if (ret < 0) {
1389 return ret;
1390 }
1391
1392 /* There can only be one pending IRQ set in the bitmap at a time, so try
1393 to find it and save its number instead (-1 for none). */
1394 env->interrupt_injected = -1;
1395 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1396 if (sregs.interrupt_bitmap[i]) {
1397 bit = ctz64(sregs.interrupt_bitmap[i]);
1398 env->interrupt_injected = i * 64 + bit;
1399 break;
1400 }
1401 }
1402
1403 get_seg(&env->segs[R_CS], &sregs.cs);
1404 get_seg(&env->segs[R_DS], &sregs.ds);
1405 get_seg(&env->segs[R_ES], &sregs.es);
1406 get_seg(&env->segs[R_FS], &sregs.fs);
1407 get_seg(&env->segs[R_GS], &sregs.gs);
1408 get_seg(&env->segs[R_SS], &sregs.ss);
1409
1410 get_seg(&env->tr, &sregs.tr);
1411 get_seg(&env->ldt, &sregs.ldt);
1412
1413 env->idt.limit = sregs.idt.limit;
1414 env->idt.base = sregs.idt.base;
1415 env->gdt.limit = sregs.gdt.limit;
1416 env->gdt.base = sregs.gdt.base;
1417
1418 env->cr[0] = sregs.cr0;
1419 env->cr[2] = sregs.cr2;
1420 env->cr[3] = sregs.cr3;
1421 env->cr[4] = sregs.cr4;
1422
1423 env->efer = sregs.efer;
1424
1425 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1426
1427 #define HFLAG_COPY_MASK \
1428 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1429 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1430 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1431 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1432
1433 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1434 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1435 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1436 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1437 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1438 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1439 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1440
1441 if (env->efer & MSR_EFER_LMA) {
1442 hflags |= HF_LMA_MASK;
1443 }
1444
1445 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1446 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1447 } else {
1448 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1449 (DESC_B_SHIFT - HF_CS32_SHIFT);
1450 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1451 (DESC_B_SHIFT - HF_SS32_SHIFT);
1452 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1453 !(hflags & HF_CS32_MASK)) {
1454 hflags |= HF_ADDSEG_MASK;
1455 } else {
1456 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1457 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1458 }
1459 }
1460 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1461
1462 return 0;
1463 }
1464
1465 static int kvm_get_msrs(X86CPU *cpu)
1466 {
1467 CPUX86State *env = &cpu->env;
1468 struct {
1469 struct kvm_msrs info;
1470 struct kvm_msr_entry entries[100];
1471 } msr_data;
1472 struct kvm_msr_entry *msrs = msr_data.entries;
1473 int ret, i, n;
1474
1475 n = 0;
1476 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1477 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1478 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1479 msrs[n++].index = MSR_PAT;
1480 if (has_msr_star) {
1481 msrs[n++].index = MSR_STAR;
1482 }
1483 if (has_msr_hsave_pa) {
1484 msrs[n++].index = MSR_VM_HSAVE_PA;
1485 }
1486 if (has_msr_tsc_adjust) {
1487 msrs[n++].index = MSR_TSC_ADJUST;
1488 }
1489 if (has_msr_tsc_deadline) {
1490 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1491 }
1492 if (has_msr_misc_enable) {
1493 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1494 }
1495 if (has_msr_feature_control) {
1496 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1497 }
1498 if (has_msr_bndcfgs) {
1499 msrs[n++].index = MSR_IA32_BNDCFGS;
1500 }
1501
1502 if (!env->tsc_valid) {
1503 msrs[n++].index = MSR_IA32_TSC;
1504 env->tsc_valid = !runstate_is_running();
1505 }
1506
1507 #ifdef TARGET_X86_64
1508 if (lm_capable_kernel) {
1509 msrs[n++].index = MSR_CSTAR;
1510 msrs[n++].index = MSR_KERNELGSBASE;
1511 msrs[n++].index = MSR_FMASK;
1512 msrs[n++].index = MSR_LSTAR;
1513 }
1514 #endif
1515 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1516 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1517 if (has_msr_async_pf_en) {
1518 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1519 }
1520 if (has_msr_pv_eoi_en) {
1521 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1522 }
1523 if (has_msr_kvm_steal_time) {
1524 msrs[n++].index = MSR_KVM_STEAL_TIME;
1525 }
1526 if (has_msr_architectural_pmu) {
1527 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1528 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1529 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1530 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1531 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1532 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1533 }
1534 for (i = 0; i < num_architectural_pmu_counters; i++) {
1535 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1536 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1537 }
1538 }
1539
1540 if (env->mcg_cap) {
1541 msrs[n++].index = MSR_MCG_STATUS;
1542 msrs[n++].index = MSR_MCG_CTL;
1543 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1544 msrs[n++].index = MSR_MC0_CTL + i;
1545 }
1546 }
1547
1548 if (has_msr_hv_hypercall) {
1549 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1550 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1551 }
1552 if (has_msr_hv_vapic) {
1553 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1554 }
1555 if (has_msr_hv_tsc) {
1556 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1557 }
1558
1559 msr_data.info.nmsrs = n;
1560 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1561 if (ret < 0) {
1562 return ret;
1563 }
1564
1565 for (i = 0; i < ret; i++) {
1566 uint32_t index = msrs[i].index;
1567 switch (index) {
1568 case MSR_IA32_SYSENTER_CS:
1569 env->sysenter_cs = msrs[i].data;
1570 break;
1571 case MSR_IA32_SYSENTER_ESP:
1572 env->sysenter_esp = msrs[i].data;
1573 break;
1574 case MSR_IA32_SYSENTER_EIP:
1575 env->sysenter_eip = msrs[i].data;
1576 break;
1577 case MSR_PAT:
1578 env->pat = msrs[i].data;
1579 break;
1580 case MSR_STAR:
1581 env->star = msrs[i].data;
1582 break;
1583 #ifdef TARGET_X86_64
1584 case MSR_CSTAR:
1585 env->cstar = msrs[i].data;
1586 break;
1587 case MSR_KERNELGSBASE:
1588 env->kernelgsbase = msrs[i].data;
1589 break;
1590 case MSR_FMASK:
1591 env->fmask = msrs[i].data;
1592 break;
1593 case MSR_LSTAR:
1594 env->lstar = msrs[i].data;
1595 break;
1596 #endif
1597 case MSR_IA32_TSC:
1598 env->tsc = msrs[i].data;
1599 break;
1600 case MSR_TSC_ADJUST:
1601 env->tsc_adjust = msrs[i].data;
1602 break;
1603 case MSR_IA32_TSCDEADLINE:
1604 env->tsc_deadline = msrs[i].data;
1605 break;
1606 case MSR_VM_HSAVE_PA:
1607 env->vm_hsave = msrs[i].data;
1608 break;
1609 case MSR_KVM_SYSTEM_TIME:
1610 env->system_time_msr = msrs[i].data;
1611 break;
1612 case MSR_KVM_WALL_CLOCK:
1613 env->wall_clock_msr = msrs[i].data;
1614 break;
1615 case MSR_MCG_STATUS:
1616 env->mcg_status = msrs[i].data;
1617 break;
1618 case MSR_MCG_CTL:
1619 env->mcg_ctl = msrs[i].data;
1620 break;
1621 case MSR_IA32_MISC_ENABLE:
1622 env->msr_ia32_misc_enable = msrs[i].data;
1623 break;
1624 case MSR_IA32_FEATURE_CONTROL:
1625 env->msr_ia32_feature_control = msrs[i].data;
1626 break;
1627 case MSR_IA32_BNDCFGS:
1628 env->msr_bndcfgs = msrs[i].data;
1629 break;
1630 default:
1631 if (msrs[i].index >= MSR_MC0_CTL &&
1632 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1633 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1634 }
1635 break;
1636 case MSR_KVM_ASYNC_PF_EN:
1637 env->async_pf_en_msr = msrs[i].data;
1638 break;
1639 case MSR_KVM_PV_EOI_EN:
1640 env->pv_eoi_en_msr = msrs[i].data;
1641 break;
1642 case MSR_KVM_STEAL_TIME:
1643 env->steal_time_msr = msrs[i].data;
1644 break;
1645 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1646 env->msr_fixed_ctr_ctrl = msrs[i].data;
1647 break;
1648 case MSR_CORE_PERF_GLOBAL_CTRL:
1649 env->msr_global_ctrl = msrs[i].data;
1650 break;
1651 case MSR_CORE_PERF_GLOBAL_STATUS:
1652 env->msr_global_status = msrs[i].data;
1653 break;
1654 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1655 env->msr_global_ovf_ctrl = msrs[i].data;
1656 break;
1657 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1658 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1659 break;
1660 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1661 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1662 break;
1663 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1664 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1665 break;
1666 case HV_X64_MSR_HYPERCALL:
1667 env->msr_hv_hypercall = msrs[i].data;
1668 break;
1669 case HV_X64_MSR_GUEST_OS_ID:
1670 env->msr_hv_guest_os_id = msrs[i].data;
1671 break;
1672 case HV_X64_MSR_APIC_ASSIST_PAGE:
1673 env->msr_hv_vapic = msrs[i].data;
1674 break;
1675 case HV_X64_MSR_REFERENCE_TSC:
1676 env->msr_hv_tsc = msrs[i].data;
1677 break;
1678 }
1679 }
1680
1681 return 0;
1682 }
1683
1684 static int kvm_put_mp_state(X86CPU *cpu)
1685 {
1686 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1687
1688 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1689 }
1690
1691 static int kvm_get_mp_state(X86CPU *cpu)
1692 {
1693 CPUState *cs = CPU(cpu);
1694 CPUX86State *env = &cpu->env;
1695 struct kvm_mp_state mp_state;
1696 int ret;
1697
1698 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1699 if (ret < 0) {
1700 return ret;
1701 }
1702 env->mp_state = mp_state.mp_state;
1703 if (kvm_irqchip_in_kernel()) {
1704 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1705 }
1706 return 0;
1707 }
1708
1709 static int kvm_get_apic(X86CPU *cpu)
1710 {
1711 DeviceState *apic = cpu->apic_state;
1712 struct kvm_lapic_state kapic;
1713 int ret;
1714
1715 if (apic && kvm_irqchip_in_kernel()) {
1716 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1717 if (ret < 0) {
1718 return ret;
1719 }
1720
1721 kvm_get_apic_state(apic, &kapic);
1722 }
1723 return 0;
1724 }
1725
1726 static int kvm_put_apic(X86CPU *cpu)
1727 {
1728 DeviceState *apic = cpu->apic_state;
1729 struct kvm_lapic_state kapic;
1730
1731 if (apic && kvm_irqchip_in_kernel()) {
1732 kvm_put_apic_state(apic, &kapic);
1733
1734 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1735 }
1736 return 0;
1737 }
1738
1739 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1740 {
1741 CPUX86State *env = &cpu->env;
1742 struct kvm_vcpu_events events;
1743
1744 if (!kvm_has_vcpu_events()) {
1745 return 0;
1746 }
1747
1748 events.exception.injected = (env->exception_injected >= 0);
1749 events.exception.nr = env->exception_injected;
1750 events.exception.has_error_code = env->has_error_code;
1751 events.exception.error_code = env->error_code;
1752 events.exception.pad = 0;
1753
1754 events.interrupt.injected = (env->interrupt_injected >= 0);
1755 events.interrupt.nr = env->interrupt_injected;
1756 events.interrupt.soft = env->soft_interrupt;
1757
1758 events.nmi.injected = env->nmi_injected;
1759 events.nmi.pending = env->nmi_pending;
1760 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1761 events.nmi.pad = 0;
1762
1763 events.sipi_vector = env->sipi_vector;
1764
1765 events.flags = 0;
1766 if (level >= KVM_PUT_RESET_STATE) {
1767 events.flags |=
1768 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1769 }
1770
1771 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1772 }
1773
1774 static int kvm_get_vcpu_events(X86CPU *cpu)
1775 {
1776 CPUX86State *env = &cpu->env;
1777 struct kvm_vcpu_events events;
1778 int ret;
1779
1780 if (!kvm_has_vcpu_events()) {
1781 return 0;
1782 }
1783
1784 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1785 if (ret < 0) {
1786 return ret;
1787 }
1788 env->exception_injected =
1789 events.exception.injected ? events.exception.nr : -1;
1790 env->has_error_code = events.exception.has_error_code;
1791 env->error_code = events.exception.error_code;
1792
1793 env->interrupt_injected =
1794 events.interrupt.injected ? events.interrupt.nr : -1;
1795 env->soft_interrupt = events.interrupt.soft;
1796
1797 env->nmi_injected = events.nmi.injected;
1798 env->nmi_pending = events.nmi.pending;
1799 if (events.nmi.masked) {
1800 env->hflags2 |= HF2_NMI_MASK;
1801 } else {
1802 env->hflags2 &= ~HF2_NMI_MASK;
1803 }
1804
1805 env->sipi_vector = events.sipi_vector;
1806
1807 return 0;
1808 }
1809
1810 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1811 {
1812 CPUState *cs = CPU(cpu);
1813 CPUX86State *env = &cpu->env;
1814 int ret = 0;
1815 unsigned long reinject_trap = 0;
1816
1817 if (!kvm_has_vcpu_events()) {
1818 if (env->exception_injected == 1) {
1819 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1820 } else if (env->exception_injected == 3) {
1821 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1822 }
1823 env->exception_injected = -1;
1824 }
1825
1826 /*
1827 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1828 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1829 * by updating the debug state once again if single-stepping is on.
1830 * Another reason to call kvm_update_guest_debug here is a pending debug
1831 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1832 * reinject them via SET_GUEST_DEBUG.
1833 */
1834 if (reinject_trap ||
1835 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1836 ret = kvm_update_guest_debug(cs, reinject_trap);
1837 }
1838 return ret;
1839 }
1840
1841 static int kvm_put_debugregs(X86CPU *cpu)
1842 {
1843 CPUX86State *env = &cpu->env;
1844 struct kvm_debugregs dbgregs;
1845 int i;
1846
1847 if (!kvm_has_debugregs()) {
1848 return 0;
1849 }
1850
1851 for (i = 0; i < 4; i++) {
1852 dbgregs.db[i] = env->dr[i];
1853 }
1854 dbgregs.dr6 = env->dr[6];
1855 dbgregs.dr7 = env->dr[7];
1856 dbgregs.flags = 0;
1857
1858 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1859 }
1860
1861 static int kvm_get_debugregs(X86CPU *cpu)
1862 {
1863 CPUX86State *env = &cpu->env;
1864 struct kvm_debugregs dbgregs;
1865 int i, ret;
1866
1867 if (!kvm_has_debugregs()) {
1868 return 0;
1869 }
1870
1871 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1872 if (ret < 0) {
1873 return ret;
1874 }
1875 for (i = 0; i < 4; i++) {
1876 env->dr[i] = dbgregs.db[i];
1877 }
1878 env->dr[4] = env->dr[6] = dbgregs.dr6;
1879 env->dr[5] = env->dr[7] = dbgregs.dr7;
1880
1881 return 0;
1882 }
1883
1884 int kvm_arch_put_registers(CPUState *cpu, int level)
1885 {
1886 X86CPU *x86_cpu = X86_CPU(cpu);
1887 int ret;
1888
1889 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1890
1891 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
1892 ret = kvm_put_msr_feature_control(x86_cpu);
1893 if (ret < 0) {
1894 return ret;
1895 }
1896 }
1897
1898 ret = kvm_getput_regs(x86_cpu, 1);
1899 if (ret < 0) {
1900 return ret;
1901 }
1902 ret = kvm_put_xsave(x86_cpu);
1903 if (ret < 0) {
1904 return ret;
1905 }
1906 ret = kvm_put_xcrs(x86_cpu);
1907 if (ret < 0) {
1908 return ret;
1909 }
1910 ret = kvm_put_sregs(x86_cpu);
1911 if (ret < 0) {
1912 return ret;
1913 }
1914 /* must be before kvm_put_msrs */
1915 ret = kvm_inject_mce_oldstyle(x86_cpu);
1916 if (ret < 0) {
1917 return ret;
1918 }
1919 ret = kvm_put_msrs(x86_cpu, level);
1920 if (ret < 0) {
1921 return ret;
1922 }
1923 if (level >= KVM_PUT_RESET_STATE) {
1924 ret = kvm_put_mp_state(x86_cpu);
1925 if (ret < 0) {
1926 return ret;
1927 }
1928 ret = kvm_put_apic(x86_cpu);
1929 if (ret < 0) {
1930 return ret;
1931 }
1932 }
1933
1934 ret = kvm_put_tscdeadline_msr(x86_cpu);
1935 if (ret < 0) {
1936 return ret;
1937 }
1938
1939 ret = kvm_put_vcpu_events(x86_cpu, level);
1940 if (ret < 0) {
1941 return ret;
1942 }
1943 ret = kvm_put_debugregs(x86_cpu);
1944 if (ret < 0) {
1945 return ret;
1946 }
1947 /* must be last */
1948 ret = kvm_guest_debug_workarounds(x86_cpu);
1949 if (ret < 0) {
1950 return ret;
1951 }
1952 return 0;
1953 }
1954
1955 int kvm_arch_get_registers(CPUState *cs)
1956 {
1957 X86CPU *cpu = X86_CPU(cs);
1958 int ret;
1959
1960 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1961
1962 ret = kvm_getput_regs(cpu, 0);
1963 if (ret < 0) {
1964 return ret;
1965 }
1966 ret = kvm_get_xsave(cpu);
1967 if (ret < 0) {
1968 return ret;
1969 }
1970 ret = kvm_get_xcrs(cpu);
1971 if (ret < 0) {
1972 return ret;
1973 }
1974 ret = kvm_get_sregs(cpu);
1975 if (ret < 0) {
1976 return ret;
1977 }
1978 ret = kvm_get_msrs(cpu);
1979 if (ret < 0) {
1980 return ret;
1981 }
1982 ret = kvm_get_mp_state(cpu);
1983 if (ret < 0) {
1984 return ret;
1985 }
1986 ret = kvm_get_apic(cpu);
1987 if (ret < 0) {
1988 return ret;
1989 }
1990 ret = kvm_get_vcpu_events(cpu);
1991 if (ret < 0) {
1992 return ret;
1993 }
1994 ret = kvm_get_debugregs(cpu);
1995 if (ret < 0) {
1996 return ret;
1997 }
1998 return 0;
1999 }
2000
2001 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2002 {
2003 X86CPU *x86_cpu = X86_CPU(cpu);
2004 CPUX86State *env = &x86_cpu->env;
2005 int ret;
2006
2007 /* Inject NMI */
2008 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2009 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2010 DPRINTF("injected NMI\n");
2011 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2012 if (ret < 0) {
2013 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2014 strerror(-ret));
2015 }
2016 }
2017
2018 /* Force the VCPU out of its inner loop to process any INIT requests
2019 * or (for userspace APIC, but it is cheap to combine the checks here)
2020 * pending TPR access reports.
2021 */
2022 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2023 cpu->exit_request = 1;
2024 }
2025
2026 if (!kvm_irqchip_in_kernel()) {
2027 /* Try to inject an interrupt if the guest can accept it */
2028 if (run->ready_for_interrupt_injection &&
2029 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2030 (env->eflags & IF_MASK)) {
2031 int irq;
2032
2033 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2034 irq = cpu_get_pic_interrupt(env);
2035 if (irq >= 0) {
2036 struct kvm_interrupt intr;
2037
2038 intr.irq = irq;
2039 DPRINTF("injected interrupt %d\n", irq);
2040 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2041 if (ret < 0) {
2042 fprintf(stderr,
2043 "KVM: injection failed, interrupt lost (%s)\n",
2044 strerror(-ret));
2045 }
2046 }
2047 }
2048
2049 /* If we have an interrupt but the guest is not ready to receive an
2050 * interrupt, request an interrupt window exit. This will
2051 * cause a return to userspace as soon as the guest is ready to
2052 * receive interrupts. */
2053 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2054 run->request_interrupt_window = 1;
2055 } else {
2056 run->request_interrupt_window = 0;
2057 }
2058
2059 DPRINTF("setting tpr\n");
2060 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2061 }
2062 }
2063
2064 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2065 {
2066 X86CPU *x86_cpu = X86_CPU(cpu);
2067 CPUX86State *env = &x86_cpu->env;
2068
2069 if (run->if_flag) {
2070 env->eflags |= IF_MASK;
2071 } else {
2072 env->eflags &= ~IF_MASK;
2073 }
2074 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2075 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2076 }
2077
2078 int kvm_arch_process_async_events(CPUState *cs)
2079 {
2080 X86CPU *cpu = X86_CPU(cs);
2081 CPUX86State *env = &cpu->env;
2082
2083 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2084 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2085 assert(env->mcg_cap);
2086
2087 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2088
2089 kvm_cpu_synchronize_state(cs);
2090
2091 if (env->exception_injected == EXCP08_DBLE) {
2092 /* this means triple fault */
2093 qemu_system_reset_request();
2094 cs->exit_request = 1;
2095 return 0;
2096 }
2097 env->exception_injected = EXCP12_MCHK;
2098 env->has_error_code = 0;
2099
2100 cs->halted = 0;
2101 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2102 env->mp_state = KVM_MP_STATE_RUNNABLE;
2103 }
2104 }
2105
2106 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2107 kvm_cpu_synchronize_state(cs);
2108 do_cpu_init(cpu);
2109 }
2110
2111 if (kvm_irqchip_in_kernel()) {
2112 return 0;
2113 }
2114
2115 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2116 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2117 apic_poll_irq(cpu->apic_state);
2118 }
2119 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2120 (env->eflags & IF_MASK)) ||
2121 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2122 cs->halted = 0;
2123 }
2124 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2125 kvm_cpu_synchronize_state(cs);
2126 do_cpu_sipi(cpu);
2127 }
2128 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2129 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2130 kvm_cpu_synchronize_state(cs);
2131 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2132 env->tpr_access_type);
2133 }
2134
2135 return cs->halted;
2136 }
2137
2138 static int kvm_handle_halt(X86CPU *cpu)
2139 {
2140 CPUState *cs = CPU(cpu);
2141 CPUX86State *env = &cpu->env;
2142
2143 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2144 (env->eflags & IF_MASK)) &&
2145 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2146 cs->halted = 1;
2147 return EXCP_HLT;
2148 }
2149
2150 return 0;
2151 }
2152
2153 static int kvm_handle_tpr_access(X86CPU *cpu)
2154 {
2155 CPUState *cs = CPU(cpu);
2156 struct kvm_run *run = cs->kvm_run;
2157
2158 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2159 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2160 : TPR_ACCESS_READ);
2161 return 1;
2162 }
2163
2164 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2165 {
2166 static const uint8_t int3 = 0xcc;
2167
2168 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2169 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2170 return -EINVAL;
2171 }
2172 return 0;
2173 }
2174
2175 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2176 {
2177 uint8_t int3;
2178
2179 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2180 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2181 return -EINVAL;
2182 }
2183 return 0;
2184 }
2185
2186 static struct {
2187 target_ulong addr;
2188 int len;
2189 int type;
2190 } hw_breakpoint[4];
2191
2192 static int nb_hw_breakpoint;
2193
2194 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2195 {
2196 int n;
2197
2198 for (n = 0; n < nb_hw_breakpoint; n++) {
2199 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2200 (hw_breakpoint[n].len == len || len == -1)) {
2201 return n;
2202 }
2203 }
2204 return -1;
2205 }
2206
2207 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2208 target_ulong len, int type)
2209 {
2210 switch (type) {
2211 case GDB_BREAKPOINT_HW:
2212 len = 1;
2213 break;
2214 case GDB_WATCHPOINT_WRITE:
2215 case GDB_WATCHPOINT_ACCESS:
2216 switch (len) {
2217 case 1:
2218 break;
2219 case 2:
2220 case 4:
2221 case 8:
2222 if (addr & (len - 1)) {
2223 return -EINVAL;
2224 }
2225 break;
2226 default:
2227 return -EINVAL;
2228 }
2229 break;
2230 default:
2231 return -ENOSYS;
2232 }
2233
2234 if (nb_hw_breakpoint == 4) {
2235 return -ENOBUFS;
2236 }
2237 if (find_hw_breakpoint(addr, len, type) >= 0) {
2238 return -EEXIST;
2239 }
2240 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2241 hw_breakpoint[nb_hw_breakpoint].len = len;
2242 hw_breakpoint[nb_hw_breakpoint].type = type;
2243 nb_hw_breakpoint++;
2244
2245 return 0;
2246 }
2247
2248 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2249 target_ulong len, int type)
2250 {
2251 int n;
2252
2253 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2254 if (n < 0) {
2255 return -ENOENT;
2256 }
2257 nb_hw_breakpoint--;
2258 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2259
2260 return 0;
2261 }
2262
2263 void kvm_arch_remove_all_hw_breakpoints(void)
2264 {
2265 nb_hw_breakpoint = 0;
2266 }
2267
2268 static CPUWatchpoint hw_watchpoint;
2269
2270 static int kvm_handle_debug(X86CPU *cpu,
2271 struct kvm_debug_exit_arch *arch_info)
2272 {
2273 CPUState *cs = CPU(cpu);
2274 CPUX86State *env = &cpu->env;
2275 int ret = 0;
2276 int n;
2277
2278 if (arch_info->exception == 1) {
2279 if (arch_info->dr6 & (1 << 14)) {
2280 if (cs->singlestep_enabled) {
2281 ret = EXCP_DEBUG;
2282 }
2283 } else {
2284 for (n = 0; n < 4; n++) {
2285 if (arch_info->dr6 & (1 << n)) {
2286 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2287 case 0x0:
2288 ret = EXCP_DEBUG;
2289 break;
2290 case 0x1:
2291 ret = EXCP_DEBUG;
2292 cs->watchpoint_hit = &hw_watchpoint;
2293 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2294 hw_watchpoint.flags = BP_MEM_WRITE;
2295 break;
2296 case 0x3:
2297 ret = EXCP_DEBUG;
2298 cs->watchpoint_hit = &hw_watchpoint;
2299 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2300 hw_watchpoint.flags = BP_MEM_ACCESS;
2301 break;
2302 }
2303 }
2304 }
2305 }
2306 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2307 ret = EXCP_DEBUG;
2308 }
2309 if (ret == 0) {
2310 cpu_synchronize_state(cs);
2311 assert(env->exception_injected == -1);
2312
2313 /* pass to guest */
2314 env->exception_injected = arch_info->exception;
2315 env->has_error_code = 0;
2316 }
2317
2318 return ret;
2319 }
2320
2321 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2322 {
2323 const uint8_t type_code[] = {
2324 [GDB_BREAKPOINT_HW] = 0x0,
2325 [GDB_WATCHPOINT_WRITE] = 0x1,
2326 [GDB_WATCHPOINT_ACCESS] = 0x3
2327 };
2328 const uint8_t len_code[] = {
2329 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2330 };
2331 int n;
2332
2333 if (kvm_sw_breakpoints_active(cpu)) {
2334 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2335 }
2336 if (nb_hw_breakpoint > 0) {
2337 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2338 dbg->arch.debugreg[7] = 0x0600;
2339 for (n = 0; n < nb_hw_breakpoint; n++) {
2340 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2341 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2342 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2343 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2344 }
2345 }
2346 }
2347
2348 static bool host_supports_vmx(void)
2349 {
2350 uint32_t ecx, unused;
2351
2352 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2353 return ecx & CPUID_EXT_VMX;
2354 }
2355
2356 #define VMX_INVALID_GUEST_STATE 0x80000021
2357
2358 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2359 {
2360 X86CPU *cpu = X86_CPU(cs);
2361 uint64_t code;
2362 int ret;
2363
2364 switch (run->exit_reason) {
2365 case KVM_EXIT_HLT:
2366 DPRINTF("handle_hlt\n");
2367 ret = kvm_handle_halt(cpu);
2368 break;
2369 case KVM_EXIT_SET_TPR:
2370 ret = 0;
2371 break;
2372 case KVM_EXIT_TPR_ACCESS:
2373 ret = kvm_handle_tpr_access(cpu);
2374 break;
2375 case KVM_EXIT_FAIL_ENTRY:
2376 code = run->fail_entry.hardware_entry_failure_reason;
2377 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2378 code);
2379 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2380 fprintf(stderr,
2381 "\nIf you're running a guest on an Intel machine without "
2382 "unrestricted mode\n"
2383 "support, the failure can be most likely due to the guest "
2384 "entering an invalid\n"
2385 "state for Intel VT. For example, the guest maybe running "
2386 "in big real mode\n"
2387 "which is not supported on less recent Intel processors."
2388 "\n\n");
2389 }
2390 ret = -1;
2391 break;
2392 case KVM_EXIT_EXCEPTION:
2393 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2394 run->ex.exception, run->ex.error_code);
2395 ret = -1;
2396 break;
2397 case KVM_EXIT_DEBUG:
2398 DPRINTF("kvm_exit_debug\n");
2399 ret = kvm_handle_debug(cpu, &run->debug.arch);
2400 break;
2401 default:
2402 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2403 ret = -1;
2404 break;
2405 }
2406
2407 return ret;
2408 }
2409
2410 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2411 {
2412 X86CPU *cpu = X86_CPU(cs);
2413 CPUX86State *env = &cpu->env;
2414
2415 kvm_cpu_synchronize_state(cs);
2416 return !(env->cr[0] & CR0_PE_MASK) ||
2417 ((env->segs[R_CS].selector & 3) != 3);
2418 }
2419
2420 void kvm_arch_init_irq_routing(KVMState *s)
2421 {
2422 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2423 /* If kernel can't do irq routing, interrupt source
2424 * override 0->2 cannot be set up as required by HPET.
2425 * So we have to disable it.
2426 */
2427 no_hpet = 1;
2428 }
2429 /* We know at this point that we're using the in-kernel
2430 * irqchip, so we can use irqfds, and on x86 we know
2431 * we can use msi via irqfd and GSI routing.
2432 */
2433 kvm_irqfds_allowed = true;
2434 kvm_msi_via_irqfd_allowed = true;
2435 kvm_gsi_routing_allowed = true;
2436 }
2437
2438 /* Classic KVM device assignment interface. Will remain x86 only. */
2439 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2440 uint32_t flags, uint32_t *dev_id)
2441 {
2442 struct kvm_assigned_pci_dev dev_data = {
2443 .segnr = dev_addr->domain,
2444 .busnr = dev_addr->bus,
2445 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2446 .flags = flags,
2447 };
2448 int ret;
2449
2450 dev_data.assigned_dev_id =
2451 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2452
2453 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2454 if (ret < 0) {
2455 return ret;
2456 }
2457
2458 *dev_id = dev_data.assigned_dev_id;
2459
2460 return 0;
2461 }
2462
2463 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2464 {
2465 struct kvm_assigned_pci_dev dev_data = {
2466 .assigned_dev_id = dev_id,
2467 };
2468
2469 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2470 }
2471
2472 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2473 uint32_t irq_type, uint32_t guest_irq)
2474 {
2475 struct kvm_assigned_irq assigned_irq = {
2476 .assigned_dev_id = dev_id,
2477 .guest_irq = guest_irq,
2478 .flags = irq_type,
2479 };
2480
2481 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2482 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2483 } else {
2484 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2485 }
2486 }
2487
2488 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2489 uint32_t guest_irq)
2490 {
2491 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2492 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2493
2494 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2495 }
2496
2497 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2498 {
2499 struct kvm_assigned_pci_dev dev_data = {
2500 .assigned_dev_id = dev_id,
2501 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2502 };
2503
2504 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2505 }
2506
2507 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2508 uint32_t type)
2509 {
2510 struct kvm_assigned_irq assigned_irq = {
2511 .assigned_dev_id = dev_id,
2512 .flags = type,
2513 };
2514
2515 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2516 }
2517
2518 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2519 {
2520 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2521 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2522 }
2523
2524 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2525 {
2526 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2527 KVM_DEV_IRQ_GUEST_MSI, virq);
2528 }
2529
2530 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2531 {
2532 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2533 KVM_DEV_IRQ_HOST_MSI);
2534 }
2535
2536 bool kvm_device_msix_supported(KVMState *s)
2537 {
2538 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2539 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2540 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2541 }
2542
2543 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2544 uint32_t nr_vectors)
2545 {
2546 struct kvm_assigned_msix_nr msix_nr = {
2547 .assigned_dev_id = dev_id,
2548 .entry_nr = nr_vectors,
2549 };
2550
2551 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2552 }
2553
2554 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2555 int virq)
2556 {
2557 struct kvm_assigned_msix_entry msix_entry = {
2558 .assigned_dev_id = dev_id,
2559 .gsi = virq,
2560 .entry = vector,
2561 };
2562
2563 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2564 }
2565
2566 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2567 {
2568 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2569 KVM_DEV_IRQ_GUEST_MSIX, 0);
2570 }
2571
2572 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2573 {
2574 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2575 KVM_DEV_IRQ_HOST_MSIX);
2576 }
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