target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "cpu.h"
  27 #include "gdbstub.h"
  28 #include "host-utils.h"
  29 #include "hw/pc.h"
  30 #include "hw/apic.h"
  31 #include "ioport.h"
  32
  33 //#define DEBUG_KVM
  34
  35 #ifdef DEBUG_KVM
  36 #define DPRINTF(fmt, ...) \
  37     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  38 #else
  39 #define DPRINTF(fmt, ...) \
  40     do { } while (0)
  41 #endif
  42
  43 #define MSR_KVM_WALL_CLOCK  0x11
  44 #define MSR_KVM_SYSTEM_TIME 0x12
  45
  46 #ifndef BUS_MCEERR_AR
  47 #define BUS_MCEERR_AR 4
  48 #endif
  49 #ifndef BUS_MCEERR_AO
  50 #define BUS_MCEERR_AO 5
  51 #endif
  52
  53 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  54     KVM_CAP_INFO(SET_TSS_ADDR),
  55     KVM_CAP_INFO(EXT_CPUID),
  56     KVM_CAP_INFO(MP_STATE),
  57     KVM_CAP_LAST_INFO
  58 };
  59
  60 static bool has_msr_star;
  61 static bool has_msr_hsave_pa;
  62 static bool has_msr_tsc_deadline;
  63 static bool has_msr_async_pf_en;
  64 static bool has_msr_misc_enable;
  65 static int lm_capable_kernel;
  66
  67 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  68 {
  69     struct kvm_cpuid2 *cpuid;
  70     int r, size;
  71
  72     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  73     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  74     cpuid->nent = max;
  75     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  76     if (r == 0 && cpuid->nent >= max) {
  77         r = -E2BIG;
  78     }
  79     if (r < 0) {
  80         if (r == -E2BIG) {
  81             g_free(cpuid);
  82             return NULL;
  83         } else {
  84             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  85                     strerror(-r));
  86             exit(1);
  87         }
  88     }
  89     return cpuid;
  90 }
  91
  92 struct kvm_para_features {
  93     int cap;
  94     int feature;
  95 } para_features[] = {
  96     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
  97     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
  98     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
  99     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 100     { -1, -1 }
 101 };
 102
 103 static int get_para_features(KVMState *s)
 104 {
 105     int i, features = 0;
 106
 107     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 108         if (kvm_check_extension(s, para_features[i].cap)) {
 109             features |= (1 << para_features[i].feature);
 110         }
 111     }
 112
 113     return features;
 114 }
 115
 116
 117 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 118                                       uint32_t index, int reg)
 119 {
 120     struct kvm_cpuid2 *cpuid;
 121     int i, max;
 122     uint32_t ret = 0;
 123     uint32_t cpuid_1_edx;
 124     int has_kvm_features = 0;
 125
 126     max = 1;
 127     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 128         max *= 2;
 129     }
 130
 131     for (i = 0; i < cpuid->nent; ++i) {
 132         if (cpuid->entries[i].function == function &&
 133             cpuid->entries[i].index == index) {
 134             if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
 135                 has_kvm_features = 1;
 136             }
 137             switch (reg) {
 138             case R_EAX:
 139                 ret = cpuid->entries[i].eax;
 140                 break;
 141             case R_EBX:
 142                 ret = cpuid->entries[i].ebx;
 143                 break;
 144             case R_ECX:
 145                 ret = cpuid->entries[i].ecx;
 146                 break;
 147             case R_EDX:
 148                 ret = cpuid->entries[i].edx;
 149                 switch (function) {
 150                 case 1:
 151                     /* KVM before 2.6.30 misreports the following features */
 152                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 153                     break;
 154                 case 0x80000001:
 155                     /* On Intel, kvm returns cpuid according to the Intel spec,
 156                      * so add missing bits according to the AMD spec:
 157                      */
 158                     cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 159                     ret |= cpuid_1_edx & 0x183f7ff;
 160                     break;
 161                 }
 162                 break;
 163             }
 164         }
 165     }
 166
 167     g_free(cpuid);
 168
 169     /* fallback for older kernels */
 170     if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
 171         ret = get_para_features(s);
 172     }
 173
 174     return ret;
 175 }
 176
 177 typedef struct HWPoisonPage {
 178     ram_addr_t ram_addr;
 179     QLIST_ENTRY(HWPoisonPage) list;
 180 } HWPoisonPage;
 181
 182 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 183     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 184
 185 static void kvm_unpoison_all(void *param)
 186 {
 187     HWPoisonPage *page, *next_page;
 188
 189     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 190         QLIST_REMOVE(page, list);
 191         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 192         g_free(page);
 193     }
 194 }
 195
 196 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 197 {
 198     HWPoisonPage *page;
 199
 200     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 201         if (page->ram_addr == ram_addr) {
 202             return;
 203         }
 204     }
 205     page = g_malloc(sizeof(HWPoisonPage));
 206     page->ram_addr = ram_addr;
 207     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 208 }
 209
 210 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 211                                      int *max_banks)
 212 {
 213     int r;
 214
 215     r = kvm_check_extension(s, KVM_CAP_MCE);
 216     if (r > 0) {
 217         *max_banks = r;
 218         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 219     }
 220     return -ENOSYS;
 221 }
 222
 223 static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
 224 {
 225     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 226                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 227     uint64_t mcg_status = MCG_STATUS_MCIP;
 228
 229     if (code == BUS_MCEERR_AR) {
 230         status |= MCI_STATUS_AR | 0x134;
 231         mcg_status |= MCG_STATUS_EIPV;
 232     } else {
 233         status |= 0xc0;
 234         mcg_status |= MCG_STATUS_RIPV;
 235     }
 236     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 237                        (MCM_ADDR_PHYS << 6) | 0xc,
 238                        cpu_x86_support_mca_broadcast(env) ?
 239                        MCE_INJECT_BROADCAST : 0);
 240 }
 241
 242 static void hardware_memory_error(void)
 243 {
 244     fprintf(stderr, "Hardware memory error!\n");
 245     exit(1);
 246 }
 247
 248 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
 249 {
 250     ram_addr_t ram_addr;
 251     target_phys_addr_t paddr;
 252
 253     if ((env->mcg_cap & MCG_SER_P) && addr
 254         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 255         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 256             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr,
 257                                                &paddr)) {
 258             fprintf(stderr, "Hardware memory error for memory used by "
 259                     "QEMU itself instead of guest system!\n");
 260             /* Hope we are lucky for AO MCE */
 261             if (code == BUS_MCEERR_AO) {
 262                 return 0;
 263             } else {
 264                 hardware_memory_error();
 265             }
 266         }
 267         kvm_hwpoison_page_add(ram_addr);
 268         kvm_mce_inject(env, paddr, code);
 269     } else {
 270         if (code == BUS_MCEERR_AO) {
 271             return 0;
 272         } else if (code == BUS_MCEERR_AR) {
 273             hardware_memory_error();
 274         } else {
 275             return 1;
 276         }
 277     }
 278     return 0;
 279 }
 280
 281 int kvm_arch_on_sigbus(int code, void *addr)
 282 {
 283     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 284         ram_addr_t ram_addr;
 285         target_phys_addr_t paddr;
 286
 287         /* Hope we are lucky for AO MCE */
 288         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 289             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr,
 290                                                &paddr)) {
 291             fprintf(stderr, "Hardware memory error for memory used by "
 292                     "QEMU itself instead of guest system!: %p\n", addr);
 293             return 0;
 294         }
 295         kvm_hwpoison_page_add(ram_addr);
 296         kvm_mce_inject(first_cpu, paddr, code);
 297     } else {
 298         if (code == BUS_MCEERR_AO) {
 299             return 0;
 300         } else if (code == BUS_MCEERR_AR) {
 301             hardware_memory_error();
 302         } else {
 303             return 1;
 304         }
 305     }
 306     return 0;
 307 }
 308
 309 static int kvm_inject_mce_oldstyle(CPUState *env)
 310 {
 311     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 312         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 313         struct kvm_x86_mce mce;
 314
 315         env->exception_injected = -1;
 316
 317         /*
 318          * There must be at least one bank in use if an MCE is pending.
 319          * Find it and use its values for the event injection.
 320          */
 321         for (bank = 0; bank < bank_num; bank++) {
 322             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 323                 break;
 324             }
 325         }
 326         assert(bank < bank_num);
 327
 328         mce.bank = bank;
 329         mce.status = env->mce_banks[bank * 4 + 1];
 330         mce.mcg_status = env->mcg_status;
 331         mce.addr = env->mce_banks[bank * 4 + 2];
 332         mce.misc = env->mce_banks[bank * 4 + 3];
 333
 334         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 335     }
 336     return 0;
 337 }
 338
 339 static void cpu_update_state(void *opaque, int running, RunState state)
 340 {
 341     CPUState *env = opaque;
 342
 343     if (running) {
 344         env->tsc_valid = false;
 345     }
 346 }
 347
 348 int kvm_arch_init_vcpu(CPUState *env)
 349 {
 350     struct {
 351         struct kvm_cpuid2 cpuid;
 352         struct kvm_cpuid_entry2 entries[100];
 353     } QEMU_PACKED cpuid_data;
 354     KVMState *s = env->kvm_state;
 355     uint32_t limit, i, j, cpuid_i;
 356     uint32_t unused;
 357     struct kvm_cpuid_entry2 *c;
 358     uint32_t signature[3];
 359     int r;
 360
 361     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 362
 363     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 364     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 365     env->cpuid_ext_features |= i;
 366
 367     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 368                                                              0, R_EDX);
 369     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 370                                                              0, R_ECX);
 371     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 372                                                              0, R_EDX);
 373
 374     cpuid_i = 0;
 375
 376     /* Paravirtualization CPUIDs */
 377     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 378     c = &cpuid_data.entries[cpuid_i++];
 379     memset(c, 0, sizeof(*c));
 380     c->function = KVM_CPUID_SIGNATURE;
 381     c->eax = 0;
 382     c->ebx = signature[0];
 383     c->ecx = signature[1];
 384     c->edx = signature[2];
 385
 386     c = &cpuid_data.entries[cpuid_i++];
 387     memset(c, 0, sizeof(*c));
 388     c->function = KVM_CPUID_FEATURES;
 389     c->eax = env->cpuid_kvm_features &
 390         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 391
 392     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 393
 394     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 395
 396     for (i = 0; i <= limit; i++) {
 397         c = &cpuid_data.entries[cpuid_i++];
 398
 399         switch (i) {
 400         case 2: {
 401             /* Keep reading function 2 till all the input is received */
 402             int times;
 403
 404             c->function = i;
 405             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 406                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 407             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 408             times = c->eax & 0xff;
 409
 410             for (j = 1; j < times; ++j) {
 411                 c = &cpuid_data.entries[cpuid_i++];
 412                 c->function = i;
 413                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 414                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 415             }
 416             break;
 417         }
 418         case 4:
 419         case 0xb:
 420         case 0xd:
 421             for (j = 0; ; j++) {
 422                 if (i == 0xd && j == 64) {
 423                     break;
 424                 }
 425                 c->function = i;
 426                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 427                 c->index = j;
 428                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 429
 430                 if (i == 4 && c->eax == 0) {
 431                     break;
 432                 }
 433                 if (i == 0xb && !(c->ecx & 0xff00)) {
 434                     break;
 435                 }
 436                 if (i == 0xd && c->eax == 0) {
 437                     continue;
 438                 }
 439                 c = &cpuid_data.entries[cpuid_i++];
 440             }
 441             break;
 442         default:
 443             c->function = i;
 444             c->flags = 0;
 445             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 446             break;
 447         }
 448     }
 449     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 450
 451     for (i = 0x80000000; i <= limit; i++) {
 452         c = &cpuid_data.entries[cpuid_i++];
 453
 454         c->function = i;
 455         c->flags = 0;
 456         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 457     }
 458
 459     /* Call Centaur's CPUID instructions they are supported. */
 460     if (env->cpuid_xlevel2 > 0) {
 461         env->cpuid_ext4_features &=
 462             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 463         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 464
 465         for (i = 0xC0000000; i <= limit; i++) {
 466             c = &cpuid_data.entries[cpuid_i++];
 467
 468             c->function = i;
 469             c->flags = 0;
 470             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 471         }
 472     }
 473
 474     cpuid_data.cpuid.nent = cpuid_i;
 475
 476     if (((env->cpuid_version >> 8)&0xF) >= 6
 477         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 478         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 479         uint64_t mcg_cap;
 480         int banks;
 481         int ret;
 482
 483         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 484         if (ret < 0) {
 485             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 486             return ret;
 487         }
 488
 489         if (banks > MCE_BANKS_DEF) {
 490             banks = MCE_BANKS_DEF;
 491         }
 492         mcg_cap &= MCE_CAP_DEF;
 493         mcg_cap |= banks;
 494         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 495         if (ret < 0) {
 496             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 497             return ret;
 498         }
 499
 500         env->mcg_cap = mcg_cap;
 501     }
 502
 503     qemu_add_vm_change_state_handler(cpu_update_state, env);
 504
 505     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 506     if (r) {
 507         return r;
 508     }
 509
 510     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 511     if (r && env->tsc_khz) {
 512         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 513         if (r < 0) {
 514             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 515             return r;
 516         }
 517     }
 518
 519     return 0;
 520 }
 521
 522 void kvm_arch_reset_vcpu(CPUState *env)
 523 {
 524     env->exception_injected = -1;
 525     env->interrupt_injected = -1;
 526     env->xcr0 = 1;
 527     if (kvm_irqchip_in_kernel()) {
 528         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 529                                           KVM_MP_STATE_UNINITIALIZED;
 530     } else {
 531         env->mp_state = KVM_MP_STATE_RUNNABLE;
 532     }
 533 }
 534
 535 static int kvm_get_supported_msrs(KVMState *s)
 536 {
 537     static int kvm_supported_msrs;
 538     int ret = 0;
 539
 540     /* first time */
 541     if (kvm_supported_msrs == 0) {
 542         struct kvm_msr_list msr_list, *kvm_msr_list;
 543
 544         kvm_supported_msrs = -1;
 545
 546         /* Obtain MSR list from KVM.  These are the MSRs that we must
 547          * save/restore */
 548         msr_list.nmsrs = 0;
 549         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 550         if (ret < 0 && ret != -E2BIG) {
 551             return ret;
 552         }
 553         /* Old kernel modules had a bug and could write beyond the provided
 554            memory. Allocate at least a safe amount of 1K. */
 555         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 556                                               msr_list.nmsrs *
 557                                               sizeof(msr_list.indices[0])));
 558
 559         kvm_msr_list->nmsrs = msr_list.nmsrs;
 560         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 561         if (ret >= 0) {
 562             int i;
 563
 564             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 565                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 566                     has_msr_star = true;
 567                     continue;
 568                 }
 569                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 570                     has_msr_hsave_pa = true;
 571                     continue;
 572                 }
 573                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 574                     has_msr_tsc_deadline = true;
 575                     continue;
 576                 }
 577                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 578                     has_msr_misc_enable = true;
 579                     continue;
 580                 }
 581             }
 582         }
 583
 584         g_free(kvm_msr_list);
 585     }
 586
 587     return ret;
 588 }
 589
 590 int kvm_arch_init(KVMState *s)
 591 {
 592     uint64_t identity_base = 0xfffbc000;
 593     int ret;
 594     struct utsname utsname;
 595
 596     ret = kvm_get_supported_msrs(s);
 597     if (ret < 0) {
 598         return ret;
 599     }
 600
 601     uname(&utsname);
 602     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 603
 604     /*
 605      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 606      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 607      * Since these must be part of guest physical memory, we need to allocate
 608      * them, both by setting their start addresses in the kernel and by
 609      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 610      *
 611      * Older KVM versions may not support setting the identity map base. In
 612      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 613      * size.
 614      */
 615     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 616         /* Allows up to 16M BIOSes. */
 617         identity_base = 0xfeffc000;
 618
 619         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 620         if (ret < 0) {
 621             return ret;
 622         }
 623     }
 624
 625     /* Set TSS base one page after EPT identity map. */
 626     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 627     if (ret < 0) {
 628         return ret;
 629     }
 630
 631     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 632     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 633     if (ret < 0) {
 634         fprintf(stderr, "e820_add_entry() table is full\n");
 635         return ret;
 636     }
 637     qemu_register_reset(kvm_unpoison_all, NULL);
 638
 639     return 0;
 640 }
 641
 642 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 643 {
 644     lhs->selector = rhs->selector;
 645     lhs->base = rhs->base;
 646     lhs->limit = rhs->limit;
 647     lhs->type = 3;
 648     lhs->present = 1;
 649     lhs->dpl = 3;
 650     lhs->db = 0;
 651     lhs->s = 1;
 652     lhs->l = 0;
 653     lhs->g = 0;
 654     lhs->avl = 0;
 655     lhs->unusable = 0;
 656 }
 657
 658 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 659 {
 660     unsigned flags = rhs->flags;
 661     lhs->selector = rhs->selector;
 662     lhs->base = rhs->base;
 663     lhs->limit = rhs->limit;
 664     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 665     lhs->present = (flags & DESC_P_MASK) != 0;
 666     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 667     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 668     lhs->s = (flags & DESC_S_MASK) != 0;
 669     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 670     lhs->g = (flags & DESC_G_MASK) != 0;
 671     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 672     lhs->unusable = 0;
 673 }
 674
 675 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 676 {
 677     lhs->selector = rhs->selector;
 678     lhs->base = rhs->base;
 679     lhs->limit = rhs->limit;
 680     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 681                  (rhs->present * DESC_P_MASK) |
 682                  (rhs->dpl << DESC_DPL_SHIFT) |
 683                  (rhs->db << DESC_B_SHIFT) |
 684                  (rhs->s * DESC_S_MASK) |
 685                  (rhs->l << DESC_L_SHIFT) |
 686                  (rhs->g * DESC_G_MASK) |
 687                  (rhs->avl * DESC_AVL_MASK);
 688 }
 689
 690 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 691 {
 692     if (set) {
 693         *kvm_reg = *qemu_reg;
 694     } else {
 695         *qemu_reg = *kvm_reg;
 696     }
 697 }
 698
 699 static int kvm_getput_regs(CPUState *env, int set)
 700 {
 701     struct kvm_regs regs;
 702     int ret = 0;
 703
 704     if (!set) {
 705         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 706         if (ret < 0) {
 707             return ret;
 708         }
 709     }
 710
 711     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 712     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 713     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 714     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 715     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 716     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 717     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 718     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 719 #ifdef TARGET_X86_64
 720     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 721     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 722     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 723     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 724     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 725     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 726     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 727     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 728 #endif
 729
 730     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 731     kvm_getput_reg(&regs.rip, &env->eip, set);
 732
 733     if (set) {
 734         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 735     }
 736
 737     return ret;
 738 }
 739
 740 static int kvm_put_fpu(CPUState *env)
 741 {
 742     struct kvm_fpu fpu;
 743     int i;
 744
 745     memset(&fpu, 0, sizeof fpu);
 746     fpu.fsw = env->fpus & ~(7 << 11);
 747     fpu.fsw |= (env->fpstt & 7) << 11;
 748     fpu.fcw = env->fpuc;
 749     fpu.last_opcode = env->fpop;
 750     fpu.last_ip = env->fpip;
 751     fpu.last_dp = env->fpdp;
 752     for (i = 0; i < 8; ++i) {
 753         fpu.ftwx |= (!env->fptags[i]) << i;
 754     }
 755     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 756     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 757     fpu.mxcsr = env->mxcsr;
 758
 759     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 760 }
 761
 762 #define XSAVE_FCW_FSW     0
 763 #define XSAVE_FTW_FOP     1
 764 #define XSAVE_CWD_RIP     2
 765 #define XSAVE_CWD_RDP     4
 766 #define XSAVE_MXCSR       6
 767 #define XSAVE_ST_SPACE    8
 768 #define XSAVE_XMM_SPACE   40
 769 #define XSAVE_XSTATE_BV   128
 770 #define XSAVE_YMMH_SPACE  144
 771
 772 static int kvm_put_xsave(CPUState *env)
 773 {
 774     int i, r;
 775     struct kvm_xsave* xsave;
 776     uint16_t cwd, swd, twd;
 777
 778     if (!kvm_has_xsave()) {
 779         return kvm_put_fpu(env);
 780     }
 781
 782     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 783     memset(xsave, 0, sizeof(struct kvm_xsave));
 784     twd = 0;
 785     swd = env->fpus & ~(7 << 11);
 786     swd |= (env->fpstt & 7) << 11;
 787     cwd = env->fpuc;
 788     for (i = 0; i < 8; ++i) {
 789         twd |= (!env->fptags[i]) << i;
 790     }
 791     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 792     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 793     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 794     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 795     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 796             sizeof env->fpregs);
 797     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 798             sizeof env->xmm_regs);
 799     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 800     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 801     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 802             sizeof env->ymmh_regs);
 803     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 804     g_free(xsave);
 805     return r;
 806 }
 807
 808 static int kvm_put_xcrs(CPUState *env)
 809 {
 810     struct kvm_xcrs xcrs;
 811
 812     if (!kvm_has_xcrs()) {
 813         return 0;
 814     }
 815
 816     xcrs.nr_xcrs = 1;
 817     xcrs.flags = 0;
 818     xcrs.xcrs[0].xcr = 0;
 819     xcrs.xcrs[0].value = env->xcr0;
 820     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 821 }
 822
 823 static int kvm_put_sregs(CPUState *env)
 824 {
 825     struct kvm_sregs sregs;
 826
 827     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 828     if (env->interrupt_injected >= 0) {
 829         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 830                 (uint64_t)1 << (env->interrupt_injected % 64);
 831     }
 832
 833     if ((env->eflags & VM_MASK)) {
 834         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 835         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 836         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 837         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 838         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 839         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 840     } else {
 841         set_seg(&sregs.cs, &env->segs[R_CS]);
 842         set_seg(&sregs.ds, &env->segs[R_DS]);
 843         set_seg(&sregs.es, &env->segs[R_ES]);
 844         set_seg(&sregs.fs, &env->segs[R_FS]);
 845         set_seg(&sregs.gs, &env->segs[R_GS]);
 846         set_seg(&sregs.ss, &env->segs[R_SS]);
 847     }
 848
 849     set_seg(&sregs.tr, &env->tr);
 850     set_seg(&sregs.ldt, &env->ldt);
 851
 852     sregs.idt.limit = env->idt.limit;
 853     sregs.idt.base = env->idt.base;
 854     sregs.gdt.limit = env->gdt.limit;
 855     sregs.gdt.base = env->gdt.base;
 856
 857     sregs.cr0 = env->cr[0];
 858     sregs.cr2 = env->cr[2];
 859     sregs.cr3 = env->cr[3];
 860     sregs.cr4 = env->cr[4];
 861
 862     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 863     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 864
 865     sregs.efer = env->efer;
 866
 867     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 868 }
 869
 870 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 871                               uint32_t index, uint64_t value)
 872 {
 873     entry->index = index;
 874     entry->data = value;
 875 }
 876
 877 static int kvm_put_msrs(CPUState *env, int level)
 878 {
 879     struct {
 880         struct kvm_msrs info;
 881         struct kvm_msr_entry entries[100];
 882     } msr_data;
 883     struct kvm_msr_entry *msrs = msr_data.entries;
 884     int n = 0;
 885
 886     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 887     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 888     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 889     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 890     if (has_msr_star) {
 891         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 892     }
 893     if (has_msr_hsave_pa) {
 894         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 895     }
 896     if (has_msr_tsc_deadline) {
 897         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
 898     }
 899     if (has_msr_misc_enable) {
 900         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
 901                           env->msr_ia32_misc_enable);
 902     }
 903 #ifdef TARGET_X86_64
 904     if (lm_capable_kernel) {
 905         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 906         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 907         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 908         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 909     }
 910 #endif
 911     if (level == KVM_PUT_FULL_STATE) {
 912         /*
 913          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 914          * writeback. Until this is fixed, we only write the offset to SMP
 915          * guests after migration, desynchronizing the VCPUs, but avoiding
 916          * huge jump-backs that would occur without any writeback at all.
 917          */
 918         if (smp_cpus == 1 || env->tsc != 0) {
 919             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 920         }
 921     }
 922     /*
 923      * The following paravirtual MSRs have side effects on the guest or are
 924      * too heavy for normal writeback. Limit them to reset or full state
 925      * updates.
 926      */
 927     if (level >= KVM_PUT_RESET_STATE) {
 928         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 929                           env->system_time_msr);
 930         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 931         if (has_msr_async_pf_en) {
 932             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
 933                               env->async_pf_en_msr);
 934         }
 935     }
 936     if (env->mcg_cap) {
 937         int i;
 938
 939         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 940         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 941         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 942             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 943         }
 944     }
 945
 946     msr_data.info.nmsrs = n;
 947
 948     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 949
 950 }
 951
 952
 953 static int kvm_get_fpu(CPUState *env)
 954 {
 955     struct kvm_fpu fpu;
 956     int i, ret;
 957
 958     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 959     if (ret < 0) {
 960         return ret;
 961     }
 962
 963     env->fpstt = (fpu.fsw >> 11) & 7;
 964     env->fpus = fpu.fsw;
 965     env->fpuc = fpu.fcw;
 966     env->fpop = fpu.last_opcode;
 967     env->fpip = fpu.last_ip;
 968     env->fpdp = fpu.last_dp;
 969     for (i = 0; i < 8; ++i) {
 970         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 971     }
 972     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 973     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 974     env->mxcsr = fpu.mxcsr;
 975
 976     return 0;
 977 }
 978
 979 static int kvm_get_xsave(CPUState *env)
 980 {
 981     struct kvm_xsave* xsave;
 982     int ret, i;
 983     uint16_t cwd, swd, twd;
 984
 985     if (!kvm_has_xsave()) {
 986         return kvm_get_fpu(env);
 987     }
 988
 989     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 990     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 991     if (ret < 0) {
 992         g_free(xsave);
 993         return ret;
 994     }
 995
 996     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
 997     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
 998     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
 999     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1000     env->fpstt = (swd >> 11) & 7;
1001     env->fpus = swd;
1002     env->fpuc = cwd;
1003     for (i = 0; i < 8; ++i) {
1004         env->fptags[i] = !((twd >> i) & 1);
1005     }
1006     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1007     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1008     env->mxcsr = xsave->region[XSAVE_MXCSR];
1009     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1010             sizeof env->fpregs);
1011     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1012             sizeof env->xmm_regs);
1013     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1014     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1015             sizeof env->ymmh_regs);
1016     g_free(xsave);
1017     return 0;
1018 }
1019
1020 static int kvm_get_xcrs(CPUState *env)
1021 {
1022     int i, ret;
1023     struct kvm_xcrs xcrs;
1024
1025     if (!kvm_has_xcrs()) {
1026         return 0;
1027     }
1028
1029     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1030     if (ret < 0) {
1031         return ret;
1032     }
1033
1034     for (i = 0; i < xcrs.nr_xcrs; i++) {
1035         /* Only support xcr0 now */
1036         if (xcrs.xcrs[0].xcr == 0) {
1037             env->xcr0 = xcrs.xcrs[0].value;
1038             break;
1039         }
1040     }
1041     return 0;
1042 }
1043
1044 static int kvm_get_sregs(CPUState *env)
1045 {
1046     struct kvm_sregs sregs;
1047     uint32_t hflags;
1048     int bit, i, ret;
1049
1050     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1051     if (ret < 0) {
1052         return ret;
1053     }
1054
1055     /* There can only be one pending IRQ set in the bitmap at a time, so try
1056        to find it and save its number instead (-1 for none). */
1057     env->interrupt_injected = -1;
1058     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1059         if (sregs.interrupt_bitmap[i]) {
1060             bit = ctz64(sregs.interrupt_bitmap[i]);
1061             env->interrupt_injected = i * 64 + bit;
1062             break;
1063         }
1064     }
1065
1066     get_seg(&env->segs[R_CS], &sregs.cs);
1067     get_seg(&env->segs[R_DS], &sregs.ds);
1068     get_seg(&env->segs[R_ES], &sregs.es);
1069     get_seg(&env->segs[R_FS], &sregs.fs);
1070     get_seg(&env->segs[R_GS], &sregs.gs);
1071     get_seg(&env->segs[R_SS], &sregs.ss);
1072
1073     get_seg(&env->tr, &sregs.tr);
1074     get_seg(&env->ldt, &sregs.ldt);
1075
1076     env->idt.limit = sregs.idt.limit;
1077     env->idt.base = sregs.idt.base;
1078     env->gdt.limit = sregs.gdt.limit;
1079     env->gdt.base = sregs.gdt.base;
1080
1081     env->cr[0] = sregs.cr0;
1082     env->cr[2] = sregs.cr2;
1083     env->cr[3] = sregs.cr3;
1084     env->cr[4] = sregs.cr4;
1085
1086     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1087
1088     env->efer = sregs.efer;
1089     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1090
1091 #define HFLAG_COPY_MASK \
1092     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1093        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1094        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1095        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1096
1097     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1098     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1099     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1100                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1101     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1102     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1103                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1104
1105     if (env->efer & MSR_EFER_LMA) {
1106         hflags |= HF_LMA_MASK;
1107     }
1108
1109     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1110         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1111     } else {
1112         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1113                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1114         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1115                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1116         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1117             !(hflags & HF_CS32_MASK)) {
1118             hflags |= HF_ADDSEG_MASK;
1119         } else {
1120             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1121                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1122         }
1123     }
1124     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1125
1126     return 0;
1127 }
1128
1129 static int kvm_get_msrs(CPUState *env)
1130 {
1131     struct {
1132         struct kvm_msrs info;
1133         struct kvm_msr_entry entries[100];
1134     } msr_data;
1135     struct kvm_msr_entry *msrs = msr_data.entries;
1136     int ret, i, n;
1137
1138     n = 0;
1139     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1140     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1141     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1142     msrs[n++].index = MSR_PAT;
1143     if (has_msr_star) {
1144         msrs[n++].index = MSR_STAR;
1145     }
1146     if (has_msr_hsave_pa) {
1147         msrs[n++].index = MSR_VM_HSAVE_PA;
1148     }
1149     if (has_msr_tsc_deadline) {
1150         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1151     }
1152     if (has_msr_misc_enable) {
1153         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1154     }
1155
1156     if (!env->tsc_valid) {
1157         msrs[n++].index = MSR_IA32_TSC;
1158         env->tsc_valid = !runstate_is_running();
1159     }
1160
1161 #ifdef TARGET_X86_64
1162     if (lm_capable_kernel) {
1163         msrs[n++].index = MSR_CSTAR;
1164         msrs[n++].index = MSR_KERNELGSBASE;
1165         msrs[n++].index = MSR_FMASK;
1166         msrs[n++].index = MSR_LSTAR;
1167     }
1168 #endif
1169     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1170     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1171     if (has_msr_async_pf_en) {
1172         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1173     }
1174
1175     if (env->mcg_cap) {
1176         msrs[n++].index = MSR_MCG_STATUS;
1177         msrs[n++].index = MSR_MCG_CTL;
1178         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1179             msrs[n++].index = MSR_MC0_CTL + i;
1180         }
1181     }
1182
1183     msr_data.info.nmsrs = n;
1184     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1185     if (ret < 0) {
1186         return ret;
1187     }
1188
1189     for (i = 0; i < ret; i++) {
1190         switch (msrs[i].index) {
1191         case MSR_IA32_SYSENTER_CS:
1192             env->sysenter_cs = msrs[i].data;
1193             break;
1194         case MSR_IA32_SYSENTER_ESP:
1195             env->sysenter_esp = msrs[i].data;
1196             break;
1197         case MSR_IA32_SYSENTER_EIP:
1198             env->sysenter_eip = msrs[i].data;
1199             break;
1200         case MSR_PAT:
1201             env->pat = msrs[i].data;
1202             break;
1203         case MSR_STAR:
1204             env->star = msrs[i].data;
1205             break;
1206 #ifdef TARGET_X86_64
1207         case MSR_CSTAR:
1208             env->cstar = msrs[i].data;
1209             break;
1210         case MSR_KERNELGSBASE:
1211             env->kernelgsbase = msrs[i].data;
1212             break;
1213         case MSR_FMASK:
1214             env->fmask = msrs[i].data;
1215             break;
1216         case MSR_LSTAR:
1217             env->lstar = msrs[i].data;
1218             break;
1219 #endif
1220         case MSR_IA32_TSC:
1221             env->tsc = msrs[i].data;
1222             break;
1223         case MSR_IA32_TSCDEADLINE:
1224             env->tsc_deadline = msrs[i].data;
1225             break;
1226         case MSR_VM_HSAVE_PA:
1227             env->vm_hsave = msrs[i].data;
1228             break;
1229         case MSR_KVM_SYSTEM_TIME:
1230             env->system_time_msr = msrs[i].data;
1231             break;
1232         case MSR_KVM_WALL_CLOCK:
1233             env->wall_clock_msr = msrs[i].data;
1234             break;
1235         case MSR_MCG_STATUS:
1236             env->mcg_status = msrs[i].data;
1237             break;
1238         case MSR_MCG_CTL:
1239             env->mcg_ctl = msrs[i].data;
1240             break;
1241         case MSR_IA32_MISC_ENABLE:
1242             env->msr_ia32_misc_enable = msrs[i].data;
1243             break;
1244         default:
1245             if (msrs[i].index >= MSR_MC0_CTL &&
1246                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1247                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1248             }
1249             break;
1250         case MSR_KVM_ASYNC_PF_EN:
1251             env->async_pf_en_msr = msrs[i].data;
1252             break;
1253         }
1254     }
1255
1256     return 0;
1257 }
1258
1259 static int kvm_put_mp_state(CPUState *env)
1260 {
1261     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1262
1263     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1264 }
1265
1266 static int kvm_get_mp_state(CPUState *env)
1267 {
1268     struct kvm_mp_state mp_state;
1269     int ret;
1270
1271     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1272     if (ret < 0) {
1273         return ret;
1274     }
1275     env->mp_state = mp_state.mp_state;
1276     if (kvm_irqchip_in_kernel()) {
1277         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1278     }
1279     return 0;
1280 }
1281
1282 static int kvm_put_vcpu_events(CPUState *env, int level)
1283 {
1284     struct kvm_vcpu_events events;
1285
1286     if (!kvm_has_vcpu_events()) {
1287         return 0;
1288     }
1289
1290     events.exception.injected = (env->exception_injected >= 0);
1291     events.exception.nr = env->exception_injected;
1292     events.exception.has_error_code = env->has_error_code;
1293     events.exception.error_code = env->error_code;
1294
1295     events.interrupt.injected = (env->interrupt_injected >= 0);
1296     events.interrupt.nr = env->interrupt_injected;
1297     events.interrupt.soft = env->soft_interrupt;
1298
1299     events.nmi.injected = env->nmi_injected;
1300     events.nmi.pending = env->nmi_pending;
1301     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1302
1303     events.sipi_vector = env->sipi_vector;
1304
1305     events.flags = 0;
1306     if (level >= KVM_PUT_RESET_STATE) {
1307         events.flags |=
1308             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1309     }
1310
1311     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1312 }
1313
1314 static int kvm_get_vcpu_events(CPUState *env)
1315 {
1316     struct kvm_vcpu_events events;
1317     int ret;
1318
1319     if (!kvm_has_vcpu_events()) {
1320         return 0;
1321     }
1322
1323     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1324     if (ret < 0) {
1325        return ret;
1326     }
1327     env->exception_injected =
1328        events.exception.injected ? events.exception.nr : -1;
1329     env->has_error_code = events.exception.has_error_code;
1330     env->error_code = events.exception.error_code;
1331
1332     env->interrupt_injected =
1333         events.interrupt.injected ? events.interrupt.nr : -1;
1334     env->soft_interrupt = events.interrupt.soft;
1335
1336     env->nmi_injected = events.nmi.injected;
1337     env->nmi_pending = events.nmi.pending;
1338     if (events.nmi.masked) {
1339         env->hflags2 |= HF2_NMI_MASK;
1340     } else {
1341         env->hflags2 &= ~HF2_NMI_MASK;
1342     }
1343
1344     env->sipi_vector = events.sipi_vector;
1345
1346     return 0;
1347 }
1348
1349 static int kvm_guest_debug_workarounds(CPUState *env)
1350 {
1351     int ret = 0;
1352     unsigned long reinject_trap = 0;
1353
1354     if (!kvm_has_vcpu_events()) {
1355         if (env->exception_injected == 1) {
1356             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1357         } else if (env->exception_injected == 3) {
1358             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1359         }
1360         env->exception_injected = -1;
1361     }
1362
1363     /*
1364      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1365      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1366      * by updating the debug state once again if single-stepping is on.
1367      * Another reason to call kvm_update_guest_debug here is a pending debug
1368      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1369      * reinject them via SET_GUEST_DEBUG.
1370      */
1371     if (reinject_trap ||
1372         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1373         ret = kvm_update_guest_debug(env, reinject_trap);
1374     }
1375     return ret;
1376 }
1377
1378 static int kvm_put_debugregs(CPUState *env)
1379 {
1380     struct kvm_debugregs dbgregs;
1381     int i;
1382
1383     if (!kvm_has_debugregs()) {
1384         return 0;
1385     }
1386
1387     for (i = 0; i < 4; i++) {
1388         dbgregs.db[i] = env->dr[i];
1389     }
1390     dbgregs.dr6 = env->dr[6];
1391     dbgregs.dr7 = env->dr[7];
1392     dbgregs.flags = 0;
1393
1394     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1395 }
1396
1397 static int kvm_get_debugregs(CPUState *env)
1398 {
1399     struct kvm_debugregs dbgregs;
1400     int i, ret;
1401
1402     if (!kvm_has_debugregs()) {
1403         return 0;
1404     }
1405
1406     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1407     if (ret < 0) {
1408         return ret;
1409     }
1410     for (i = 0; i < 4; i++) {
1411         env->dr[i] = dbgregs.db[i];
1412     }
1413     env->dr[4] = env->dr[6] = dbgregs.dr6;
1414     env->dr[5] = env->dr[7] = dbgregs.dr7;
1415
1416     return 0;
1417 }
1418
1419 int kvm_arch_put_registers(CPUState *env, int level)
1420 {
1421     int ret;
1422
1423     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1424
1425     ret = kvm_getput_regs(env, 1);
1426     if (ret < 0) {
1427         return ret;
1428     }
1429     ret = kvm_put_xsave(env);
1430     if (ret < 0) {
1431         return ret;
1432     }
1433     ret = kvm_put_xcrs(env);
1434     if (ret < 0) {
1435         return ret;
1436     }
1437     ret = kvm_put_sregs(env);
1438     if (ret < 0) {
1439         return ret;
1440     }
1441     /* must be before kvm_put_msrs */
1442     ret = kvm_inject_mce_oldstyle(env);
1443     if (ret < 0) {
1444         return ret;
1445     }
1446     ret = kvm_put_msrs(env, level);
1447     if (ret < 0) {
1448         return ret;
1449     }
1450     if (level >= KVM_PUT_RESET_STATE) {
1451         ret = kvm_put_mp_state(env);
1452         if (ret < 0) {
1453             return ret;
1454         }
1455     }
1456     ret = kvm_put_vcpu_events(env, level);
1457     if (ret < 0) {
1458         return ret;
1459     }
1460     ret = kvm_put_debugregs(env);
1461     if (ret < 0) {
1462         return ret;
1463     }
1464     /* must be last */
1465     ret = kvm_guest_debug_workarounds(env);
1466     if (ret < 0) {
1467         return ret;
1468     }
1469     return 0;
1470 }
1471
1472 int kvm_arch_get_registers(CPUState *env)
1473 {
1474     int ret;
1475
1476     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1477
1478     ret = kvm_getput_regs(env, 0);
1479     if (ret < 0) {
1480         return ret;
1481     }
1482     ret = kvm_get_xsave(env);
1483     if (ret < 0) {
1484         return ret;
1485     }
1486     ret = kvm_get_xcrs(env);
1487     if (ret < 0) {
1488         return ret;
1489     }
1490     ret = kvm_get_sregs(env);
1491     if (ret < 0) {
1492         return ret;
1493     }
1494     ret = kvm_get_msrs(env);
1495     if (ret < 0) {
1496         return ret;
1497     }
1498     ret = kvm_get_mp_state(env);
1499     if (ret < 0) {
1500         return ret;
1501     }
1502     ret = kvm_get_vcpu_events(env);
1503     if (ret < 0) {
1504         return ret;
1505     }
1506     ret = kvm_get_debugregs(env);
1507     if (ret < 0) {
1508         return ret;
1509     }
1510     return 0;
1511 }
1512
1513 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1514 {
1515     int ret;
1516
1517     /* Inject NMI */
1518     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1519         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1520         DPRINTF("injected NMI\n");
1521         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1522         if (ret < 0) {
1523             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1524                     strerror(-ret));
1525         }
1526     }
1527
1528     if (!kvm_irqchip_in_kernel()) {
1529         /* Force the VCPU out of its inner loop to process the INIT request */
1530         if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1531             env->exit_request = 1;
1532         }
1533
1534         /* Try to inject an interrupt if the guest can accept it */
1535         if (run->ready_for_interrupt_injection &&
1536             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1537             (env->eflags & IF_MASK)) {
1538             int irq;
1539
1540             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1541             irq = cpu_get_pic_interrupt(env);
1542             if (irq >= 0) {
1543                 struct kvm_interrupt intr;
1544
1545                 intr.irq = irq;
1546                 DPRINTF("injected interrupt %d\n", irq);
1547                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1548                 if (ret < 0) {
1549                     fprintf(stderr,
1550                             "KVM: injection failed, interrupt lost (%s)\n",
1551                             strerror(-ret));
1552                 }
1553             }
1554         }
1555
1556         /* If we have an interrupt but the guest is not ready to receive an
1557          * interrupt, request an interrupt window exit.  This will
1558          * cause a return to userspace as soon as the guest is ready to
1559          * receive interrupts. */
1560         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1561             run->request_interrupt_window = 1;
1562         } else {
1563             run->request_interrupt_window = 0;
1564         }
1565
1566         DPRINTF("setting tpr\n");
1567         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1568     }
1569 }
1570
1571 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1572 {
1573     if (run->if_flag) {
1574         env->eflags |= IF_MASK;
1575     } else {
1576         env->eflags &= ~IF_MASK;
1577     }
1578     cpu_set_apic_tpr(env->apic_state, run->cr8);
1579     cpu_set_apic_base(env->apic_state, run->apic_base);
1580 }
1581
1582 int kvm_arch_process_async_events(CPUState *env)
1583 {
1584     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1585         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1586         assert(env->mcg_cap);
1587
1588         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1589
1590         kvm_cpu_synchronize_state(env);
1591
1592         if (env->exception_injected == EXCP08_DBLE) {
1593             /* this means triple fault */
1594             qemu_system_reset_request();
1595             env->exit_request = 1;
1596             return 0;
1597         }
1598         env->exception_injected = EXCP12_MCHK;
1599         env->has_error_code = 0;
1600
1601         env->halted = 0;
1602         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1603             env->mp_state = KVM_MP_STATE_RUNNABLE;
1604         }
1605     }
1606
1607     if (kvm_irqchip_in_kernel()) {
1608         return 0;
1609     }
1610
1611     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1612          (env->eflags & IF_MASK)) ||
1613         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1614         env->halted = 0;
1615     }
1616     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1617         kvm_cpu_synchronize_state(env);
1618         do_cpu_init(env);
1619     }
1620     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1621         kvm_cpu_synchronize_state(env);
1622         do_cpu_sipi(env);
1623     }
1624
1625     return env->halted;
1626 }
1627
1628 static int kvm_handle_halt(CPUState *env)
1629 {
1630     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1631           (env->eflags & IF_MASK)) &&
1632         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1633         env->halted = 1;
1634         return EXCP_HLT;
1635     }
1636
1637     return 0;
1638 }
1639
1640 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1641 {
1642     static const uint8_t int3 = 0xcc;
1643
1644     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1645         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1646         return -EINVAL;
1647     }
1648     return 0;
1649 }
1650
1651 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1652 {
1653     uint8_t int3;
1654
1655     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1656         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1657         return -EINVAL;
1658     }
1659     return 0;
1660 }
1661
1662 static struct {
1663     target_ulong addr;
1664     int len;
1665     int type;
1666 } hw_breakpoint[4];
1667
1668 static int nb_hw_breakpoint;
1669
1670 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1671 {
1672     int n;
1673
1674     for (n = 0; n < nb_hw_breakpoint; n++) {
1675         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1676             (hw_breakpoint[n].len == len || len == -1)) {
1677             return n;
1678         }
1679     }
1680     return -1;
1681 }
1682
1683 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1684                                   target_ulong len, int type)
1685 {
1686     switch (type) {
1687     case GDB_BREAKPOINT_HW:
1688         len = 1;
1689         break;
1690     case GDB_WATCHPOINT_WRITE:
1691     case GDB_WATCHPOINT_ACCESS:
1692         switch (len) {
1693         case 1:
1694             break;
1695         case 2:
1696         case 4:
1697         case 8:
1698             if (addr & (len - 1)) {
1699                 return -EINVAL;
1700             }
1701             break;
1702         default:
1703             return -EINVAL;
1704         }
1705         break;
1706     default:
1707         return -ENOSYS;
1708     }
1709
1710     if (nb_hw_breakpoint == 4) {
1711         return -ENOBUFS;
1712     }
1713     if (find_hw_breakpoint(addr, len, type) >= 0) {
1714         return -EEXIST;
1715     }
1716     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1717     hw_breakpoint[nb_hw_breakpoint].len = len;
1718     hw_breakpoint[nb_hw_breakpoint].type = type;
1719     nb_hw_breakpoint++;
1720
1721     return 0;
1722 }
1723
1724 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1725                                   target_ulong len, int type)
1726 {
1727     int n;
1728
1729     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1730     if (n < 0) {
1731         return -ENOENT;
1732     }
1733     nb_hw_breakpoint--;
1734     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1735
1736     return 0;
1737 }
1738
1739 void kvm_arch_remove_all_hw_breakpoints(void)
1740 {
1741     nb_hw_breakpoint = 0;
1742 }
1743
1744 static CPUWatchpoint hw_watchpoint;
1745
1746 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1747 {
1748     int ret = 0;
1749     int n;
1750
1751     if (arch_info->exception == 1) {
1752         if (arch_info->dr6 & (1 << 14)) {
1753             if (cpu_single_env->singlestep_enabled) {
1754                 ret = EXCP_DEBUG;
1755             }
1756         } else {
1757             for (n = 0; n < 4; n++) {
1758                 if (arch_info->dr6 & (1 << n)) {
1759                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1760                     case 0x0:
1761                         ret = EXCP_DEBUG;
1762                         break;
1763                     case 0x1:
1764                         ret = EXCP_DEBUG;
1765                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1766                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1767                         hw_watchpoint.flags = BP_MEM_WRITE;
1768                         break;
1769                     case 0x3:
1770                         ret = EXCP_DEBUG;
1771                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1772                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1773                         hw_watchpoint.flags = BP_MEM_ACCESS;
1774                         break;
1775                     }
1776                 }
1777             }
1778         }
1779     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1780         ret = EXCP_DEBUG;
1781     }
1782     if (ret == 0) {
1783         cpu_synchronize_state(cpu_single_env);
1784         assert(cpu_single_env->exception_injected == -1);
1785
1786         /* pass to guest */
1787         cpu_single_env->exception_injected = arch_info->exception;
1788         cpu_single_env->has_error_code = 0;
1789     }
1790
1791     return ret;
1792 }
1793
1794 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1795 {
1796     const uint8_t type_code[] = {
1797         [GDB_BREAKPOINT_HW] = 0x0,
1798         [GDB_WATCHPOINT_WRITE] = 0x1,
1799         [GDB_WATCHPOINT_ACCESS] = 0x3
1800     };
1801     const uint8_t len_code[] = {
1802         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1803     };
1804     int n;
1805
1806     if (kvm_sw_breakpoints_active(env)) {
1807         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1808     }
1809     if (nb_hw_breakpoint > 0) {
1810         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1811         dbg->arch.debugreg[7] = 0x0600;
1812         for (n = 0; n < nb_hw_breakpoint; n++) {
1813             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1814             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1815                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1816                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1817         }
1818     }
1819 }
1820
1821 static bool host_supports_vmx(void)
1822 {
1823     uint32_t ecx, unused;
1824
1825     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1826     return ecx & CPUID_EXT_VMX;
1827 }
1828
1829 #define VMX_INVALID_GUEST_STATE 0x80000021
1830
1831 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1832 {
1833     uint64_t code;
1834     int ret;
1835
1836     switch (run->exit_reason) {
1837     case KVM_EXIT_HLT:
1838         DPRINTF("handle_hlt\n");
1839         ret = kvm_handle_halt(env);
1840         break;
1841     case KVM_EXIT_SET_TPR:
1842         ret = 0;
1843         break;
1844     case KVM_EXIT_FAIL_ENTRY:
1845         code = run->fail_entry.hardware_entry_failure_reason;
1846         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1847                 code);
1848         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1849             fprintf(stderr,
1850                     "\nIf you're running a guest on an Intel machine without "
1851                         "unrestricted mode\n"
1852                     "support, the failure can be most likely due to the guest "
1853                         "entering an invalid\n"
1854                     "state for Intel VT. For example, the guest maybe running "
1855                         "in big real mode\n"
1856                     "which is not supported on less recent Intel processors."
1857                         "\n\n");
1858         }
1859         ret = -1;
1860         break;
1861     case KVM_EXIT_EXCEPTION:
1862         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1863                 run->ex.exception, run->ex.error_code);
1864         ret = -1;
1865         break;
1866     case KVM_EXIT_DEBUG:
1867         DPRINTF("kvm_exit_debug\n");
1868         ret = kvm_handle_debug(&run->debug.arch);
1869         break;
1870     default:
1871         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1872         ret = -1;
1873         break;
1874     }
1875
1876     return ret;
1877 }
1878
1879 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1880 {
1881     return !(env->cr[0] & CR0_PE_MASK) ||
1882            ((env->segs[R_CS].selector  & 3) != 3);
1883 }