target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31 #include "kvm_x86.h"
  32
  33 #ifdef CONFIG_KVM_PARA
  34 #include <linux/kvm_para.h>
  35 #endif
  36 //
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  58     KVM_CAP_INFO(SET_TSS_ADDR),
  59     KVM_CAP_INFO(EXT_CPUID),
  60     KVM_CAP_INFO(MP_STATE),
  61     KVM_CAP_LAST_INFO
  62 };
  63
  64 static bool has_msr_star;
  65 static bool has_msr_hsave_pa;
  66 static int lm_capable_kernel;
  67
  68 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  69 {
  70     struct kvm_cpuid2 *cpuid;
  71     int r, size;
  72
  73     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  74     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  75     cpuid->nent = max;
  76     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  77     if (r == 0 && cpuid->nent >= max) {
  78         r = -E2BIG;
  79     }
  80     if (r < 0) {
  81         if (r == -E2BIG) {
  82             qemu_free(cpuid);
  83             return NULL;
  84         } else {
  85             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  86                     strerror(-r));
  87             exit(1);
  88         }
  89     }
  90     return cpuid;
  91 }
  92
  93 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  94                                       uint32_t index, int reg)
  95 {
  96     struct kvm_cpuid2 *cpuid;
  97     int i, max;
  98     uint32_t ret = 0;
  99     uint32_t cpuid_1_edx;
 100
 101     max = 1;
 102     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 103         max *= 2;
 104     }
 105
 106     for (i = 0; i < cpuid->nent; ++i) {
 107         if (cpuid->entries[i].function == function &&
 108             cpuid->entries[i].index == index) {
 109             switch (reg) {
 110             case R_EAX:
 111                 ret = cpuid->entries[i].eax;
 112                 break;
 113             case R_EBX:
 114                 ret = cpuid->entries[i].ebx;
 115                 break;
 116             case R_ECX:
 117                 ret = cpuid->entries[i].ecx;
 118                 break;
 119             case R_EDX:
 120                 ret = cpuid->entries[i].edx;
 121                 switch (function) {
 122                 case 1:
 123                     /* KVM before 2.6.30 misreports the following features */
 124                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 125                     break;
 126                 case 0x80000001:
 127                     /* On Intel, kvm returns cpuid according to the Intel spec,
 128                      * so add missing bits according to the AMD spec:
 129                      */
 130                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 131                     ret |= cpuid_1_edx & 0x183f7ff;
 132                     break;
 133                 }
 134                 break;
 135             }
 136         }
 137     }
 138
 139     qemu_free(cpuid);
 140
 141     return ret;
 142 }
 143
 144 #ifdef CONFIG_KVM_PARA
 145 struct kvm_para_features {
 146     int cap;
 147     int feature;
 148 } para_features[] = {
 149     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 150     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 151     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 152 #ifdef KVM_CAP_ASYNC_PF
 153     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 154 #endif
 155     { -1, -1 }
 156 };
 157
 158 static int get_para_features(CPUState *env)
 159 {
 160     int i, features = 0;
 161
 162     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 163         if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
 164             features |= (1 << para_features[i].feature);
 165         }
 166     }
 167     return features;
 168 }
 169 #endif
 170
 171 #ifdef KVM_CAP_MCE
 172 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 173                                      int *max_banks)
 174 {
 175     int r;
 176
 177     r = kvm_check_extension(s, KVM_CAP_MCE);
 178     if (r > 0) {
 179         *max_banks = r;
 180         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 181     }
 182     return -ENOSYS;
 183 }
 184
 185 static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
 186 {
 187     return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
 188 }
 189
 190 static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
 191 {
 192     return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
 193 }
 194
 195 static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
 196 {
 197     struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
 198     int r;
 199
 200     kmsrs->nmsrs = n;
 201     memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
 202     r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
 203     memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
 204     free(kmsrs);
 205     return r;
 206 }
 207
 208 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
 209 static int kvm_mce_in_progress(CPUState *env)
 210 {
 211     struct kvm_msr_entry msr_mcg_status = {
 212         .index = MSR_MCG_STATUS,
 213     };
 214     int r;
 215
 216     r = kvm_get_msr(env, &msr_mcg_status, 1);
 217     if (r == -1 || r == 0) {
 218         fprintf(stderr, "Failed to get MCE status\n");
 219         return 0;
 220     }
 221     return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
 222 }
 223
 224 struct kvm_x86_mce_data
 225 {
 226     CPUState *env;
 227     struct kvm_x86_mce *mce;
 228     int abort_on_error;
 229 };
 230
 231 static void kvm_do_inject_x86_mce(void *_data)
 232 {
 233     struct kvm_x86_mce_data *data = _data;
 234     int r;
 235
 236     /* If there is an MCE exception being processed, ignore this SRAO MCE */
 237     if ((data->env->mcg_cap & MCG_SER_P) &&
 238         !(data->mce->status & MCI_STATUS_AR)) {
 239         if (kvm_mce_in_progress(data->env)) {
 240             return;
 241         }
 242     }
 243
 244     r = kvm_set_mce(data->env, data->mce);
 245     if (r < 0) {
 246         perror("kvm_set_mce FAILED");
 247         if (data->abort_on_error) {
 248             abort();
 249         }
 250     }
 251 }
 252
 253 static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce,
 254                                   int flag)
 255 {
 256     struct kvm_x86_mce_data data = {
 257         .env = env,
 258         .mce = mce,
 259         .abort_on_error = (flag & ABORT_ON_ERROR),
 260     };
 261
 262     if (!env->mcg_cap) {
 263         fprintf(stderr, "MCE support is not enabled!\n");
 264         return;
 265     }
 266
 267     run_on_cpu(env, kvm_do_inject_x86_mce, &data);
 268 }
 269
 270 static void kvm_mce_broadcast_rest(CPUState *env);
 271 #endif
 272
 273 void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
 274                         uint64_t mcg_status, uint64_t addr, uint64_t misc,
 275                         int flag)
 276 {
 277 #ifdef KVM_CAP_MCE
 278     struct kvm_x86_mce mce = {
 279         .bank = bank,
 280         .status = status,
 281         .mcg_status = mcg_status,
 282         .addr = addr,
 283         .misc = misc,
 284     };
 285
 286     if (flag & MCE_BROADCAST) {
 287         kvm_mce_broadcast_rest(cenv);
 288     }
 289
 290     kvm_inject_x86_mce_on(cenv, &mce, flag);
 291 #else
 292     if (flag & ABORT_ON_ERROR) {
 293         abort();
 294     }
 295 #endif
 296 }
 297
 298 int kvm_arch_init_vcpu(CPUState *env)
 299 {
 300     struct {
 301         struct kvm_cpuid2 cpuid;
 302         struct kvm_cpuid_entry2 entries[100];
 303     } __attribute__((packed)) cpuid_data;
 304     uint32_t limit, i, j, cpuid_i;
 305     uint32_t unused;
 306     struct kvm_cpuid_entry2 *c;
 307 #ifdef CONFIG_KVM_PARA
 308     uint32_t signature[3];
 309 #endif
 310
 311     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 312
 313     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 314     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 315     env->cpuid_ext_features |= i;
 316
 317     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 318                                                              0, R_EDX);
 319     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 320                                                              0, R_ECX);
 321     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 322                                                              0, R_EDX);
 323
 324
 325     cpuid_i = 0;
 326
 327 #ifdef CONFIG_KVM_PARA
 328     /* Paravirtualization CPUIDs */
 329     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 330     c = &cpuid_data.entries[cpuid_i++];
 331     memset(c, 0, sizeof(*c));
 332     c->function = KVM_CPUID_SIGNATURE;
 333     c->eax = 0;
 334     c->ebx = signature[0];
 335     c->ecx = signature[1];
 336     c->edx = signature[2];
 337
 338     c = &cpuid_data.entries[cpuid_i++];
 339     memset(c, 0, sizeof(*c));
 340     c->function = KVM_CPUID_FEATURES;
 341     c->eax = env->cpuid_kvm_features & get_para_features(env);
 342 #endif
 343
 344     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 345
 346     for (i = 0; i <= limit; i++) {
 347         c = &cpuid_data.entries[cpuid_i++];
 348
 349         switch (i) {
 350         case 2: {
 351             /* Keep reading function 2 till all the input is received */
 352             int times;
 353
 354             c->function = i;
 355             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 356                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 357             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 358             times = c->eax & 0xff;
 359
 360             for (j = 1; j < times; ++j) {
 361                 c = &cpuid_data.entries[cpuid_i++];
 362                 c->function = i;
 363                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 364                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 365             }
 366             break;
 367         }
 368         case 4:
 369         case 0xb:
 370         case 0xd:
 371             for (j = 0; ; j++) {
 372                 c->function = i;
 373                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 374                 c->index = j;
 375                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 376
 377                 if (i == 4 && c->eax == 0) {
 378                     break;
 379                 }
 380                 if (i == 0xb && !(c->ecx & 0xff00)) {
 381                     break;
 382                 }
 383                 if (i == 0xd && c->eax == 0) {
 384                     break;
 385                 }
 386                 c = &cpuid_data.entries[cpuid_i++];
 387             }
 388             break;
 389         default:
 390             c->function = i;
 391             c->flags = 0;
 392             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 393             break;
 394         }
 395     }
 396     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 397
 398     for (i = 0x80000000; i <= limit; i++) {
 399         c = &cpuid_data.entries[cpuid_i++];
 400
 401         c->function = i;
 402         c->flags = 0;
 403         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 404     }
 405
 406     cpuid_data.cpuid.nent = cpuid_i;
 407
 408 #ifdef KVM_CAP_MCE
 409     if (((env->cpuid_version >> 8)&0xF) >= 6
 410         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 411         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 412         uint64_t mcg_cap;
 413         int banks;
 414
 415         if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) {
 416             perror("kvm_get_mce_cap_supported FAILED");
 417         } else {
 418             if (banks > MCE_BANKS_DEF)
 419                 banks = MCE_BANKS_DEF;
 420             mcg_cap &= MCE_CAP_DEF;
 421             mcg_cap |= banks;
 422             if (kvm_setup_mce(env, &mcg_cap)) {
 423                 perror("kvm_setup_mce FAILED");
 424             } else {
 425                 env->mcg_cap = mcg_cap;
 426             }
 427         }
 428     }
 429 #endif
 430
 431     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 432 }
 433
 434 void kvm_arch_reset_vcpu(CPUState *env)
 435 {
 436     env->exception_injected = -1;
 437     env->interrupt_injected = -1;
 438     env->xcr0 = 1;
 439     if (kvm_irqchip_in_kernel()) {
 440         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 441                                           KVM_MP_STATE_UNINITIALIZED;
 442     } else {
 443         env->mp_state = KVM_MP_STATE_RUNNABLE;
 444     }
 445 }
 446
 447 static int kvm_get_supported_msrs(KVMState *s)
 448 {
 449     static int kvm_supported_msrs;
 450     int ret = 0;
 451
 452     /* first time */
 453     if (kvm_supported_msrs == 0) {
 454         struct kvm_msr_list msr_list, *kvm_msr_list;
 455
 456         kvm_supported_msrs = -1;
 457
 458         /* Obtain MSR list from KVM.  These are the MSRs that we must
 459          * save/restore */
 460         msr_list.nmsrs = 0;
 461         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 462         if (ret < 0 && ret != -E2BIG) {
 463             return ret;
 464         }
 465         /* Old kernel modules had a bug and could write beyond the provided
 466            memory. Allocate at least a safe amount of 1K. */
 467         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 468                                               msr_list.nmsrs *
 469                                               sizeof(msr_list.indices[0])));
 470
 471         kvm_msr_list->nmsrs = msr_list.nmsrs;
 472         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 473         if (ret >= 0) {
 474             int i;
 475
 476             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 477                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 478                     has_msr_star = true;
 479                     continue;
 480                 }
 481                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 482                     has_msr_hsave_pa = true;
 483                     continue;
 484                 }
 485             }
 486         }
 487
 488         free(kvm_msr_list);
 489     }
 490
 491     return ret;
 492 }
 493
 494 int kvm_arch_init(KVMState *s)
 495 {
 496     uint64_t identity_base = 0xfffbc000;
 497     int ret;
 498     struct utsname utsname;
 499
 500     ret = kvm_get_supported_msrs(s);
 501     if (ret < 0) {
 502         return ret;
 503     }
 504
 505     uname(&utsname);
 506     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 507
 508     /*
 509      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 510      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 511      * Since these must be part of guest physical memory, we need to allocate
 512      * them, both by setting their start addresses in the kernel and by
 513      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 514      *
 515      * Older KVM versions may not support setting the identity map base. In
 516      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 517      * size.
 518      */
 519 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 520     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 521         /* Allows up to 16M BIOSes. */
 522         identity_base = 0xfeffc000;
 523
 524         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 525         if (ret < 0) {
 526             return ret;
 527         }
 528     }
 529 #endif
 530     /* Set TSS base one page after EPT identity map. */
 531     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 532     if (ret < 0) {
 533         return ret;
 534     }
 535
 536     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 537     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 538     if (ret < 0) {
 539         fprintf(stderr, "e820_add_entry() table is full\n");
 540         return ret;
 541     }
 542
 543     return 0;
 544 }
 545
 546 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 547 {
 548     lhs->selector = rhs->selector;
 549     lhs->base = rhs->base;
 550     lhs->limit = rhs->limit;
 551     lhs->type = 3;
 552     lhs->present = 1;
 553     lhs->dpl = 3;
 554     lhs->db = 0;
 555     lhs->s = 1;
 556     lhs->l = 0;
 557     lhs->g = 0;
 558     lhs->avl = 0;
 559     lhs->unusable = 0;
 560 }
 561
 562 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 563 {
 564     unsigned flags = rhs->flags;
 565     lhs->selector = rhs->selector;
 566     lhs->base = rhs->base;
 567     lhs->limit = rhs->limit;
 568     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 569     lhs->present = (flags & DESC_P_MASK) != 0;
 570     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 571     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 572     lhs->s = (flags & DESC_S_MASK) != 0;
 573     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 574     lhs->g = (flags & DESC_G_MASK) != 0;
 575     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 576     lhs->unusable = 0;
 577 }
 578
 579 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 580 {
 581     lhs->selector = rhs->selector;
 582     lhs->base = rhs->base;
 583     lhs->limit = rhs->limit;
 584     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 585                  (rhs->present * DESC_P_MASK) |
 586                  (rhs->dpl << DESC_DPL_SHIFT) |
 587                  (rhs->db << DESC_B_SHIFT) |
 588                  (rhs->s * DESC_S_MASK) |
 589                  (rhs->l << DESC_L_SHIFT) |
 590                  (rhs->g * DESC_G_MASK) |
 591                  (rhs->avl * DESC_AVL_MASK);
 592 }
 593
 594 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 595 {
 596     if (set) {
 597         *kvm_reg = *qemu_reg;
 598     } else {
 599         *qemu_reg = *kvm_reg;
 600     }
 601 }
 602
 603 static int kvm_getput_regs(CPUState *env, int set)
 604 {
 605     struct kvm_regs regs;
 606     int ret = 0;
 607
 608     if (!set) {
 609         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 610         if (ret < 0) {
 611             return ret;
 612         }
 613     }
 614
 615     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 616     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 617     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 618     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 619     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 620     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 621     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 622     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 623 #ifdef TARGET_X86_64
 624     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 625     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 626     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 627     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 628     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 629     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 630     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 631     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 632 #endif
 633
 634     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 635     kvm_getput_reg(&regs.rip, &env->eip, set);
 636
 637     if (set) {
 638         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 639     }
 640
 641     return ret;
 642 }
 643
 644 static int kvm_put_fpu(CPUState *env)
 645 {
 646     struct kvm_fpu fpu;
 647     int i;
 648
 649     memset(&fpu, 0, sizeof fpu);
 650     fpu.fsw = env->fpus & ~(7 << 11);
 651     fpu.fsw |= (env->fpstt & 7) << 11;
 652     fpu.fcw = env->fpuc;
 653     for (i = 0; i < 8; ++i) {
 654         fpu.ftwx |= (!env->fptags[i]) << i;
 655     }
 656     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 657     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 658     fpu.mxcsr = env->mxcsr;
 659
 660     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 661 }
 662
 663 #ifdef KVM_CAP_XSAVE
 664 #define XSAVE_CWD_RIP     2
 665 #define XSAVE_CWD_RDP     4
 666 #define XSAVE_MXCSR       6
 667 #define XSAVE_ST_SPACE    8
 668 #define XSAVE_XMM_SPACE   40
 669 #define XSAVE_XSTATE_BV   128
 670 #define XSAVE_YMMH_SPACE  144
 671 #endif
 672
 673 static int kvm_put_xsave(CPUState *env)
 674 {
 675 #ifdef KVM_CAP_XSAVE
 676     int i, r;
 677     struct kvm_xsave* xsave;
 678     uint16_t cwd, swd, twd, fop;
 679
 680     if (!kvm_has_xsave()) {
 681         return kvm_put_fpu(env);
 682     }
 683
 684     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 685     memset(xsave, 0, sizeof(struct kvm_xsave));
 686     cwd = swd = twd = fop = 0;
 687     swd = env->fpus & ~(7 << 11);
 688     swd |= (env->fpstt & 7) << 11;
 689     cwd = env->fpuc;
 690     for (i = 0; i < 8; ++i) {
 691         twd |= (!env->fptags[i]) << i;
 692     }
 693     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 694     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 695     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 696             sizeof env->fpregs);
 697     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 698             sizeof env->xmm_regs);
 699     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 700     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 701     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 702             sizeof env->ymmh_regs);
 703     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 704     qemu_free(xsave);
 705     return r;
 706 #else
 707     return kvm_put_fpu(env);
 708 #endif
 709 }
 710
 711 static int kvm_put_xcrs(CPUState *env)
 712 {
 713 #ifdef KVM_CAP_XCRS
 714     struct kvm_xcrs xcrs;
 715
 716     if (!kvm_has_xcrs()) {
 717         return 0;
 718     }
 719
 720     xcrs.nr_xcrs = 1;
 721     xcrs.flags = 0;
 722     xcrs.xcrs[0].xcr = 0;
 723     xcrs.xcrs[0].value = env->xcr0;
 724     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 725 #else
 726     return 0;
 727 #endif
 728 }
 729
 730 static int kvm_put_sregs(CPUState *env)
 731 {
 732     struct kvm_sregs sregs;
 733
 734     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 735     if (env->interrupt_injected >= 0) {
 736         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 737                 (uint64_t)1 << (env->interrupt_injected % 64);
 738     }
 739
 740     if ((env->eflags & VM_MASK)) {
 741         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 742         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 743         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 744         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 745         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 746         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 747     } else {
 748         set_seg(&sregs.cs, &env->segs[R_CS]);
 749         set_seg(&sregs.ds, &env->segs[R_DS]);
 750         set_seg(&sregs.es, &env->segs[R_ES]);
 751         set_seg(&sregs.fs, &env->segs[R_FS]);
 752         set_seg(&sregs.gs, &env->segs[R_GS]);
 753         set_seg(&sregs.ss, &env->segs[R_SS]);
 754     }
 755
 756     set_seg(&sregs.tr, &env->tr);
 757     set_seg(&sregs.ldt, &env->ldt);
 758
 759     sregs.idt.limit = env->idt.limit;
 760     sregs.idt.base = env->idt.base;
 761     sregs.gdt.limit = env->gdt.limit;
 762     sregs.gdt.base = env->gdt.base;
 763
 764     sregs.cr0 = env->cr[0];
 765     sregs.cr2 = env->cr[2];
 766     sregs.cr3 = env->cr[3];
 767     sregs.cr4 = env->cr[4];
 768
 769     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 770     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 771
 772     sregs.efer = env->efer;
 773
 774     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 775 }
 776
 777 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 778                               uint32_t index, uint64_t value)
 779 {
 780     entry->index = index;
 781     entry->data = value;
 782 }
 783
 784 static int kvm_put_msrs(CPUState *env, int level)
 785 {
 786     struct {
 787         struct kvm_msrs info;
 788         struct kvm_msr_entry entries[100];
 789     } msr_data;
 790     struct kvm_msr_entry *msrs = msr_data.entries;
 791     int n = 0;
 792
 793     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 794     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 795     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 796     if (has_msr_star) {
 797         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 798     }
 799     if (has_msr_hsave_pa) {
 800         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 801     }
 802 #ifdef TARGET_X86_64
 803     if (lm_capable_kernel) {
 804         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 805         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 806         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 807         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 808     }
 809 #endif
 810     if (level == KVM_PUT_FULL_STATE) {
 811         /*
 812          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 813          * writeback. Until this is fixed, we only write the offset to SMP
 814          * guests after migration, desynchronizing the VCPUs, but avoiding
 815          * huge jump-backs that would occur without any writeback at all.
 816          */
 817         if (smp_cpus == 1 || env->tsc != 0) {
 818             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 819         }
 820     }
 821     /*
 822      * The following paravirtual MSRs have side effects on the guest or are
 823      * too heavy for normal writeback. Limit them to reset or full state
 824      * updates.
 825      */
 826     if (level >= KVM_PUT_RESET_STATE) {
 827         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 828                           env->system_time_msr);
 829         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 830 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
 831         kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
 832 #endif
 833     }
 834 #ifdef KVM_CAP_MCE
 835     if (env->mcg_cap) {
 836         int i;
 837
 838         if (level == KVM_PUT_RESET_STATE) {
 839             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 840         } else if (level == KVM_PUT_FULL_STATE) {
 841             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 842             kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 843             for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 844                 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 845             }
 846         }
 847     }
 848 #endif
 849
 850     msr_data.info.nmsrs = n;
 851
 852     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 853
 854 }
 855
 856
 857 static int kvm_get_fpu(CPUState *env)
 858 {
 859     struct kvm_fpu fpu;
 860     int i, ret;
 861
 862     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 863     if (ret < 0) {
 864         return ret;
 865     }
 866
 867     env->fpstt = (fpu.fsw >> 11) & 7;
 868     env->fpus = fpu.fsw;
 869     env->fpuc = fpu.fcw;
 870     for (i = 0; i < 8; ++i) {
 871         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 872     }
 873     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 874     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 875     env->mxcsr = fpu.mxcsr;
 876
 877     return 0;
 878 }
 879
 880 static int kvm_get_xsave(CPUState *env)
 881 {
 882 #ifdef KVM_CAP_XSAVE
 883     struct kvm_xsave* xsave;
 884     int ret, i;
 885     uint16_t cwd, swd, twd, fop;
 886
 887     if (!kvm_has_xsave()) {
 888         return kvm_get_fpu(env);
 889     }
 890
 891     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 892     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 893     if (ret < 0) {
 894         qemu_free(xsave);
 895         return ret;
 896     }
 897
 898     cwd = (uint16_t)xsave->region[0];
 899     swd = (uint16_t)(xsave->region[0] >> 16);
 900     twd = (uint16_t)xsave->region[1];
 901     fop = (uint16_t)(xsave->region[1] >> 16);
 902     env->fpstt = (swd >> 11) & 7;
 903     env->fpus = swd;
 904     env->fpuc = cwd;
 905     for (i = 0; i < 8; ++i) {
 906         env->fptags[i] = !((twd >> i) & 1);
 907     }
 908     env->mxcsr = xsave->region[XSAVE_MXCSR];
 909     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 910             sizeof env->fpregs);
 911     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 912             sizeof env->xmm_regs);
 913     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 914     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 915             sizeof env->ymmh_regs);
 916     qemu_free(xsave);
 917     return 0;
 918 #else
 919     return kvm_get_fpu(env);
 920 #endif
 921 }
 922
 923 static int kvm_get_xcrs(CPUState *env)
 924 {
 925 #ifdef KVM_CAP_XCRS
 926     int i, ret;
 927     struct kvm_xcrs xcrs;
 928
 929     if (!kvm_has_xcrs()) {
 930         return 0;
 931     }
 932
 933     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 934     if (ret < 0) {
 935         return ret;
 936     }
 937
 938     for (i = 0; i < xcrs.nr_xcrs; i++) {
 939         /* Only support xcr0 now */
 940         if (xcrs.xcrs[0].xcr == 0) {
 941             env->xcr0 = xcrs.xcrs[0].value;
 942             break;
 943         }
 944     }
 945     return 0;
 946 #else
 947     return 0;
 948 #endif
 949 }
 950
 951 static int kvm_get_sregs(CPUState *env)
 952 {
 953     struct kvm_sregs sregs;
 954     uint32_t hflags;
 955     int bit, i, ret;
 956
 957     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 958     if (ret < 0) {
 959         return ret;
 960     }
 961
 962     /* There can only be one pending IRQ set in the bitmap at a time, so try
 963        to find it and save its number instead (-1 for none). */
 964     env->interrupt_injected = -1;
 965     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 966         if (sregs.interrupt_bitmap[i]) {
 967             bit = ctz64(sregs.interrupt_bitmap[i]);
 968             env->interrupt_injected = i * 64 + bit;
 969             break;
 970         }
 971     }
 972
 973     get_seg(&env->segs[R_CS], &sregs.cs);
 974     get_seg(&env->segs[R_DS], &sregs.ds);
 975     get_seg(&env->segs[R_ES], &sregs.es);
 976     get_seg(&env->segs[R_FS], &sregs.fs);
 977     get_seg(&env->segs[R_GS], &sregs.gs);
 978     get_seg(&env->segs[R_SS], &sregs.ss);
 979
 980     get_seg(&env->tr, &sregs.tr);
 981     get_seg(&env->ldt, &sregs.ldt);
 982
 983     env->idt.limit = sregs.idt.limit;
 984     env->idt.base = sregs.idt.base;
 985     env->gdt.limit = sregs.gdt.limit;
 986     env->gdt.base = sregs.gdt.base;
 987
 988     env->cr[0] = sregs.cr0;
 989     env->cr[2] = sregs.cr2;
 990     env->cr[3] = sregs.cr3;
 991     env->cr[4] = sregs.cr4;
 992
 993     cpu_set_apic_base(env->apic_state, sregs.apic_base);
 994
 995     env->efer = sregs.efer;
 996     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
 997
 998 #define HFLAG_COPY_MASK \
 999     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1000        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1001        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1002        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1003
1004     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1005     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1006     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1007                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1008     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1009     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1010                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1011
1012     if (env->efer & MSR_EFER_LMA) {
1013         hflags |= HF_LMA_MASK;
1014     }
1015
1016     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1017         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1018     } else {
1019         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1020                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1021         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1022                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1023         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1024             !(hflags & HF_CS32_MASK)) {
1025             hflags |= HF_ADDSEG_MASK;
1026         } else {
1027             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1028                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1029         }
1030     }
1031     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1032
1033     return 0;
1034 }
1035
1036 static int kvm_get_msrs(CPUState *env)
1037 {
1038     struct {
1039         struct kvm_msrs info;
1040         struct kvm_msr_entry entries[100];
1041     } msr_data;
1042     struct kvm_msr_entry *msrs = msr_data.entries;
1043     int ret, i, n;
1044
1045     n = 0;
1046     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1047     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1048     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1049     if (has_msr_star) {
1050         msrs[n++].index = MSR_STAR;
1051     }
1052     if (has_msr_hsave_pa) {
1053         msrs[n++].index = MSR_VM_HSAVE_PA;
1054     }
1055     msrs[n++].index = MSR_IA32_TSC;
1056 #ifdef TARGET_X86_64
1057     if (lm_capable_kernel) {
1058         msrs[n++].index = MSR_CSTAR;
1059         msrs[n++].index = MSR_KERNELGSBASE;
1060         msrs[n++].index = MSR_FMASK;
1061         msrs[n++].index = MSR_LSTAR;
1062     }
1063 #endif
1064     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1065     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1066 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1067     msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1068 #endif
1069
1070 #ifdef KVM_CAP_MCE
1071     if (env->mcg_cap) {
1072         msrs[n++].index = MSR_MCG_STATUS;
1073         msrs[n++].index = MSR_MCG_CTL;
1074         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1075             msrs[n++].index = MSR_MC0_CTL + i;
1076         }
1077     }
1078 #endif
1079
1080     msr_data.info.nmsrs = n;
1081     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1082     if (ret < 0) {
1083         return ret;
1084     }
1085
1086     for (i = 0; i < ret; i++) {
1087         switch (msrs[i].index) {
1088         case MSR_IA32_SYSENTER_CS:
1089             env->sysenter_cs = msrs[i].data;
1090             break;
1091         case MSR_IA32_SYSENTER_ESP:
1092             env->sysenter_esp = msrs[i].data;
1093             break;
1094         case MSR_IA32_SYSENTER_EIP:
1095             env->sysenter_eip = msrs[i].data;
1096             break;
1097         case MSR_STAR:
1098             env->star = msrs[i].data;
1099             break;
1100 #ifdef TARGET_X86_64
1101         case MSR_CSTAR:
1102             env->cstar = msrs[i].data;
1103             break;
1104         case MSR_KERNELGSBASE:
1105             env->kernelgsbase = msrs[i].data;
1106             break;
1107         case MSR_FMASK:
1108             env->fmask = msrs[i].data;
1109             break;
1110         case MSR_LSTAR:
1111             env->lstar = msrs[i].data;
1112             break;
1113 #endif
1114         case MSR_IA32_TSC:
1115             env->tsc = msrs[i].data;
1116             break;
1117         case MSR_VM_HSAVE_PA:
1118             env->vm_hsave = msrs[i].data;
1119             break;
1120         case MSR_KVM_SYSTEM_TIME:
1121             env->system_time_msr = msrs[i].data;
1122             break;
1123         case MSR_KVM_WALL_CLOCK:
1124             env->wall_clock_msr = msrs[i].data;
1125             break;
1126 #ifdef KVM_CAP_MCE
1127         case MSR_MCG_STATUS:
1128             env->mcg_status = msrs[i].data;
1129             break;
1130         case MSR_MCG_CTL:
1131             env->mcg_ctl = msrs[i].data;
1132             break;
1133 #endif
1134         default:
1135 #ifdef KVM_CAP_MCE
1136             if (msrs[i].index >= MSR_MC0_CTL &&
1137                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1138                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1139             }
1140 #endif
1141             break;
1142 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1143         case MSR_KVM_ASYNC_PF_EN:
1144             env->async_pf_en_msr = msrs[i].data;
1145             break;
1146 #endif
1147         }
1148     }
1149
1150     return 0;
1151 }
1152
1153 static int kvm_put_mp_state(CPUState *env)
1154 {
1155     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1156
1157     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1158 }
1159
1160 static int kvm_get_mp_state(CPUState *env)
1161 {
1162     struct kvm_mp_state mp_state;
1163     int ret;
1164
1165     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1166     if (ret < 0) {
1167         return ret;
1168     }
1169     env->mp_state = mp_state.mp_state;
1170     if (kvm_irqchip_in_kernel()) {
1171         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1172     }
1173     return 0;
1174 }
1175
1176 static int kvm_put_vcpu_events(CPUState *env, int level)
1177 {
1178 #ifdef KVM_CAP_VCPU_EVENTS
1179     struct kvm_vcpu_events events;
1180
1181     if (!kvm_has_vcpu_events()) {
1182         return 0;
1183     }
1184
1185     events.exception.injected = (env->exception_injected >= 0);
1186     events.exception.nr = env->exception_injected;
1187     events.exception.has_error_code = env->has_error_code;
1188     events.exception.error_code = env->error_code;
1189
1190     events.interrupt.injected = (env->interrupt_injected >= 0);
1191     events.interrupt.nr = env->interrupt_injected;
1192     events.interrupt.soft = env->soft_interrupt;
1193
1194     events.nmi.injected = env->nmi_injected;
1195     events.nmi.pending = env->nmi_pending;
1196     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1197
1198     events.sipi_vector = env->sipi_vector;
1199
1200     events.flags = 0;
1201     if (level >= KVM_PUT_RESET_STATE) {
1202         events.flags |=
1203             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1204     }
1205
1206     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1207 #else
1208     return 0;
1209 #endif
1210 }
1211
1212 static int kvm_get_vcpu_events(CPUState *env)
1213 {
1214 #ifdef KVM_CAP_VCPU_EVENTS
1215     struct kvm_vcpu_events events;
1216     int ret;
1217
1218     if (!kvm_has_vcpu_events()) {
1219         return 0;
1220     }
1221
1222     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1223     if (ret < 0) {
1224        return ret;
1225     }
1226     env->exception_injected =
1227        events.exception.injected ? events.exception.nr : -1;
1228     env->has_error_code = events.exception.has_error_code;
1229     env->error_code = events.exception.error_code;
1230
1231     env->interrupt_injected =
1232         events.interrupt.injected ? events.interrupt.nr : -1;
1233     env->soft_interrupt = events.interrupt.soft;
1234
1235     env->nmi_injected = events.nmi.injected;
1236     env->nmi_pending = events.nmi.pending;
1237     if (events.nmi.masked) {
1238         env->hflags2 |= HF2_NMI_MASK;
1239     } else {
1240         env->hflags2 &= ~HF2_NMI_MASK;
1241     }
1242
1243     env->sipi_vector = events.sipi_vector;
1244 #endif
1245
1246     return 0;
1247 }
1248
1249 static int kvm_guest_debug_workarounds(CPUState *env)
1250 {
1251     int ret = 0;
1252 #ifdef KVM_CAP_SET_GUEST_DEBUG
1253     unsigned long reinject_trap = 0;
1254
1255     if (!kvm_has_vcpu_events()) {
1256         if (env->exception_injected == 1) {
1257             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1258         } else if (env->exception_injected == 3) {
1259             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1260         }
1261         env->exception_injected = -1;
1262     }
1263
1264     /*
1265      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1266      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1267      * by updating the debug state once again if single-stepping is on.
1268      * Another reason to call kvm_update_guest_debug here is a pending debug
1269      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1270      * reinject them via SET_GUEST_DEBUG.
1271      */
1272     if (reinject_trap ||
1273         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1274         ret = kvm_update_guest_debug(env, reinject_trap);
1275     }
1276 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1277     return ret;
1278 }
1279
1280 static int kvm_put_debugregs(CPUState *env)
1281 {
1282 #ifdef KVM_CAP_DEBUGREGS
1283     struct kvm_debugregs dbgregs;
1284     int i;
1285
1286     if (!kvm_has_debugregs()) {
1287         return 0;
1288     }
1289
1290     for (i = 0; i < 4; i++) {
1291         dbgregs.db[i] = env->dr[i];
1292     }
1293     dbgregs.dr6 = env->dr[6];
1294     dbgregs.dr7 = env->dr[7];
1295     dbgregs.flags = 0;
1296
1297     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1298 #else
1299     return 0;
1300 #endif
1301 }
1302
1303 static int kvm_get_debugregs(CPUState *env)
1304 {
1305 #ifdef KVM_CAP_DEBUGREGS
1306     struct kvm_debugregs dbgregs;
1307     int i, ret;
1308
1309     if (!kvm_has_debugregs()) {
1310         return 0;
1311     }
1312
1313     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1314     if (ret < 0) {
1315         return ret;
1316     }
1317     for (i = 0; i < 4; i++) {
1318         env->dr[i] = dbgregs.db[i];
1319     }
1320     env->dr[4] = env->dr[6] = dbgregs.dr6;
1321     env->dr[5] = env->dr[7] = dbgregs.dr7;
1322 #endif
1323
1324     return 0;
1325 }
1326
1327 int kvm_arch_put_registers(CPUState *env, int level)
1328 {
1329     int ret;
1330
1331     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1332
1333     ret = kvm_getput_regs(env, 1);
1334     if (ret < 0) {
1335         return ret;
1336     }
1337     ret = kvm_put_xsave(env);
1338     if (ret < 0) {
1339         return ret;
1340     }
1341     ret = kvm_put_xcrs(env);
1342     if (ret < 0) {
1343         return ret;
1344     }
1345     ret = kvm_put_sregs(env);
1346     if (ret < 0) {
1347         return ret;
1348     }
1349     ret = kvm_put_msrs(env, level);
1350     if (ret < 0) {
1351         return ret;
1352     }
1353     if (level >= KVM_PUT_RESET_STATE) {
1354         ret = kvm_put_mp_state(env);
1355         if (ret < 0) {
1356             return ret;
1357         }
1358     }
1359     ret = kvm_put_vcpu_events(env, level);
1360     if (ret < 0) {
1361         return ret;
1362     }
1363     ret = kvm_put_debugregs(env);
1364     if (ret < 0) {
1365         return ret;
1366     }
1367     /* must be last */
1368     ret = kvm_guest_debug_workarounds(env);
1369     if (ret < 0) {
1370         return ret;
1371     }
1372     return 0;
1373 }
1374
1375 int kvm_arch_get_registers(CPUState *env)
1376 {
1377     int ret;
1378
1379     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1380
1381     ret = kvm_getput_regs(env, 0);
1382     if (ret < 0) {
1383         return ret;
1384     }
1385     ret = kvm_get_xsave(env);
1386     if (ret < 0) {
1387         return ret;
1388     }
1389     ret = kvm_get_xcrs(env);
1390     if (ret < 0) {
1391         return ret;
1392     }
1393     ret = kvm_get_sregs(env);
1394     if (ret < 0) {
1395         return ret;
1396     }
1397     ret = kvm_get_msrs(env);
1398     if (ret < 0) {
1399         return ret;
1400     }
1401     ret = kvm_get_mp_state(env);
1402     if (ret < 0) {
1403         return ret;
1404     }
1405     ret = kvm_get_vcpu_events(env);
1406     if (ret < 0) {
1407         return ret;
1408     }
1409     ret = kvm_get_debugregs(env);
1410     if (ret < 0) {
1411         return ret;
1412     }
1413     return 0;
1414 }
1415
1416 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1417 {
1418     /* Inject NMI */
1419     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1420         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1421         DPRINTF("injected NMI\n");
1422         kvm_vcpu_ioctl(env, KVM_NMI);
1423     }
1424
1425     /* Try to inject an interrupt if the guest can accept it */
1426     if (run->ready_for_interrupt_injection &&
1427         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1428         (env->eflags & IF_MASK)) {
1429         int irq;
1430
1431         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1432         irq = cpu_get_pic_interrupt(env);
1433         if (irq >= 0) {
1434             struct kvm_interrupt intr;
1435             intr.irq = irq;
1436             /* FIXME: errors */
1437             DPRINTF("injected interrupt %d\n", irq);
1438             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1439         }
1440     }
1441
1442     /* If we have an interrupt but the guest is not ready to receive an
1443      * interrupt, request an interrupt window exit.  This will
1444      * cause a return to userspace as soon as the guest is ready to
1445      * receive interrupts. */
1446     if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1447         run->request_interrupt_window = 1;
1448     } else {
1449         run->request_interrupt_window = 0;
1450     }
1451
1452     DPRINTF("setting tpr\n");
1453     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1454
1455     return 0;
1456 }
1457
1458 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1459 {
1460     if (run->if_flag) {
1461         env->eflags |= IF_MASK;
1462     } else {
1463         env->eflags &= ~IF_MASK;
1464     }
1465     cpu_set_apic_tpr(env->apic_state, run->cr8);
1466     cpu_set_apic_base(env->apic_state, run->apic_base);
1467
1468     return 0;
1469 }
1470
1471 int kvm_arch_process_irqchip_events(CPUState *env)
1472 {
1473     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1474         kvm_cpu_synchronize_state(env);
1475         do_cpu_init(env);
1476         env->exception_index = EXCP_HALTED;
1477     }
1478
1479     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1480         kvm_cpu_synchronize_state(env);
1481         do_cpu_sipi(env);
1482     }
1483
1484     return env->halted;
1485 }
1486
1487 static int kvm_handle_halt(CPUState *env)
1488 {
1489     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1490           (env->eflags & IF_MASK)) &&
1491         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1492         env->halted = 1;
1493         env->exception_index = EXCP_HLT;
1494         return 0;
1495     }
1496
1497     return 1;
1498 }
1499
1500 static bool host_supports_vmx(void)
1501 {
1502     uint32_t ecx, unused;
1503
1504     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1505     return ecx & CPUID_EXT_VMX;
1506 }
1507
1508 #define VMX_INVALID_GUEST_STATE 0x80000021
1509
1510 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1511 {
1512     uint64_t code;
1513     int ret = 0;
1514
1515     switch (run->exit_reason) {
1516     case KVM_EXIT_HLT:
1517         DPRINTF("handle_hlt\n");
1518         ret = kvm_handle_halt(env);
1519         break;
1520     case KVM_EXIT_SET_TPR:
1521         ret = 1;
1522         break;
1523     case KVM_EXIT_FAIL_ENTRY:
1524         code = run->fail_entry.hardware_entry_failure_reason;
1525         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1526                 code);
1527         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1528             fprintf(stderr,
1529                     "\nIf you're runnning a guest on an Intel machine without "
1530                         "unrestricted mode\n"
1531                     "support, the failure can be most likely due to the guest "
1532                         "entering an invalid\n"
1533                     "state for Intel VT. For example, the guest maybe running "
1534                         "in big real mode\n"
1535                     "which is not supported on less recent Intel processors."
1536                         "\n\n");
1537         }
1538         ret = -1;
1539         break;
1540     case KVM_EXIT_EXCEPTION:
1541         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1542                 run->ex.exception, run->ex.error_code);
1543         ret = -1;
1544         break;
1545     default:
1546         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1547         ret = -1;
1548         break;
1549     }
1550
1551     return ret;
1552 }
1553
1554 #ifdef KVM_CAP_SET_GUEST_DEBUG
1555 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1556 {
1557     static const uint8_t int3 = 0xcc;
1558
1559     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1560         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1561         return -EINVAL;
1562     }
1563     return 0;
1564 }
1565
1566 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1567 {
1568     uint8_t int3;
1569
1570     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1571         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1572         return -EINVAL;
1573     }
1574     return 0;
1575 }
1576
1577 static struct {
1578     target_ulong addr;
1579     int len;
1580     int type;
1581 } hw_breakpoint[4];
1582
1583 static int nb_hw_breakpoint;
1584
1585 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1586 {
1587     int n;
1588
1589     for (n = 0; n < nb_hw_breakpoint; n++) {
1590         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1591             (hw_breakpoint[n].len == len || len == -1)) {
1592             return n;
1593         }
1594     }
1595     return -1;
1596 }
1597
1598 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1599                                   target_ulong len, int type)
1600 {
1601     switch (type) {
1602     case GDB_BREAKPOINT_HW:
1603         len = 1;
1604         break;
1605     case GDB_WATCHPOINT_WRITE:
1606     case GDB_WATCHPOINT_ACCESS:
1607         switch (len) {
1608         case 1:
1609             break;
1610         case 2:
1611         case 4:
1612         case 8:
1613             if (addr & (len - 1)) {
1614                 return -EINVAL;
1615             }
1616             break;
1617         default:
1618             return -EINVAL;
1619         }
1620         break;
1621     default:
1622         return -ENOSYS;
1623     }
1624
1625     if (nb_hw_breakpoint == 4) {
1626         return -ENOBUFS;
1627     }
1628     if (find_hw_breakpoint(addr, len, type) >= 0) {
1629         return -EEXIST;
1630     }
1631     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1632     hw_breakpoint[nb_hw_breakpoint].len = len;
1633     hw_breakpoint[nb_hw_breakpoint].type = type;
1634     nb_hw_breakpoint++;
1635
1636     return 0;
1637 }
1638
1639 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1640                                   target_ulong len, int type)
1641 {
1642     int n;
1643
1644     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1645     if (n < 0) {
1646         return -ENOENT;
1647     }
1648     nb_hw_breakpoint--;
1649     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1650
1651     return 0;
1652 }
1653
1654 void kvm_arch_remove_all_hw_breakpoints(void)
1655 {
1656     nb_hw_breakpoint = 0;
1657 }
1658
1659 static CPUWatchpoint hw_watchpoint;
1660
1661 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1662 {
1663     int handle = 0;
1664     int n;
1665
1666     if (arch_info->exception == 1) {
1667         if (arch_info->dr6 & (1 << 14)) {
1668             if (cpu_single_env->singlestep_enabled) {
1669                 handle = 1;
1670             }
1671         } else {
1672             for (n = 0; n < 4; n++) {
1673                 if (arch_info->dr6 & (1 << n)) {
1674                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1675                     case 0x0:
1676                         handle = 1;
1677                         break;
1678                     case 0x1:
1679                         handle = 1;
1680                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1681                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1682                         hw_watchpoint.flags = BP_MEM_WRITE;
1683                         break;
1684                     case 0x3:
1685                         handle = 1;
1686                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1687                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1688                         hw_watchpoint.flags = BP_MEM_ACCESS;
1689                         break;
1690                     }
1691                 }
1692             }
1693         }
1694     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1695         handle = 1;
1696     }
1697     if (!handle) {
1698         cpu_synchronize_state(cpu_single_env);
1699         assert(cpu_single_env->exception_injected == -1);
1700
1701         cpu_single_env->exception_injected = arch_info->exception;
1702         cpu_single_env->has_error_code = 0;
1703     }
1704
1705     return handle;
1706 }
1707
1708 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1709 {
1710     const uint8_t type_code[] = {
1711         [GDB_BREAKPOINT_HW] = 0x0,
1712         [GDB_WATCHPOINT_WRITE] = 0x1,
1713         [GDB_WATCHPOINT_ACCESS] = 0x3
1714     };
1715     const uint8_t len_code[] = {
1716         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1717     };
1718     int n;
1719
1720     if (kvm_sw_breakpoints_active(env)) {
1721         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1722     }
1723     if (nb_hw_breakpoint > 0) {
1724         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1725         dbg->arch.debugreg[7] = 0x0600;
1726         for (n = 0; n < nb_hw_breakpoint; n++) {
1727             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1728             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1729                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1730                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1731         }
1732     }
1733 }
1734 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1735
1736 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1737 {
1738     return !(env->cr[0] & CR0_PE_MASK) ||
1739            ((env->segs[R_CS].selector  & 3) != 3);
1740 }
1741
1742 static void hardware_memory_error(void)
1743 {
1744     fprintf(stderr, "Hardware memory error!\n");
1745     exit(1);
1746 }
1747
1748 #ifdef KVM_CAP_MCE
1749 static void kvm_mce_broadcast_rest(CPUState *env)
1750 {
1751     struct kvm_x86_mce mce = {
1752         .bank = 1,
1753         .status = MCI_STATUS_VAL | MCI_STATUS_UC,
1754         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1755         .addr = 0,
1756         .misc = 0,
1757     };
1758     CPUState *cenv;
1759
1760     /* Broadcast MCA signal for processor version 06H_EH and above */
1761     if (cpu_x86_support_mca_broadcast(env)) {
1762         for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1763             if (cenv == env) {
1764                 continue;
1765             }
1766             kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR);
1767         }
1768     }
1769 }
1770
1771 static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr)
1772 {
1773     struct kvm_x86_mce mce = {
1774         .bank = 9,
1775         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1776                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1777                   | MCI_STATUS_AR | 0x134,
1778         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV,
1779         .addr = paddr,
1780         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1781     };
1782     int r;
1783
1784     r = kvm_set_mce(env, &mce);
1785     if (r < 0) {
1786         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1787         abort();
1788     }
1789     kvm_mce_broadcast_rest(env);
1790 }
1791
1792 static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr)
1793 {
1794     struct kvm_x86_mce mce = {
1795         .bank = 9,
1796         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1797                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1798                   | 0xc0,
1799         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1800         .addr = paddr,
1801         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1802     };
1803     int r;
1804
1805     r = kvm_set_mce(env, &mce);
1806     if (r < 0) {
1807         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1808         abort();
1809     }
1810     kvm_mce_broadcast_rest(env);
1811 }
1812
1813 static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr)
1814 {
1815     struct kvm_x86_mce mce = {
1816         .bank = 9,
1817         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1818                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1819                   | 0xc0,
1820         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1821         .addr = paddr,
1822         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1823     };
1824
1825     kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR);
1826     kvm_mce_broadcast_rest(env);
1827 }
1828
1829 #endif
1830
1831 int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1832 {
1833 #if defined(KVM_CAP_MCE)
1834     void *vaddr;
1835     ram_addr_t ram_addr;
1836     target_phys_addr_t paddr;
1837
1838     if ((env->mcg_cap & MCG_SER_P) && addr
1839         && (code == BUS_MCEERR_AR
1840             || code == BUS_MCEERR_AO)) {
1841         vaddr = (void *)addr;
1842         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1843             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1844             fprintf(stderr, "Hardware memory error for memory used by "
1845                     "QEMU itself instead of guest system!\n");
1846             /* Hope we are lucky for AO MCE */
1847             if (code == BUS_MCEERR_AO) {
1848                 return 0;
1849             } else {
1850                 hardware_memory_error();
1851             }
1852         }
1853
1854         if (code == BUS_MCEERR_AR) {
1855             /* Fake an Intel architectural Data Load SRAR UCR */
1856             kvm_mce_inj_srar_dataload(env, paddr);
1857         } else {
1858             /*
1859              * If there is an MCE excpetion being processed, ignore
1860              * this SRAO MCE
1861              */
1862             if (!kvm_mce_in_progress(env)) {
1863                 /* Fake an Intel architectural Memory scrubbing UCR */
1864                 kvm_mce_inj_srao_memscrub(env, paddr);
1865             }
1866         }
1867     } else
1868 #endif
1869     {
1870         if (code == BUS_MCEERR_AO) {
1871             return 0;
1872         } else if (code == BUS_MCEERR_AR) {
1873             hardware_memory_error();
1874         } else {
1875             return 1;
1876         }
1877     }
1878     return 0;
1879 }
1880
1881 int kvm_on_sigbus(int code, void *addr)
1882 {
1883 #if defined(KVM_CAP_MCE)
1884     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1885         void *vaddr;
1886         ram_addr_t ram_addr;
1887         target_phys_addr_t paddr;
1888
1889         /* Hope we are lucky for AO MCE */
1890         vaddr = addr;
1891         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1892             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1893             fprintf(stderr, "Hardware memory error for memory used by "
1894                     "QEMU itself instead of guest system!: %p\n", addr);
1895             return 0;
1896         }
1897         kvm_mce_inj_srao_memscrub2(first_cpu, paddr);
1898     } else
1899 #endif
1900     {
1901         if (code == BUS_MCEERR_AO) {
1902             return 0;
1903         } else if (code == BUS_MCEERR_AR) {
1904             hardware_memory_error();
1905         } else {
1906             return 1;
1907         }
1908     }
1909     return 0;
1910 }