target-i386/machine.c

   1 #include "qemu/osdep.h"
   2 #include "hw/hw.h"
   3 #include "hw/boards.h"
   4 #include "hw/i386/pc.h"
   5 #include "hw/isa/isa.h"
   6 #include "migration/cpu.h"
   7
   8 #include "cpu.h"
   9 #include "sysemu/kvm.h"
  10
  11 #include "qemu/error-report.h"
  12
  13 static const VMStateDescription vmstate_segment = {
  14     .name = "segment",
  15     .version_id = 1,
  16     .minimum_version_id = 1,
  17     .fields = (VMStateField[]) {
  18         VMSTATE_UINT32(selector, SegmentCache),
  19         VMSTATE_UINTTL(base, SegmentCache),
  20         VMSTATE_UINT32(limit, SegmentCache),
  21         VMSTATE_UINT32(flags, SegmentCache),
  22         VMSTATE_END_OF_LIST()
  23     }
  24 };
  25
  26 #define VMSTATE_SEGMENT(_field, _state) {                            \
  27     .name       = (stringify(_field)),                               \
  28     .size       = sizeof(SegmentCache),                              \
  29     .vmsd       = &vmstate_segment,                                  \
  30     .flags      = VMS_STRUCT,                                        \
  31     .offset     = offsetof(_state, _field)                           \
  32             + type_check(SegmentCache,typeof_field(_state, _field))  \
  33 }
  34
  35 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  36     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  37
  38 static const VMStateDescription vmstate_xmm_reg = {
  39     .name = "xmm_reg",
  40     .version_id = 1,
  41     .minimum_version_id = 1,
  42     .fields = (VMStateField[]) {
  43         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  44         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  45         VMSTATE_END_OF_LIST()
  46     }
  47 };
  48
  49 #define VMSTATE_XMM_REGS(_field, _state, _start)                         \
  50     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  51                              vmstate_xmm_reg, ZMMReg)
  52
  53 /* YMMH format is the same as XMM, but for bits 128-255 */
  54 static const VMStateDescription vmstate_ymmh_reg = {
  55     .name = "ymmh_reg",
  56     .version_id = 1,
  57     .minimum_version_id = 1,
  58     .fields = (VMStateField[]) {
  59         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  60         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  61         VMSTATE_END_OF_LIST()
  62     }
  63 };
  64
  65 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v)               \
  66     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v,    \
  67                              vmstate_ymmh_reg, ZMMReg)
  68
  69 static const VMStateDescription vmstate_zmmh_reg = {
  70     .name = "zmmh_reg",
  71     .version_id = 1,
  72     .minimum_version_id = 1,
  73     .fields = (VMStateField[]) {
  74         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  75         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
  76         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
  77         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
  78         VMSTATE_END_OF_LIST()
  79     }
  80 };
  81
  82 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start)                   \
  83     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  84                              vmstate_zmmh_reg, ZMMReg)
  85
  86 #ifdef TARGET_X86_64
  87 static const VMStateDescription vmstate_hi16_zmm_reg = {
  88     .name = "hi16_zmm_reg",
  89     .version_id = 1,
  90     .minimum_version_id = 1,
  91     .fields = (VMStateField[]) {
  92         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  93         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  94         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  95         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  96         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  97         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
  98         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
  99         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
 100         VMSTATE_END_OF_LIST()
 101     }
 102 };
 103
 104 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start)               \
 105     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
 106                              vmstate_hi16_zmm_reg, ZMMReg)
 107 #endif
 108
 109 static const VMStateDescription vmstate_bnd_regs = {
 110     .name = "bnd_regs",
 111     .version_id = 1,
 112     .minimum_version_id = 1,
 113     .fields = (VMStateField[]) {
 114         VMSTATE_UINT64(lb, BNDReg),
 115         VMSTATE_UINT64(ub, BNDReg),
 116         VMSTATE_END_OF_LIST()
 117     }
 118 };
 119
 120 #define VMSTATE_BND_REGS(_field, _state, _n)          \
 121     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
 122
 123 static const VMStateDescription vmstate_mtrr_var = {
 124     .name = "mtrr_var",
 125     .version_id = 1,
 126     .minimum_version_id = 1,
 127     .fields = (VMStateField[]) {
 128         VMSTATE_UINT64(base, MTRRVar),
 129         VMSTATE_UINT64(mask, MTRRVar),
 130         VMSTATE_END_OF_LIST()
 131     }
 132 };
 133
 134 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
 135     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
 136
 137 static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
 138 {
 139     fprintf(stderr, "call put_fpreg() with invalid arguments\n");
 140     exit(0);
 141 }
 142
 143 /* XXX: add that in a FPU generic layer */
 144 union x86_longdouble {
 145     uint64_t mant;
 146     uint16_t exp;
 147 };
 148
 149 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
 150 #define EXPBIAS1 1023
 151 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
 152 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
 153
 154 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
 155 {
 156     int e;
 157     /* mantissa */
 158     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 159     /* exponent + sign */
 160     e = EXPD1(temp) - EXPBIAS1 + 16383;
 161     e |= SIGND1(temp) >> 16;
 162     p->exp = e;
 163 }
 164
 165 static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
 166 {
 167     FPReg *fp_reg = opaque;
 168     uint64_t mant;
 169     uint16_t exp;
 170
 171     qemu_get_be64s(f, &mant);
 172     qemu_get_be16s(f, &exp);
 173     fp_reg->d = cpu_set_fp80(mant, exp);
 174     return 0;
 175 }
 176
 177 static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
 178 {
 179     FPReg *fp_reg = opaque;
 180     uint64_t mant;
 181     uint16_t exp;
 182     /* we save the real CPU data (in case of MMX usage only 'mant'
 183        contains the MMX register */
 184     cpu_get_fp80(&mant, &exp, fp_reg->d);
 185     qemu_put_be64s(f, &mant);
 186     qemu_put_be16s(f, &exp);
 187 }
 188
 189 static const VMStateInfo vmstate_fpreg = {
 190     .name = "fpreg",
 191     .get  = get_fpreg,
 192     .put  = put_fpreg,
 193 };
 194
 195 static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
 196 {
 197     union x86_longdouble *p = opaque;
 198     uint64_t mant;
 199
 200     qemu_get_be64s(f, &mant);
 201     p->mant = mant;
 202     p->exp = 0xffff;
 203     return 0;
 204 }
 205
 206 static const VMStateInfo vmstate_fpreg_1_mmx = {
 207     .name = "fpreg_1_mmx",
 208     .get  = get_fpreg_1_mmx,
 209     .put  = put_fpreg_error,
 210 };
 211
 212 static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
 213 {
 214     union x86_longdouble *p = opaque;
 215     uint64_t mant;
 216
 217     qemu_get_be64s(f, &mant);
 218     fp64_to_fp80(p, mant);
 219     return 0;
 220 }
 221
 222 static const VMStateInfo vmstate_fpreg_1_no_mmx = {
 223     .name = "fpreg_1_no_mmx",
 224     .get  = get_fpreg_1_no_mmx,
 225     .put  = put_fpreg_error,
 226 };
 227
 228 static bool fpregs_is_0(void *opaque, int version_id)
 229 {
 230     X86CPU *cpu = opaque;
 231     CPUX86State *env = &cpu->env;
 232
 233     return (env->fpregs_format_vmstate == 0);
 234 }
 235
 236 static bool fpregs_is_1_mmx(void *opaque, int version_id)
 237 {
 238     X86CPU *cpu = opaque;
 239     CPUX86State *env = &cpu->env;
 240     int guess_mmx;
 241
 242     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 243                  (env->fpus_vmstate & 0x3800) == 0);
 244     return (guess_mmx && (env->fpregs_format_vmstate == 1));
 245 }
 246
 247 static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
 248 {
 249     X86CPU *cpu = opaque;
 250     CPUX86State *env = &cpu->env;
 251     int guess_mmx;
 252
 253     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 254                  (env->fpus_vmstate & 0x3800) == 0);
 255     return (!guess_mmx && (env->fpregs_format_vmstate == 1));
 256 }
 257
 258 #define VMSTATE_FP_REGS(_field, _state, _n)                               \
 259     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
 260     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
 261     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
 262
 263 static bool version_is_5(void *opaque, int version_id)
 264 {
 265     return version_id == 5;
 266 }
 267
 268 #ifdef TARGET_X86_64
 269 static bool less_than_7(void *opaque, int version_id)
 270 {
 271     return version_id < 7;
 272 }
 273
 274 static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 275 {
 276     uint64_t *v = pv;
 277     *v = qemu_get_be32(f);
 278     return 0;
 279 }
 280
 281 static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 282 {
 283     uint64_t *v = pv;
 284     qemu_put_be32(f, *v);
 285 }
 286
 287 static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
 288     .name = "uint64_as_uint32",
 289     .get  = get_uint64_as_uint32,
 290     .put  = put_uint64_as_uint32,
 291 };
 292
 293 #define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
 294     VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
 295 #endif
 296
 297 static void cpu_pre_save(void *opaque)
 298 {
 299     X86CPU *cpu = opaque;
 300     CPUX86State *env = &cpu->env;
 301     int i;
 302
 303     /* FPU */
 304     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 305     env->fptag_vmstate = 0;
 306     for(i = 0; i < 8; i++) {
 307         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 308     }
 309
 310     env->fpregs_format_vmstate = 0;
 311
 312     /*
 313      * Real mode guest segments register DPL should be zero.
 314      * Older KVM version were setting it wrongly.
 315      * Fixing it will allow live migration to host with unrestricted guest
 316      * support (otherwise the migration will fail with invalid guest state
 317      * error).
 318      */
 319     if (!(env->cr[0] & CR0_PE_MASK) &&
 320         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 321         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 322         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 323         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 324         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 325         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 326         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 327     }
 328
 329 }
 330
 331 static int cpu_post_load(void *opaque, int version_id)
 332 {
 333     X86CPU *cpu = opaque;
 334     CPUState *cs = CPU(cpu);
 335     CPUX86State *env = &cpu->env;
 336     int i;
 337
 338     if (env->tsc_khz && env->user_tsc_khz &&
 339         env->tsc_khz != env->user_tsc_khz) {
 340         error_report("Mismatch between user-specified TSC frequency and "
 341                      "migrated TSC frequency");
 342         return -EINVAL;
 343     }
 344
 345     /*
 346      * Real mode guest segments register DPL should be zero.
 347      * Older KVM version were setting it wrongly.
 348      * Fixing it will allow live migration from such host that don't have
 349      * restricted guest support to a host with unrestricted guest support
 350      * (otherwise the migration will fail with invalid guest state
 351      * error).
 352      */
 353     if (!(env->cr[0] & CR0_PE_MASK) &&
 354         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 355         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 356         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 357         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 358         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 359         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 360         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 361     }
 362
 363     /* Older versions of QEMU incorrectly used CS.DPL as the CPL when
 364      * running under KVM.  This is wrong for conforming code segments.
 365      * Luckily, in our implementation the CPL field of hflags is redundant
 366      * and we can get the right value from the SS descriptor privilege level.
 367      */
 368     env->hflags &= ~HF_CPL_MASK;
 369     env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 370
 371     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 372     env->fpus = env->fpus_vmstate & ~0x3800;
 373     env->fptag_vmstate ^= 0xff;
 374     for(i = 0; i < 8; i++) {
 375         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 376     }
 377     update_fp_status(env);
 378
 379     cpu_breakpoint_remove_all(cs, BP_CPU);
 380     cpu_watchpoint_remove_all(cs, BP_CPU);
 381     {
 382         /* Indicate all breakpoints disabled, as they are, then
 383            let the helper re-enable them.  */
 384         target_ulong dr7 = env->dr[7];
 385         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
 386         cpu_x86_update_dr7(env, dr7);
 387     }
 388     tlb_flush(cs, 1);
 389
 390     if (tcg_enabled()) {
 391         cpu_smm_update(cpu);
 392     }
 393     return 0;
 394 }
 395
 396 static bool async_pf_msr_needed(void *opaque)
 397 {
 398     X86CPU *cpu = opaque;
 399
 400     return cpu->env.async_pf_en_msr != 0;
 401 }
 402
 403 static bool pv_eoi_msr_needed(void *opaque)
 404 {
 405     X86CPU *cpu = opaque;
 406
 407     return cpu->env.pv_eoi_en_msr != 0;
 408 }
 409
 410 static bool steal_time_msr_needed(void *opaque)
 411 {
 412     X86CPU *cpu = opaque;
 413
 414     return cpu->env.steal_time_msr != 0;
 415 }
 416
 417 static const VMStateDescription vmstate_steal_time_msr = {
 418     .name = "cpu/steal_time_msr",
 419     .version_id = 1,
 420     .minimum_version_id = 1,
 421     .needed = steal_time_msr_needed,
 422     .fields = (VMStateField[]) {
 423         VMSTATE_UINT64(env.steal_time_msr, X86CPU),
 424         VMSTATE_END_OF_LIST()
 425     }
 426 };
 427
 428 static const VMStateDescription vmstate_async_pf_msr = {
 429     .name = "cpu/async_pf_msr",
 430     .version_id = 1,
 431     .minimum_version_id = 1,
 432     .needed = async_pf_msr_needed,
 433     .fields = (VMStateField[]) {
 434         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
 435         VMSTATE_END_OF_LIST()
 436     }
 437 };
 438
 439 static const VMStateDescription vmstate_pv_eoi_msr = {
 440     .name = "cpu/async_pv_eoi_msr",
 441     .version_id = 1,
 442     .minimum_version_id = 1,
 443     .needed = pv_eoi_msr_needed,
 444     .fields = (VMStateField[]) {
 445         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
 446         VMSTATE_END_OF_LIST()
 447     }
 448 };
 449
 450 static bool fpop_ip_dp_needed(void *opaque)
 451 {
 452     X86CPU *cpu = opaque;
 453     CPUX86State *env = &cpu->env;
 454
 455     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 456 }
 457
 458 static const VMStateDescription vmstate_fpop_ip_dp = {
 459     .name = "cpu/fpop_ip_dp",
 460     .version_id = 1,
 461     .minimum_version_id = 1,
 462     .needed = fpop_ip_dp_needed,
 463     .fields = (VMStateField[]) {
 464         VMSTATE_UINT16(env.fpop, X86CPU),
 465         VMSTATE_UINT64(env.fpip, X86CPU),
 466         VMSTATE_UINT64(env.fpdp, X86CPU),
 467         VMSTATE_END_OF_LIST()
 468     }
 469 };
 470
 471 static bool tsc_adjust_needed(void *opaque)
 472 {
 473     X86CPU *cpu = opaque;
 474     CPUX86State *env = &cpu->env;
 475
 476     return env->tsc_adjust != 0;
 477 }
 478
 479 static const VMStateDescription vmstate_msr_tsc_adjust = {
 480     .name = "cpu/msr_tsc_adjust",
 481     .version_id = 1,
 482     .minimum_version_id = 1,
 483     .needed = tsc_adjust_needed,
 484     .fields = (VMStateField[]) {
 485         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
 486         VMSTATE_END_OF_LIST()
 487     }
 488 };
 489
 490 static bool tscdeadline_needed(void *opaque)
 491 {
 492     X86CPU *cpu = opaque;
 493     CPUX86State *env = &cpu->env;
 494
 495     return env->tsc_deadline != 0;
 496 }
 497
 498 static const VMStateDescription vmstate_msr_tscdeadline = {
 499     .name = "cpu/msr_tscdeadline",
 500     .version_id = 1,
 501     .minimum_version_id = 1,
 502     .needed = tscdeadline_needed,
 503     .fields = (VMStateField[]) {
 504         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
 505         VMSTATE_END_OF_LIST()
 506     }
 507 };
 508
 509 static bool misc_enable_needed(void *opaque)
 510 {
 511     X86CPU *cpu = opaque;
 512     CPUX86State *env = &cpu->env;
 513
 514     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 515 }
 516
 517 static bool feature_control_needed(void *opaque)
 518 {
 519     X86CPU *cpu = opaque;
 520     CPUX86State *env = &cpu->env;
 521
 522     return env->msr_ia32_feature_control != 0;
 523 }
 524
 525 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 526     .name = "cpu/msr_ia32_misc_enable",
 527     .version_id = 1,
 528     .minimum_version_id = 1,
 529     .needed = misc_enable_needed,
 530     .fields = (VMStateField[]) {
 531         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
 532         VMSTATE_END_OF_LIST()
 533     }
 534 };
 535
 536 static const VMStateDescription vmstate_msr_ia32_feature_control = {
 537     .name = "cpu/msr_ia32_feature_control",
 538     .version_id = 1,
 539     .minimum_version_id = 1,
 540     .needed = feature_control_needed,
 541     .fields = (VMStateField[]) {
 542         VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
 543         VMSTATE_END_OF_LIST()
 544     }
 545 };
 546
 547 static bool pmu_enable_needed(void *opaque)
 548 {
 549     X86CPU *cpu = opaque;
 550     CPUX86State *env = &cpu->env;
 551     int i;
 552
 553     if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
 554         env->msr_global_status || env->msr_global_ovf_ctrl) {
 555         return true;
 556     }
 557     for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
 558         if (env->msr_fixed_counters[i]) {
 559             return true;
 560         }
 561     }
 562     for (i = 0; i < MAX_GP_COUNTERS; i++) {
 563         if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
 564             return true;
 565         }
 566     }
 567
 568     return false;
 569 }
 570
 571 static const VMStateDescription vmstate_msr_architectural_pmu = {
 572     .name = "cpu/msr_architectural_pmu",
 573     .version_id = 1,
 574     .minimum_version_id = 1,
 575     .needed = pmu_enable_needed,
 576     .fields = (VMStateField[]) {
 577         VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
 578         VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
 579         VMSTATE_UINT64(env.msr_global_status, X86CPU),
 580         VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
 581         VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
 582         VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
 583         VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
 584         VMSTATE_END_OF_LIST()
 585     }
 586 };
 587
 588 static bool mpx_needed(void *opaque)
 589 {
 590     X86CPU *cpu = opaque;
 591     CPUX86State *env = &cpu->env;
 592     unsigned int i;
 593
 594     for (i = 0; i < 4; i++) {
 595         if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
 596             return true;
 597         }
 598     }
 599
 600     if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
 601         return true;
 602     }
 603
 604     return !!env->msr_bndcfgs;
 605 }
 606
 607 static const VMStateDescription vmstate_mpx = {
 608     .name = "cpu/mpx",
 609     .version_id = 1,
 610     .minimum_version_id = 1,
 611     .needed = mpx_needed,
 612     .fields = (VMStateField[]) {
 613         VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
 614         VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
 615         VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
 616         VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
 617         VMSTATE_END_OF_LIST()
 618     }
 619 };
 620
 621 static bool hyperv_hypercall_enable_needed(void *opaque)
 622 {
 623     X86CPU *cpu = opaque;
 624     CPUX86State *env = &cpu->env;
 625
 626     return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
 627 }
 628
 629 static const VMStateDescription vmstate_msr_hypercall_hypercall = {
 630     .name = "cpu/msr_hyperv_hypercall",
 631     .version_id = 1,
 632     .minimum_version_id = 1,
 633     .needed = hyperv_hypercall_enable_needed,
 634     .fields = (VMStateField[]) {
 635         VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
 636         VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
 637         VMSTATE_END_OF_LIST()
 638     }
 639 };
 640
 641 static bool hyperv_vapic_enable_needed(void *opaque)
 642 {
 643     X86CPU *cpu = opaque;
 644     CPUX86State *env = &cpu->env;
 645
 646     return env->msr_hv_vapic != 0;
 647 }
 648
 649 static const VMStateDescription vmstate_msr_hyperv_vapic = {
 650     .name = "cpu/msr_hyperv_vapic",
 651     .version_id = 1,
 652     .minimum_version_id = 1,
 653     .needed = hyperv_vapic_enable_needed,
 654     .fields = (VMStateField[]) {
 655         VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
 656         VMSTATE_END_OF_LIST()
 657     }
 658 };
 659
 660 static bool hyperv_time_enable_needed(void *opaque)
 661 {
 662     X86CPU *cpu = opaque;
 663     CPUX86State *env = &cpu->env;
 664
 665     return env->msr_hv_tsc != 0;
 666 }
 667
 668 static const VMStateDescription vmstate_msr_hyperv_time = {
 669     .name = "cpu/msr_hyperv_time",
 670     .version_id = 1,
 671     .minimum_version_id = 1,
 672     .needed = hyperv_time_enable_needed,
 673     .fields = (VMStateField[]) {
 674         VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
 675         VMSTATE_END_OF_LIST()
 676     }
 677 };
 678
 679 static bool hyperv_crash_enable_needed(void *opaque)
 680 {
 681     X86CPU *cpu = opaque;
 682     CPUX86State *env = &cpu->env;
 683     int i;
 684
 685     for (i = 0; i < HV_X64_MSR_CRASH_PARAMS; i++) {
 686         if (env->msr_hv_crash_params[i]) {
 687             return true;
 688         }
 689     }
 690     return false;
 691 }
 692
 693 static const VMStateDescription vmstate_msr_hyperv_crash = {
 694     .name = "cpu/msr_hyperv_crash",
 695     .version_id = 1,
 696     .minimum_version_id = 1,
 697     .needed = hyperv_crash_enable_needed,
 698     .fields = (VMStateField[]) {
 699         VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params,
 700                              X86CPU, HV_X64_MSR_CRASH_PARAMS),
 701         VMSTATE_END_OF_LIST()
 702     }
 703 };
 704
 705 static bool hyperv_runtime_enable_needed(void *opaque)
 706 {
 707     X86CPU *cpu = opaque;
 708     CPUX86State *env = &cpu->env;
 709
 710     return env->msr_hv_runtime != 0;
 711 }
 712
 713 static const VMStateDescription vmstate_msr_hyperv_runtime = {
 714     .name = "cpu/msr_hyperv_runtime",
 715     .version_id = 1,
 716     .minimum_version_id = 1,
 717     .needed = hyperv_runtime_enable_needed,
 718     .fields = (VMStateField[]) {
 719         VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
 720         VMSTATE_END_OF_LIST()
 721     }
 722 };
 723
 724 static bool hyperv_synic_enable_needed(void *opaque)
 725 {
 726     X86CPU *cpu = opaque;
 727     CPUX86State *env = &cpu->env;
 728     int i;
 729
 730     if (env->msr_hv_synic_control != 0 ||
 731         env->msr_hv_synic_evt_page != 0 ||
 732         env->msr_hv_synic_msg_page != 0) {
 733         return true;
 734     }
 735
 736     for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
 737         if (env->msr_hv_synic_sint[i] != 0) {
 738             return true;
 739         }
 740     }
 741
 742     return false;
 743 }
 744
 745 static const VMStateDescription vmstate_msr_hyperv_synic = {
 746     .name = "cpu/msr_hyperv_synic",
 747     .version_id = 1,
 748     .minimum_version_id = 1,
 749     .needed = hyperv_synic_enable_needed,
 750     .fields = (VMStateField[]) {
 751         VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
 752         VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
 753         VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
 754         VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU,
 755                              HV_SYNIC_SINT_COUNT),
 756         VMSTATE_END_OF_LIST()
 757     }
 758 };
 759
 760 static bool hyperv_stimer_enable_needed(void *opaque)
 761 {
 762     X86CPU *cpu = opaque;
 763     CPUX86State *env = &cpu->env;
 764     int i;
 765
 766     for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
 767         if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
 768             return true;
 769         }
 770     }
 771     return false;
 772 }
 773
 774 static const VMStateDescription vmstate_msr_hyperv_stimer = {
 775     .name = "cpu/msr_hyperv_stimer",
 776     .version_id = 1,
 777     .minimum_version_id = 1,
 778     .needed = hyperv_stimer_enable_needed,
 779     .fields = (VMStateField[]) {
 780         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config,
 781                              X86CPU, HV_SYNIC_STIMER_COUNT),
 782         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count,
 783                              X86CPU, HV_SYNIC_STIMER_COUNT),
 784         VMSTATE_END_OF_LIST()
 785     }
 786 };
 787
 788 static bool avx512_needed(void *opaque)
 789 {
 790     X86CPU *cpu = opaque;
 791     CPUX86State *env = &cpu->env;
 792     unsigned int i;
 793
 794     for (i = 0; i < NB_OPMASK_REGS; i++) {
 795         if (env->opmask_regs[i]) {
 796             return true;
 797         }
 798     }
 799
 800     for (i = 0; i < CPU_NB_REGS; i++) {
 801 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
 802         if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
 803             ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
 804             return true;
 805         }
 806 #ifdef TARGET_X86_64
 807         if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
 808             ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
 809             ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
 810             ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
 811             return true;
 812         }
 813 #endif
 814     }
 815
 816     return false;
 817 }
 818
 819 static const VMStateDescription vmstate_avx512 = {
 820     .name = "cpu/avx512",
 821     .version_id = 1,
 822     .minimum_version_id = 1,
 823     .needed = avx512_needed,
 824     .fields = (VMStateField[]) {
 825         VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
 826         VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
 827 #ifdef TARGET_X86_64
 828         VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
 829 #endif
 830         VMSTATE_END_OF_LIST()
 831     }
 832 };
 833
 834 static bool xss_needed(void *opaque)
 835 {
 836     X86CPU *cpu = opaque;
 837     CPUX86State *env = &cpu->env;
 838
 839     return env->xss != 0;
 840 }
 841
 842 static const VMStateDescription vmstate_xss = {
 843     .name = "cpu/xss",
 844     .version_id = 1,
 845     .minimum_version_id = 1,
 846     .needed = xss_needed,
 847     .fields = (VMStateField[]) {
 848         VMSTATE_UINT64(env.xss, X86CPU),
 849         VMSTATE_END_OF_LIST()
 850     }
 851 };
 852
 853 #ifdef TARGET_X86_64
 854 static bool pkru_needed(void *opaque)
 855 {
 856     X86CPU *cpu = opaque;
 857     CPUX86State *env = &cpu->env;
 858
 859     return env->pkru != 0;
 860 }
 861
 862 static const VMStateDescription vmstate_pkru = {
 863     .name = "cpu/pkru",
 864     .version_id = 1,
 865     .minimum_version_id = 1,
 866     .needed = pkru_needed,
 867     .fields = (VMStateField[]){
 868         VMSTATE_UINT32(env.pkru, X86CPU),
 869         VMSTATE_END_OF_LIST()
 870     }
 871 };
 872 #endif
 873
 874 static bool tsc_khz_needed(void *opaque)
 875 {
 876     X86CPU *cpu = opaque;
 877     CPUX86State *env = &cpu->env;
 878     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
 879     PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
 880     return env->tsc_khz && pcmc->save_tsc_khz;
 881 }
 882
 883 static const VMStateDescription vmstate_tsc_khz = {
 884     .name = "cpu/tsc_khz",
 885     .version_id = 1,
 886     .minimum_version_id = 1,
 887     .needed = tsc_khz_needed,
 888     .fields = (VMStateField[]) {
 889         VMSTATE_INT64(env.tsc_khz, X86CPU),
 890         VMSTATE_END_OF_LIST()
 891     }
 892 };
 893
 894 VMStateDescription vmstate_x86_cpu = {
 895     .name = "cpu",
 896     .version_id = 12,
 897     .minimum_version_id = 3,
 898     .pre_save = cpu_pre_save,
 899     .post_load = cpu_post_load,
 900     .fields = (VMStateField[]) {
 901         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
 902         VMSTATE_UINTTL(env.eip, X86CPU),
 903         VMSTATE_UINTTL(env.eflags, X86CPU),
 904         VMSTATE_UINT32(env.hflags, X86CPU),
 905         /* FPU */
 906         VMSTATE_UINT16(env.fpuc, X86CPU),
 907         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
 908         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
 909         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
 910         VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
 911
 912         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
 913         VMSTATE_SEGMENT(env.ldt, X86CPU),
 914         VMSTATE_SEGMENT(env.tr, X86CPU),
 915         VMSTATE_SEGMENT(env.gdt, X86CPU),
 916         VMSTATE_SEGMENT(env.idt, X86CPU),
 917
 918         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
 919 #ifdef TARGET_X86_64
 920         /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
 921         VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
 922         VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
 923         VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
 924         VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
 925 #else
 926         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
 927         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
 928 #endif
 929
 930         VMSTATE_UINTTL(env.cr[0], X86CPU),
 931         VMSTATE_UINTTL(env.cr[2], X86CPU),
 932         VMSTATE_UINTTL(env.cr[3], X86CPU),
 933         VMSTATE_UINTTL(env.cr[4], X86CPU),
 934         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
 935         /* MMU */
 936         VMSTATE_INT32(env.a20_mask, X86CPU),
 937         /* XMM */
 938         VMSTATE_UINT32(env.mxcsr, X86CPU),
 939         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
 940
 941 #ifdef TARGET_X86_64
 942         VMSTATE_UINT64(env.efer, X86CPU),
 943         VMSTATE_UINT64(env.star, X86CPU),
 944         VMSTATE_UINT64(env.lstar, X86CPU),
 945         VMSTATE_UINT64(env.cstar, X86CPU),
 946         VMSTATE_UINT64(env.fmask, X86CPU),
 947         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
 948 #endif
 949         VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
 950
 951         VMSTATE_UINT64_V(env.pat, X86CPU, 5),
 952         VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
 953
 954         VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5),
 955         VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
 956         VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
 957         VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
 958         VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
 959         VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
 960         VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
 961         VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
 962         VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
 963         VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
 964         VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
 965         /* MTRRs */
 966         VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
 967         VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
 968         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
 969         /* KVM-related states */
 970         VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
 971         VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
 972         VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
 973         VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
 974         VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
 975         VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
 976         VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
 977         VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
 978         VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
 979         /* MCE */
 980         VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
 981         VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
 982         VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
 983         VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
 984         /* rdtscp */
 985         VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
 986         /* KVM pvclock msr */
 987         VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
 988         VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
 989         /* XSAVE related fields */
 990         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
 991         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
 992         VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
 993         VMSTATE_END_OF_LIST()
 994         /* The above list is not sorted /wrt version numbers, watch out! */
 995     },
 996     .subsections = (const VMStateDescription*[]) {
 997         &vmstate_async_pf_msr,
 998         &vmstate_pv_eoi_msr,
 999         &vmstate_steal_time_msr,
1000         &vmstate_fpop_ip_dp,
1001         &vmstate_msr_tsc_adjust,
1002         &vmstate_msr_tscdeadline,
1003         &vmstate_msr_ia32_misc_enable,
1004         &vmstate_msr_ia32_feature_control,
1005         &vmstate_msr_architectural_pmu,
1006         &vmstate_mpx,
1007         &vmstate_msr_hypercall_hypercall,
1008         &vmstate_msr_hyperv_vapic,
1009         &vmstate_msr_hyperv_time,
1010         &vmstate_msr_hyperv_crash,
1011         &vmstate_msr_hyperv_runtime,
1012         &vmstate_msr_hyperv_synic,
1013         &vmstate_msr_hyperv_stimer,
1014         &vmstate_avx512,
1015         &vmstate_xss,
1016         &vmstate_tsc_khz,
1017 #ifdef TARGET_X86_64
1018         &vmstate_pkru,
1019 #endif
1020         NULL
1021     }
1022 };