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Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.
[mirror_qemu.git] / target-i386 / opreg_template.h
1 /*
2 * i386 micro operations (templates for various register related
3 * operations)
4 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 void OPPROTO glue(op_movl_A0,REGNAME)(void)
22 {
23 A0 = (uint32_t)REG;
24 }
25
26 void OPPROTO glue(op_addl_A0,REGNAME)(void)
27 {
28 A0 = (uint32_t)(A0 + REG);
29 }
30
31 void OPPROTO glue(glue(op_addl_A0,REGNAME),_s1)(void)
32 {
33 A0 = (uint32_t)(A0 + (REG << 1));
34 }
35
36 void OPPROTO glue(glue(op_addl_A0,REGNAME),_s2)(void)
37 {
38 A0 = (uint32_t)(A0 + (REG << 2));
39 }
40
41 void OPPROTO glue(glue(op_addl_A0,REGNAME),_s3)(void)
42 {
43 A0 = (uint32_t)(A0 + (REG << 3));
44 }
45
46 #ifdef TARGET_X86_64
47 void OPPROTO glue(op_movq_A0,REGNAME)(void)
48 {
49 A0 = REG;
50 }
51
52 void OPPROTO glue(op_addq_A0,REGNAME)(void)
53 {
54 A0 = (A0 + REG);
55 }
56
57 void OPPROTO glue(glue(op_addq_A0,REGNAME),_s1)(void)
58 {
59 A0 = (A0 + (REG << 1));
60 }
61
62 void OPPROTO glue(glue(op_addq_A0,REGNAME),_s2)(void)
63 {
64 A0 = (A0 + (REG << 2));
65 }
66
67 void OPPROTO glue(glue(op_addq_A0,REGNAME),_s3)(void)
68 {
69 A0 = (A0 + (REG << 3));
70 }
71 #endif
72
73 void OPPROTO glue(op_movl_T0,REGNAME)(void)
74 {
75 T0 = REG;
76 }
77
78 void OPPROTO glue(op_movl_T1,REGNAME)(void)
79 {
80 T1 = REG;
81 }
82
83 void OPPROTO glue(op_movh_T0,REGNAME)(void)
84 {
85 T0 = REG >> 8;
86 }
87
88 void OPPROTO glue(op_movh_T1,REGNAME)(void)
89 {
90 T1 = REG >> 8;
91 }
92
93 void OPPROTO glue(glue(op_movl,REGNAME),_T0)(void)
94 {
95 REG = (uint32_t)T0;
96 }
97
98 void OPPROTO glue(glue(op_movl,REGNAME),_T1)(void)
99 {
100 REG = (uint32_t)T1;
101 }
102
103 void OPPROTO glue(glue(op_movl,REGNAME),_A0)(void)
104 {
105 REG = (uint32_t)A0;
106 }
107
108 #ifdef TARGET_X86_64
109 void OPPROTO glue(glue(op_movq,REGNAME),_T0)(void)
110 {
111 REG = T0;
112 }
113
114 void OPPROTO glue(glue(op_movq,REGNAME),_T1)(void)
115 {
116 REG = T1;
117 }
118
119 void OPPROTO glue(glue(op_movq,REGNAME),_A0)(void)
120 {
121 REG = A0;
122 }
123 #endif
124
125 /* mov T1 to REG if T0 is true */
126 void OPPROTO glue(glue(op_cmovw,REGNAME),_T1_T0)(void)
127 {
128 if (T0)
129 REG = (REG & ~0xffff) | (T1 & 0xffff);
130 FORCE_RET();
131 }
132
133 void OPPROTO glue(glue(op_cmovl,REGNAME),_T1_T0)(void)
134 {
135 if (T0)
136 REG = (uint32_t)T1;
137 FORCE_RET();
138 }
139
140 #ifdef TARGET_X86_64
141 void OPPROTO glue(glue(op_cmovq,REGNAME),_T1_T0)(void)
142 {
143 if (T0)
144 REG = T1;
145 FORCE_RET();
146 }
147 #endif
148
149 /* NOTE: T0 high order bits are ignored */
150 void OPPROTO glue(glue(op_movw,REGNAME),_T0)(void)
151 {
152 REG = (REG & ~0xffff) | (T0 & 0xffff);
153 }
154
155 /* NOTE: T0 high order bits are ignored */
156 void OPPROTO glue(glue(op_movw,REGNAME),_T1)(void)
157 {
158 REG = (REG & ~0xffff) | (T1 & 0xffff);
159 }
160
161 /* NOTE: A0 high order bits are ignored */
162 void OPPROTO glue(glue(op_movw,REGNAME),_A0)(void)
163 {
164 REG = (REG & ~0xffff) | (A0 & 0xffff);
165 }
166
167 /* NOTE: T0 high order bits are ignored */
168 void OPPROTO glue(glue(op_movb,REGNAME),_T0)(void)
169 {
170 REG = (REG & ~0xff) | (T0 & 0xff);
171 }
172
173 /* NOTE: T0 high order bits are ignored */
174 void OPPROTO glue(glue(op_movh,REGNAME),_T0)(void)
175 {
176 REG = (REG & ~0xff00) | ((T0 & 0xff) << 8);
177 }
178
179 /* NOTE: T1 high order bits are ignored */
180 void OPPROTO glue(glue(op_movb,REGNAME),_T1)(void)
181 {
182 REG = (REG & ~0xff) | (T1 & 0xff);
183 }
184
185 /* NOTE: T1 high order bits are ignored */
186 void OPPROTO glue(glue(op_movh,REGNAME),_T1)(void)
187 {
188 REG = (REG & ~0xff00) | ((T1 & 0xff) << 8);
189 }
190